CN214477482U - Wafer level packaging structure containing optical sensing chip and mobile terminal - Google Patents
Wafer level packaging structure containing optical sensing chip and mobile terminal Download PDFInfo
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- CN214477482U CN214477482U CN202023275584.3U CN202023275584U CN214477482U CN 214477482 U CN214477482 U CN 214477482U CN 202023275584 U CN202023275584 U CN 202023275584U CN 214477482 U CN214477482 U CN 214477482U
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Abstract
The utility model discloses a wafer level packaging structure containing optical induction chip, include: glass, cofferdams, wafers, shading layers, passivation layers, seed layers, metal circuits, solder masks and solder balls; the cofferdam is arranged on the glass; the wafer is pressed with the glass with the cofferdam, wherein the wafer is provided with a signal welding pad and a photosensitive area; arranging a groove on the wafer, and arranging a silicon through hole above the groove; the light shielding layer and the passivation layer are arranged on the surface of the wafer; forming a laser hole on the signal pad; and depositing the seed layer on the surface of the wafer and the inner wall of the silicon through hole, and arranging the metal circuit. The utility model has the advantages that: the shading layer is directly arranged on the silicon surface of the wafer instead of the top layer, so that the problem that the soldering tin salient points (solder balls) have no shading structure can be solved, and the marking can be carried out by using a conventional laser coding mode.
Description
Technical Field
The utility model relates to an optical induction field, concretely relates to wafer level packaging structure and mobile terminal who contains optical induction chip.
Background
The optical sensor chip plays an important role in capturing images, and the optical sensor chip is widely used in electronic products such as digital cameras (digital cameras), digital video cameras (digital video recorders), mobile phones (mobile phones), solar cells, screens, lighting devices, and the like.
With the development of technology, the demand for the sensing accuracy of the optical sensor chip is also increasing. The conventional wafer level package structure including the optical sensor chip has the following problems:
the solder bumps (solder balls) are not provided with shading structures, so that the solder bumps (solder balls) are still transparent in a special application scene, and shadows projected by the solder bumps (solder balls) appear during chip imaging; moreover, the light shielding layer is at the top, and if the code marking is performed by using a laser method, the light shielding layer is damaged, so that light leakage is caused.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to provide a wafer level packaging structure and mobile terminal that contain the optical sensing chip, to sensitization chip in some special application scenes, avoid the metal of chip back encapsulation preparation to walk the line and the formation of image interference problem that soldering tin bump (tin ball) isotructure brought.
In order to solve the above technical problem, the utility model provides a wafer level packaging structure who contains optical induction chip, include: glass, cofferdams, wafers, shading layers, passivation layers, seed layers, metal circuits, solder masks and solder balls; the cofferdam is arranged on the glass; the wafer is pressed with the glass with the cofferdam, wherein the wafer is provided with a signal welding pad and a photosensitive area; arranging a groove on the wafer, and arranging a silicon through hole above the groove; the light shielding layer and the passivation layer are arranged on the surface of the wafer; forming a laser hole on the signal pad; depositing the seed layer on the surface of the wafer and the inner wall of the silicon through hole, and arranging the metal circuit; the wafer surface is provided with the solder mask layer and the solder balls, wherein the shading layer, the passivation layer, the seed layer, the metal circuit, the solder mask layer and the solder balls are sequentially distributed from bottom to top.
The utility model has the advantages that:
the shading layer is directly arranged on the silicon surface of the wafer instead of the top layer, so that the problem that the soldering tin salient points (solder balls) have no shading structure can be solved, and the marking can be carried out by using a conventional laser coding mode.
In one embodiment, the thickness of the glass is 100-1100 um; the cofferdams are arranged in an annular mode, and the cofferdams are single-circle or multi-circle.
In one embodiment, the material of the cofferdam is self-adhesive.
In one embodiment, the wafer and the glass are pressed together by bonding glue.
In one embodiment, the thickness of the wafer is 50-200 um.
In one embodiment, the light shielding layer is made of metal and is divided into two layers of titanium and copper; the titanium is below the copper.
In one embodiment, the thickness of the copper is 2-20 um, and the thickness of the titanium is 0.1-1 um.
In one embodiment, the seed layer is made of metal and is divided into two layers of titanium and copper; the titanium is below the copper.
In one embodiment, the thickness of the titanium is 0.1-1 um, and the thickness of the copper is 0.5-3 um.
Based on the same inventive concept, the present invention further provides a mobile terminal, which includes any one of the above wafer level package structures including an optical sensor chip.
Drawings
FIG. 1 is a schematic view of a cofferdam for manufacturing the wafer level package structure with optical sensor chip according to the present invention
Fig. 2 is a schematic diagram illustrating the pressing of the wafer and the glass cofferdam in the manufacturing method of the wafer level package structure including the optical sensing chip according to the present invention.
Fig. 3 is a schematic diagram illustrating the thinning of the silicon surface in the manufacturing method of the wafer level package structure including the optical sensor chip according to the present invention.
Fig. 4 is a schematic diagram of forming a trench in the method for fabricating a wafer level package structure including an optical sensor chip according to the present invention.
Fig. 5 is a schematic diagram of a manufacturing light shielding layer in the manufacturing method of the wafer level package structure including the optical sensor chip according to the present invention.
Fig. 6 is a schematic diagram of through-silicon-via manufacturing in the method for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
Fig. 7 is a schematic diagram of passivation in the method for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
Fig. 8 is a schematic diagram of laser drilling in the method for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
Fig. 9 is a schematic diagram of the pvd process in the method for fabricating the wafer level package structure including the optical sensing chip according to the present invention.
Fig. 10 is a schematic diagram of a metal circuit for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
Fig. 11 is a schematic diagram of manufacturing a solder mask layer in the manufacturing method of the wafer level package structure including the optical sensor chip according to the present invention.
FIG. 12 is a schematic diagram of a method for manufacturing solder balls in a wafer level package structure including an optical sensor chip according to the present invention.
Fig. 13 is a schematic diagram illustrating wafer dicing in the method for manufacturing a wafer level package structure including an optical sensor chip according to the present invention.
Detailed Description
The present invention is further described with reference to the following drawings and specific embodiments so that those skilled in the art can better understand the present invention and can implement the present invention, but the embodiments are not to be construed as limiting the present invention.
Referring to fig. 12, a wafer level package structure including an optical sensor chip includes: glass 101, cofferdam 102, wafer 106, shading layer 201, passivation layer 109, seed layer 111, metal circuit 112, solder mask layer 113 and solder ball 114; the cofferdam is arranged on the glass; the wafer is pressed with the glass with the cofferdam, wherein the wafer is provided with a signal welding pad 104 and a photosensitive area 105; arranging a groove 107 on the wafer, and arranging a through silicon via 108 above the groove; the light shielding layer and the passivation layer are arranged on the surface of the wafer; forming a laser hole 110 on the signal pad; depositing the seed layer on the surface of the wafer and the inner wall of the silicon through hole, and arranging the metal circuit; the wafer surface is provided with the solder mask layer and the solder balls, wherein the shading layer, the passivation layer, the seed layer, the metal circuit, the solder mask layer and the solder balls are sequentially distributed from bottom to top. The thickness of the glass is within the range of 100-1100 um; the cofferdams are arranged in an annular mode, and the cofferdams are single-circle or multi-circle.
The material of the cofferdam is sticky. And the wafer and the glass are pressed together through bonding glue. The thickness of the wafer is 50-200 um. The shading layer is made of metal and is divided into two layers of titanium and copper; the titanium is below the copper. More specifically, the thickness of copper is 2 ~ 20um, the thickness of titanium is 0.1 ~ 1 um. The seed layer is made of metal and is divided into two layers of titanium and copper; the titanium is below the copper. More specifically, the thickness of titanium is 0.1 ~ 1um, the thickness of copper is 0.5 ~ 3 um.
For the wafer level package structure including the optical sensor chip of the present invention, the following method for manufacturing the wafer level package structure including the optical sensor chip can be used for further understanding.
Based on the same inventive concept, the present invention further provides a mobile terminal, which includes any one of the above wafer level package structures including an optical sensor chip.
Referring to fig. 1 to 13, a method for fabricating a wafer level package structure including an optical sensor chip includes: manufacturing a cofferdam 102 on the surface of the glass 101; pressing a wafer 106 and glass with cofferdams, wherein the wafer is provided with a signal pad 104 and a photosensitive area 105; thinning silicon of the wafer; manufacturing a groove 107 above the thinned silicon substrate; manufacturing a light shielding layer 201 on the silicon surface; fabricating a through-silicon via 108 over the trench; passivating the silicon surface to form a passivation layer 109; performing laser drilling to break down the signal welding pad and form a laser hole 110 on the signal welding pad; depositing a seed layer 111 on the surface of the wafer and the inner wall of the silicon through hole, and arranging a metal circuit 112; a solder resist layer 113 and solder balls 114 are provided on the surface of the wafer.
The following introduces a specific application scenario of the fabrication method of the wafer level package structure including the optical sensor chip of the present invention:
firstly, the method comprises the following steps: processing the cofferdam:
referring to FIG. 1, a bank 102 is formed on a surface of a glass 101, and the thickness of the glass is generally in the range of 100 to 1100 μm. The glass dam serves to protect the photosensitive region 105 from external contamination, and is a supporting connection between the glass and the wafer 106 where the optical sensor chips are located. The cofferdams are annularly arranged on the single optical induction chip and can have different annular shapes. Can be a single circle or a plurality of circles. The cofferdam can be manufactured by the photoetching technology of organic photosensitive materials, or the methods of 3D printing, screen printing and the like. Preferably, the dam material is self-adhesive and has good thermal and chemical stability.
II, secondly: and (3) pressing the wafer and the glass cofferdam:
referring to fig. 2, the glass with dam is attached to the wafer 106 of optical sensor chips. Because the material of the cofferdam is sticky, each optical sensing chip is stuck by the cofferdam. According to the characteristics of the dam material, bonding glue 103 is used for pressing in order to obtain better bonding strength. If necessary, a special wafer-level pressing machine equipment can be used, and the wafer-level pressing machine equipment performs whole-piece pressing on the wafer-level pressing machine equipment by means of equipment parameters such as temperature, vacuum and pressure.
Thirdly, the method comprises the following steps: thinning of silicon surface
Referring to fig. 3, the silicon 106 of the wafer is thinned. In order to realize ultra-thin packaged chips, the silicon substrate needs to be thinned. The diamond grinding wheel can be used for mechanical grinding processing, or mechanical chemical grinding and polishing, or plasma dry etching, or wet etching by using fluorine-containing chemical liquid. The thickness of the silicon of the thinned wafer is generally within the range of 50-200 um, and the thickness can be adjusted at will according to specific application requirements. Preferably, the method comprises mechanically grinding with a diamond-impregnated wheel and then dry etching with plasma. The method has the advantages that the mechanical grinding processing is fast, but stress and micro-damage layers are generated on the silicon surface, and then the micro-damage layers are removed by using a plasma dry etching method, so that the surface stress is released, and the problem of wafer warping is solved. After thinning as shown in fig. 3.
Fourthly, the method comprises the following steps: etching bath
Referring to fig. 4, a trench is etched. A trench 107 is formed above the thinned silicon substrate 102. The most mature method is to etch away the excess silicon by using photolithography and dry etching processes to form the trench. Covering a silicon surface with a photoetching material with photosensitive characteristic, then applying a mask plate with a special pattern to carry out photosensitive treatment under light with specific wavelength, and then developing by using a chemical agent to manufacture a photoresist pattern. The part uncovered by the photoresist is etched and removed by active fluorine ion, thereby achieving the purpose of removing the silicon. A wet etch process may also be used instead of a dry etch process. After the silicon etching is finished, the photoresist on the surface of the protective layer is removed, and then the silicon surface is cleaned.
Fifthly: manufacture of light-shielding layer
Referring to fig. 5, a layer of metal 201 is fabricated on the silicon surface. The metal is mainly used for eliminating defects such as poor imaging (shadow of solder bumps) and ghost images of the photosensitive chip. In order to meet the light shielding requirement, the light shielding layer is on the silicon surface, and the area of the light shielding layer covers the whole back surface of the chip as much as possible.
A shading layer is manufactured on the silicon surface, and the shading layer is mainly used for eliminating defects such as poor imaging and ghost of the photosensitive chip. The material may be metal (titanium/copper/nickel/chromium) or organic material. The process for manufacturing the shading layer can be that the needed metal is sputtered to the silicon surface through physical vapor deposition, titanium is plated firstly and then copper is plated in order to enhance the bonding force, the titanium is plated on the silicon surface firstly under the effect of enhancing the bonding force with the silicon, the thickness of the copper is 2-20 microns generally, and the thickness of the titanium is 0.1-1 micron. Specifically, the method can be realized by a single process or a combination of processes such as spin coating, spraying, semiconductor photoetching and semiconductor etching.
Sixthly, the method comprises the following steps: through silicon via
Referring to fig. 6, the through silicon via 108 is etched. A through-silicon via 108 is made over the trench 107. The most mature method is to etch away the excess silicon by using a photolithography process and a dry etching process to etch out the through-silicon via. Covering a silicon surface with a photoetching material with photosensitive characteristic, then applying a mask plate with a special pattern to carry out photosensitive treatment under light with specific wavelength, and then developing by using a chemical agent to manufacture a photoresist pattern. The part uncovered by the photoresist is etched and removed by active fluorine ion, thereby achieving the purpose of removing the silicon. A wet etch process may also be used instead of a dry etch process. After the silicon etching is finished, the photoresist on the surface of the protective layer is removed, and then the silicon surface is cleaned. The structure is as shown in FIG. 6;
seventhly, the method comprises the following steps: passivation of
Referring to fig. 7, since silicon is a semiconductor, passivation may function as insulation. The structure is shown in figure 7.
Eighthly: laser drilling
Referring to fig. 8, the back lead is padded by breaking through the signal pad.
Nine: physical vapor deposition
Referring to fig. 9, a thin seed layer 111 is deposited on the back surface of the wafer and the inner wall of the through silicon via by magnetron sputtering. The seed layer achieves two purposes, namely, the bonding force between metal and a substrate is enhanced, and the seed layer is prepared for electroplating and depositing metal circuits. Common seed layer metals are titanium/copper, chromium/copper, and the like. Preferably an environmentally friendly and low cost titanium/copper structure. The thickness of titanium is 0.1-1 um, and the thickness of copper is 0.5-3 um, generally according to the degree of depth and the angle of through-silicon-via and adjust.
Ten: metal circuit
Referring to fig. 10, the metal lines may be disposed by a conventional method, which is not described herein.
Eleven: solder mask
Referring to fig. 11, the purpose of providing the solder mask is to protect the circuit, and the solder mask may be provided by using an existing method, which is not described herein again.
Twelve: tin ball
Referring to fig. 12, the solder balls may be disposed by a conventional method, which is not described herein again.
Thirteen: cutting of
Referring to fig. 13, the wafer is diced, and the wafer after wafer level packaging is diced into individual chips 115; the machining may be performed using a metal blade or a laser cutting technique.
The above-mentioned embodiments are merely preferred embodiments for fully illustrating the present invention, and the scope of the present invention is not limited thereto. Equivalent substitutes or changes made by the technical personnel in the technical field on the basis of the utility model are all within the protection scope of the utility model. The protection scope of the present invention is subject to the claims.
Claims (10)
1. A wafer level package structure including an optical sensor chip, comprising: glass, cofferdams, wafers, shading layers, passivation layers, seed layers, metal circuits, solder masks and solder balls; the cofferdam is arranged on the glass; the wafer is pressed with the glass with the cofferdam, wherein the wafer is provided with a signal welding pad and a photosensitive area; arranging a groove on the wafer, and arranging a silicon through hole above the groove; the light shielding layer and the passivation layer are arranged on the surface of the wafer; forming a laser hole on the signal pad; depositing the seed layer on the surface of the wafer and the inner wall of the silicon through hole, and arranging the metal circuit; the wafer surface is provided with the solder mask layer and the solder balls, wherein the shading layer, the passivation layer, the seed layer, the metal circuit, the solder mask layer and the solder balls are sequentially distributed from bottom to top.
2. The wafer-level package structure comprising an optical sensor chip as claimed in claim 1, wherein the glass has a thickness of 100-1100 um; the cofferdams are arranged in an annular mode, and the cofferdams are single-circle or multi-circle.
3. The wafer-level package structure comprising an optically sensitive chip of claim 1, wherein the material of said dam is self-adhesive.
4. The wafer-level package structure comprising an optically sensitive chip of claim 1, wherein the wafer and the glass are bonded together by a bonding glue.
5. The wafer-level package structure comprising an optical sensor chip as claimed in claim 1, wherein the wafer has a thickness of 50-200 um.
6. The wafer level package structure including an optical sensor chip as claimed in claim 1, wherein the light shielding layer is made of metal and is divided into two layers of ti and cu; the titanium is below the copper.
7. The wafer level package structure with optical sensor chip as claimed in claim 6, wherein the thickness of copper is 2-20 um, and the thickness of titanium is 0.1-1 um.
8. The wafer level package structure comprising an optical sensor chip as claimed in claim 1, wherein the seed layer is made of metal, and the seed layer is divided into two layers of titanium and copper; the titanium is below the copper.
9. The wafer level package structure of claim 8, wherein the thickness of the titanium is 0.1-1 um, and the thickness of the copper is 0.5-3 um.
10. A mobile terminal, characterized in that the mobile terminal comprises the wafer-level package structure containing the optical sensor chip according to any one of claims 1 to 9.
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| CN112713162A (en) * | 2020-12-29 | 2021-04-27 | 苏州科阳半导体有限公司 | Manufacturing method of wafer-level packaging structure containing optical sensing chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112713162A (en) * | 2020-12-29 | 2021-04-27 | 苏州科阳半导体有限公司 | Manufacturing method of wafer-level packaging structure containing optical sensing chip |
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