CN113990966A - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN113990966A CN113990966A CN202111450702.6A CN202111450702A CN113990966A CN 113990966 A CN113990966 A CN 113990966A CN 202111450702 A CN202111450702 A CN 202111450702A CN 113990966 A CN113990966 A CN 113990966A
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- optical coating
- package structure
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000001681 protective effect Effects 0.000 claims abstract description 53
- 230000003287 optical effect Effects 0.000 claims abstract description 39
- 238000000576 coating method Methods 0.000 claims abstract description 34
- 239000011248 coating agent Substances 0.000 claims abstract description 33
- 238000003466 welding Methods 0.000 claims abstract description 32
- 238000002834 transmittance Methods 0.000 claims abstract description 14
- 230000006698 induction Effects 0.000 claims abstract description 12
- 239000011247 coating layer Substances 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 40
- 239000000758 substrate Substances 0.000 claims description 19
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 230000000149 penetrating effect Effects 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 239000002952 polymeric resin Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229920003002 synthetic resin Polymers 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 239000011521 glass Substances 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 239000005416 organic matter Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000005304 optical glass Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000001028 reflection method Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14634—Assemblies, i.e. Hybrid structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
Abstract
The invention discloses a chip packaging structure and a chip packaging method, wherein the chip packaging structure comprises the following components: the chip to be packaged comprises a first surface and a second surface which are opposite, wherein the first surface is provided with an induction area and a welding pad coupled with the induction area; the optical coating is formed on the first surface and covers the sensing area; the protective film is formed on the surface of the optical coating layer, which deviates from the chip to be packaged, the protective film is made of organic matters, the light transmittance of the organic matters is greater than 95%, the refractive index is 1.5-1.52, the Shore hardness is 70-80 HD, and gaps do not exist between the protective film and the induction area. The invention directly forms a protective film with extremely high light transmittance and enough hardness on the surface of the optical coating, and has simple process and small thickness.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a chip package structure and a chip package method.
Background
A Complementary Metal Oxide Semiconductor (CMOS) Image Sensor (CIS) is mainly applied to the fields of low-pixel mobile phones, security monitoring and the like before smart phones appear. With the further upgrading and development of smart phones, CIS chips are gradually developed to high-end and customized. With the improvement of the resolution of a high-end CIS chip, the Pixel (Pixel) is smaller and smaller, and the Quantum Efficiency (QE) is correspondingly smaller. In order to increase the QE, CIS manufacturers often resort to increasing the optical area, increasing the amount of light entering, or using a high transmittance glass cover plate. In this process, two major challenges exist: for wafer-level advanced packaging technology, the increasingly large optical sensing area makes up for Cavity dams (Cavity Dam) for chip edge support glass cover plates without foothold; on the other hand, how to improve the light transmittance of the glass to the utmost is also a challenge for a few major mainstream CIS manufacturers.
For the improvement of the light transmittance of the glass cover plate, the light transmittance of the glass is improved by plating a layer of Anti-Reflection (AR) film on the glass, so that the effect of improving QE is achieved, but the light transmittance can only reach 96% by an Anti-Reflection method; sputtering AR after the glass thickness is reduced to 100um is also a great challenge, with very low feasibility. Meanwhile, Dam originally used for supporting the glass cover plate can be replaced by transparent resin glue with bonding capability due to lack of space, but the problem of light transmittance limit of the optical glass cannot be solved.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a chip packaging method, which can overcome the problem of poor light transmission in the prior art.
To achieve the above object, an embodiment of the present invention provides a chip package structure, including:
the chip to be packaged comprises a first surface and a second surface which are opposite, wherein the first surface is provided with an induction area and a welding pad coupled with the induction area;
the optical coating is formed on the first surface and covers the sensing area;
the protective film is formed on the surface, away from the chip to be packaged, of the optical coating, the protective film is made of organic matters, the light transmittance of the organic matters is greater than 95%, the refractive index is 1.5-1.52, and the Shore hardness is 70-80 HD;
wherein there is no gap between the protective film and the sensing region.
In one or more embodiments, the material of the protective film is epoxy resin.
In one or more embodiments, the protective film has a thickness of less than 5 μm.
In one or more embodiments, the optical coating is a polymer resin.
In one or more embodiments, the optical coating is SiO2。
In one or more embodiments, the second surface of the chip to be packaged is provided with a welding protrusion and a via hole penetrating through the chip to be packaged, the via hole exposes the welding pad, and the welding protrusion is electrically connected with the welding pad through a rewiring layer arranged in the via hole.
In one or more embodiments, the chip to be packaged is an image sensor chip.
In order to achieve the above object, an embodiment of the present invention provides a packaging method for a chip packaging structure, including:
providing a wafer, wherein the wafer comprises a plurality of chips to be packaged which are arranged in an array, the chips to be packaged comprise a first surface and a second surface which are opposite, and the first surface is provided with an induction area and a welding pad which is coupled with the induction area;
forming an optical coating on the first surface of the wafer, wherein the optical coating covers the sensing area;
forming a protective film on the surface of the optical coating, wherein the protective film is made of an organic matter, the light transmittance of the organic matter is more than 95%, the refractive index is 1.5-1.52, and the Shore hardness is 70-80 HD; wherein there is no gap between the protective film and the sensing region.
In one or more embodiments, the method further comprises:
providing a protective substrate, wherein the protective substrate is attached to the surface of the protective film through temporary bonding glue;
arranging a welding bump on the second surface of each chip to be packaged, wherein the welding bump is electrically connected with the welding pad and is used for being electrically connected with an external circuit;
cutting the wafer, the optical coating and the protective substrate through a cutting process to form a plurality of packaging structures of the chips to be packaged;
and stripping the protective substrate.
In one or more embodiments, the method for providing a solder bump on the second surface of each of the chips to be packaged includes:
forming a through hole penetrating through the wafer on the second surface of each chip to be packaged, wherein the through hole is used for exposing the welding pad;
forming an insulating layer covering the second surface of the chip to be packaged and the side wall of the through hole, wherein the welding pad is exposed out of the insulating layer;
forming a rewiring layer connected with the welding pad on the surface of the insulating layer;
forming a solder mask layer with an opening on the surface of the rewiring layer and the surface of the insulating layer, wherein the opening exposes part of the rewiring layer;
and manufacturing a welding bulge in the opening.
Compared with the prior art, the invention directly forms a protective film with extremely high light transmittance and enough hardness on the surface of the optical coating, and has simple process and small thickness.
Drawings
Fig. 1 is a schematic structural diagram of a package structure of a chip according to an embodiment of the invention;
fig. 2a to 2i are schematic diagrams of intermediate structures formed by a chip packaging method according to an embodiment of the invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
As shown in fig. 1, a chip package structure 100 according to a preferred embodiment of the present invention includes a chip 10 to be packaged, an optical coating 20, and a protective film 30. The chip 10 to be packaged comprises a first surface 11 and a second surface 12 which are opposite, wherein the first surface 11 is provided with a sensing area 111 and a welding pad 112 coupled with the sensing area 111; the optical coating 20 is formed on the first surface 11 and covers the sensing region 111; a protective film 30 is formed on the surface of the optical coating 20 facing away from the chip 10 to be packaged, wherein no gap exists between the protective film 30 and the sensing region 111.
The sensing region 111 of the chip 10 to be packaged is provided with a plurality of pixel points arranged in an array. The chip 10 to be packaged is preferably a photosensitive chip, which may be an image sensing chip, and the pixel points are used for sensing optical information passing through the protective film 30 and the optical coating 20 and generating image information according to the optical information.
Generally, when the chip 10 to be packaged is packaged, in order to obtain a thin package structure, the second surface of the chip 10 to be packaged needs to be thinned, and specifically, the second surface of the chip 10 to be packaged may be thinned through mechanical grinding or chemical etching.
The optical coating 20 covers at least the surface of the sensing region 111 to form a horizontal layer, the protective film 30 covers the surface of the optical coating 20 and at least corresponds to the upper part of the sensing region 111, and no gap exists between the protective film 30 and the optical coating 20.
In some embodiments, the optical coating 20 employs a polymer resin. In a preferred embodiment, the optical coating 20 may be SiO2。
The protective film 30 is made of a light-transmitting material, and covers the surface of the optical coating 20 to prevent physical damage. In some embodiments, the protective film is made of an organic material, the light transmittance of the organic material is greater than 95%, the refractive index is 1.5 to 1.52, the shore hardness is 70 to 80HD, and preferably, the protective film is made of epoxy resin.
In some embodiments, the second surface 12 of the chip 10 to be packaged is provided with a solder bump 13 and a via 14 penetrating through the chip to be packaged, the via 14 exposes the pad 112, and the solder bump 13 is electrically connected to the pad 112 through a redistribution layer 15 disposed in the via 14.
An insulating layer 16 is further arranged between the rewiring layer 15 and the chip 10 to be packaged, and the insulating layer 16 covers the side wall of the through hole 14 and exposes the bottom of the through hole 14, so that the rewiring layer 15 is electrically connected with the welding pad 112. The redistribution layer 15 covers the bottom of the via 14 and the insulating layer 16. The welding projection 13 is positioned on the surface of the insulating layer 16. Specifically, a solder resist layer 17 is further disposed on the surface of the rewiring layer 15, and the surface of the solder resist layer 17 is provided with an opening provided with the welding bump 13, so that the welding bump 13 is disposed, and the rewiring layer 15 at the opening is electrically connected with the welding bump 13.
In the embodiment shown in fig. 1, the via 14 is a double-step via, and the via 14 includes a groove 141 disposed on the second surface 12 of the chip to be packaged and a through hole 142 located in the groove 141 and penetrating through the chip 10 to be packaged. The depth of the groove 141 is smaller than the thickness of the chip 10 to be packaged, and does not penetrate through the chip 10 to be packaged; through holes 142 are formed on the basis of the grooves 141, and the through holes 142 penetrate through the chip 10 to be packaged to expose the pads 112.
In the present case, through directly forming protective film on optical coating's surface, the luminousness is good, and the hardness is high, and simple manufacture.
As shown in fig. 2a to fig. 2i, the present embodiment further provides a packaging method of a chip packaging structure, including the following steps:
referring to fig. 2a, a wafer is provided, where the wafer includes a plurality of chips 10 to be packaged (2 chips 10 to be packaged are schematically illustrated in the figure), the chip 10 to be packaged includes a first surface 11 and a second surface 12 opposite to the first surface, and the first surface 11 has a sensing region 111 and a pad 112 coupled to the sensing region 111.
Referring to fig. 2b, an optical coating 20 is formed on the first surface 11 of the wafer by a coating method, and the optical coating 20 covers the sensing region 111.
Referring to fig. 2c, a protective film 30 is formed on the surface of the optical coating layer 20 by coating, and the material of the protective film 30 is epoxy resin. . Wherein there is no gap between the protective film 30 and the sensing region 111.
Referring to fig. 2d, a protective substrate 40 is provided, and the protective substrate 40 is attached to the surface of the protective film 30 by a temporary bonding paste 50.
The chip 10 to be packaged is attached to the protection substrate 40, so that the protection substrate 40 needs to prevent the chip 10 to be packaged from deforming due to warpage, thermal expansion and the like in the production process, and the deformation of the chip to be packaged caused by the deformation of the protection substrate 40 is avoided. Optionally, the protective substrate is a rigid carrier, and the thermal expansion coefficient and the young's modulus of the protective substrate are matched with the chip 10 to be packaged and the temporary bonding adhesive 50, so that warpage can be effectively controlled. The protective substrate can not deform at the temperature of more than 175 ℃ and can bear the erosion of chemicals. Specifically, the protective substrate 40 is a steel plate, a glass plate, or a silicon wafer.
In some embodiments, the temporary bonding paste 50 is a high temperature debonding paste, a photolytic bonding paste, a chemical etch debonding paste, or a zone debonding paste. The temporary bonding adhesive 50 can be debonded by a debonding process that is simple, safe, and easy to implement, and in some embodiments, the temporary bonding adhesive 50 may also be a thermal release tape.
Referring to fig. 2e, a through hole 14 penetrating through the wafer is formed on the second surface 12 of each chip 10 to be packaged, and the through hole 14 is used for exposing the pad 112.
Referring to fig. 2f, an insulating layer 16 is formed to cover the second surface 12 of the chip 10 to be packaged and the sidewall of the via 14, and the insulating layer 16 exposes the pad 112.
Referring to fig. 2g, a redistribution layer 15 connected to the pad 112 is formed on the surface of the insulating layer 16.
Referring to fig. 2h, a solder resist layer 17 having an opening exposing a portion of the redistribution layer 15 is formed on the surface of the redistribution layer 15 and the surface of the insulating layer 16. And arranging a welding bump 13 on the second surface of each chip to be packaged, wherein the welding bump 13 is electrically connected with the welding pad 112 and is used for being electrically connected with an external circuit.
Referring to fig. 2i, the wafer, the optical coating 20 and the protective substrate 30 are diced along a dicing line 200 by a dicing process to form a plurality of package structures 100 of the chips to be packaged;
the protective substrate 40 is peeled off to form the package structure 100 shown in fig. 1.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. A chip package structure, comprising:
the chip to be packaged comprises a first surface and a second surface which are opposite, wherein the first surface is provided with an induction area and a welding pad coupled with the induction area;
the optical coating is formed on the first surface and covers the sensing area;
the protective film is formed on the surface of the optical coating layer, which is far away from the chip to be packaged, the protective film is made of organic matters, the light transmittance of the organic matters is more than 95%, the refractive index is 1.5-1.52, the Shore hardness is 70-80 HD,
wherein there is no gap between the protective film and the sensing region.
2. The chip package structure of claim 1, wherein the protective film is made of epoxy resin.
3. The chip package structure of claim 1, wherein the protective film has a thickness of less than 5 μm.
4. The chip package structure of claim 1, wherein the optical coating is a polymer resin.
5. The chip package structure of claim 1, wherein the optical coating is SiO2。
6. The chip package structure of claim 1, wherein the second surface of the chip to be packaged is provided with a solder bump and a via penetrating through the chip to be packaged, the via exposing the pad, and the solder bump is electrically connected to the pad through a redistribution layer disposed in the via.
7. The chip package structure of claim 1, wherein the chip to be packaged is an image sensor chip.
8. A method for packaging the chip package structure according to any one of claims 1 to 7, comprising:
providing a wafer, wherein the wafer comprises a plurality of chips to be packaged which are arranged in an array, the chips to be packaged comprise a first surface and a second surface which are opposite, and the first surface is provided with an induction area and a welding pad which is coupled with the induction area;
forming an optical coating on the first surface of the wafer, wherein the optical coating covers the sensing area; and forming a protective film on the surface of the optical coating, wherein the protective film is made of organic matters, the light transmittance of the organic matters is more than 95%, the refractive index is 1.5-1.52, the Shore hardness is 70-80 HD, and no gap exists between the protective film and the induction area.
9. The packaging method of claim 8, further comprising:
providing a protective substrate, wherein the protective substrate is attached to the surface of the protective film through temporary bonding glue;
arranging a welding bump on the second surface of each chip to be packaged, wherein the welding bump is electrically connected with the welding pad and is used for being electrically connected with an external circuit;
cutting the wafer, the optical coating and the protective substrate through a cutting process to form a plurality of packaging structures of the chips to be packaged;
and stripping the protective substrate.
10. The packaging method according to claim 9, wherein the step of providing a bonding bump on the second surface of each of the chips to be packaged comprises:
forming a through hole penetrating through the wafer on the second surface of each chip to be packaged, wherein the through hole is used for exposing the welding pad;
forming an insulating layer covering the second surface of the chip to be packaged and the side wall of the through hole, wherein the welding pad is exposed out of the insulating layer;
forming a rewiring layer connected with the welding pad on the surface of the insulating layer;
forming a solder mask layer with an opening on the surface of the rewiring layer and the surface of the insulating layer, wherein the opening exposes part of the rewiring layer;
and manufacturing a welding bulge in the opening.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111450702.6A CN113990966A (en) | 2021-12-01 | 2021-12-01 | Chip packaging structure and packaging method |
| PCT/CN2022/077045 WO2023097896A1 (en) | 2021-12-01 | 2022-02-21 | Packaging structure for chip and packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111450702.6A CN113990966A (en) | 2021-12-01 | 2021-12-01 | Chip packaging structure and packaging method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113990966A true CN113990966A (en) | 2022-01-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111450702.6A Pending CN113990966A (en) | 2021-12-01 | 2021-12-01 | Chip packaging structure and packaging method |
Country Status (2)
| Country | Link |
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| CN (1) | CN113990966A (en) |
| WO (1) | WO2023097896A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023097896A1 (en) * | 2021-12-01 | 2023-06-08 | 苏州晶方半导体科技股份有限公司 | Packaging structure for chip and packaging method |
| CN116544209A (en) * | 2023-07-03 | 2023-08-04 | 苏州科阳半导体有限公司 | Light-emitting chip and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011243749A (en) * | 2010-05-18 | 2011-12-01 | Panasonic Corp | Solid state image pickup device and manufacturing method thereof |
| CN104201115A (en) * | 2014-09-12 | 2014-12-10 | 苏州晶方半导体科技股份有限公司 | Wafer-level fingerprint recognition chip packaging structure and method |
| US11114483B2 (en) * | 2018-08-10 | 2021-09-07 | Omnivision Technologies, Inc. | Cavityless chip-scale image-sensor package |
| CN113990966A (en) * | 2021-12-01 | 2022-01-28 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and packaging method |
-
2021
- 2021-12-01 CN CN202111450702.6A patent/CN113990966A/en active Pending
-
2022
- 2022-02-21 WO PCT/CN2022/077045 patent/WO2023097896A1/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023097896A1 (en) * | 2021-12-01 | 2023-06-08 | 苏州晶方半导体科技股份有限公司 | Packaging structure for chip and packaging method |
| CN116544209A (en) * | 2023-07-03 | 2023-08-04 | 苏州科阳半导体有限公司 | Light-emitting chip and preparation method thereof |
| CN116544209B (en) * | 2023-07-03 | 2023-09-26 | 苏州科阳半导体有限公司 | Light-emitting chip and preparation method thereof |
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| Publication number | Publication date |
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| WO2023097896A1 (en) | 2023-06-08 |
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