WO2023097896A1

WO2023097896A1 - Packaging structure for chip and packaging method

Info

Publication number: WO2023097896A1
Application number: PCT/CN2022/077045
Authority: WO
Inventors: 汤杰夫; 王鑫琴; 杨剑宏; 王蔚
Original assignee: 苏州晶方半导体科技股份有限公司
Priority date: 2021-12-01
Filing date: 2022-02-21
Publication date: 2023-06-08
Also published as: CN113990966A

Abstract

Disclosed are a packaging structure for a chip and a packaging method. The packaging structure comprises: a chip to be packaged, comprising a first surface and a second surface opposite to each other, the first surface having a sensing region and a pad coupled to the sensing region; an optical coating that is formed on the first surface and covers the sensing region; and a protective film formed on the surface of the optical coating facing away from said chip, the protective film being made of organic matter, and the light transmittance of the organic matter being greater than 95%, the refractive index thereof being 1.5-1.52 and the Shore hardness thereof being 70-80 HD, wherein there is no gap between the protective film and the sensing region. According to the present invention, a protective film having extremely high light transmittance and enough hardness is directly formed on the surface of the optical coating, so that the process is simple, and the thickness is small.

Description

Chip packaging structure and packaging method

The present invention claims the priority of the Chinese patent application with the application number 202111450702.6 and the invention title "chip packaging structure and packaging method" submitted to the China Patent Office on December 01, 2021, the entire content of which is incorporated herein by reference middle.

technical field

The invention relates to the technical field of semiconductors, in particular to a chip packaging structure and packaging method.

Background technique

Complementary Metal Oxide Semiconductor (CMOS) Semiconductor Image Sensor (CMOS Image Sensor, CIS) was mainly used in low-pixel mobile phones and security monitoring and other fields before the emergence of smartphones. With the further upgrading and development of smart phones, CIS chips are gradually developing towards high-end and customized. As the resolution of high-end CIS chips increases, the pixel (Pixel) becomes smaller and smaller, and the quantum efficiency (Quantum Efficiency, QE) is correspondingly smaller. In order to improve its QE, CIS manufacturers often increase the area of the optical area, increase the amount of light entering, or use a glass cover with high light transmittance. In this process, there are two major challenges: For wafer-level advanced packaging technology, the increasing proportion of the optical sensing area makes there is no room for the cavity dam used to support the glass cover on the edge of the chip. ; On the other hand, how to increase the light transmittance of the glass to the extreme is also a challenge faced by several major CIS manufacturers.

In terms of improving the light transmittance of the glass cover, the current mainstream method is to increase the light transmittance of the glass by coating a layer of anti-reflection film (Anti-Reflection, AR) on the glass, so as to achieve the effect of improving the QE, but through The light transmittance of the anti-reflection method can only reach 96%; after the thickness of the glass is reduced to 100um, sputtering AR is also a great challenge, and the feasibility is extremely low. At the same time, the Dam originally used to support the glass cover will also be replaced with a transparent resin glue capable of bonding due to lack of space, but it still cannot solve the problem of the limit of light transmittance of optical glass.

The information disclosed in this Background section is only for enhancing the understanding of the general background of the present invention and should not be taken as an acknowledgment or any form of suggestion that the information constitutes the prior art that is already known to those skilled in the art.

Contents of the invention

The purpose of the present invention is to provide a chip packaging structure and packaging method, which can overcome the problem of poor light transmission in the prior art.

In order to achieve the above purpose, an embodiment of the present invention provides a chip packaging structure, including:

a chip to be packaged, including an opposite first surface and a second surface, the first surface has a sensing area and a bonding pad coupled with the sensing area;

an optical coating formed on the first surface and covering the sensing area;

A protective film, formed on the surface of the optical coating away from the chip to be packaged, the material of the protective film is organic, the light transmittance of the organic is greater than 95%, the refractive index is 1.5-1.52, and the Shore hardness is 70～80HD;

Wherein, there is no gap between the protective film and the sensing area.

In one or more embodiments, the protective film is made of epoxy resin.

In one or more embodiments, the thickness of the protective film is less than 5 μm.

In one or more embodiments, the optical coating uses a polymer resin.

In one or more embodiments, the optical coating is SiO2.

In one or more embodiments, the second surface of the chip to be packaged is provided with a welding bump and a via hole passing through the chip to be packaged, the via hole exposes the pad, and the soldering bump are electrically connected to the welding pad through the redistribution layer arranged in the via hole.

In one or more embodiments, the chip to be packaged is an image sensor chip.

In order to achieve the above object, an embodiment of the present invention provides a packaging method for a chip packaging structure, including:

A wafer is provided, the wafer includes a plurality of chips to be packaged arranged in an array, the chip to be packaged includes a first surface and a second surface opposite to each other, the first surface has a sensing area and the sensing area Coupling pads;

forming an optical coating on the first surface of the wafer, the optical coating covering the sensing area;

A protective film is formed on the surface of the optical coating, the material of the protective film is organic, the light transmittance of the organic is greater than 95%, the refractive index is 1.5-1.52, and the Shore hardness is 70-80HD; wherein, There is no gap between the protective film and the sensing area.

In one or more embodiments, it also includes:

A protective substrate is provided, and the protective substrate is mounted on the surface of the protective film through a temporary bonding glue;

Soldering bumps are provided on the second surface of each of the chips to be packaged, and the soldering bumps are electrically connected to the pads and are used for electrical connection with an external circuit;

Dividing the wafer, the optical coating and the protective substrate through a dicing process to form a plurality of packaging structures of the chips to be packaged;

The protective substrate is peeled off.

In one or more embodiments, the method for arranging solder bumps on the second surface of each chip to be packaged includes:

forming a via hole through the wafer on the second surface of each chip to be packaged, and the via hole is used to expose the pad;

forming an insulating layer covering the second surface of the chip to be packaged and the sidewall of the via hole, the insulating layer exposing the pad;

forming a rewiring layer connected to the pad on the surface of the insulating layer;

forming a solder resist layer with openings on the surface of the rewiring layer and the surface of the insulating layer, the openings exposing part of the rewiring layer;

Solder bumps are made in the openings.

Compared with the prior art, the invention directly forms a protective film with extremely high light transmittance and sufficient hardness on the surface of the optical coating, with simple process and small thickness.

Description of drawings

FIG. 1 is a schematic structural view of a package structure of a chip according to an embodiment of the present invention;

2a-2i are schematic diagrams of an intermediate structure formed by a chip packaging method according to an embodiment of the present invention.

Detailed ways

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific embodiments.

Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations thereof such as "includes" or "includes" and the like will be understood to include the stated elements or constituents, and not Other elements or other components are not excluded.

As shown in FIG. 1 , a chip packaging structure 100 according to a preferred embodiment of the present invention includes a chip to be packaged 10 , an optical coating 20 and a protective film 30 . The chip 10 to be packaged includes an opposite first surface 11 and a second surface 12, the first surface 11 has a sensing area 111 and a bonding pad 112 coupled with the sensing area 111; the optical coating 20 is formed on the first surface 11 and covers the sensing region 111; the protective film 30 is formed on the surface of the optical coating 20 away from the chip 10 to be packaged, wherein there is no protective film 30 and the sensing region 111 gap.

The sensing area 111 of the chip to be packaged 10 is provided with a plurality of pixels arranged in an array. The chip 10 to be packaged is preferably a photosensitive chip, and may be an image sensor chip. The pixels are used to sense the light information passing through the protective film 30 and the optical coating 20, and generate image information according to the light information.

Generally, when the chip 10 to be packaged is packaged, in order to obtain a thinner packaging structure, it is necessary to thin the second surface of the chip 10 to be packaged. Specifically, it can be treated by mechanical grinding or chemical etching. The second surface of the packaged chip 10 is thinned.

The optical coating 20 at least covers the surface of the sensing area 111 to form a horizontal layer, the protective film 30 covers the surface of the optical coating 20, and at least corresponds to the top of the sensing area 111, and there is no gap between the protective film 30 and the optical coating 20. gap.

In some embodiments, the optical coating 20 uses a polymer resin. In a preferred embodiment, the optical coating 20 may be SiO2.

The protective film 30 is made of light-transmitting material, which covers the surface of the optical coating 20 to avoid physical damage. In some embodiments, the material of the protective film is organic matter, the light transmittance of the organic matter is greater than 95%, the refractive index is 1.5-1.52, and the Shore hardness is 70-80HD. Preferably, the protective film The material is epoxy resin.

In some embodiments, the second surface 12 of the chip to be packaged 10 is provided with a welding bump 13 and a via hole 14 passing through the chip to be packaged, the via hole 14 exposes the solder pad 112, the The welding bump 13 is electrically connected to the welding pad 112 through the redistribution layer 15 disposed in the via hole 14 .

An insulating layer 16 is also arranged between the rewiring layer 15 and the chip 10 to be packaged. The insulating layer 16 covers the sidewall of the via hole 14 and exposes the bottom of the via hole 14, so that the rewiring layer 15 and the welding pad 112 electrical connections. The redistribution layer 15 covers the bottom of the via hole 14 and the insulating layer 16 . The welding bump 13 is located on the surface of the insulating layer 16 . Specifically, a solder resist layer 17 is also provided on the surface of the rewiring layer 15, and the solder resist layer 17 has an opening provided with a solder bump 13 on the surface, so that the solder bump 13 is arranged so that the solder bump 13 and the opening The redistribution layer 15 is electrically connected.

In the embodiment shown in FIG. 1 , the via hole 14 is a double-layer stepped via hole. At this time, the via hole 14 includes a groove 141 arranged on the second surface 12 of the chip to be packaged and a groove 141 located in the groove. 141 and penetrate through the through hole 142 of the chip 10 to be packaged. The depth of the groove 141 is less than the thickness of the chip to be packaged 10, and does not penetrate the chip to be packaged 10; a through hole 142 is formed on the basis of the groove 141, and the through hole 142 penetrates through the chip to be packaged 10 to expose the pad 112.

In this case, by directly forming a protective film on the surface of the optical coating, the light transmittance is good, the hardness is high, and the production is simple.

As shown in FIGS. 2a to 2i , this embodiment also provides a packaging method for a chip packaging structure, including the following steps:

As shown in Fig. 2a, a wafer is provided, and the wafer includes a plurality of chips 10 to be packaged in an array (in the figure, two chips 10 to be packaged are taken as an example for schematic illustration), and the chips 10 to be packaged are It includes opposite first surface 11 and second surface 12 , the first surface 11 has a sensing area 111 and a pad 112 coupled with the sensing area 111 .

As shown in FIG. 2 b , an optical coating 20 is formed on the first surface 11 of the wafer by coating, and the optical coating 20 covers the sensing region 111 .

As shown in FIG. 2 c , a protective film 30 is formed on the surface of the optical coating 20 by coating, and the material of the protective film 30 is epoxy resin. Wherein, there is no gap between the protective film 30 and the sensing region 111 .

As shown in FIG. 2 d , a protective substrate 40 is provided, and the protective substrate 40 is mounted on the surface of the protective film 30 through a temporary bonding glue 50 .

The chip to be packaged 10 is mounted on the protective substrate 40 , so the protective substrate 40 needs to meet the requirement that the chip to be packaged 10 does not undergo deformation such as warping and thermal expansion during the production process, so as to avoid deformation of the chip to be packaged caused by the deformation of the protective substrate 40 . Optionally, the protective substrate is a rigid carrier, and the thermal expansion coefficient and Young's modulus of the protective substrate match the chip 10 to be packaged and the temporary bonding adhesive 50 , which can effectively control warpage. The protection substrate can not be deformed when the temperature is greater than 175° C., and can withstand chemical corrosion. Specifically, the protective substrate 40 is a steel plate, a glass plate or a silicon wafer.

In some embodiments, the temporary bonding glue 50 is a pyrolytic bonding glue, a photolytic bonding glue, a chemical corrosion debonding glue or a zone debonding glue. The temporary bonding adhesive 50 can be debonded through a debonding process, and the debonding process is simple, safe and easy to implement. In some embodiments, the temporary bonding adhesive 50 can also be a thermal release tape.

As shown in FIG. 2 e , a via hole 14 penetrating the wafer is formed on the second surface 12 of each chip 10 to be packaged, and the via hole 14 is used to expose the pad 112 .

As shown in FIG. 2 f , an insulating layer 16 covering the second surface 12 of the chip to be packaged 10 and the sidewall of the via hole 14 is formed, and the insulating layer 16 exposes the pad 112 .

As shown in FIG. 2 g , a rewiring layer 15 connected to the solder pad 112 is formed on the surface of the insulating layer 16 .

As shown in FIG. 2 h , a solder resist layer 17 with openings is formed on the surface of the rewiring layer 15 and the surface of the insulating layer 16 , and the openings expose part of the rewiring layer 15 . Welding bumps 13 are provided on the second surface of each chip to be packaged, and the soldering bumps 13 are electrically connected to the pads 112 and used for electrical connection with an external circuit.

As shown in FIG. 2i, the wafer, the optical coating 20 and the protective substrate 30 are divided along the dividing line 200 by a dicing process to form a plurality of packaging structures 100 of the chips to be packaged;

The protection substrate 40 is peeled off to form the packaging structure 100 shown in FIG. 1 .

The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. These descriptions are not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling others skilled in the art to make and use various exemplary embodiments of the invention, as well as various Choose and change. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

A package structure for a chip, characterized in that it comprises:

a chip to be packaged, including an opposite first surface and a second surface, the first surface has a sensing area and a bonding pad coupled with the sensing area;

an optical coating formed on the first surface and covering the sensing area;

A protective film, formed on the surface of the optical coating away from the chip to be packaged, the material of the protective film is organic, the light transmittance of the organic is greater than 95%, the refractive index is 1.5-1.52, and the Shore hardness is 70～80HD,

Wherein, there is no gap between the protective film and the sensing area.
The packaging structure of the chip according to claim 1, wherein the material of the protective film is epoxy resin.
The chip packaging structure according to claim 1, wherein the thickness of the protective film is less than 5 μm.
The chip packaging structure according to claim 1, wherein the optical coating is made of polymer resin.
The chip packaging structure according to claim 1, wherein the optical coating is SiO2.
The packaging structure of the chip according to claim 1, wherein the second surface of the chip to be packaged is provided with a welding bump and a via hole passing through the chip to be packaged, and the via hole exposes the solder joint. The welding bump is electrically connected to the welding pad through the redistribution layer arranged in the via hole.
The chip packaging structure according to claim 1, wherein the chip to be packaged is an image sensor chip.
A packaging method for the packaging structure of a chip according to any one of claims 1 to 7, characterized in that it comprises:

A wafer is provided, the wafer includes a plurality of chips to be packaged arranged in an array, the chip to be packaged includes a first surface and a second surface opposite to each other, the first surface has a sensing area and the sensing area Coupling pads;

An optical coating is formed on the first surface of the wafer, and the optical coating covers the sensing area; a protective film is formed on the surface of the optical coating, and the material of the protective film is an organic substance, and the organic substance The light transmittance is greater than 95%, the refractive index is 1.5-1.52, and the Shore hardness is 70-80 HD, wherein there is no gap between the protective film and the sensing area.
The packaging method according to claim 8, further comprising:

A protective substrate is provided, and the protective substrate is mounted on the surface of the protective film through a temporary bonding glue;

Soldering bumps are provided on the second surface of each of the chips to be packaged, and the soldering bumps are electrically connected to the pads and are used for electrical connection with an external circuit;

Dividing the wafer, the optical coating and the protective substrate through a dicing process to form a plurality of packaging structures of the chips to be packaged;

The protective substrate is peeled off.
The packaging method according to claim 9, wherein the method of arranging solder bumps on the second surface of each chip to be packaged comprises:

forming a via hole through the wafer on the second surface of each chip to be packaged, and the via hole is used to expose the pad;

forming an insulating layer covering the second surface of the chip to be packaged and the sidewall of the via hole, the insulating layer exposing the pad;

forming a rewiring layer connected to the pad on the surface of the insulating layer;

forming a solder resist layer with openings on the surface of the rewiring layer and the surface of the insulating layer, the openings exposing part of the rewiring layer;

Solder bumps are made in the openings.