CN109860065B - Fan-out type packaging method - Google Patents
Fan-out type packaging method Download PDFInfo
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- CN109860065B CN109860065B CN201910113228.4A CN201910113228A CN109860065B CN 109860065 B CN109860065 B CN 109860065B CN 201910113228 A CN201910113228 A CN 201910113228A CN 109860065 B CN109860065 B CN 109860065B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Abstract
The application discloses a fan-out type packaging method, which comprises the following steps: providing a carrying disc, wherein the carrying disc comprises a first side and a second side which are arranged oppositely; fixing the back of at least one chip on the first side of the carrying disc, wherein the chip is provided with a front surface and the back surface, the front surface is provided with a bonding pad, and a position corresponding to the bonding pad is provided with a light resistance; and forming a plastic packaging layer on the first side of the carrying disc, wherein the plastic packaging layer covers the chip and the light resistor. Through the mode, the protection on the front side of the chip can be enhanced.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a fan-out type packaging method.
Background
Fan-out packages are rapidly becoming a hotspot in new semiconductor packaging technologies due to their advantages of miniaturization, low cost, and high integration.
In the existing fan-out package, the back surface of the chip is usually embedded into a plastic package layer, and then a dielectric layer and a redistribution layer are formed on the front surface of the chip, and the redistribution layer is electrically connected with a pad on the front surface of the chip.
The inventor of the application finds that the side surfaces and the back surfaces of the periphery of the chip of the existing fan-out type packaging device are protected by the plastic packaging material in the long-term research process, but the front surface of the chip is only protected by the dielectric layer, and when the front surface of the chip is impacted by stress, the front surface circuit of the chip is easily damaged, so that the function failure is caused, the yield of the chip is reduced, and the quality of a product is influenced.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a fan-out type packaging method which can enhance protection on the front side of a chip.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a fan-out packaging method, wherein the packaging method comprises the following steps: providing a carrying disc, wherein the carrying disc comprises a first side and a second side which are arranged oppositely; fixing the back surface of at least one chip on the first side of the carrying disc, wherein the chip is provided with a front surface and the back surface, the front surface is provided with a bonding pad, and a light resistance is arranged at a position corresponding to the bonding pad; and forming a plastic packaging layer on the first side of the carrying disc, wherein the plastic packaging layer covers the chip and the light resistor.
Wherein the packaging method further comprises, before fixing the back side of at least one chip on the first side of the boat: providing at least one wafer, wherein the wafer is provided with a front surface and a back surface, the wafer is provided with a plurality of chips arranged in a matrix, and scribing grooves are formed among the chips; the front surface of the chip is the front surface of the wafer, and the back surface of the chip is the back surface of the wafer; forming the photoresist on the bonding pad of the chip; grinding the back side of the wafer so that the thickness of the wafer is less than or equal to a threshold value; and cutting the scribing grooves of the wafer to obtain single chips.
Wherein the wafer includes a first wafer and a second wafer, and the cutting the scribe line of the wafer includes: cutting the first wafer to obtain a first chip, and cutting the second wafer to obtain a second chip; said securing a back side of at least one chip on said first side of said boat, comprising: fixing the back of at least one first chip and the back of at least one second chip on the first side of the carrier plate.
Wherein the packaging method further comprises: and grinding the surface of the plastic packaging layer, which is back to the chip, so that the photoresist is exposed.
Wherein, grind the surface of the said plastic-sealed layer back to the said chip, so as to make the said photoresistance expose, afterwards, the said packaging method also includes: removing the photoresist; and forming a patterned metal rewiring layer on the front surface of the chip, wherein the metal rewiring layer is electrically connected with the bonding pad, and one side of the metal rewiring layer, which is far away from the chip, is on the same horizontal plane.
Wherein, before forming a metal rewiring layer on the front surface of the chip, the packaging method further comprises: forming a first dielectric layer on one side of the plastic packaging layer, which is far away from the chip, wherein a first opening is formed in the position, corresponding to the bonding pad, of the first dielectric layer; forming a metal rewiring layer on the front surface of the chip, including: and forming a metal rewiring layer on the first dielectric layer.
Wherein after the forming of the metal re-wiring layer on the first dielectric layer, the packaging method further comprises: forming a second dielectric layer on the metal rewiring layer, wherein a second opening is formed in the second dielectric layer; and implanting a solder ball in the second opening, wherein the solder ball is electrically connected with the metal rewiring layer.
Before grinding the surface of the plastic packaging layer away from the chip, the packaging method further comprises: and removing the carrying disc.
Wherein after the removing the carrier tray, the packaging method further comprises: and arranging a protective film on the back surface of the chip.
Wherein said securing a back side of at least one chip on said first side of said boat comprises: fixing the back surfaces of at least two of the chips on the first side of the carrier plate; after the protective film is arranged on the back surface of the chip, the packaging method further comprises the following steps: and cutting the area between at least two chips to form a single packaged device, wherein at least one chip is contained in the single packaged device.
The beneficial effect of this application is: different from the situation of the prior art, in the fan-out type packaging method provided by the application, the back surface of the chip is fixed on the first side of the carrying disc, the front surface of the chip is provided with a bonding pad, and a light resistance is arranged at the position corresponding to the bonding pad; the plastic packaging layer formed on the first side of the carrying disc covers the chip and the light resistor, and the regions of the front side of the chip except the light resistor are covered by the plastic packaging layer; the plastic packaging layer on the front side of the chip can reduce the influence on the circuit on the front side of the chip when the chip is subjected to stress impact to a great extent, the yield of the chip is improved, and the quality of a product is improved.
In addition, because the redundant plastic packaging layer on the front surface of the chip is removed in a grinding mode, the plastic packaging layers on the front surfaces of the chips can be on the same horizontal plane, and therefore the height difference of the junction of the chip and the plastic packaging layers in the prior art is reduced; the side, far away from the chip, of the metal rewiring layer formed on the surface of the plastic package layer in the later period can also be positioned on the same horizontal plane, so that the height difference of the metal rewiring layer in the prior art is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart of one embodiment of a fan-out packaging method in the prior art;
FIG. 2 is a schematic structural diagram of an embodiment corresponding to steps S101 to S106 in FIG. 1;
FIG. 3 is a schematic diagram of one embodiment of a fan-out package device in the prior art;
FIG. 4 is a schematic flow chart diagram illustrating an embodiment of a fan-out packaging method of the present application;
FIG. 5 is a schematic structural diagram of an embodiment corresponding to steps S201 to S207 in FIG. 4;
FIG. 6 is a schematic diagram of the structure of one embodiment of a corresponding fan-out packaged device after step S207 in FIG. 4;
FIG. 7 is a schematic flow chart diagram illustrating another embodiment of the fan-out packaging method of the present application before step S202 in FIG. 4;
FIG. 8 is a schematic structural diagram of an embodiment corresponding to steps S301 to S304 in FIG. 7;
FIG. 9 is a schematic structural diagram of one embodiment of a fan-out package device of the present application;
FIG. 10 is a schematic structural diagram of another embodiment of a fan-out packaged device of the present application;
FIG. 11 is a schematic structural diagram of another embodiment of a fan-out packaged device of the present application;
fig. 12 is a schematic structural diagram of another embodiment of a fan-out package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The structure of the fan-out package method and the fan-out package device in the prior art will be described first.
Referring to fig. 1-2, fig. 1 is a schematic flow chart illustrating an embodiment of a fan-out packaging method in the prior art, and fig. 2 is a schematic structural diagram illustrating an embodiment corresponding to steps S101-S106 in fig. 1, where the packaging method includes:
s101: a boat 10 is provided, the boat 10 including first and second oppositely disposed sides 100, 102. Specifically, please refer to fig. 2a. Typically, the first side 100 of the boat 10 is further provided with an adhesive film 12, such as a double-sided tape, to enable the post chip 14 to be initially fixed to the boat 10.
S102: a front side 140 of at least one chip 14 is fixed to the first side 100 of the boat 10, wherein the chip 14 is provided with a front side 140 and a rear side 142, and the front side 140 is provided with a bonding pad 144. Specifically, referring to fig. 2b, the front surface 140 of the chip 14 can be fixed to the adhesive film 12 and further fixed to the carrier 10.
S103: a molding layer 16 is formed on the first side 100 of the boat 10, and the molding layer 16 covers the side surfaces (not labeled) and the back surface 142 of the chip 14. Specifically, please refer to fig. 2c.
S104: the boat 10 is removed. Specifically, referring to fig. 2d, when the first side 100 of the carrier tray 10 is covered with the adhesive film 12, the carrier tray 10 can be removed by peeling off the adhesive film 12.
S105: a first insulating layer 18 is formed on the front surface 140 of the chip 14, and a first via (not shown) is formed at a position of the first insulating layer 18 corresponding to the pad 144. Specifically, please refer to fig. 2e.
S106: a metal rewiring layer 11 is formed on the first insulating layer 18 on the side away from the chip 14, and the metal rewiring layer 11 is electrically connected to the pad 144. Specifically, please refer to fig. 2f.
Of course, referring to fig. 3 in the prior art, fig. 3 is a schematic structural diagram of an embodiment of a fan-out package device in the prior art. The fan-out package device may further include a second insulating layer 13 on the basis of fig. 2f, the second insulating layer 13 is located on a side of the metal redistribution layer 11 away from the chip 14, and a second via hole (not labeled) is disposed on the second insulating layer 13; and the solder ball 15 is positioned in the second through hole, and the solder ball 15 is electrically connected with the metal rewiring layer 11.
As can be seen from the above, in the prior art, the front surface 140 of the chip 14 is covered with only the first insulating layer 18, or the first insulating layer 18 and the second insulating layer 13, when the front surface 140 of the chip 14 is impacted by a stress, the circuit on the front surface 140 of the chip is easily damaged, which results in a functional failure, reducing the yield of the chip and affecting the quality of the product.
In addition, when the adhesive film 12 is adhered to the carrier tray 10, and the plastic package layer 16 is formed in the step S103, if at least two chips 14 are disposed on the carrier tray 10 and the two chips 14 have different heights, the two chips 14 are stressed differently under the pressure of the plastic package mold, the chips 14 with different heights are embedded into the adhesive film 12 to different depths, and after the plastic package layer 16 is formed, a height difference exists at a boundary (for example, an area indicated by an arrow in fig. 2 c) between the chip 14 and the plastic package layer 16, and the existence of the height difference adversely affects subsequent processes, for example, the formation of the first insulating layer 18, the formation of the metal redistribution layer 11, and the like.
Referring to fig. 4-5, fig. 4 is a schematic flow diagram illustrating an embodiment of a fan-out packaging method of the present application, and fig. 5 is a schematic structural diagram illustrating an embodiment corresponding to steps S201 to S207 in fig. 4, where the packaging method includes:
s201: a boat 20 is provided, the boat 20 including oppositely disposed first 200 and second 202 sides.
Specifically, as shown in fig. 5a, the material of the tray 20 may be a hard material such as metal, silicon, plastic, etc., and the first side 200 of the tray 20 has a good horizontal property.
In addition, in this embodiment, after the step S201, the method further includes: an adhesive film 22 is disposed on the surface of the first side 200 of the tray 20, the adhesive film 22 is a removable adhesive film and has adhesiveness, for example, the adhesive film 22 is a double-sided tape; the rear chip 24 may be adhered to the adhesive film 22 to achieve a primary fixing of the position of the carrier plate 20.
S202: a back surface 240 of at least one chip 24 is fixed on the first side 200 of the boat 20, wherein the chip 24 is provided with a front surface 242 and the back surface 240, the front surface 242 is provided with pads 244, and the photoresist 26 is provided at positions corresponding to the pads 244.
Specifically, as shown in fig. 5b, in the present embodiment, a plurality of (e.g., one, two, three, etc.) chips 24 may be uniformly attached to the boat 20. The plurality of chips 24 may be of the same type or different types, for example, fig. 5b includes two types of chips 24, a first chip 24a and a second chip 24b, on the tray 20.
In an embodiment, please refer to fig. 7-8, fig. 7 is a schematic flowchart illustrating another embodiment of a fan-out packaging method before step S202 in fig. 4, fig. 8 is a schematic structural diagram illustrating an embodiment corresponding to steps S301 to S304 in fig. 7, and before step S202, the packaging method further includes:
s301: providing at least one wafer 30, wherein the wafer 30 is provided with a front surface 300 and a back surface 302, the wafer 30 is provided with a plurality of chips 24 arranged in a matrix, and scribing grooves 304 are formed among the chips 24; the front side (not labeled) of chip 24 is the front side 300 of wafer 30 and the back side (not labeled) of chip 24 is the back side 302 of wafer 30.
Specifically, as shown in fig. 8a, the chip 24 is a silicon substrate, a germanium substrate, or the like. A semiconductor device (not shown) and a bonding pad 244 are formed in the chip 24, and the semiconductor device and the bonding pad 244 may be located on the same side surface of the chip 24 or located on different side surfaces of the chip 24. When the semiconductor device and the pad 244 are located on different side surfaces of the chip 24, the pad 24 is electrically connected to the semiconductor device with a via penetrating the chip 24.
Further, in this embodiment, the number of discs 30 may be one, two, three, etc., for example, the discs 30 may include a first disc and a second disc, the first disc and the second disc being of different types.
S302: a photoresist 26 is formed on the pads 244 of the chip 24.
Specifically, as shown in fig. 8b, photoresist coating, exposing and developing processes may be performed on the front surface 300 of the wafer 30 to form the photoresist 26 on the pads 244 of the chip 24. The photoresist 26 may be a positive photoresist or a negative photoresist.
S303: the back side 302 of the wafer 30 is ground such that the thickness of the wafer 30 is equal to or less than the threshold value.
Specifically, as shown in fig. 8c, the threshold may be 100 microns, the thickness of the polished wafer 30 may be 50 microns, 80 microns, 100 microns, etc., and the on-resistance of the later chip 24 is reduced by reducing the thickness of the wafer 30.
S304: the dicing grooves 304 of the wafer 30 are cut to obtain individual chips 24.
Specifically, as shown in fig. 8d, in the present embodiment, one or more cuts may be made at the scribe line 304 of the wafer 30 by using plasma, laser, or blade to obtain a plurality of single chips 24.
In another embodiment, when the disc 30 includes a first disc and a second disc, the step S304 includes: the first wafer is cut to obtain first chips 24a, and the second wafer is cut to obtain second chips 24b. The step S202 specifically includes: a rear side (not labeled) of the at least one first chip 24a and a rear side (not labeled) of the at least one second chip 24b are fixed on the first side 200 of the boat 20. Since the types of the first chip 24a and the second chip 24b may be different, the ends of all the photoresists 26 on the carrier plate 20 facing away from the carrier plate 20 may not be on the same horizontal plane,
s203: a molding compound 28 is formed on the first side 200 of the boat 20, and the molding compound 28 covers the chip 24 and the photoresist 26.
Specifically, as shown in fig. 5c, the molding layer 28 may be made of epoxy resin. In the present embodiment, the front surface 242 of the chip 24 except for the photoresist 26 is covered by the molding layer 28; the molding layer 28 on the front side 242 of the chip 24 can greatly reduce the influence on the circuit on the front side 242 of the chip 24 when the chip 24 is subjected to stress impact, thereby improving the yield of the chip 24 and improving the quality of the product. It should be noted that the fan-out package device structure formed in fig. 5c may be sold separately or after subsequent processing.
In other embodiments, with continuing reference to fig. 4, the packaging method provided in the present application further includes: s204: the boat 20 is removed.
Specifically, as shown in fig. 5d, when the glue film 22 is disposed on the blade 20, the blade 20 can be removed by removing the glue film 22. It should be noted that the fan-out package device structure formed in fig. 5d may be sold separately or after subsequent processing.
In another embodiment, with continuing reference to fig. 4, the packaging method provided herein further includes: s205: the surface of the molding layer 28 opposite to the chip 24 is polished to expose the photoresist 26.
Specifically, as shown in fig. 5e, in the present embodiment, the ends of all the photo-resists 26 opposite to the chip 24 may not be on the same horizontal plane, and all the photo-resists 26 may be exposed by grinding the molding layer 28; after all of the photoresist 26 is exposed, polishing may be stopped or continued for a distance. In addition, in the present embodiment, when the molding layer 28 is polished, a carrier plate may be attached to the back surface of the chip 24, or the sequence of the step S205 and the step S204 may be reversed, that is, the carrier plate 20 is removed after the molding layer 28 is polished. Since the excess molding compound 28 on the front side 242 of the chip 24 is removed by grinding, the molding compound 28 on the front side 242 of the chip 24 can be on the same horizontal plane, thereby reducing the height difference existing at the interface between the chip 24 and the molding compound 28 in the prior art. It should be noted that the fan-out package device structure formed in fig. 5e can be sold separately or after subsequent processing.
In another embodiment, with continuing reference to fig. 4, the packaging method provided by the present application further includes:
s206: the photoresist 26 is removed.
Specifically, as shown in fig. 5f, the photoresist 26 may be removed by stripping, for example. After the photoresist 26 is removed, the molding layer 28 is etched to form via holes (not shown).
S207: a patterned metal redistribution layer 21 is formed on the front side 242 of the chip 24, wherein the metal redistribution layer 21 is electrically connected to the bonding pad 244, and a side of the metal redistribution layer 21 away from the chip 24 is on the same horizontal plane.
Specifically, as shown in fig. 5g, in the present embodiment, the side of the molding layer 28 away from the chip 24 is at the same level by grinding, and then the side of the metal redistribution layer 21 formed subsequently on the molding layer 28 away from the chip 24 is at the same level.
In another embodiment, referring to fig. 5g, before the step S207, the packaging method further includes: forming a first dielectric layer 23 on the side of the molding compound layer 28 away from the chip 24, and forming a first opening (not labeled) in a position of the first dielectric layer 23 corresponding to the pad 244; in this embodiment, the first dielectric layer 23 may cover the sidewalls of the etched via of the molding layer 28 and cover a portion of the pad 244. Step S207 specifically includes: a patterned metal redistribution layer 21 is formed on the first dielectric layer 23 away from the chip 24, and the metal redistribution layer 21 fills the etched via and is electrically connected to the pad 244. It should be noted that the fan-out packaged device structure formed in fig. 5g can be sold separately, and the fan-out packaged device can be electrically connected to an external device directly through the metal rewiring layer 21.
Of course, in other embodiments, please refer to fig. 6, and fig. 6 is a schematic structural diagram of an embodiment of the fan-out package device after step S207 in fig. 4. After step S207, the packaging method provided by the present application further includes:
A. referring to fig. 6a, a second dielectric layer 25 is formed on the metal redistribution layer 21, and a second opening (not labeled) is formed on the second dielectric layer 25; the first dielectric layer 23 and the second dielectric layer 25 form a wrapping effect of the metal rewiring layer 21. When the first dielectric layer 23 and the second dielectric layer 25 are made of low dielectric coefficient materials, the leakage current of the metal rewiring layer 21 can be reduced, and the capacitance effect between the wires can be reduced; in addition, the heat generation of the metal rewiring layer 21 can be reduced, the function of the chip 24 can be enhanced, and the quality of a packaged device can be improved.
B. Referring to fig. 6b, solder balls 27 are implanted in the second openings, and the solder balls 27 and the metal redistribution layer 21 are electrically connected. In this embodiment, a ball placement machine may be used to place the solder balls 27 in the second openings. It should be noted that the fan-out package device structure formed in fig. 6b can be sold separately, and the fan-out package device can be electrically connected with an external device directly through the solder balls 27.
In another embodiment, to enhance the protection of the fan-out package device, referring to fig. 6c, the packaging method provided by the present application further includes: a protective film 29 is provided on the back surface 240 of the chip 24. The material of the protective film 29 may be similar to that of the molding layer 28, such as epoxy resin, and the fan-out package device may be formed into a six-sided package through this step, so as to enhance the protection of the fan-out package device. The step of providing the protective film 29 may be any step after removing the carrier 20.
In another embodiment, the step S202 of fig. 4 of fixing the back surface 240 of the at least one chip 24 on the first side 200 of the boat 20 includes: securing the back surfaces 240 of the at least two chips 24 to the first side 200 of the boat 20; after the protective film 29 is disposed on the back surface 240 of the chip 24, the packaging method provided by the present application further includes: referring to fig. 6d, the area between at least two chips 24 is cut to form a single packaged device, wherein the single packaged device includes at least one (e.g., one, two, three, etc.) chip 24.
The fan-out package device formed by the above steps in the present application will be further described in terms of structure. Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a fan-out package device according to the present application. The fan-out package device provided by the present application includes:
at least one chip 24, the chip 24 including a front surface 242 and a back surface 240, the front surface 242 being provided with pads 244, and a photoresist 26 being provided at positions corresponding to the pads 244; in the present embodiment, the number of the chips 24 may be plural, and the types of the plural chips 24 may be the same or different, for example, the chips 24 include a first chip 24a and a second chip 24b. The thickness of the chip 24 is equal to or less than 100 microns, such as 50 microns, 80 microns, 100 microns, and the like.
The molding layer 28 covers the side surfaces and the front surface 242 of the chip 24, and does not cover the back surface 240 of the chip 24. In this embodiment, the molding layer 28 may be made of epoxy resin. In the present embodiment, the front surface 242 of the chip 24 except for the photoresist 26 is covered by the molding layer 28; the molding layer 28 on the front side 242 of the chip 24 can greatly reduce the influence on the circuit on the front side 242 of the chip 24 when the chip 24 is subjected to stress impact, thereby improving the yield of the chip 24 and improving the quality of the product.
In one embodiment, the side of the molding layer 28 away from the chip 24 is at the same level. As shown in fig. 9, the molding layer 28 may cover the photoresist 26. Of course, in other embodiments, as shown in fig. 10, fig. 10 is a schematic structural diagram of another embodiment of the fan-out package device of the present application, in which the molding layer 28a and the photoresist 26a are on the same horizontal plane, and the photoresist 26a is exposed from the molding layer 28 a. In the present embodiment, since the molding layers 28/28a on the front surface 242 of the chip 24 are on the same horizontal plane, the height difference existing at the interface between the chip 24 and the molding layers 28/28a in the prior art is reduced.
In another embodiment, please refer to fig. 11, fig. 11 is a schematic structural diagram of another embodiment of the package device of the present application, the package device further includes: a boat 20 positioned on the back side 240 of the chip 24; and the adhesive film 22 is positioned between the carrier disc 20 and the chip 24 and used for fixing the carrier disc 20 and the chip 24.
It should be noted that the structure of the packaged device provided in fig. 9-11 can be sold directly, and the downstream manufacturer can continue to perform subsequent processing after purchasing the packaged device.
Of course, in this application, it may also be manufactured as a complete packaged device for sale. Referring to fig. 12, fig. 12 is a schematic structural diagram of another embodiment of a fan-out package device according to the present application.
The fan-out package device includes:
at least one chip 24, the chip 24 comprising a front side 242 and a back side 240, the front side 242 being provided with pads 244; in the present embodiment, the number of the chips 24 may be plural, and the types of the plural chips 24 may be the same or different. The thickness of the chip 24 is equal to or less than 100 micrometers, such as 50 micrometers, 80 micrometers, 100 micrometers, and the like.
The molding layer 28 covers the side surface and the front surface 242 of the chip 24, and a via hole (not labeled) is disposed at a position corresponding to the pad 244 to connect the pad 244 and the outside. In this embodiment, the molding layer 28 may be made of epoxy resin, and the side of the molding layer 28 away from the chip 24 is on the same horizontal plane. In the present embodiment, the front surface 242 of the chip 24 except for the corresponding pad 244 is covered by the molding layer 28; the molding layer 28 on the front side 242 of the chip 24 can greatly reduce the influence on the circuit on the front side 242 of the chip 24 when the chip 24 is subjected to stress impact, thereby improving the yield of the chip 24 and improving the quality of the product.
With continued reference to fig. 12, the packaged device provided herein further includes: the metal rewiring layer 21 is positioned on one side of the plastic packaging layer 28, which is far away from the chip 24, and is electrically connected with the bonding pad 244; the side of the metal redistribution layer 24 away from the chip 24 is at the same level. In the present embodiment, since the molding layer 28 on the front surface 242 of the chip 24 is on the same horizontal plane, the height difference existing at the interface between the chip 24 and the molding layer 28 in the prior art is reduced.
In another embodiment, the packaged device provided by the present application further comprises: the first dielectric layer 23 is located between the metal redistribution layer 21 and the plastic package layer 28, and a first opening (not labeled) is disposed at a position of the first dielectric layer 23 corresponding to the pad 244. A second dielectric layer 25, located on a side of the metal redistribution layer 21 away from the chip 24, and a second opening (not labeled) is formed on a side of the second dielectric layer 25 corresponding to the metal redistribution layer 21; and a solder ball 27 located in the second opening, wherein the solder ball 27 and the metal redistribution layer 21 are electrically connected. In the embodiment, when the first dielectric layer 23 and the second dielectric layer 25 are made of low dielectric constant materials, the leakage current of the metal redistribution layer 21 can be reduced, and the capacitance effect between the wires can be reduced; in addition, the heat generation of the metal rewiring layer 21 can be reduced, the function of the chip 24 can be enhanced, and the quality of a packaged device can be improved.
In yet another embodiment, referring again to fig. 12, the packaged device provided by the present application further includes: and a protective film 29 on the back surface 240 of the chip 24. The material of the protective film 29 may be similar to that of the molding layer 28, for example, epoxy resin, and the protective film 29 may be disposed to form a six-sided encapsulation of the fan-out package device, so as to enhance the protection of the fan-out package device.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (9)
1. A fan-out packaging method, the packaging method comprising:
providing a carrying disc, wherein the carrying disc comprises a first side and a second side which are arranged oppositely;
fixing the back surface of at least one chip on the first side of the carrying disc, wherein the chip is provided with a front surface and the back surface, the front surface is provided with a bonding pad, and a light resistance is arranged at a position corresponding to the bonding pad;
forming a molding layer on the first side of the carrier platter;
grinding the surface of the plastic packaging layer, which is opposite to the chip, so that the photoresist is exposed; and the plastic packaging layer covers the region except the photoresist in the front surface of the chip.
2. The method of claim 1, wherein prior to securing the back side of the at least one chip on the first side of the boat, the method further comprises:
providing at least one wafer, wherein the wafer is provided with a front surface and a back surface, the wafer is provided with a plurality of chips arranged in a matrix, and scribing grooves are formed among the chips; the front surface of the chip is the front surface of the wafer, and the back surface of the chip is the back surface of the wafer;
forming the photoresist on the bonding pad of the chip;
grinding the back side of the wafer so that the thickness of the wafer is less than or equal to a threshold value;
and cutting the scribing grooves of the wafer to obtain single chips.
3. The packaging method according to claim 2,
the wafer comprises a first wafer and a second wafer, and the cutting the scribing grooves of the wafer comprises: cutting the first wafer to obtain a first chip, and cutting the second wafer to obtain a second chip;
said securing a back side of at least one chip on said first side of said boat, comprising: fixing the back of at least one first chip and the back of at least one second chip on the first side of the carrier plate.
4. The packaging method according to claim 1, wherein the grinding of the surface of the molding compound layer opposite to the chip to expose the photoresist, and thereafter, the packaging method further comprises:
removing the photoresist;
and forming a patterned metal rewiring layer on the front surface of the chip, wherein the metal rewiring layer is electrically connected with the bonding pad, and one side of the metal rewiring layer, which is far away from the chip, is on the same horizontal plane.
5. The packaging method according to claim 4,
before forming a metal rewiring layer on the front surface of the chip, the packaging method further includes: forming a first dielectric layer on one side of the plastic packaging layer, which is far away from the chip, wherein a first opening is formed in the position, corresponding to the bonding pad, of the first dielectric layer;
forming a metal rewiring layer on the front surface of the chip, including: and forming a metal rewiring layer on the first dielectric layer.
6. The packaging method of claim 5, wherein after the forming a metal re-routing layer on the first dielectric layer, the packaging method further comprises:
forming a second dielectric layer on the metal rewiring layer, wherein a second opening is formed in the second dielectric layer;
and implanting a solder ball in the second opening, wherein the solder ball is electrically connected with the metal rewiring layer.
7. The packaging method according to claim 1, wherein before the grinding the surface of the molding layer away from the chip, the packaging method further comprises:
and removing the carrying disc.
8. The method of claim 7, wherein after the removing the boat, the method further comprises:
and arranging a protective film on the back surface of the chip.
9. The method of packaging of claim 8, wherein securing the back side of the at least one chip on the first side of the boat comprises: fixing the back surfaces of at least two of the chips on the first side of the carrier plate;
after the protective film is arranged on the back surface of the chip, the packaging method further comprises the following steps: and cutting the area between at least two chips to form a single packaged device, wherein at least one chip is contained in the single packaged device.
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| CN104051287B (en) * | 2013-03-15 | 2017-06-16 | 台湾积体电路制造股份有限公司 | It is fanned out to interconnection structure and forming method thereof |
| US9941244B2 (en) * | 2013-12-09 | 2018-04-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protective layer for contact pads in fan-out interconnect structure and method of forming same |
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