CN111312599B - Fan-out type packaging method and fan-out type packaging device - Google Patents

Fan-out type packaging method and fan-out type packaging device Download PDF

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Publication number
CN111312599B
CN111312599B CN202010121665.3A CN202010121665A CN111312599B CN 111312599 B CN111312599 B CN 111312599B CN 202010121665 A CN202010121665 A CN 202010121665A CN 111312599 B CN111312599 B CN 111312599B
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underfill
chip
layer
functional surface
metal
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CN111312599A (en
Inventor
王耀尘
李尚轩
石佩佩
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Nantong Tongfu Microelectronics Co ltd
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Nantong Tongfu Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

Abstract

The application provides a fan-out type packaging method and a fan-out type packaging device, wherein the packaging method comprises the following steps: attaching one end of a metal column to a carrying disc, wherein the metal column is positioned on a functional surface of a chip and is electrically connected with a bonding pad on the functional surface of the chip; forming underfill between the functional surface of the chip and the carrier tray, the underfill covering the metal posts; forming a plastic packaging layer on one side of the carrying disc, which is provided with the chip, wherein the plastic packaging layer covers the chip and the underfill; and removing the carrying disc. Through the mode, the underfill can be used for fixing the chip, and then the probability of offset and flying offset of the chip in the press-fit forming process is reduced.

Description

Fan-out type packaging method and fan-out type packaging device
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a fan-out package method and a fan-out package device.
Background
The existing fan-out packaging method for forming six-sided protection comprises the following steps: adhering the non-functional surfaces of the plurality of chips to a carrying disc by using a crystal grain adhesion process; sealing the carrier disc by molding compound, and pressing the carrier disc into a mold to form a fan-out type packaging device with five-surface protection; and removing the carrying disc, and adhering the non-functional surface of the chip by using an adhesive film to form a fan-out type packaging device with six-sided protection.
The inventor of the present application found in the long-term research process that the problems of chip offset and flying offset occur in the press-molding process.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a fan-out type packaging method and a fan-out type packaging device, wherein an underfill can be used for fixing a chip, and then the probability of offset and flying offset of the chip in the press-fit molding process is reduced.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a fan-out packaging method, comprising: attaching one end of a metal column to a carrying disc, wherein the metal column is positioned on a functional surface of a chip and is electrically connected with a bonding pad on the functional surface of the chip; forming underfill between the functional surface of the chip and the carrier tray, the underfill covering the metal posts; forming a plastic packaging layer on one side of the carrying disc, which is provided with the chip, wherein the plastic packaging layer covers the chip and the underfill; and removing the carrying disc.
Wherein, in the direction from the carrying disc to the functional surface of the chip, the vertical section of the underfill is trapezoidal.
Wherein, said form underfill between said functional surface of said chip and said carrier disc, comprising: a dam is formed between the edge of the functional surface of the chip and the carrying disc, and the metal column is positioned in an area surrounded by the dam; and forming the underfill in the area surrounded by the box dam.
And the underfill is made of the same material as the box dam.
Before one end of the metal column is attached to the carrying disc, the packaging method comprises the following steps: providing a wafer, wherein the wafer is provided with a plurality of chips arranged in a matrix, scribing grooves are formed among the chips, the wafer comprises a front surface and a back surface, and the bonding pads of the chips are positioned on the front surface; forming a first rewiring layer on the front surface of the wafer, wherein the first rewiring layer is electrically connected with the bonding pad on the front surface; forming the metal pillar on the side of the first rewiring layer away from the wafer, wherein the metal pillar is electrically connected with the first rewiring layer; and cutting along the scribing grooves to obtain single chips.
Wherein after the removing the carrier tray, the packaging method further comprises: and forming a second rewiring layer on the plastic packaging layer and one side surface of the underfill, which is close to the functional surface, wherein the second rewiring layer is electrically connected with the part of the metal column, which is exposed from the underfill.
In order to solve the above technical problem, another technical solution adopted by the present application is: providing a fan-out packaged device, the packaged device comprising: the chip comprises a functional surface and a non-functional surface which are oppositely arranged, and a bonding pad is arranged on the functional surface; the metal column is correspondingly arranged at the position of the bonding pad and is electrically connected with the bonding pad; underfill, cover said functional surface and said metal post; the plastic package layer covers the non-functional surface of the chip, the side surface of the chip adjacent to the non-functional surface and the side surface of the underfill, and the metal column, the plastic package layer and the underfill are flush with one side of the non-functional surface.
Wherein the packaged device further comprises: and the box dam is positioned between the side surface of the underfill and the plastic packaging layer.
And the dam and the underfill are made of the same material.
Wherein the packaged device further comprises: the first rewiring layer is positioned between the bonding pad and the metal column and is electrically connected with the bonding pad and the metal column; and the second rewiring layer is positioned on the plastic packaging layer and the surface of one side, close to the functional surface, of the underfill, and is electrically connected with the exposed area of the metal column from the underfill.
Different from the prior art, in the fan-out type packaging method provided by the application, one side of the functional surface of the chip faces the carrying disc, underfill is arranged between the functional surface of the chip and the carrying disc, and the formed plastic packaging layer can cover the chip and the underfill. The beneficial effect of this application is: the underfill is used for fixing the chip, so that the probability of chip deviation and chip flying deviation caused by the influence of the external force of mold flow is reduced when the chip is subjected to follow-up press molding to form a plastic packaging layer; and in the six-side protection process provided by the application, one side of the non-functional surface of the chip is covered by the plastic package layer, the traditional adhesive film attached to one side of the non-functional surface of the chip is not needed, and the price of the adhesive film is expensive, so that the product cost can be greatly reduced by adopting the packaging method provided by the application. In addition, the fan-out type packaging method provided by the application can be widely applied to the semiconductor packaging industry, the structural stability of the chip and the quality of a packaged product are greatly improved, and the fan-out type packaging method is a brand new six-side protection packaging technology which is innovated by global packaging factories.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a fan-out packaging method according to the present application;
FIG. 2 is a schematic flow chart illustrating an embodiment of a fan-out packaging method before step S101 in FIG. 1;
FIG. 3 is a schematic structural view of an embodiment of a wafer;
FIG. 4a is a schematic cross-sectional view of one embodiment of the wafer of FIG. 3;
FIG. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 2;
FIG. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in FIG. 2;
FIG. 4d is a schematic structural diagram of an embodiment corresponding to step S204 in FIG. 2;
FIG. 5a is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 1;
FIG. 5b is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 1;
FIG. 5c is a schematic structural diagram of an embodiment corresponding to step S103 in FIG. 1;
FIG. 5d is a schematic structural diagram of an embodiment corresponding to step S104 in FIG. 1;
fig. 6 is a schematic structural diagram of an embodiment of a fan-out package device according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a fan-out packaging method according to the present application, the fan-out packaging method including:
s101: one end of the metal pillar 14 is attached to the carrier plate 20, wherein the metal pillar 14 is located on the functional surface 1002 of the chip 100 and electrically connected to the pad 1000 on the functional surface 1002 of the chip 100.
In one embodiment, please refer to fig. 2, wherein fig. 2 is a flowchart illustrating an embodiment of a fan-out packaging method according to the present application before step S101 in fig. 1. Before the step S101, the fan-out packaging method provided by the present application further includes:
s201: a wafer 10 is provided, the wafer 10 is provided with a plurality of chips 100 arranged in a matrix, scribing grooves 102 are arranged among the chips 100, the wafer 10 comprises a front surface 104 and a back surface 106, and bonding pads 1000 of the chips 100 are positioned on the front surface 104.
Specifically, referring to fig. 3 and fig. 4a, fig. 3 is a schematic structural diagram of an embodiment of a wafer, and fig. 4a is a schematic cross-sectional diagram of the embodiment of the wafer in fig. 3. The wafer 10 may be any commercially available wafer, and the wafer 10 may be a silicon substrate, a germanium substrate, or the like. The chip 100 may perform signal transmission with an external circuit through the bonding pads 1000 on the surface thereof.
S202: a first redistribution layer 12 is formed on the front surface 104 of the wafer 10, and the first redistribution layer 12 is electrically connected to the pads 1000 on the front surface 104.
Specifically, please refer to fig. 4b, wherein fig. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in fig. 2. The above process of forming the first redistribution layer 12 may be: forming a first passivation layer on the front surface 104 of the wafer 10, wherein a first through hole is formed in a position of the first passivation layer corresponding to the pad 1000; forming a first seed layer on a side of the first passivation layer away from the front surface 104, where the first seed layer may be made of at least one of aluminum, copper, gold, and silver, and the process for forming the first seed layer may be a sputtering process or a physical vapor deposition process; a first mask layer is formed on the surface of the first seed layer, and a first opening is formed at a position of the first mask layer corresponding to the pad 1000, wherein the first mask layer is made of at least one of photoresist, silicon oxide, silicon nitride, and amorphous carbon. The first rewiring layer 12 may include a first passivation layer, a first seed layer, and a first mask layer at this time.
S203: a metal pillar 14 is formed on the first redistribution layer 12 on the side away from the wafer 10, and the metal pillar 14 is electrically connected to the first redistribution layer 12.
Specifically, please refer to fig. 4c, wherein fig. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in fig. 2. The above process of forming the metal pillar 14 may be: a metal pillar 14 is formed in the first opening by electroplating.
In addition, after the metal posts 14 are formed, the fan-out packaging method provided by the present application may further include: the first mask layer is removed and the first seed layer except the metal pillar 14 is removed. The final first rewiring layer 12 may include only the first seed layer and the first passivation layer under the metal pillar 14.
S204: dicing is performed along the dicing grooves 102 to obtain individual chips 100.
Specifically, please refer to fig. 4d, wherein fig. 4d is a schematic structural diagram of an embodiment corresponding to step S204 in fig. 2. To facilitate the cutting, before the step S204, the fan-out package method provided by the present application further includes: the back side 106 of the wafer 10 is ground to thin the wafer 10. The functional side 1002 of the chip 100 is on the same side as the front side 104 of the wafer 10, and the non-functional side 1004 of the chip 100 is on the same side as the back side 106 of the wafer 10.
Further, referring to fig. 5a, fig. 5a is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 1. The step S101 specifically includes: the double-sided tape 22 is attached to the carrier tray 20, and the material of the carrier tray 20 may be metal, hard plastic, etc. At least one chip 100 with good cutting and testing performance is adhered to the double-sided adhesive tape 22 through a chip bonding machine, at this time, the functional surface 1002 of the chip 100 faces the carrying disc 20, and the metal column 14 is in contact with the double-sided adhesive tape 22.
S102: an underfill 16 is formed between the functional surface 1002 of the chip 100 and the carrier plate 20, and the underfill 16 covers the metal posts 14.
Specifically, please refer to fig. 5b, wherein fig. 5b is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 1. In the present embodiment, the underfill 16 has a trapezoidal vertical cross section in the direction from the carrier 20 to the functional surface 1002 of the chip 100. The underfill 16 may be formed by an underfill process, and the trapezoidal design of the underfill 16 may improve the stability of the chip 100 and the carrier tray 20 during the subsequent bonding process.
In another embodiment, in order to better define the position of the underfill 16, the step S102 specifically includes: a dam (not shown) is formed between the edge of the functional surface 1002 of the chip 100 and the carrier plate 20, and the metal posts 14 are located in the area surrounded by the dam; underfill 16 is formed in the area enclosed by the dam. Preferably, the underfill 16 is the same material as the dam.
S103: a molding layer 18 is formed on the carrier tray 20 on the side where the chips 100 are disposed, and the molding layer 18 covers the chips 100 and the underfill 16.
Specifically, please refer to fig. 5c, wherein fig. 5c is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 1. The molding layer 18 may be made of epoxy resin, and may be formed by a pressing process.
S104: the boat 20 is removed.
Specifically, as shown in fig. 5d, after the carrier tray 20 is removed, since the carrier tray 20 and the metal pillar 14 are connected by the double-sided tape 22, the carrier tray 20 can be removed by peeling off the double-sided tape 22. In addition, the metal posts 14, underfill 16, and molding layer 18 are found flush on one side after removal of the boat 20.
The underfill 16 is used for fixing the chip 100, so that the probability of the chip 100 shifting and flying caused by the influence of the external force of the mold flow is reduced when the chip 100 is pressed and molded to form the plastic packaging layer 18 in the subsequent process; in addition, in the six-surface protection process provided by the application, one side of the non-functional surface 1004 of the chip 100 is covered by the plastic packaging layer 18, a traditional adhesive film attached to one side of the non-functional surface 1004 of the chip 100 is not needed, and the price of the adhesive film is expensive, so that the fan-out packaging method provided by the application can greatly reduce the product cost.
In addition, after the step S104 removes the tray, the fan-out package method provided by the present application further includes: a second redistribution layer 11 is formed on the plastic encapsulation layer 18 and the surface of the underfill 16 near the functional surface 1002, and the second redistribution layer 11 is electrically connected to the exposed portion of the metal pillar 14 from the underfill 16. Specifically, as shown in fig. 6, fig. 6 is a schematic structural diagram of an embodiment of the fan-out package device of the present application. The above process of forming the second rewiring layer 11 may be: forming a second passivation layer 110 on the surface of the plastic encapsulation layer 18 and the underfill 16 close to one side of the functional surface 1002, wherein a second through hole (not labeled) is formed in a position, corresponding to the metal pillar 14, of the second passivation layer 110; forming a first metal layer 112 on a side of the second passivation layer 110 away from the molding layer 16, where the first metal layer 112 may be made of at least one of aluminum, copper, gold, and silver, and a process of forming the first metal layer 112 may be a sputtering process or a physical vapor deposition process; forming a third passivation layer 114 on the surface of the first metal layer 112, and forming a third via hole (not labeled) at a position of the third passivation layer 114 corresponding to the first metal layer 112; a second metal layer 116 is formed at the third via. The finally formed second re-wiring layer 11 may include a second passivation layer 110, a first metal layer 112, a second passivation layer 114, and a second metal layer 116. Of course, in other embodiments, the structure of the second redistribution layer 11 may be other, and the present application does not limit this.
In a preferred embodiment, the specific process of the fan-out packaging method includes: A. and providing a wafer, and forming a first rewiring layer and metal columns on the front surface of the wafer, wherein the metal columns are electrically connected with bonding pads on the front surface of the wafer through the first rewiring layer. B. And grinding the back surface of the wafer, and cutting along the scribing grooves on the wafer to obtain single chips. C. And uniformly sticking at least one chip onto the carrying disc, wherein the metal columns arranged on the chip are in contact with the carrying disc. D. And forming underfill between the functional surface of the chip and the carrier disc, wherein the underfill covers the metal posts. E. And forming a plastic packaging layer on one side of the carrying disc, wherein the chip and the underfill are covered by the plastic packaging layer. F. And removing the carrying disc. G. And forming a second rewiring layer on the plastic packaging layer and the surface of one side, close to the functional surface, of the underfill, wherein the second rewiring layer is electrically connected with the part, exposed from the underfill, of the metal column.
The fan-out package device provided by the present application and prepared by the above fan-out package method will be further described from the structural point of view. Referring again to fig. 6, the fan-out package device provided by the present application includes:
the chip 100 includes a functional surface 1002 and a non-functional surface 1004 disposed opposite to each other, and a pad 1000 is disposed on the functional surface 1002. The chip 100 may perform signal transmission with an external circuit through the pad 1000.
And the metal column 14 is correspondingly arranged at the position of the bonding pad 1000 and is electrically connected with the bonding pad 1000. The metal pillar 14 may be made of copper.
Underfill 16 covers the functional surface 1002 and the metal posts 14.
The molding layer 18 covers the non-functional surface 1004 of the chip 100, the side surface of the chip 100 adjacent to the non-functional surface 1004, and the side surface of the underfill 16, and the metal posts 14, the molding layer 18 and the underfill 16 are flush with each other on the side away from the non-functional surface 1004. The molding layer 18 may be made of epoxy resin.
In one embodiment, the fan-out package device provided herein further comprises: dams (not shown) are positioned between the sides of the underfill 16 and the molding layer 18 to limit the placement of the underfill 16 during the manufacturing process. Preferably, the dam and underfill 16 are the same material.
In yet another embodiment, the fan-out package device provided herein further includes:
a first rewiring layer 12 located between the pad 1000 and the metal pillar 14 and electrically connected to the pad 1000 and the metal pillar 14; in this embodiment, the first redistribution layer 12 may include a first passivation layer and a first seed layer, the first passivation layer may be located on the functional surface 1002 of the chip 100, and a first through hole is disposed at a position corresponding to the pad 1000, the first seed layer is correspondingly disposed at the first through hole, and the metal pillar 14 is correspondingly disposed on the first seed layer.
The second redistribution layer 11 is disposed on the molding compound layer 18 and one side surface of the underfill 16 close to the functional surface 1002, and is electrically connected to the region where the metal pillar 14 is exposed from the underfill 16. In the present embodiment, the second re-wiring layer 11 may include a second passivation layer 110, a first metal layer 112, a third passivation layer 114, and a second metal layer 116. The second passivation layer 110 may be disposed on the surface of the molding layer 18 and the underfill 16 near the functional surface 1002, and a second through hole (not shown) may be disposed at a position corresponding to the metal pillar 14; the first metal layer 112 may cover the second via hole and a portion of the second passivation layer 110 around the second via hole; the third passivation layer 114 covers one side of the first metal layer 112, and a third through hole is formed at a position corresponding to the first metal layer 112; second metal layer 116 covers the third via and a portion of third passivation layer 114 around the third via.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims (9)

1. A fan-out packaging method, the packaging method comprising:
attaching one end of a metal column to a carrying disc, wherein the metal column is positioned on a functional surface of a chip and is electrically connected with a bonding pad on the functional surface of the chip;
forming underfill between the functional surface of the chip and the carrier tray, the underfill covering the metal posts;
forming a plastic packaging layer on one side of the carrying disc, which is provided with the chip, wherein the plastic packaging layer covers the chip and the underfill;
removing the carrying disc;
wherein, before attaching one end of metal column on year dish, include:
providing a wafer, wherein the wafer is provided with a plurality of chips arranged in a matrix, scribing grooves are formed among the chips, the wafer comprises a front surface and a back surface, and the bonding pads of the chips are positioned on the front surface;
forming a first rewiring layer on the front surface of the wafer, wherein the first rewiring layer is electrically connected with the bonding pad on the front surface;
forming the metal pillar on the side of the first rewiring layer away from the wafer, wherein the metal pillar is electrically connected with the first rewiring layer;
and cutting along the scribing grooves to obtain single chips.
2. The packaging method according to claim 1,
and in the direction from the carrying disc to the functional surface of the chip, the vertical section of the underfill is trapezoidal.
3. The method of claim 1 or 2, wherein the forming an underfill between the functional side of the chip and the carrier tray comprises:
a dam is formed between the edge of the functional surface of the chip and the carrying disc, and the metal column is positioned in an area surrounded by the dam;
and forming the underfill in the area surrounded by the box dam.
4. The packaging method according to claim 3,
the underfill is the same as the material of the box dam.
5. The method of claim 1, wherein after the removing the boat, the method further comprises:
and forming a second rewiring layer on the plastic packaging layer and one side surface of the underfill, which is close to the functional surface, wherein the second rewiring layer is electrically connected with the part of the metal column, which is exposed from the underfill.
6. A fan-out packaged device prepared by the packaging method of any of claims 1-5, the packaged device comprising:
the chip comprises a functional surface and a non-functional surface which are oppositely arranged, and a bonding pad is arranged on the functional surface;
the metal column is correspondingly arranged at the position of the bonding pad and is electrically connected with the bonding pad;
the first rewiring layer is positioned between the bonding pad and the metal column and is electrically connected with the bonding pad and the metal column;
underfill, cover said functional surface and said metal post;
the plastic package layer covers the non-functional surface of the chip, the side surface of the chip adjacent to the non-functional surface and the side surface of the underfill, and the metal column, the plastic package layer and the underfill are flush with one side of the non-functional surface.
7. The packaged device of claim 6, further comprising:
and the box dam is positioned between the side surface of the underfill and the plastic packaging layer.
8. The packaged device of claim 7,
the box dam and the underfill are made of the same material.
9. The packaged device of claim 6, further comprising:
and the second rewiring layer is positioned on the plastic packaging layer and the surface of one side, close to the functional surface, of the underfill, and is electrically connected with the exposed area of the metal column from the underfill.
CN202010121665.3A 2020-02-26 2020-02-26 Fan-out type packaging method and fan-out type packaging device Active CN111312599B (en)

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CN111312599B true CN111312599B (en) 2022-02-11

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CN108242405A (en) * 2016-12-27 2018-07-03 冠宝科技股份有限公司 A kind of no substrate semiconductor encapsulation making method

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CN102386105A (en) * 2010-09-01 2012-03-21 群成科技股份有限公司 Packaging method with four flat sides and without pin and structure manufactured by packaging method
CN108242405A (en) * 2016-12-27 2018-07-03 冠宝科技股份有限公司 A kind of no substrate semiconductor encapsulation making method

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