CN111312600A - Fan-out type packaging method, fan-out type packaging device and fan-out type packaging body - Google Patents
Fan-out type packaging method, fan-out type packaging device and fan-out type packaging body Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
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Abstract
The application provides a fan-out type packaging method, a fan-out type packaging device and a fan-out type packaging body, wherein the fan-out type packaging method comprises the following steps: providing a wafer, wherein the wafer is provided with a plurality of chips arranged in a matrix, scribing grooves are formed among the chips, the wafer comprises a front surface and a back surface, and bonding pads of the chips are positioned on the front surface; cutting along the scribing grooves from the front surface of the wafer to form a plurality of grooves which do not penetrate through the wafer; forming a plastic packaging layer in the front surface of the wafer and the groove; follow the recess is right the disc is cut to obtain single packaging body, include singly in the single packaging body the chip, the plastic envelope covers the chip is provided with the surface of pad just at least partial side of chip is followed expose in the plastic envelope layer. Through the mode, the wafer can be subjected to plastic package treatment on the whole wafer, and a single chip pasting process is not needed.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a fan-out package method, a fan-out package device, and a fan-out package body.
Background
The existing fan-out packaging method comprises the following steps: cutting the wafer into a plurality of chips; adhering the non-functional surfaces of the plurality of chips to a carrying disc by using a crystal grain adhesion process; sealing the carrier disc by molding compound, and pressing the carrier disc into a mold so that the functional surface of the chip is covered by the molding layer; the carrier plate is removed, and the non-functional surface of the chip is adhered by using the adhesive film.
The inventor of the present application finds, in a long-term research process, that the previous process of the fan-out package method includes a process of attaching the non-functional surfaces of the plurality of chips to the carrier tray, which takes a long time, and problems such as chip offset and chip flying offset may occur in the attaching process.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a fan-out type packaging method, a fan-out type packaging device and a fan-out type packaging body, which can carry out plastic package processing on the whole wafer without carrying out a single chip pasting process.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a fan-out packaging method, comprising: providing a wafer, wherein the wafer is provided with a plurality of chips arranged in a matrix, scribing grooves are formed among the chips, the wafer comprises a front surface and a back surface, and bonding pads of the chips are positioned on the front surface; cutting along the scribing grooves from the front surface of the wafer to form a plurality of grooves which do not penetrate through the wafer; forming a plastic packaging layer in the front surface of the wafer and the groove; follow the recess is right the disc is cut to obtain single packaging body, include singly in the single packaging body the chip, the plastic envelope covers the chip is provided with the surface of pad just at least partial side of chip is followed expose in the plastic envelope layer.
Before the wafer is cut along the groove to obtain a single package, the fan-out packaging method further includes: grinding the back surface of the wafer, wherein the groove does not penetrate through the ground wafer; and adhering an adhesive film to the back surface of the ground wafer.
Wherein, in the direction from the front surface to the back surface, the vertical section of the groove is rectangular.
Wherein, said follow the recess is to the wafer cuts to obtain single encapsulation body, include: and cutting the wafer along the central axis of the groove to obtain a single package body, wherein step parts are formed on the side surfaces of the single chips contained in the single package body, and the plastic package layer covers the step parts but does not cover the side surfaces except the step parts.
Wherein before the dicing along the scribe line from the front surface of the wafer, the fan-out packaging method further comprises: forming a first rewiring layer on the front surface of the wafer, wherein the first rewiring layer is electrically connected with the bonding pad on the front surface; and forming metal columns on the side, away from the wafer, of the first rewiring layer, wherein the metal columns are electrically connected with the first rewiring layer.
Wherein the forming of the plastic package layer in the front surface of the wafer and the groove comprises: attaching the back side of the wafer to a carrier disc; forming the plastic packaging layer on one side of the carrying disc, which is provided with the wafer, wherein the plastic packaging layer covers the front surface of the wafer, the groove, the first rewiring layer and the metal column; and removing the carrying disc.
After the tray is removed, the fan-out packaging method further includes: grinding the plastic packaging layer on one side of the front surface of the wafer to enable the metal columns to be exposed out of the plastic packaging layer; and forming a second rewiring layer on the front surface of the wafer, wherein the second rewiring layer is electrically connected with the metal column.
In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided a fan-out package device, comprising: the chip packaging structure comprises a wafer, a plurality of chips arranged in a matrix, a groove which is not communicated with the wafer and is arranged between every two adjacent chips, a bonding pad of each chip is positioned on the front surface of the wafer, and the groove is formed by cutting the front surface of the wafer along a scribing groove; and the plastic packaging layer covers the front surface of the wafer and the groove.
Wherein, in the direction from the front surface to the back surface, the vertical section of the groove is rectangular.
Wherein the fan-out package device further comprises: and the adhesive film is arranged on the back surface of the wafer.
Wherein the fan-out package device further comprises: the first rewiring layer is positioned on the front surface of the wafer and is electrically connected with the bonding pad; and the metal column is positioned on one side of the first rewiring layer, which is far away from the wafer, is electrically connected with the first rewiring layer and is flush with the plastic packaging layer.
Wherein the fan-out package device further comprises: and the second rewiring layer is positioned on one side of the plastic packaging layer, which is far away from the wafer, and is electrically connected with the metal column.
In order to solve the above technical problem, another technical solution adopted by the present application is: the utility model provides a fan-out type packaging body, fan-out type packaging body is formed by the disc that is provided with the plastic envelope layer along the recess cutting that does not link up the disc, fan-out type packaging body includes: the chip comprises a functional surface and a non-functional surface which are oppositely arranged, and a bonding pad is arranged on the functional surface; and the plastic packaging layer covers the functional surface of the chip, and at least part of the side surface of the chip is exposed out of the plastic packaging layer.
Wherein at least part of the edge of the functional surface of the chip is provided with a recess, and the plastic packaging layer covers the recess but does not cover the side surface except the recess.
Wherein, in the direction from the functional surface to the non-functional surface, the vertical section of the recess is rectangular.
And an adhesive film is arranged on the non-functional surface of the chip, and the size of the adhesive film is larger than or equal to that of the non-functional surface of the chip.
Wherein the fan-out package further comprises: a first rewiring layer located on the functional surface of the chip and electrically connected to the bonding pad; and the metal column is positioned on one side of the first rewiring layer, which is far away from the chip, is electrically connected with the first rewiring layer and is level to the plastic packaging layer.
Wherein the fan-out package further comprises: and the second rewiring layer is positioned on one side of the plastic packaging layer, which is far away from the chip, and is electrically connected with the metal column.
Different from the prior art, the fan-out packaging method provided by the application comprises the following steps: cutting the front surface of the wafer along the scribing grooves to form a plurality of grooves which do not penetrate through the wafer; then forming a plastic packaging layer on the front surface of the wafer and in the groove; and then cutting the wafer along the groove to obtain a single package body, wherein the single package body comprises a single chip, the surface of the chip, which is provided with the bonding pad, is covered by the plastic package layer, and at least part of the side surface of the chip is exposed out of the plastic package layer. The fan-out type packaging method provided by the application is characterized in that non-cutting-through cutting processing is carried out on a wafer, and a single packaging body with 4.5 surfaces protected is obtained by pressing and molding the whole wafer and finally cutting the whole wafer; the other side of the wafer may be glued by a glue film to form a 5.5-sided protection prior to subsequent or final dicing. The beneficial effect of this application is: according to the method, the 4.5-surface protection forming process reduces the process of splitting a wafer into a single chip and a single chip pasting process in the previous process, so that the operation time can be greatly reduced, the manufacturing process cost is further reduced to a great extent, the problems of chip deviation, chip flying deviation, chip cracking and the like do not exist, the quality of the fan-out type packaging body with 5.5-surface protection is improved, and the yield of the fan-out type packaging body is improved; in addition, the side surface of the chip which is not covered by the plastic packaging layer is beneficial to heat dissipation of the packaging body.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a fan-out packaging method according to the present application;
FIG. 2 is a schematic structural view of an embodiment of a wafer;
FIG. 3a is a schematic structural diagram of one embodiment before step S102 in FIG. 1;
FIG. 3b is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 1;
FIG. 3c is a schematic structural diagram of an embodiment corresponding to step S103 in FIG. 1;
FIG. 4 is a schematic flow chart illustrating an embodiment of step S103 in FIG. 1;
FIG. 5a is a schematic structural diagram of an embodiment corresponding to step S201 in FIG. 4;
FIG. 5b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 4;
FIG. 6 is a schematic flow chart illustrating an embodiment of the fan-out packaging method according to the present application after step S203 in FIG. 4;
FIG. 7a is a schematic structural diagram of an embodiment corresponding to step S301 in FIG. 6;
FIG. 7b is a schematic structural diagram of an embodiment corresponding to step S302 in FIG. 6;
FIG. 8 is a schematic flowchart illustrating an embodiment of a fan-out packaging method according to the present application after step S103 in FIG. 1;
FIG. 9a is a schematic structural diagram of an embodiment corresponding to step S401 in FIG. 8;
FIG. 9b is a schematic structural diagram of an embodiment corresponding to step S402 in FIG. 8;
fig. 10 is a schematic structural diagram of an embodiment of a fan-out package according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a fan-out packaging method according to the present application, the fan-out packaging method including:
s101: a wafer 10 is provided, the wafer 10 is provided with a plurality of chips 100 arranged in a matrix, scribe lines 102 are provided between the chips 100, the wafer 10 includes a front surface (not shown in fig. 2) and a back surface (not shown in fig. 2), and pads (not shown in fig. 2) of the chips 100 are located on the front surface.
Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of a wafer. The wafer 10 may be any commercially available wafer, and the wafer 10 may be a silicon substrate, a germanium substrate, or the like, and may have a size of 8 inches, 12 inches, or the like. The chip 100 may perform signal transmission with an external circuit through pads on the surface thereof.
S102: a cut is made from the front side 104 of the wafer 10 along the scribe line 102 to form a plurality of recesses 106 that do not extend through the wafer 10.
In one embodiment, please refer to fig. 3a, where fig. 3a is a schematic structural diagram of a corresponding embodiment before step S102 in fig. 1. Before the step S102, the packaging method provided by the present application further includes:
A. a first redistribution layer 12 is formed on the front surface 104 of the wafer 10, and the first redistribution layer 12 is electrically connected to the pads 1000 on the front surface 104. Specifically, the process of forming the first redistribution layer 12 may be: forming a first passivation layer on the front surface 104 of the wafer 10, wherein a first through hole is formed in a position of the first passivation layer corresponding to the pad 1000; forming a first seed layer on a side of the first passivation layer away from the front surface 104, where the first seed layer may be made of at least one of aluminum, copper, gold, and silver, and the process for forming the first seed layer may be a sputtering process or a physical vapor deposition process; a first mask layer is formed on the surface of the first seed layer, and a first opening is formed at a position of the first mask layer corresponding to the pad 1000, wherein the first mask layer is made of at least one of photoresist, silicon oxide, silicon nitride, and amorphous carbon. The first rewiring layer 12 may include a first passivation layer, a first seed layer, and a first mask layer at this time.
B. A metal pillar 14 is formed on the first redistribution layer 12 on the side away from the wafer 10, and the metal pillar 14 is electrically connected to the first redistribution layer 12. Specifically, the process of forming the metal pillar 14 may be: a metal pillar 14 is formed in the first opening by electroplating.
In addition, after the step B, the fan-out package method provided by the present application may further include: the first mask layer is removed and the first seed layer except the metal pillar 14 is removed. The final first rewiring layer 12 may include only the first seed layer and the first passivation layer under the metal pillar 14.
In another embodiment, as shown in fig. 3b, fig. 3b is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 1. The vertical cross section of the groove 106 formed in the above step S102 is rectangular in the front surface 104 to back surface 108 direction. The rectangular recess 106 is easy to form. Of course, in other embodiments, the vertical cross section of the groove 106 may also be tapered in the direction from the front surface 104 to the back surface 108, which is not limited in this application. The recess 106 may be formed by laser cutting, and the depth of the recess 106 is determined according to the total height of the circuit designed in the chip 100, and generally, the depth of the recess 106 is greater than or equal to the total height of the circuit designed in the chip 100, for example, the depth of the recess 106 exceeds the thickness of the bonding pad 1000.
S103: the molding layer 16 is formed on the front surface 104 of the wafer 10 and in the recesses 106.
Specifically, please refer to fig. 3c, wherein fig. 3c is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 1. The molding layer 16 may be made of epoxy resin, and may be formed by a pressing process, in which case the molding layer 16 may cover the front surface 104 of the wafer 10 and the metal posts 14.
In one embodiment, please refer to fig. 4, fig. 4 is a schematic flowchart illustrating an embodiment of step S103 in fig. 1, where the step S103 specifically includes:
s201: the back side 108 of the wafer 10 is attached to the carrier plate 20.
Specifically, as shown in fig. 5a, fig. 5a is a schematic structural diagram of an embodiment corresponding to step S201 in fig. 4. The back surface 108 of the wafer 10 can be adhered to the carrier plate 20 by a double-sided adhesive, the size of the carrier plate 20 can be larger than that of the wafer 10, the material of the carrier plate 20 can be metal or hard plastic, and the like, and the carrier plate 20 can reduce the probability of breakage of the wafer 10 in the plastic packaging process.
In addition, referring again to fig. 2, the edge 101 of the wafer 10 is provided with an annular non-functional area 103, i.e., the area defined by the dashed line and the edge 101 in fig. 2, and the dashed line in fig. 2 is not actually present, but is drawn for more clearly indicating the position of the non-functional area 103. Before the step S201, the fan-out packaging method provided by the present application further includes: the non-functional region 103 is cut away. The non-functional area 103 is generally provided with a positioning part and the like, and is not provided with a circuit, so that the use of subsequent plastic packaging materials can be reduced by removing the non-functional area 103 before plastic packaging, and the cost is reduced.
S202: the carrier tray 20 is provided with a molding layer 16 on the side where the wafer 10 is disposed, and the molding layer 16 covers the front surface 104 of the wafer 10, the grooves 106, the first rewiring layer 12 and the metal posts 14.
Specifically, as shown in fig. 5b, fig. 5b is a schematic structural diagram of an embodiment corresponding to step S202 in fig. 4. In this embodiment, the molding layer 16 may further cover the side surface of the wafer 10, which is not limited in this application.
S203: the boat 20 is removed.
Specifically, as shown in fig. 3c, the carrier tray 20 is removed, and the carrier tray 20 is attached to the back surface 108 of the wafer 10 by a double-sided adhesive tape, so that the carrier tray 20 can be removed by peeling the double-sided adhesive tape.
Further, referring to fig. 6, fig. 6 is a schematic flow chart of an embodiment of the fan-out packaging method after step S203 in fig. 4, where the fan-out packaging method provided in the present application further includes:
s301: the molding layer 16 on the front side 104 of the wafer 10 is ground so that the metal posts 14 are exposed from the molding layer 16.
Specifically, as shown in fig. 7a, fig. 7a is a schematic structural diagram of an embodiment corresponding to step S301 in fig. 6. Through this step S301, the metal posts 14 are flush with the molding layer 16.
S302: a second rewiring layer 11 is formed on the front surface 104 of the wafer 10, and the second rewiring layer 11 is electrically connected to the metal posts 14.
Specifically, as shown in fig. 7b, fig. 7b is a schematic structural diagram of an embodiment corresponding to step S302 in fig. 6. The above process of forming the second rewiring layer 11 may be: forming a second passivation layer 110 on the molding layer 16, wherein a second through hole (not labeled) is formed in a position of the second passivation layer 110 corresponding to the metal pillar 14; forming a second seed layer 112 on a side of the second passivation layer 110 away from the molding layer 16, where the material of the second seed layer 112 may be at least one of aluminum, copper, gold, and silver, and the process for forming the second seed layer 112 may be a sputtering process or a physical vapor deposition process; forming a second mask layer (not shown) on the surface of the second seed layer 112, and forming a second opening (not shown) at a position of the second mask layer corresponding to the metal pillar 14, wherein the second mask layer is made of at least one of photoresist, silicon oxide, silicon nitride, and amorphous carbon; forming a conductive block 114 in the second opening; the second mask layer is removed and the second seed layer 112 is removed except for the conductive bumps 114. The finally formed second re-wiring layer 11 includes a second passivation layer 110, conductive bumps 114, and a second seed layer 112 underlying the conductive bumps 114.
S104: the wafer 10 is cut along the grooves 106 to obtain single packages, each package contains a single chip 100, the molding layer 16 covers the surface of the chip 100 provided with the bonding pad 1000, and at least part of the side surface of the chip 100 is exposed from the molding layer 16.
In an embodiment, please refer to fig. 8, fig. 8 is a flowchart illustrating an embodiment of the fan-out packaging method before step S104 in fig. 1, where before step S104, for example, between step S103 and step S104, the fan-out packaging method further includes:
s401: the back surface 108 of the wafer 10 is polished so that the grooves 106 do not penetrate the polished wafer 10.
Specifically, referring to fig. 9a, fig. 9a is a schematic structural diagram of an embodiment corresponding to step S401 in fig. 8.
S402: the adhesive film 18 is attached to the back surface 108 of the ground wafer 10.
Specifically, as shown in fig. 9b, fig. 9b is a schematic structural diagram of an embodiment corresponding to step S402 in fig. 8. The adhesive film 18 is disposed in a manner that protects the back side 108 of the wafer 10.
Further, the step S104 specifically includes: the wafer 10 is cut along the central axis L of the groove 106 to obtain a single package 22, a step portion 1008 is formed on the side surface 1006 of the single chip 100 included in the single package 22, and the plastic package layer 16 covers the step portion 1008 but does not cover the side surface 1006 except the step portion 1008. Specifically, please refer to fig. 9b and fig. 10, wherein fig. 10 is a schematic structural diagram of an embodiment of the fan-out package of the present application.
In a preferred embodiment, the specific process of the fan-out packaging method includes: A. and providing a wafer, and forming a first rewiring layer and metal columns on the front surface of the wafer, wherein the metal columns are electrically connected with bonding pads on the front surface of the wafer through the first rewiring layer. B. And grinding the back surface of the wafer, and cutting along the cutting grooves on the wafer to form a plurality of grooves which do not penetrate through the wafer. C. And cutting to remove the non-functional area on the periphery of the wafer. D. The back side of the wafer is attached to a carrier plate. E. The carrier disk is sealed by a molding compound and is press-molded to form a molding layer that covers the wafer and the metal posts on the front side of the wafer. F. And (4) removing the carrier disc. G. And grinding the plastic packaging layer on the front surface of the wafer to enable the metal columns to be exposed from the plastic packaging layer. H. And forming a second rewiring layer on the surface of the plastic packaging layer, wherein the second rewiring layer is electrically connected with the metal column. I. And grinding the back surface of the wafer, wherein the groove does not penetrate through the ground wafer. J. And adhering a glue film to the back of the wafer. K. And cutting the wafer along the central axis of the groove to obtain a plurality of single packages.
The fan-out package device and the fan-out package provided herein that can be sold separately are further described from a structural point of view.
Referring again to fig. 9b, the fan-out package device provided by the present application includes a wafer 10 and a molding layer 16. The wafer 10 is provided with a plurality of chips 100 arranged in a matrix, a groove 106 not penetrating the wafer 10 is provided between adjacent chips 100, and the bonding pad 1000 of the chip 100 is located on the front surface 104 of the wafer 10. The molding layer 16 covers the front surface 104 of the wafer 10 and the recesses 106. The groove 106 is formed by cutting along the scribe line from the front side 104 of the wafer 10, that is, the position of the groove 106 corresponds to the position of the scribe line on the original incoming wafer 10, and the depth of the groove 106 is greater than the depth of the scribe line. The depth of the specific recess 106 is determined according to the total height of the circuit designed in the chip 100, and generally, the depth of the recess 106 is equal to or greater than the total height of the circuit designed in the chip 100, for example, the depth of the recess 106 exceeds the thickness of the bonding pad 1000.
In one embodiment, the vertical cross-section of the grooves 106 is rectangular in the direction from the front side 104 to the back side 108 of the wafer 10. Of course, in other embodiments, the vertical cross-section of the groove 106 may also be tapered, trapezoidal, etc.
In yet another embodiment, with continued reference to fig. 9b, the fan-out package device provided herein further includes an adhesive film 18 disposed on the back side 108 of the wafer 10 for protecting the wafer 10.
In yet another embodiment, with continued reference to fig. 9b, the fan-out package device provided herein further includes a first redistribution layer 12 and metal studs 14. Specifically, the first redistribution layer 12 is located on the front side 104 of the wafer 10 and electrically connected to the pads 1000; the metal pillar 14 is located on the side of the first redistribution layer 12 away from the wafer 10, the metal pillar 14 is electrically connected to the first redistribution layer 12, and the metal pillar 14 is flush with the molding layer 16. In this embodiment, the first redistribution layer 12 may include a first passivation layer and a first seed layer, the first passivation layer may be located on the front surface 104 of the wafer 10, and a first through hole is disposed at a position corresponding to the pad 1000, the first seed layer is correspondingly disposed at the first through hole, and the metal pillar 14 is correspondingly disposed on the first seed layer.
In yet another embodiment, referring to fig. 9b again, the fan-out package device provided by the present application further includes a second redistribution layer 11 located on a side of the molding compound layer 16 away from the wafer 10, and the second redistribution layer 11 is electrically connected to the portion of the metal pillar 14 exposed from the molding compound layer 16. Specifically, the second re-wiring layer 11 may include a second passivation layer 110, a second seed layer 112, and a conductive bump 114. The second passivation layer 110 may be located on a side of the molding compound layer 16 away from the wafer 10, and a second through hole is disposed at a position corresponding to the metal pillar 14; the second seed layer 112 covers the second via hole, and the conductive bumps 114 are correspondingly disposed on the second seed layer 112.
Referring to fig. 10 again, fig. 10 is a schematic structural diagram of an embodiment of the fan-out package of the present application. The fan-out package provided in fig. 10 can be formed by cutting the wafer 10 provided with the molding layer 16 in fig. 9b along the grooves 106 not penetrating the wafer 10, and the fan-out package 22 includes the chips 100 and the molding layer 16. The chip 100 comprises a functional surface 1002 and a non-functional surface 1004 which are oppositely arranged, and a bonding pad 1000 is arranged on the functional surface 1002; the molding layer 16 covers the functional surface 1002 of the chip 100, and at least a portion of the side surface 1006 of the chip 100 is exposed from the molding layer 16.
In one embodiment, at least a portion of the edge of the functional surface 1002 of the chip 100 has a recess 1001 in the direction from the non-functional surface 1004 to the functional surface 1002, and the molding layer 16 covers the recess 1001 but does not cover the side surfaces 1006 outside the recess 1001. Preferably, the vertical cross-section of the recess 1001 in the direction from the functional side 1002 to the non-functional side 1004 is rectangular.
In yet another embodiment, the adhesive film 18 is disposed on the non-functional surface 1004 of the chip 100, and the size of the adhesive film 18 is equal to or larger than the size of the non-functional surface 1004 of the chip 100. This design may allow the non-functional side 1004 of the chip 100 to be protected to reduce damage to the chip 100.
Further, the fan-out package 22 provided by the present application further includes a first redistribution layer 12 and a metal pillar 14. The first redistribution layer 12 is located on the functional surface 1002 of the chip 10 and electrically connected to the pad 1000. The metal pillar 14 is located on the side of the first redistribution layer 12 away from the chip 10, the metal pillar 14 is electrically connected to the first redistribution layer 12, and the metal pillar 14 is flush with the molding layer 16. In this embodiment, the first redistribution layer 12 may include a first passivation layer and a first seed layer, the first passivation layer may be located on the functional surface 1002 of the chip 100, and a first through hole is disposed at a position corresponding to the pad 1000, the first seed layer is correspondingly disposed at the first through hole, and the metal pillar 14 is correspondingly disposed on the first seed layer.
Further, the fan-out package 22 provided by the present application further includes a second redistribution layer 11 located on the side of the molding compound layer 16 away from the chip 100, and the second redistribution layer 11 is electrically connected to the metal pillar 14. Specifically, the second re-wiring layer 11 may include a second passivation layer 110, a second seed layer 112, and a conductive bump 114. The second passivation layer 110 may be located on a side of the molding compound layer 16 away from the wafer 10, and a second through hole is disposed at a position corresponding to the metal pillar 14; the second seed layer 112 covers the second via hole, and the conductive bumps 114 are correspondingly disposed on the second seed layer 112.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (18)
1. A fan-out packaging method, comprising:
providing a wafer, wherein the wafer is provided with a plurality of chips arranged in a matrix, scribing grooves are formed among the chips, the wafer comprises a front surface and a back surface, and bonding pads of the chips are positioned on the front surface;
cutting along the scribing grooves from the front surface of the wafer to form a plurality of grooves which do not penetrate through the wafer;
forming a plastic packaging layer in the front surface of the wafer and the groove;
follow the recess is right the disc is cut to obtain single packaging body, include singly in the single packaging body the chip, the plastic envelope covers the chip is provided with the surface of pad just at least partial side of chip is followed expose in the plastic envelope layer.
2. The fan-out packaging method of claim 1, wherein before the dicing the wafer along the grooves to obtain the individual packages, the fan-out packaging method further comprises:
grinding the back surface of the wafer, wherein the groove does not penetrate through the ground wafer;
and adhering an adhesive film to the back surface of the ground wafer.
3. The fan-out packaging method of claim 1 or 2,
in the direction from the front face to the back face, the vertical section of the groove is rectangular.
4. The fan-out packaging method of claim 3, wherein the cutting the wafer along the grooves to obtain single packages comprises:
and cutting the wafer along the central axis of the groove to obtain a single package body, wherein step parts are formed on the side surfaces of the single chips contained in the single package body, and the plastic package layer covers the step parts but does not cover the side surfaces except the step parts.
5. The fan-out packaging method of claim 1, wherein prior to the cutting along the scribe line from the front side of the wafer, the fan-out packaging method further comprises:
forming a first rewiring layer on the front surface of the wafer, wherein the first rewiring layer is electrically connected with the bonding pad on the front surface;
and forming metal columns on the side, away from the wafer, of the first rewiring layer, wherein the metal columns are electrically connected with the first rewiring layer.
6. The fan-out packaging method of claim 5, wherein the forming of the molding layer in the front side of the wafer and the groove comprises:
attaching the back side of the wafer to a carrier disc;
forming the plastic packaging layer on one side of the carrying disc, which is provided with the wafer, wherein the plastic packaging layer covers the front surface of the wafer, the groove, the first rewiring layer and the metal column;
and removing the carrying disc.
7. The fan-out packaging method of claim 6, wherein after the removing the carrier tray, the fan-out packaging method further comprises:
grinding the plastic packaging layer on one side of the front surface of the wafer to enable the metal columns to be exposed out of the plastic packaging layer;
and forming a second rewiring layer on the front surface of the wafer, wherein the second rewiring layer is electrically connected with the metal column.
8. A fan-out package device, comprising:
the chip packaging structure comprises a wafer, a plurality of chips arranged in a matrix, a groove which is not communicated with the wafer and is arranged between every two adjacent chips, a bonding pad of each chip is positioned on the front surface of the wafer, and the groove is formed by cutting the front surface of the wafer along a scribing groove;
and the plastic packaging layer covers the front surface of the wafer and the groove.
9. The fan-out package device of claim 8,
in the direction from the front face to the back face, the vertical section of the groove is rectangular.
10. The fan-out package device of claim 8, further comprising:
and the adhesive film is arranged on the back surface of the wafer.
11. The fan-out package device of claim 8, further comprising:
the first rewiring layer is positioned on the front surface of the wafer and is electrically connected with the bonding pad;
and the metal column is positioned on one side of the first rewiring layer, which is far away from the wafer, is electrically connected with the first rewiring layer and is flush with the plastic packaging layer.
12. The fan-out package device of claim 11, further comprising:
and the second rewiring layer is positioned on one side of the plastic packaging layer, which is far away from the wafer, and is electrically connected with the metal column.
13. The utility model provides a fan-out type packaging body which characterized in that, fan-out type packaging body is followed by the disk that is provided with the plastic envelope and is not link up the recess cutting of disk forms, fan-out type packaging body includes:
the chip comprises a functional surface and a non-functional surface which are oppositely arranged, and a bonding pad is arranged on the functional surface;
and the plastic packaging layer covers the functional surface of the chip, and at least part of the side surface of the chip is exposed out of the plastic packaging layer.
14. The fan-out package of claim 13,
at least part of the edge of the functional surface of the chip is provided with a recess, and the plastic packaging layer covers the recess but does not cover the side surface except the recess.
15. The fan-out package of claim 13,
the vertical section of the recess is rectangular in the direction from the functional surface to the non-functional surface.
16. The fan-out package of claim 13,
and an adhesive film is arranged on the non-functional surface of the chip, and the size of the adhesive film is larger than or equal to that of the non-functional surface of the chip.
17. The fan-out package of claim 13, wherein the fan-out package further comprises:
a first rewiring layer located on the functional surface of the chip and electrically connected to the bonding pad;
and the metal column is positioned on one side of the first rewiring layer, which is far away from the chip, is electrically connected with the first rewiring layer and is level to the plastic packaging layer.
18. The fan-out package of claim 17, wherein the fan-out package further comprises:
and the second rewiring layer is positioned on one side of the plastic packaging layer, which is far away from the chip, and is electrically connected with the metal column.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010121668.7A CN111312600A (en) | 2020-02-26 | 2020-02-26 | Fan-out type packaging method, fan-out type packaging device and fan-out type packaging body |
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| CN202010121668.7A CN111312600A (en) | 2020-02-26 | 2020-02-26 | Fan-out type packaging method, fan-out type packaging device and fan-out type packaging body |
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