CN112216661A - Chip packaging structure and packaging method thereof - Google Patents

Chip packaging structure and packaging method thereof Download PDF

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Publication number
CN112216661A
CN112216661A CN202011326007.4A CN202011326007A CN112216661A CN 112216661 A CN112216661 A CN 112216661A CN 202011326007 A CN202011326007 A CN 202011326007A CN 112216661 A CN112216661 A CN 112216661A
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China
Prior art keywords
layer
metal
chip
plastic package
rewiring
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CN202011326007.4A
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Chinese (zh)
Inventor
徐虹
陈栋
金豆
徐霞
陈锦辉
郑芳
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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Priority to CN202011326007.4A priority Critical patent/CN112216661A/en
Publication of CN112216661A publication Critical patent/CN112216661A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a chip packaging structure and a chip packaging method, and belongs to the technical field of semiconductor packaging. Be provided with chip electrode (113), passivation layer I (210), insulating layer I (310) on chip unit body (10) of its first plastic-sealed body, set up metal connecting piece I in insulating layer I opening (311), plastic-sealed material I (510) carry out the plastic envelope with metal connecting piece I, plastic-sealed material II (610) cladding first plastic-sealed body and metal level (710) of rewiring above it form the second plastic-sealed body, set up passivation layer II (810) and metal connecting piece II (900) in the top of the second plastic-sealed body. The invention can effectively protect the front surface of the chip and improve the reliability of the product.

Description

Chip packaging structure and packaging method thereof
Technical Field
The invention relates to a chip packaging structure and a chip packaging method, and belongs to the technical field of semiconductor chip packaging.
Background
A conventional fan-out package product is shown in fig. 1, and includes a chip unit body 100 having an active surface, where the active surface of the chip unit body 100 is provided with a chip electrode 101, the active surface of the chip unit body 100 and an upper surface of the chip electrode 101 are provided with a protection layer 200, the protection layer 200 is provided with a protection layer opening above the chip electrode 101, a metal bump 300 is disposed in the protection layer opening, and the metal bump 300 is connected to the chip electrode 101 through the protection layer opening; a back surface protection layer 600 is disposed on the back surface of the chip unit body 100. The protection of the front side of the existing chip packaging product is weaker, and the problem of chip function failure easily occurs when the stress on the front side of the chip is larger.
Disclosure of Invention
The invention aims to overcome the defects of the prior packaging technology and provides a chip packaging structure with a protected chip front surface and a packaging method thereof.
The purpose of the invention is realized as follows:
the invention provides a chip packaging structure, which comprises a first plastic packaging body, a plastic packaging material II, a rewiring metal layer, a passivation layer II and a metal connecting piece II,
the first plastic package body comprises a chip unit body with an active surface and a plastic package material I, wherein a chip electrode is arranged on the active surface of the chip unit body, a passivation layer I and a passivation layer I opening are arranged on the active surface of the chip unit body and the upper surface of the chip electrode, an insulating layer I and an insulating layer I opening are arranged in the passivation layer I opening, the insulating layer I opening exposes the upper surface of the chip electrode, a metal connecting piece I is arranged in the insulating layer I opening, the metal connecting piece I is connected with the chip electrode through the insulating layer I opening, the plastic package material I carries out plastic package on the metal connecting piece I, and the upper surface of the plastic package material I is flush with the upper surface of the metal connecting piece I;
the rewiring metal layer is arranged above the first plastic package body and comprises a plurality of metal layers and insulating filling layers, the upper metal layers and the lower metal layers are connected selectively, the insulating filling layers are arranged between the metal layers, the lowest initial layer of the rewiring metal layer is provided with a lower layer bonding pad, the uppermost termination layer of the rewiring metal layer is provided with an upper layer bonding pad, the lower layer bonding pad and the upper layer bonding pad are both exposed out of the insulating filling layers, and the lower layer bonding pad is connected with the upper surface of a metal connecting piece I of the first plastic package body;
the plastic package material II covers the periphery and the back of the first plastic package body and the periphery of the rewiring metal layer to form a second plastic package body, and the upper surface of the second plastic package body is flush with the upper surface of the rewiring metal layer;
a passivation layer II and a passivation layer II opening are arranged above the second plastic package body, and the upper layer bonding pad of the rewiring metal layer is exposed out of the passivation layer II opening;
and a metal connecting piece II is arranged above the passivation layer II and is connected with the upper-layer bonding pad of the rewiring metal layer.
Optionally, the metal connecting piece i is sequentially provided with an adhesion barrier layer, a metal seed layer i and a metal bump from bottom to top, wherein the adhesion barrier layer is a composite layer formed by one or two layers of materials.
Optionally, the cross-sectional shape of the metal bump includes, but is not limited to, rectangular, circular, or oval.
Optionally, the metal seed layer i and the metal bump are of an integral structure.
Optionally, the metal connector ii sequentially includes, from bottom to top, an adhesion layer, a metal seed layer ii, a metal pillar, and a solder ball.
Optionally, the metal seed layer ii and the metal pillar are of an integral structure, and the cross-sectional shape of the metal pillar includes, but is not limited to, a rectangle, a circle, or an ellipse.
The invention also provides a packaging method of the chip packaging structure, which comprises the following processing steps:
taking an integrated circuit wafer, wherein a chip electrode and a passivation layer I are arranged on the upper surface of the integrated circuit wafer, the chip electrode realizes electrical communication in the integrated circuit wafer and partially exposes an opening of the passivation layer I to form an input/output end of the chip electrode;
step two, an insulating layer I, an opening of the insulating layer I and scribing channels are arranged on the passivation layer I through a photoetching method, the opening of the insulating layer I exposes the input/output end of the chip electrode, the scribing channels are transversely and longitudinally vertically interwoven, and the integrated circuit wafer is pre-divided into a plurality of chip unit bodies which are arranged in an array manner;
thirdly, an adhesion barrier layer is arranged in the opening of the insulating layer I by a sputtering method; sequentially arranging a metal seed layer I and a metal bump on the adhesion barrier layer by sputtering, photoetching, electroplating, photoresist removing and corrosion methods;
step four, performing primary plastic package on the adhesion barrier layer, the metal seed layer I and the metal bump by using a plastic package material I above the insulating layer I to form a first plastic package body;
removing the redundant plastic package material I on the surface of the wafer in a grinding mode, exposing the upper surface of the metal bump and forming an input/output end of the metal column;
step six, arranging a rewiring metal layer above the first plastic package body through a metal rewiring process, wherein the rewiring metal layer comprises a plurality of metal layers and insulating filling layers, the upper metal layer and the lower metal layer are selectively connected, the insulating filling layers are arranged on the metal layers and play an insulating protection role, the lowest initial layer of the rewiring metal layer is provided with a lower bonding pad, the uppermost termination layer of the rewiring metal layer is provided with an upper bonding pad, the lower bonding pad and the upper bonding pad are exposed out of the insulating layer, and the lower bonding pad is connected with the upper surface of a metal connecting piece I of the first plastic package body;
step seven, thinning the back of the wafer which is packaged and cutting the wafer into a plurality of chip monomers I with the front protected;
step eight, inversely arranging the chip monomers I on a slide glass adhered with a temporary bonding film according to a certain sequence by a bonding method;
step nine, carrying out secondary plastic package on the chip monomer I on the slide glass by using a plastic package material II to form a second plastic package body;
step ten, removing the carrier and the temporary bonding film by a bonding removing method, and exposing an upper bonding pad arranged on the uppermost termination layer of the rewiring metal layer of the chip monomer I to complete wafer reconstruction;
step eleven, a passivation layer II and a passivation layer II opening are arranged above the second plastic package body through a photoetching method, and the upper-layer bonding pad of the rewiring metal layer is exposed out of the passivation layer II opening;
step twelve, an adhesion layer is arranged in the opening of the passivation layer II by a sputtering method; sequentially performing sputtering, photoetching, electroplating, photoresist removing and corrosion on the adhesive layer, sequentially arranging a metal connecting piece II on the adhesive layer, sequentially arranging a metal seed layer II, a metal column and a solder ball on the metal connecting piece II from bottom to top,
and thirteen, cutting the plastic package body into a plurality of chip packaging monomers by a scribing method.
Further, in the third step, the metal bump is formed by an electroless plating method.
Further, in the seventh step, the bonding method is to coat or press the temporary bonding film on the surface of the carrier, and then bond the temporary bonding film and the front side of the first plastic package body together under the action of pressure, temperature and vacuum.
Further, the fourth step to the fifth step further comprise the following processes: in the fourth step, for a chip monomer I with a contraposition mark in a wafer, respectively arranging a contraposition mark protection block at the original contraposition mark position on the front surface of the chip monomer I, and then carrying out primary plastic package on the contraposition mark protection block, the adhesion barrier layer, the metal seed layer I and the metal bump by using a plastic package material I to form a first plastic package body; in the fifth step, when the grinding process is carried out to remove the redundant plastic package material I on the surface of the wafer, the alignment mark protection block is exposed while the upper surface of the metal bump is exposed.
Furthermore, in the sixth step, when the rewiring metal layer is arranged on the chip unit I with the alignment mark protection block, the alignment mark protection block above the original alignment mark can be adopted to perform accurate alignment.
Advantageous effects
1. Firstly, carrying out primary plastic package after finishing a metal bump on the front surface of a raw material wafer to form a first plastic package body, and exposing the upper surface of the metal bump to form an electrical connection surface; after the front surface plastic package is finished, arranging a rewiring metal layer, and then carrying out plastic package on the periphery and the back surface of the chip and the periphery of the rewiring metal layer to form a second plastic package body, and finishing the reconstruction of the wafer after cutting; through twice plastic packaging, a buffering effect is formed on the surface of the chip, the front surface of the chip can be effectively protected, the mechanical strength and rigidity of the front surface of the chip are improved, the damage to the surface of the chip caused by the stress of the soldering tin balls is reduced, the problem of packaging finished products of chip fragments is solved, and the reliability of the product is improved;
2. because the front surface and the back surface of the chip are both provided with the plastic package materials (EMC), the stress of the front surface and the back surface of the chip is mutually offset, the warping problem of a product is favorably improved, the subsequent metal rewiring process, the ball mounting process and the like are favorably carried out, and the process difficulty is reduced;
3. according to the invention, the adhesion barrier layer is arranged, so that the diffusion of metal atoms such as Cu and the like is effectively prevented, and the functional failure of the chip caused by the diffusion of the metal atoms is effectively avoided;
4. the process is completed on the incoming material wafer 100 with good coplanarity, so that the uniformity of exposed metal is improved, and the yield is improved;
5. in the process of the invention, the alignment mark protection block 150 is arranged, so that the plastic packaging material is prevented from shielding the original alignment mark 120, the alignment precision of the photoetching process in the metal rewiring process is improved, and the photoetching offset problem caused by wafer reconstruction is solved.
Drawings
FIG. 1 is a diagram of a conventional chip package structure;
FIG. 2 is a schematic cross-sectional view illustrating a chip package structure according to the present invention;
fig. 3A to 3R are schematic flow charts illustrating a method for packaging a chip package structure according to the present invention;
in the figure:
chip unit body 10
Chip electrode 113
Passivation layer I210
Passivation layer I opening 213
Insulating layer I310
Insulating layer I opening 311
Adhesion barrier 410
Metal bump 430
Plastic packaging material I510
Plastic packaging material II 610
Rewiring metal layer 710
Lower bonding pad 713
Upper layer pad 715
Passivation layer II 810
Passivation layer II opening 813
Metal connecting piece II 900
Adhesive layer 910
Metal pillar 920
Solder balls 950;
wafer 100
Original alignment mark 120
Alignment mark protection block 150
Slide L1
The temporary bonding film L2.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings.
Examples
The invention relates to a chip packaging structure which comprises a first plastic packaging body, a plastic packaging material II 610, a rewiring metal layer 710, a passivation layer II 810 and a metal connecting piece II 900.
The first plastic package body comprises a chip unit body 10 with an active surface and a plastic package material I510, wherein the thickness of the chip unit body 10 is usually 25-150 micrometers. The active surface of chip unit body 10 is provided with chip electrode 113, the active surface of chip unit body 10 and the upper surface of chip electrode 113 are provided with I210 of passivation layer and I opening 213 of passivation layer, set up I310 of insulating layer and I opening 311 of insulating layer in I opening 213 of passivation layer, I opening 311 of insulating layer exposes the upper surface of chip electrode 113, set up metal connecting piece I in I opening 311 of insulating layer, metal connecting piece I is connected with chip electrode 113 through I opening 311 of insulating layer. The metal connecting piece I is sequentially provided with an adhesion barrier layer 410, a metal seed layer I and a metal bump 430 from bottom to top. The material of the metal seed layer I is Cu, Ni and the like, and the thickness of the metal seed layer I is 0.01-1 micron. The metal material of the metal bump 430 includes, but is not limited to, Ti, Cu, Ni, Sn, and Au, and the cross-sectional shape thereof includes, but is not limited to, a rectangle, a circle, or an ellipse. Preferably, the metal seed layer i and the metal bump 430 are of an integral structure. The adhesion barrier layer 410 is made of Cr, Ti, TiW, V, NiV, etc., and can be a composite layer formed by one or two layers of materials, and the thickness of the adhesion barrier layer 410 is 0.1-3 microns. The adhesion barrier layer 410 functions to block metal atoms or other metal particles of the metal seed layer i and the metal bumps 430 from diffusing into the chip unit body 10, in addition to functioning to bond with the chip electrodes 113.
The plastic packaging material I510 is used for plastically packaging the metal connecting piece I, and the upper surface of the metal connecting piece I is flush with the upper surface of the metal connecting piece I; the plastic packaging material I510 is made of thermosetting polymers such as epoxy resin, phenolic resin, silica gel, amino and unsaturated resin; in order to improve the heat dissipation capability, the molding compound i 510 may be a composite material containing powder or fibers of metal, ceramic, silicon oxide, graphene, and the like.
The rewiring metal layer 710 is arranged above the first plastic package body, the rewiring metal layer 710 comprises a plurality of metal layers and insulating filling layers, the upper metal layers and the lower metal layers are selectively connected, the insulating filling layers are arranged between the metal layers, the lowest initial layer of the rewiring metal layer 710 is provided with a lower bonding pad 713, the uppermost termination layer of the rewiring metal layer 710 is provided with an upper bonding pad 715, the lower bonding pad 713 and the upper bonding pad 715 are both exposed out of the insulating filling layers, and the lower bonding pad 713 is connected with the upper surface of the metal connecting piece I of the first plastic package body;
the plastic package material II 610 covers the periphery and the back of the first plastic package body and the periphery of the rewiring metal layer 710 to form a second plastic package body, and the upper surface of the second plastic package body is flush with the upper surface of the rewiring metal layer 710; the plastic package material II 610 is made of thermosetting polymers such as epoxy resin, phenolic resin, silica gel, amino and unsaturated resin; in order to improve the heat dissipation capability, the molding compound ii 610 may be a composite material containing powder or fibers of metal, ceramic, silicon oxide, graphene, and the like.
A passivation layer II 810 and a passivation layer II opening 813 are arranged above the second plastic package body, and the passivation layer II opening 813 exposes the upper layer bonding pad 715 of the rewiring metal layer 710;
and a metal connector II 900 is arranged above the passivation layer II 810, and the metal connector II 900 is connected with the upper-layer bonding pad 715 of the rewiring metal layer 710. The metal connecting piece II 900 sequentially comprises an adhesion layer 910, a metal seed layer II, metal columns 920 and solder balls 950 from bottom to top. The material of the metal seed layer II is Cu, Ni, etc., and the thickness of the metal seed layer II is 0.01-1 micron. Usually, the metal seed layer ii and the metal pillar 920 are an integral structure, and the height of the metal pillar 920 is usually 2 to 100 micrometers. The metal material of the metal pillar 920 is generally Cu, CuNi, CuNiAu, NiAu, etc., and the cross-sectional shape thereof includes, but is not limited to, a rectangle, a circle, or an ellipse. The material of the adhesion layer 910 is Cr, Ti, TiW, V, NiV, etc., and it can be a composite layer formed by one or two layers of materials, and the thickness of the adhesion layer 910 is 0.01-2 μm. The adhesive layer 910 may function in conjunction with the upper pad 715 of the re-wiring metal layer 710.
The invention relates to a packaging method of a chip packaging structure, which comprises the following process steps:
first, as shown in fig. 3A, an integrated circuit wafer 100 is provided, the upper surface of which is provided with a chip electrode 113 and a passivation layer i 210, the chip electrode 113 implements electrical communication in the integrated circuit wafer 100 and partially exposes an opening 213 of the passivation layer i, so as to form an input/output terminal of the chip electrode 113.
Step two, as shown in fig. 3B, an insulating layer i 310, an insulating layer i opening 311 and a scribe lane 313 are formed on the passivation layer i 210 by photolithography, the insulating layer i opening 311 exposes the input/output end of the chip electrode 113, and the scribe lane 313 is vertically interlaced in the horizontal and vertical directions, so as to pre-divide the integrated circuit wafer 100 into a plurality of chip unit bodies 10 arranged in an array.
Step three, as shown in fig. 3C, an adhesion barrier layer 410 is disposed in the opening 311 of the insulating layer i by a sputtering method; the adhesion barrier layer 410 is made of Cr, Ti, TiW, V, NiV, etc., and can be a composite layer formed by one or two layers of materials, and the thickness of the adhesion barrier layer 410 is 0.1-3 microns.
And sequentially performing sputtering, photoetching, electroplating, photoresist removing and corrosion methods, sequentially arranging a metal seed layer I and a metal bump 430 on the adhesion barrier layer 410, wherein the metal material of the metal bump 430 comprises but is not limited to elements of Ti, Cu, Ni, Sn and Au, the metal bump 430 can be formed by a chemical plating method, and the cross section of the metal bump 430 is designed according to actual needs, and comprises but is not limited to a rectangle, a circle or an ellipse. The material of the metal seed layer I is Cu, Ni and the like, and the thickness of the metal seed layer I is 0.01-1 micron. Generally, the metal seed layer i and the metal bump 430 are of an integral structure; the adhesion barrier layer 410, in addition to functioning in combination with the chip electrodes 113, also functions to block the diffusion of metal atoms or other metal particles of the metal seed layer i and the metal bumps 430 into the wafer 100.
Step four, as shown in fig. 3D, performing primary plastic package on the adhesion barrier layer 410, the metal seed layer i and the metal bump 430 by using a plastic package material i 510 above the insulating layer i 310 to form a first plastic package body, wherein the front surface of the wafer 100 is protected by the first plastic package body; the plastic packaging material I510 is made of thermosetting polymers such as epoxy resin, phenolic resin, silica gel, amino and unsaturated resin; in order to improve the heat dissipation capability, the molding compound i 510 may be a composite material containing powder or fibers of metal, ceramic, silicon oxide, graphene, and the like.
Step five, as shown in fig. 3E, the excess molding compound i 510 on the surface of the wafer 100 is removed by grinding, so as to expose the upper surface of the metal bump 430, and form the input/output terminal 431 of the metal pillar.
Step six, as shown in fig. 3F, a rewiring metal layer 710 is arranged above the first plastic package body through a metal rewiring process, the rewiring metal layer 710 includes a plurality of metal layers and an insulating filling layer, the upper and lower adjacent metal layers are selectively connected, the insulating filling layer is arranged on the metal layers and plays an insulating protection role, a lower pad 713 is arranged on the lowest initial layer of the rewiring metal layer 710, an upper pad 715 is arranged on the uppermost termination layer of the rewiring metal layer, the lower pad 713 and the upper pad 715 are exposed out of the insulating layer, and the lower pad 713 is connected with the upper surface of the metal connector i of the first plastic package body.
Seventhly, as shown in fig. 3G, thinning the back surface of the wafer 100 subjected to the packaging and cutting the wafer into a plurality of chip monomers i with front surfaces protected, wherein the thickness of the chip unit body 10 formed after thinning is usually 25 to 150 micrometers; the thinning method can be mechanical thinning or chemical mechanical thinning.
Step eight, as shown in fig. 3H, the chip monomers i are reversely arranged on the carrier L1 with the temporary bonding film L2 attached thereon according to a certain sequence, preferably, the material of the temporary bonding film L2 is a thermoplastic liquid material or a film material sensitive to UV light. The bonding method is generally that a temporary bonding film L2 is coated or pressed on the surface of the carrier L1, and then the temporary bonding film and the front side of the chip monomer I are bonded together under the action of pressure, temperature and vacuum.
Step nine, as shown in fig. 3I, performing secondary plastic package on the chip monomer I on a slide L1 by using a plastic package material ii 610 to form a second plastic package body; the plastic package material II 610 is made of thermosetting polymers such as epoxy resin, phenolic resin, silica gel, amino and unsaturated resin; in order to improve the heat dissipation capability, the molding compound ii 610 may be a composite material containing powder or fibers of metal, ceramic, silicon oxide, graphene, and the like.
Step ten, as shown in fig. 3J, removing the slide glass L1 and the temporary bonding film L2 by a de-bonding method, exposing an upper bonding pad 715 arranged on the uppermost termination layer of the rewiring metal layer 710 of the chip monomer i, and completing wafer reconstruction, wherein the wafer reconstruction process overcomes the problems of large warpage and large thickness fluctuation of a chip packaging structure completed in the prior art, so that the process difficulty is reduced, and the product yield is improved; the debonding method may be thermal debonding, chemical debonding, laser debonding, or UV debonding, among others.
Step eleven, as shown in fig. 3K, a passivation layer ii 810 and a passivation layer ii opening 813 are disposed above the second plastic package body by a photolithography method, and the passivation layer ii opening 813 exposes the upper layer pad 715 of the rewiring metal layer 710.
Step twelve, as shown in fig. 3L, an adhesion layer 910 is disposed in the passivation layer ii opening 813 by sputtering again; the material of the adhesion layer 910 is Cr, Ti, TiW, V, NiV, etc., and it can be a composite layer formed by one or two layers of materials, and the thickness of the adhesion layer 910 is 0.01-2 μm.
And sequentially performing sputtering, photoetching, electroplating, photoresist removing and corrosion on the adhesion layer 910, sequentially arranging a metal connecting piece II 900 on the adhesion layer 910, wherein the metal connecting piece II 900 sequentially comprises a metal seed layer II, metal columns 920 and solder balls 950 from bottom to top, the metal material of the metal columns 920 is usually Cu, CuNi, CuNiAu, NiAu and the like, and the metal columns 920 can also be formed by a chemical plating method. The cross-sectional shape of the metal posts 920 is designed according to actual needs, including but not limited to rectangular, circular or oval.
The material of the metal seed layer II is Cu, Ni, etc., and the thickness of the metal seed layer II is 0.01-1 micron. Usually, the metal seed layer ii and the metal pillar 920 are an integral structure, and the height of the metal pillar 920 is usually 2 to 100 micrometers. The adhesive layer 910 may function in conjunction with the upper pad 715 of the re-wiring metal layer 710.
Step thirteen, as shown in fig. 3M, the plastic package body is cut into a plurality of chip package monomers by a dicing method. Scribing can be performed with a blade containing diamond or ceramic particles, or optionally with a laser.
The invention relates to a packaging method of a chip packaging structure, which comprises the following steps in the fourth step to the sixth step: in the fourth step, the original alignment mark 120 disposed on the front surface of the wafer 100 is covered while the molding compound i 510 covers the front surface of the wafer 100, as shown in fig. 3N; therefore, before the front surface of the wafer 100 is coated, the alignment mark needs to be protected, through a dispensing process or a printing process, the alignment mark protection block 150 may be disposed at the original alignment mark 120 on the front surface of the wafer 100, the alignment mark protection block 150 may be made of transparent resin or metal, the shape of the alignment mark protection block is not limited, but the alignment mark protection block can be clearly distinguished visually, as shown in fig. 3O and 3P, the alignment mark protection block 150, the adhesion barrier layer 410, the metal seed layer i and the metal bump 430 are subjected to a first plastic package by using a plastic package material i 510 to form a first plastic package body, as shown in fig. 3Q, the alignment mark protection block 150 may be disposed before the metal bump 430 is disposed, or after the metal bump 430 is disposed; in the fifth step, when the grinding process is performed to remove the excess molding compound i 510 on the surface of the wafer 100, the alignment mark protection block 150 is exposed while the upper surface of the metal bump 430 is slowly exposed, as shown in fig. 3R, so as to reduce the difficulty of the alignment process when the redistribution metal layer 710 is disposed in the sixth step, and improve the alignment accuracy.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only illustrative of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. A chip packaging structure is characterized by comprising a first plastic packaging body, a plastic packaging material II (610), a rewiring metal layer (710), a passivation layer II (810) and a metal connecting piece II (900),
the first plastic package body comprises a chip unit body (10) with an active surface and a plastic package material I (510), the active surface of the chip unit body (10) is provided with a chip electrode (113), the active surface of the chip unit body (10) and the upper surface of the chip electrode (113) are provided with a passivation layer I (210) and a passivation layer I opening (213), an insulating layer I (310) and an insulating layer I opening (311) are arranged in the passivation layer I opening (213), the insulating layer I opening (311) exposes the upper surface of the chip electrode (113), a metal connecting piece I is arranged in the opening (311) of the insulating layer I, the metal connecting piece I is connected with the chip electrode (113) through the opening (311) of the insulating layer I, the plastic packaging material I (510) is used for plastically packaging the metal connecting piece I, and the upper surface of the plastic packaging material I is flush with the upper surface of the metal connecting piece I;
the rewiring metal layer (710) is arranged above the first plastic package body, the rewiring metal layer (710) comprises a plurality of metal layers and insulating filling layers, the upper metal layers and the lower metal layers are selectively connected, the insulating filling layers are arranged between the metal layers, the lowest initial layer of the rewiring metal layer (710) is provided with a lower bonding pad (713), the uppermost termination layer of the rewiring metal layer (710) is provided with an upper bonding pad (715), the lower bonding pad (713) and the upper bonding pad (715) are exposed out of the insulating filling layers, and the lower bonding pad (713) is connected with the upper surface of the metal connecting piece I of the first plastic package body;
the plastic package material II (610) covers the periphery and the back of the first plastic package body and the periphery of the rewiring metal layer (710) to form a second plastic package body, and the upper surface of the second plastic package body is flush with the upper surface of the rewiring metal layer (710);
a passivation layer II (810) and a passivation layer II opening (813) are arranged above the second plastic package body, and the passivation layer II opening (813) exposes an upper layer bonding pad (715) of the rewiring metal layer (710);
and a metal connecting piece II (900) is arranged above the passivation layer II (810), and the metal connecting piece II (900) is connected with an upper layer bonding pad (715) of the rewiring metal layer (710).
2. The package structure of claim 1, wherein the metal connecting member I is sequentially provided with an adhesion barrier layer (410), a metal seed layer I and a metal bump (430) from bottom to top, and the adhesion barrier layer (410) is a composite layer formed by one or two layers of materials.
3. The package structure of claim 2, wherein a cross-sectional shape of the metal bump (430) includes, but is not limited to, rectangular, circular, or oval.
4. The package structure of claim 2 or 3, wherein the metal seed layer I and the metal bump (430) are a unitary structure.
5. The package structure of claim 1, wherein the metal connection member II (900) comprises an adhesion layer (910), a metal seed layer II, a metal pillar (920) and a solder ball (950) in sequence from bottom to top.
6. The package structure of claim 5, wherein the metal seed layer II and the metal pillar (920) are a unitary structure, and a cross-sectional shape of the metal pillar (920) includes but is not limited to a rectangle, a circle, or an ellipse.
7. A packaging method of a chip packaging structure comprises the following processing steps:
taking an integrated circuit wafer (100), wherein the upper surface of the integrated circuit wafer is provided with a chip electrode (113) and a passivation layer I (210), the chip electrode (113) realizes electrical communication in the integrated circuit wafer (100) and partially exposes an opening (213) of the passivation layer I to form an input/output end of the chip electrode (113);
step two, arranging an insulating layer I (310), an insulating layer I opening (311) and scribing channels (313) on the passivation layer I (210) by a photoetching method, wherein the insulating layer I opening (311) exposes the input/output end of the chip electrode (113), and the scribing channels (313) are transversely and longitudinally vertically interwoven, so that the integrated circuit wafer (100) is pre-divided into a plurality of chip unit bodies (10) which are arranged in an array;
thirdly, an adhesion barrier layer (410) is arranged in the opening (311) of the insulating layer I by a sputtering method; sequentially arranging a metal seed layer I and a metal bump (430) on the adhesion barrier layer (410) by sputtering, photoetching, electroplating, photoresist removing and corrosion methods;
fourthly, performing primary plastic package on the adhesion barrier layer (410), the metal seed layer I and the metal bump (430) above the insulating layer I (310) by using a plastic package material I (510) to form a first plastic package body;
removing the redundant plastic packaging material I (510) on the surface of the wafer (100) in a grinding mode, exposing the upper surface of the metal bump (430), and forming an input/output end (431) of the metal column;
step six, arranging a rewiring metal layer (710) above the first plastic package body through a metal rewiring process, wherein the rewiring metal layer (710) comprises a plurality of metal layers and an insulating filling layer, the upper metal layer and the lower metal layer are selectively connected, the insulating filling layer is arranged on the metal layers and plays an insulating protection role, a lower bonding pad (713) is arranged on the lowest initial layer of the rewiring metal layer (710), an upper bonding pad (715) is arranged on the uppermost termination layer of the rewiring metal layer, the lower bonding pad (713) and the upper bonding pad (715) are exposed out of the insulating layer, and the lower bonding pad (713) is connected with the upper surface of a metal connecting piece I of the first plastic package body;
step seven, thinning the back of the wafer (100) which is packaged and cutting the wafer into a plurality of chip monomers (I) with the front protected;
step eight, inversely arranging the chip monomers (I) on a slide (L1) stuck with a temporary bonding film (L2) according to a certain sequence by a bonding method;
step nine, performing secondary plastic package on the chip monomer (I) on a slide glass (L1) by using a plastic package material II (610) to form a second plastic package body;
step ten, removing the carrier (L1) and the temporary bonding film (L2) by a bonding removing method, exposing an upper bonding pad (715) arranged on the uppermost termination layer of the rewiring metal layer (710) of the chip monomer (I), and completing wafer reconstruction;
step eleven, a passivation layer II (810) and a passivation layer II opening (813) are arranged above the second plastic package body through a photoetching method, and the upper layer bonding pad (715) of the rewiring metal layer (710) is exposed out of the passivation layer II opening (813);
step twelve, an adhesion layer (910) is arranged in the opening (813) of the passivation layer II by a sputtering method; sequentially carrying out sputtering, photoetching, electroplating, photoresist removing and corrosion on the adhesive layer (910), and sequentially arranging a metal connecting piece II (900) on the adhesive layer (910), wherein the metal connecting piece II (900) sequentially comprises a metal seed layer II, a metal column (920) and a soldering tin ball (950) from bottom to top;
and thirteen, cutting the plastic package body into a plurality of chip packaging monomers by a scribing method.
8. The method of claim 7, wherein in step three, the metal bumps (430) are formed by electroless plating.
9. The packaging method according to claim 8, wherein the steps four to five further comprise the following steps: in the fourth step, for the chip monomers (I) with the alignment marks in the wafer (100), the original alignment marks (120) on the front surfaces of the chip monomers (I) are respectively provided with alignment mark protection blocks (150), and then the alignment mark protection blocks (150), the adhesion barrier layer (410), the metal seed layer I and the metal bumps (430) are subjected to primary plastic package by using a plastic package material I (510) to form a first plastic package body; in step five, when a grinding process is performed to remove the excess molding compound i (510) on the surface of the wafer (100), the alignment mark protection block (150) is exposed while the upper surface of the metal bump (430) is exposed.
10. The packaging method according to claim 9, wherein in the sixth step, when the rewiring metal layer (710) is disposed on the chip unit I having the alignment mark protection block (150), the alignment mark protection block (150) above the original alignment mark (120) is used for precise alignment.
CN202011326007.4A 2020-11-24 2020-11-24 Chip packaging structure and packaging method thereof Pending CN112216661A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023273594A1 (en) * 2021-07-02 2023-01-05 颀中科技（苏州）有限公司 Metal bump structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023273594A1 (en) * 2021-07-02 2023-01-05 颀中科技（苏州）有限公司 Metal bump structure

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