TW201911477A - Semiconductor process and semiconductor structure - Google Patents

Semiconductor process and semiconductor structure Download PDF

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Publication number
TW201911477A
TW201911477A TW107117179A TW107117179A TW201911477A TW 201911477 A TW201911477 A TW 201911477A TW 107117179 A TW107117179 A TW 107117179A TW 107117179 A TW107117179 A TW 107117179A TW 201911477 A TW201911477 A TW 201911477A
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TW
Taiwan
Prior art keywords
semiconductor
semiconductor substrate
plastic package
protective film
wafer
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TW107117179A
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Chinese (zh)
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TWI713849B (en
Inventor
楊鵬
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大陸商矽力杰半導體技術(杭州)有限公司
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Publication of TW201911477A publication Critical patent/TW201911477A/en
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Publication of TWI713849B publication Critical patent/TWI713849B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding

Abstract

The invention provides a semiconductor process and a semiconductor structure. A semiconductor substrate is half cut in the front, then a protective membrane is arranged on the front of the semiconductor substrate, and then the semiconductor substrate is thinned in the back so as to separate each semiconductor unit structure, so that reduced cutting depth prevents a cutting knife from being overused, an active surface of the semiconductor substrate is protected from damage in the process of separating each semiconductor unit, and each semiconductor unit is prevented from deviating in separation. In addition, according to the semiconductor process provided in the invention, the front of the semiconductor substrate is protected by the protective membrane, then plastic packaging and cutting of a plastic packaging material are carried out, so that bad effect of plastic packaging on the front of the semiconductor substrate is prevented; and each of six surfaces of finally formed semiconductor structure has a protective layer, thereby preventing bad effect of external environment on the semiconductor structure, and improving the reliability of the semiconductor structure.

Description

半導體製程及半導體結構Semiconductor process and semiconductor structure

本發明設計半導體技術領域,尤其涉及一種半導體製程及半導體結構。The present invention relates to the field of designing semiconductor technologies, and in particular, to a semiconductor process and a semiconductor structure.

晶圓級封裝技術是以晶圓(wafer)為加工物件,在晶圓上同時對眾多晶片進行封裝,最後切割成單個可以直接貼裝到基板或印刷電路板上的器件的技術。晶圓級封裝由於加工效率高、製造成本低、且具有輕、薄、短、小等優點,而被廣泛應用於移動可攜式電子產品中。   圖1為採用現有的晶圓封裝技術形成的單個晶片封裝器件示意圖,其主要由裸晶片01、正面保護層02、電極03及背面保護層04構成,電極03由經正面保護層02的開口與裸晶片01正面的電極焊盤011電連接,以作為圖1所示的晶片封裝器件與外部電連接的外引腳。   由圖1可見,現有的晶圓級封裝製程形成的單個晶片封裝器件只有正面與背面設置了保護層,而其它四個側面均裸露在外,容易受到外力的影響,從而影響晶片封裝器件的可靠性。Wafer-level packaging technology is a technology in which wafers are used as processing objects to package multiple wafers on a wafer at the same time, and finally cut into a single device that can be directly mounted on a substrate or a printed circuit board. Wafer-level packaging is widely used in mobile and portable electronic products due to its high processing efficiency, low manufacturing cost, and its advantages of lightness, thinness, shortness, and smallness. FIG. 1 is a schematic diagram of a single chip package device formed by the existing wafer packaging technology, which is mainly composed of a bare wafer 01, a front protective layer 02, an electrode 03, and a back protective layer 04. The electrode 03 is formed through the opening of the front protective layer 02 and The electrode pad 011 on the front surface of the bare chip 01 is electrically connected to serve as an external pin for the chip package device shown in FIG. 1 to be electrically connected to the outside. It can be seen from FIG. 1 that the single wafer package device formed by the existing wafer-level packaging process has only a front surface and a back surface provided with a protective layer, and the other four sides are exposed, which is easily affected by external forces, thereby affecting the reliability of the wafer package device. .

有鑑於此,本發明提供了一種半導體製程及半導體結構,以實現對所述半導體結構的六面均進行保護,從而保證了半導體結構的可靠性。   一種半導體製程,其特徵在於,包括:   沿半導體基板正面的切割道進行預定深度的切割,   在所述半導體基板的正面貼一層保護膜,   對所述半導體基板的背面進行減薄處理,以將所述半導體基板中的多個半導體單元結構分離。   較佳地,所述的半導體製程還包括:   進行塑封製程,以形成包封各個所述半導體單元結構的塑封體,以及,   去除所述保護膜,以使得所述塑封體的第一表面裸露各個所述半導體單元結構的正面。   較佳地,所述的半導體製程還包括:   在所述塑封體的第一表面上形成圖案化的正面保護層,所述正面保護層裸露各個所述半導體單元結構上的電極焊盤,   形成與各個所述電極焊盤電連接的引腳,   沿各個所述半導體單元結構之間的塑封料切割所述塑封體,以分離各個所述半導體單元結構,各個所述半導體單元結構的側面均被塑封料包封。   較佳地,所述的半導體製程還包括:在切割所述塑封體之前,先由所述塑封體的第二表面處開始行減薄處理,以減小所述各個半導體單元結構的厚度,然後在所述半導體單元結構的背面形成背面保護層,所述塑封體的第二表面與所述第一表面相對。   較佳地,對所述半導體基板的背面進行研磨,以將所述半導體基板上的多個半導體單元分離。   較佳地,所述半導體基板正面為有源面,所述有源面上設置有電極焊盤。   較佳地,在注入所述塑封料後,透過加熱或照射紫外線的方式使得所述保護膜與所述半導體單元結構的正面之間的黏性失效,以去除所述保護膜。   較佳地,所述塑封製程包括:   在所述半導體結構單元的背面設置模具,然而在所述保護膜和模具之間注入塑封料,以形成所述塑封體。   較佳地,所述半導體基板為晶圓,所述半導體單元結構為所述晶圓上的晶片單元,所述半導體製程為晶圓級封裝製程。   一種根據上述任意一項所述半導體製程所製備的半導體結構。   由上可見,本發明提供的半導體製程,先由半導體基板的正面進行半切割後,再在其正面設置保護膜,然後在從半導體基板的背面進行減薄處理,來分離各個半導體單元結構,從而可以既能減小切割深度,以減少切割刀具的過渡使用,還能在分離各個半導體單元的過程中,避免半導體基板的有源面的損傷,以及防止各個半導體單元在分離過程中位置的偏移。此外,依據本發明提供的半導體製程,採用所述保護膜保護半導體基板的正面後,再進行塑封製程和塑封料的切割製程,避免了塑封製程對半導體基板正面的不良影響,且最終形成的半導體結構的六個表面均有保護層,可以防止外部環境對半導體結構的不利影響,提高了半導體結構的可靠性。In view of this, the present invention provides a semiconductor process and a semiconductor structure to protect all six sides of the semiconductor structure, thereby ensuring the reliability of the semiconductor structure. A semiconductor manufacturing process includes: 包括 cutting a predetermined depth along a cutting path on the front surface of a semiconductor substrate, 贴 pasting a protective film on the front surface of the semiconductor substrate, thinning the back surface of the semiconductor substrate, The plurality of semiconductor unit structures in the semiconductor substrate are separated. Preferably, the semiconductor manufacturing process further includes: (i) performing a plastic packaging process to form a plastic package encapsulating each of the semiconductor unit structures, and (ii) removing the protective film so that each of the first surfaces of the plastic packages is exposed. The front side of the semiconductor unit structure. Preferably, the semiconductor manufacturing process further includes: forming a patterned front surface protection layer on the first surface of the plastic package, the front surface protection layer exposing electrode pads on each of the semiconductor unit structures, and forming and The pins electrically connected to each of the electrode pads are cut along the molding compound between each of the semiconductor unit structures to separate each of the semiconductor unit structures, and the sides of each of the semiconductor unit structures are plastically sealed. Material encapsulation. Preferably, the semiconductor manufacturing process further includes: before cutting the plastic package, a thinning process is started at the second surface of the plastic package to reduce the thickness of each semiconductor unit structure, and then A back surface protective layer is formed on the back surface of the semiconductor unit structure, and the second surface of the plastic package is opposite to the first surface. Preferably, the back surface of the semiconductor substrate is polished to separate a plurality of semiconductor units on the semiconductor substrate. Preferably, the front surface of the semiconductor substrate is an active surface, and electrode pads are provided on the active surface. Preferably, after the injection molding material is injected, the adhesion between the protective film and the front surface of the semiconductor unit structure is invalidated by heating or irradiating ultraviolet rays to remove the protective film. Preferably, the plastic packaging process includes: 设置 Setting a mold on the back surface of the semiconductor structure unit, but injecting a molding compound between the protective film and the mold to form the plastic package. Preferably, the semiconductor substrate is a wafer, the semiconductor unit structure is a wafer unit on the wafer, and the semiconductor process is a wafer-level packaging process. (2) A semiconductor structure prepared according to any one of the semiconductor processes described above. It can be seen from the above that the semiconductor process provided by the present invention firstly performs a half cut from the front surface of the semiconductor substrate, then sets a protective film on the front surface, and then performs a thinning process from the rear surface of the semiconductor substrate to separate the individual semiconductor unit structures, thereby It can not only reduce the cutting depth to reduce the use of cutting tools, but also avoid the damage of the active surface of the semiconductor substrate during the separation of individual semiconductor units, and prevent the position shift of the individual semiconductor units during the separation process. . In addition, according to the semiconductor manufacturing process provided by the present invention, after the front surface of the semiconductor substrate is protected by the protective film, a plastic packaging process and a cutting process of the molding compound are performed, thereby avoiding the adverse effect of the plastic packaging process on the front surface of the semiconductor substrate, and finally forming the semiconductor The six surfaces of the structure are provided with protective layers, which can prevent the adverse influence of the external environment on the semiconductor structure and improve the reliability of the semiconductor structure.

以下將參照圖式更詳細地描述本發明。在各個圖式中,相同的組成部分採用類似的圖式標記來表示。為了清楚起見,圖式中的各個部分沒有按比例繪製。此外,可能未示出某些公知的部分。為了簡明起見,可以在一幅圖中描述經過數個步驟後獲得的結構。在下文中描述了本發明的許多特定的細節,例如每個組成部分的結構、材料、尺寸、處理製程和技術,以便更清楚地理解本發明。但正如本領域的技術人員能夠理解的那樣,可以不按照這些特定的細節來實現本發明。   圖2a-2j為依據本發明實施例的半導體製程的各個製程步驟的剖面結構示意圖。下面將結合圖2a-2j來具體闡述本發明所提供的半導體製程,本發明提供的半導體製程主要包括以下步驟。   步驟1:沿半導體基板正面的切割道進行預定深度的切割。   如圖2a所示,半導體基板1包括多個半導體單元結構11,半導體基板1正面的切割道12位於各個半導體單元結構11之間。其中,半導體基板1的正面為有源面,該有源面上設置有電極焊盤111,而半導體基板1的背面則為與其有源面相對的一面。   如圖2b所示,由半導體基板1的正面的切割道12所在的位置處開始進行切割製程,切割至預定深度時停止切割,以在切割道12處形成開口。其中,所述預定深度小於半導體基板1的厚度(半導體基板1的正面與背面之間的厚度)。即在完成步驟1的切割製程後,各個半導體單元11仍未分離。   步驟2:在半導體基板1的正面貼一層保護膜2。   如圖2c所示,保護膜2可以為熱失效膜或UV失效膜(紫外線失效膜),保護膜2貼在被進行預定深度切割後的半導體基板1的正面,其覆蓋各個半導體單元結構11的正面及切割道12處的開口,從而實現了對半導體基板1的有源面的保護,以防止後續製程對半導體基板1的有源面的不良影響。   步驟3:對半導體基板1的背面進行減薄處理,以將半導體基板1中的多個半導體單元結構11分離。   如圖2d所示,在完成步驟2之後,為了便於後續製程,先將半導體基板1進行翻轉,使得半導體基板1的背面朝上,正面朝下,然後再對半導體基板的背面進行減薄處理,以分離各個半導體單元結構11,分離後的各個單元結構11均以正面朝向保護膜2的形式黏貼在保護膜2上,而不會被散落下來。因此保護膜2在除了可以保護半導體基板1的有源面不被損壞,還在步驟3用於固定各個半導體單元結構11的位置。具體的,在本實施例中,可以採用對半導體基板1的背面進行研磨的製程來實現對半導體基板1的背面進行減薄處理,以將所述半導體基板分離為多個半導體單元結構。   由此可見,先由半導體基板1的正面進行半切割後,再在其正面設置保護膜2,然後在從半導體基板1的背面進行減薄處理,來分離各個半導體單元結構11,從而可以既能減小切割深度,以減少切割刀具的過渡使用,還能在分離各個半導體單元11的過程中,避免半導體基板1的有源面的損傷,以及防止各個半導體單元11在分離過程中位置的偏移。   此外,本發明提供的半導體製程步驟還進一步包括以下步驟。   步驟4:如圖2e所示,進行塑封製程,以形成包封各個半導體單元結構11的塑封體。   具體的,在本實施例中,進行塑封製程的具體步驟可以包括:在半導體結構單元11的背面設置模具,然後在所述保護膜和模具之間注入塑封料3,以形成所述塑封體。所述塑封體由各個半導體單元結構11的背面覆蓋在保護層2上,並和保護層2一起包封各個半導體單元結構11。   步驟5:如圖2f所示,去除保護膜2,以使得所述塑封體的第一表面裸露出各個半導體單元結構11的正面。   由於保護膜2可以為熱失效膜或者UV失效膜,因此可以採用加熱或紫外線照射的方式使得保護膜2與所述塑封體的第一表面之間的黏性失效,從而使得保護膜2與所述塑封體的第一表面及半導體單元結構11的正面相分離,從而去除了保護膜2,使得半導體單元結構11上的電極焊盤111也被所述塑封體的第一表面裸露,以便於後續引腳的製作。   步驟6:如圖2g所示,在所述塑封體的第一表面上形成圖案化的正面保護層4,且使得正面保護層4裸露各個半導體單元結構11的正面上的電極焊盤111。   正面保護層4可以為採用臨時鍵合製程形成的玻璃或矽片等硬質材料。   步驟7:如圖2h所示,形成與各個電極焊盤111電連接的引腳5。   引腳5由經正面保護層4的開口與焊盤電極111電連接,且引腳5被正面保護層4裸露在外,以作為半導體單元結構11與外部電路電連接的觸點。   具體的,在本實施例中,引腳5包括延伸至正面保護層4中與焊盤電極111電連接的第一部分和位於正面保護層4上的第二部分構成,而在其它實施例中,所述引腳可以包括重佈線層和位於重佈線層上導電球,其中所述重佈線層由經正面保護層4的開口與電極焊盤111電連接,並在正面保護層4上延伸。   步驟8:沿各個半導體單元結構11之間的塑封料3切割所述塑封體,以分離各個半導體單元結構11,使得各個半導體單元結構11的側面均被塑封料3包封。   具體的,在切割完所述塑封體後,各個半導體單元結構11的背面與側面(與背面垂直的四個側面)均被塑封料包封,而各個單元結構11正面除引腳5外,均被正面保護層4所覆蓋,因此各個半導體單元結構11的六個面均被保護起來,從而避免了半導體單元結構11受到外部環境的不良影響。   而在本實施例中,為了進一步降低半導體單元結構11的厚度,還可以在進行步驟8之前,由所述塑封體的第二表面處開始進行減薄處理,以減小各個半導體單元結構的厚度,然後在所述半導體單元結構的背面形成背面保護層6,具體如圖2i所示,在形成完背面保護層6之後,再沿切割塑封體3及其背面的背面保護層6,以形成圖2j所示的半導體結構。其中所述塑封體第二表面與其第一表面相對。   在本實施例中,半導體基板1為晶圓,而半導體單元結構為晶片單元(即半導體裸晶片),則依據本發明提供的半導體製程在本實施例中為晶圓級封裝製程,與常規晶圓級封裝製程不同的是,依據本發明半導體製程的實施例提供的晶圓級封裝製程還包括形成晶片側壁保護層的製程。   由上可見,本發明提供的半導體製程,由於先由半導體基板的正面進行半切割後,再在其正面設置保護膜,然後在從半導體基板的背面進行減薄處理,來分離各個半導體單元結構,從而可以既能減小切割深度,以減少切割刀具的過渡使用,還能在分離各個半導體單元的過程中,避免半導體基板的有源面的損傷,以及防止各個半導體單元在分離過程中位置的偏移。此外,依據本發明提供的半導體製程,採用所述保護膜保護半導體基板的正面後,再進行塑封製程和塑封料的切割製程,避免了塑封製程對半導體基板正面的不良影響,且最終形成的半導體結構的六個表面均有保護層,可以防止外部環境對半導體結構的不利影響,提高了半導體結構的可靠性。   依照本發明的實施例如上文所述,這些實施例並沒有詳盡敘述所有的細節,也不限制該發明僅為所述的具體實施例。顯然,根據以上描述,可作很多的修改和變化。本說明書選取並具體描述這些實施例,是為了更好地解釋本發明的原理和實際應用,從而使所屬技術領域技術人員能很好地利用本發明以及在本發明基礎上的修改使用。本發明僅受申請專利範圍及其全部範圍和等效物的限制。Hereinafter, the present invention will be described in more detail with reference to the drawings. In each drawing, the same components are represented by similar drawing marks. For clarity, the various elements in the figures have not been drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present invention are described, such as the structure, materials, dimensions, processing processes, and techniques of each component in order to better understand the present invention. As will be understood by those skilled in the art, the invention may be practiced without these specific details. FIGS. 2a-2j are schematic cross-sectional structure diagrams of each process step of a semiconductor process according to an embodiment of the present invention. The semiconductor process provided by the present invention will be specifically described below with reference to FIGS. 2a-2j. The semiconductor process provided by the present invention mainly includes the following steps. Step 1: Cut a predetermined depth along a scribe line on the front surface of the semiconductor substrate. As shown in FIG. 2 a, the semiconductor substrate 1 includes a plurality of semiconductor unit structures 11, and the scribe lines 12 on the front surface of the semiconductor substrate 1 are located between the semiconductor unit structures 11. The front surface of the semiconductor substrate 1 is an active surface, and the electrode pad 111 is provided on the active surface. The back surface of the semiconductor substrate 1 is a surface opposite to the active surface. As shown in FIG. 2b, the cutting process is started at the position of the scribe line 12 on the front surface of the semiconductor substrate 1, and when cutting to a predetermined depth, the dicing is stopped to form an opening at the scribe line 12. Wherein, the predetermined depth is smaller than the thickness of the semiconductor substrate 1 (thickness between the front surface and the back surface of the semiconductor substrate 1). That is, after the dicing process of step 1 is completed, each semiconductor unit 11 is still not separated. Step 2: A protective film 2 is stuck on the front surface of the semiconductor substrate 1. As shown in FIG. 2c, the protective film 2 may be a thermal failure film or a UV failure film (ultraviolet failure film). The protection film 2 is affixed to the front surface of the semiconductor substrate 1 after being cut to a predetermined depth, and covers the semiconductor unit structures 11. The openings on the front surface and the dicing track 12 achieve protection of the active surface of the semiconductor substrate 1 to prevent adverse effects on the active surface of the semiconductor substrate 1 by subsequent processes. Step 3: The back surface of the semiconductor substrate 1 is thinned to separate the plurality of semiconductor unit structures 11 in the semiconductor substrate 1. As shown in FIG. 2d, after step 2 is completed, in order to facilitate subsequent processes, the semiconductor substrate 1 is first turned over so that the back surface of the semiconductor substrate 1 faces upward and the front surface faces downward, and then the back surface of the semiconductor substrate is thinned. Each semiconductor unit structure 11 is separated, and each separated unit structure 11 is adhered to the protective film 2 with the front surface facing the protective film 2 without being scattered. Therefore, in addition to protecting the active surface of the semiconductor substrate 1 from being damaged, the protective film 2 is also used to fix the position of each semiconductor unit structure 11 in step 3. Specifically, in this embodiment, a process of polishing the back surface of the semiconductor substrate 1 may be used to implement a thinning process on the back surface of the semiconductor substrate 1 to separate the semiconductor substrate into a plurality of semiconductor unit structures. It can be seen that after half-cutting the front surface of the semiconductor substrate 1, a protective film 2 is provided on the front surface thereof, and then a thinning process is performed on the rear surface of the semiconductor substrate 1 to separate the individual semiconductor unit structures 11, so that both Reducing the cutting depth to reduce the transitional use of cutting tools, and also to avoid damage to the active surface of the semiconductor substrate 1 during the process of separating individual semiconductor units 11, and to prevent the positional deviation of each semiconductor unit 11 during the separation process . In addition, the semiconductor process steps provided by the present invention further include the following steps. Step 4: As shown in FIG. 2e, a plastic packaging process is performed to form a plastic package encapsulating each semiconductor unit structure 11. Specifically, in this embodiment, the specific steps of performing the plastic packaging process may include: setting a mold on the back surface of the semiconductor structure unit 11, and then injecting a molding compound 3 between the protective film and the mold to form the plastic package. The plastic package is covered on the protective layer 2 by the back surface of each semiconductor unit structure 11, and encapsulates each semiconductor unit structure 11 together with the protective layer 2. Step 5: As shown in FIG. 2f, the protective film 2 is removed, so that the first surfaces of the plastic packages expose the front surfaces of the respective semiconductor unit structures 11. Since the protective film 2 can be a thermal failure film or a UV failure film, the adhesion between the protection film 2 and the first surface of the plastic package body can be disabled by heating or ultraviolet irradiation, so that the protection film 2 and all The first surface of the plastic package and the front surface of the semiconductor unit structure 11 are separated, so that the protective film 2 is removed, so that the electrode pad 111 on the semiconductor unit structure 11 is also exposed by the first surface of the plastic package, so as to facilitate subsequent processes. Making of pins. Step 6: As shown in FIG. 2g, a patterned front surface protection layer 4 is formed on the first surface of the plastic package, and the front surface protection layer 4 exposes the electrode pads 111 on the front surface of each semiconductor unit structure 11. The front protective layer 4 may be a hard material such as glass or silicon wafer formed by a temporary bonding process. Step 7: As shown in FIG. 2h, a pin 5 electrically connected to each electrode pad 111 is formed. The pin 5 is electrically connected to the pad electrode 111 through the opening of the front protective layer 4, and the pin 5 is exposed by the front protective layer 4 to serve as a contact for electrically connecting the semiconductor unit structure 11 with an external circuit. Specifically, in this embodiment, the pin 5 includes a first portion extending to the front protective layer 4 and electrically connected to the pad electrode 111 and a second portion located on the front protective layer 4, and in other embodiments, The pins may include a redistribution layer and a conductive ball located on the redistribution layer, wherein the redistribution layer is electrically connected to the electrode pad 111 through the opening of the front protective layer 4 and extends on the front protective layer 4. Step 8: Cut the plastic packaging body along the molding compound 3 between each semiconductor unit structure 11 to separate each semiconductor unit structure 11 so that the sides of each semiconductor unit structure 11 are encapsulated by the molding compound 3. Specifically, after the plastic package is cut, the back surface and the side surfaces (four sides perpendicular to the back surface) of each semiconductor unit structure 11 are all encapsulated by the molding compound, and the front surface of each unit structure 11 except the lead 5 is all It is covered by the front protective layer 4, so the six sides of each semiconductor unit structure 11 are protected, thereby preventing the semiconductor unit structure 11 from being adversely affected by the external environment. In this embodiment, in order to further reduce the thickness of the semiconductor unit structure 11, before performing step 8, a thinning process may be started at the second surface of the plastic package to reduce the thickness of each semiconductor unit structure. Then, a back surface protective layer 6 is formed on the back surface of the semiconductor unit structure. As shown in FIG. 2i, after forming the back surface protective layer 6, the plastic package 3 and the back surface protective layer 6 on the back surface are cut to form a pattern. 2j semiconductor structure. The second surface of the plastic package is opposite to the first surface. In this embodiment, the semiconductor substrate 1 is a wafer, and the semiconductor unit structure is a wafer unit (ie, a semiconductor bare wafer). The semiconductor process provided according to the present invention is a wafer-level packaging process in this embodiment, which is in contrast to a conventional wafer. The difference between the round-level packaging process is that the wafer-level packaging process provided by the embodiment of the semiconductor process of the present invention further includes a process of forming a protective layer for the sidewall of the wafer. As can be seen from the above, since the semiconductor process provided by the present invention first performs a half cut from the front surface of the semiconductor substrate, a protective film is provided on the front surface thereof, and then a thinning process is performed from the rear surface of the semiconductor substrate to separate the individual semiconductor unit structures. Therefore, it is possible to reduce the cutting depth to reduce the use of cutting tools, and to avoid damage to the active surface of the semiconductor substrate during the separation of individual semiconductor units, and to prevent the positional deviation of individual semiconductor units during the separation process. shift. In addition, according to the semiconductor manufacturing process provided by the present invention, after the front surface of the semiconductor substrate is protected by the protective film, a plastic packaging process and a cutting process of the molding compound are performed, thereby avoiding the adverse effect of the plastic packaging process on the front surface of the semiconductor substrate, and finally forming the semiconductor The six surfaces of the structure are provided with protective layers, which can prevent the adverse influence of the external environment on the semiconductor structure and improve the reliability of the semiconductor structure.的 The embodiments according to the present invention are as described above. These embodiments do not describe all the details in detail, nor are they limited to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. These embodiments are selected and described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The invention is limited only by the scope of the patent application and its full scope and equivalents.

1‧‧‧半導體基板1‧‧‧ semiconductor substrate

2‧‧‧保護膜2‧‧‧ protective film

3‧‧‧塑封料3‧‧‧plastic sealant

4‧‧‧正面保護層4‧‧‧ Front Cover

5‧‧‧引腳5‧‧‧pin

6‧‧‧背面保護層6‧‧‧back protective layer

11‧‧‧半導體結構單元11‧‧‧Semiconductor structural unit

12‧‧‧切割道12‧‧‧ Cutting Road

111‧‧‧電極焊盤111‧‧‧ electrode pads

01‧‧‧裸晶片01‧‧‧ bare chip

02‧‧‧正面保護層02‧‧‧ Front Cover

03‧‧‧電極03‧‧‧electrode

04‧‧‧背面保護層04‧‧‧Back protective layer

011‧‧‧電極焊盤011‧‧‧ electrode pad

透過以下參照圖式對本發明實施例的描述,本發明的上述以及其他目的、特徵和優點將更為清楚,在圖式中:   圖1為採用現有的晶圓封裝技術形成的單個晶片封裝器件示意圖;   圖2a-2j為依據本發明實施例的半導體製程的各個製程步驟的剖面結構示意圖。Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will be more clear, in the drawings: FIG. 1 is a schematic diagram of a single chip packaging device formed by the existing wafer packaging technology FIGS. 2a-2j are schematic cross-sectional structure diagrams of each process step of a semiconductor process according to an embodiment of the present invention.

Claims (10)

一種半導體製程,其特徵在於,包括:   沿半導體基板正面的切割道進行預定深度的切割,   在該半導體基板的正面貼一層保護膜,   對該半導體基板的背面進行減薄處理,以將該半導體基板中的多個半導體單元結構分離。A semiconductor manufacturing process is characterized by: 进行 cutting a predetermined depth along a cutting path on the front surface of a semiconductor substrate, 贴 pasting a protective film on the front surface of the semiconductor substrate, thinning the back surface of the semiconductor substrate to make the semiconductor substrate Multiple semiconductor cell structures are separated. 根據申請專利範圍第1項的半導體製程,其中,還包括:   進行塑封製程,以形成包封各個該半導體單元結構的塑封體,以及,   去除該保護膜,以使得該塑封體的第一表面裸露各個該半導體單元結構的正面。The semiconductor process according to item 1 of the patent application scope further includes: (i) performing a plastic packaging process to form a plastic package encapsulating each of the semiconductor unit structures, and (ii) removing the protective film so that the first surface of the plastic package is exposed The front side of each of the semiconductor cell structures. 根據申請專利範圍第2項的半導體製程,其中,還包括:   在該塑封體的第一表面上形成圖案化的正面保護層,該正面保護層裸露各個該半導體單元結構上的電極焊盤,   形成與各個該電極焊盤電連接的引腳,   沿各個該半導體單元結構之間的塑封料切割該塑封體,以分離各個該半導體單元結構,各個該半導體單元結構的側面均被塑封料包封。The semiconductor process according to item 2 of the patent application scope, further comprising: : forming a patterned front protective layer on the first surface of the plastic package, the front protective layer exposing each electrode pad on the semiconductor unit structure, 单元 forming The pins electrically connected to each of the electrode pads are cut along the molding compound between each of the semiconductor unit structures to separate each of the semiconductor unit structures, and the sides of each of the semiconductor unit structures are encapsulated by the molding compound. 根據申請專利範圍第3項的半導體製程,其中,還包括:在切割該塑封體之前,先由該塑封體的第二表面處開始行減薄處理,以減小該各個半導體單元結構的厚度,然後在該半導體單元結構的背面形成背面保護層,該塑封體的第二表面與該第一表面相對。According to the third aspect of the patent application, the semiconductor process further includes: before cutting the plastic package, a thinning process is started at the second surface of the plastic package to reduce the thickness of each semiconductor unit structure Then, a back surface protective layer is formed on the back surface of the semiconductor unit structure, and the second surface of the plastic package is opposite to the first surface. 根據申請專利範圍第1項的半導體製程,其中,對該半導體基板的背面進行研磨,以將該半導體基板上的多個半導體單元分離。According to the semiconductor process of claim 1, the rear surface of the semiconductor substrate is polished to separate a plurality of semiconductor units on the semiconductor substrate. 根據申請專利範圍第1項的半導體製程,其中,該半導體基板正面為有源面,該有源面上設置有電極焊盤。According to the semiconductor process of claim 1, the front surface of the semiconductor substrate is an active surface, and electrode pads are provided on the active surface. 根據申請專利範圍第2項的半導體製程,其中,在注入該塑封料後,透過加熱或照射紫外線的方式使得該保護膜與該半導體單元結構的正面之間的黏性失效,以去除該保護膜。The semiconductor process according to item 2 of the scope of patent application, wherein after the injection molding material is injected, the adhesion between the protective film and the front surface of the semiconductor unit structure is invalidated by heating or irradiating ultraviolet rays to remove the protective film . 根據申請專利範圍第2項的半導體製程,其中,該塑封製程包括:   在該半導體結構單元的背面設置模具, 然後在該保護膜和模具之間注入塑封料,以形成該塑封體。The semiconductor manufacturing process according to item 2 of the patent application scope, wherein the plastic packaging process includes: (1) setting a mold on the back surface of the semiconductor structural unit, and then injecting a molding compound between the protective film and the mold to form the plastic package. 根據申請專利範圍第1項的半導體製程,其中,該半導體基板為晶圓,該半導體單元結構為該晶圓上的晶片單元,該半導體製程為晶圓級封裝製程。According to the semiconductor process of claim 1, the semiconductor substrate is a wafer, the semiconductor unit structure is a wafer unit on the wafer, and the semiconductor process is a wafer-level packaging process. 一種半導體結構,該半導體結構是根據申請專利範圍第1至9項中任意一項的半導體製程所製備。A semiconductor structure is prepared according to a semiconductor process of any one of claims 1 to 9 of the scope of patent application.
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