TWI651783B - Semiconductor device and method of forming embedded wafer level chip scale packages - Google Patents

Abstract

A semiconductor device includes a semiconductor die and an encapsulant deposited on and around the semiconductor die. A semiconductor wafer system includes a plurality of semiconductor dies and a base semiconductor material. A trench is formed in the base semiconductor material. The semiconductor wafer is singulated through the trench to separate the semiconductor dies. The semiconductor dies are disposed on a carrier at a distance of 500 micrometers (μm) or less between the semiconductor dies. The encapsulation system covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulation system remains free of the fan-in interconnect structure. A portion of the encapsulant is removed from an inactive surface of the semiconductor die. The device is singulated through the encapsulant while leaving an encapsulant disposed to cover a sidewall of the semiconductor die. The encapsulation system covering the sidewalls comprises a thickness of 50 μm or less.

Description

Semiconductor device and method for forming an embedded wafer level wafer size package

The present invention is generally related to semiconductor devices and, more particularly, to a semiconductor device and method for forming a wafer level wafer size package (WLCSP).

Domestic priority claim

This application is a continuation of the U.S. Patent Application Serial No. 14/ 036, 525 filed on Sep. 25, 2013, the benefit of the benefit of U.S. Provisional Application No. 61/748,742, filed on Jan. 3, 2013. These applications are hereby incorporated by reference.

Semiconductor devices are common in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices typically include a type of electrical component, such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor field effect transistor (MOSFET). Semiconductor devices that are concentrated typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

Semiconductor devices perform a wide range of functions, such as signal processing, high speed computing, transmitting and receiving electromagnetic signals, controlling electronics, converting sunlight into electricity, and producing visual images for television displays. Semiconductor devices are found in entertainment, communications, and power In the field of switching, networking, computers and consumer products. Semiconductor devices are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

Semiconductor devices utilize the electrical properties of semiconductor materials. The structure of the semiconductor material allows the conductivity of the material to be manipulated by the application of an electric or base current or through a doping process. The doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

A semiconductor device includes an active and passive electrical structure. An active structure comprising a bi-carrier and a field effect transistor controls the flow of current. By varying the degree of doping and the application of an electric or base current, the transistor does not lift, or limit, the flow of current. A passive structure comprising resistors, capacitors, and inductors creates a relationship between voltage and current that is necessary to perform various electrical functions. The passive and active structures are electrically connected to form a circuit that enables the semiconductor device to perform high speed operations and other useful functions.

Semiconductor devices are typically fabricated using two complex processes, namely front-end manufacturing and back-end manufacturing, each of which potentially involves hundreds of steps. Front-end fabrication involves the formation of a plurality of dies on the surface of a semiconductor wafer. Each semiconductor die is typically identical and includes circuitry formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor dies from completed wafers and packaging the dies to provide structural support and environmental isolation. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and thus can refer to both a single semiconductor device and a plurality of semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume lower power, have higher performance, and can be produced more efficiently. In addition, smaller semiconductor devices have a smaller footprint that is desirable for smaller end products. Smaller semiconductor grain sizes can be achieved by improvements in the front end process of producing semiconductor dies having smaller and higher density active and passive components. The backend process can produce semiconductor device packages with smaller footprints by improvements in electrical interconnects and encapsulants.

A conventional semiconductor wafer typically includes a plurality of semiconductor dies separated by a scribe line. Active and passive circuits are formed in one surface of each semiconductor die. An interconnect structure can be formed on the surface of the semiconductor die. The semiconductor wafer is singulated into individual semiconductor dies for use in various electronic products. An important feature of semiconductor manufacturing is high yield and corresponding low cost.

Semiconductor wafers are fabricated to have various diameters and semiconductor grain sizes in accordance with the equipment used to produce the semiconductor wafer and semiconductor die. Semiconductor processing equipment is typically developed based on each particular semiconductor die size and incoming semiconductor wafer size. For example, a 200 mm (mm) wafer is processed using 200 mm equipment, and a 300 mm wafer is processed using 300 mm equipment. The semiconductor grains singulated from a wafer are processed on a carrier. The size of the carrier is selected depending on the size of the semiconductor die to be processed. For example, a 10 mm by 10 mm semiconductor die is processed using a different device than a 5 mm by 5 mm semiconductor die. Thus, the equipment used to package a semiconductor device is limited by the processing power of the particular semiconductor die size or semiconductor wafer size that the device is designed for. Additional investment in manufacturing equipment is necessary as the incoming semiconductor die size and semiconductor wafer size change. The investment in equipment for a particular size of semiconductor die or semiconductor wafer creates a capital investment risk for the manufacturer of the semiconductor device. When the size of the incoming semiconductor wafer changes, the equipment for a particular wafer becomes obsolete. Similarly, designed to be used Carriers and devices for semiconductor dies of a particular size may become obsolete because such carriers are limited in their ability to handle semiconductor dies of different sizes. Continuous development and implementation of different equipment increases the cost of the final semiconductor device.

Semiconductor wafers are available in a variety of diameters and are typically processed using fabrication equipment designed for each particular size of semiconductor die. Semiconductor dies are typically encapsulated within a semiconductor package for electrical interconnection, structural support, and environmental protection of the die. If a portion of the semiconductor die is exposed to an external element, especially when the die is surface mounted, the semiconductor may be damaged or deteriorated. For example, the semiconductor die may be damaged or deteriorated during processing and exposure. Semiconductor dies are also damaged during singulation of semiconductor wafers and during formation of individual semiconductor packages. Single granulation through the semiconductor material may cause cracking or fragmentation of the semiconductor grains.

There is a need to reduce damage to semiconductor dies during fabrication of wafer level wafer size packages (WLCSP). Thus, in one embodiment, the invention is a method of fabricating a semiconductor device comprising: disposing a semiconductor die, depositing an encapsulant on and around the semiconductor die, from the semiconductor die A surface removes a portion of the encapsulant and forms an interconnect structure over the semiconductor die while the encapsulant does not have the interconnect structure.

In another embodiment, the invention is a method of fabricating a semiconductor device comprising: disposing a semiconductor die, depositing an encapsulation on and around the semiconductor die, and forming over the semiconductor die An interconnect structure while the envelope is not provided with the interconnect structure.

In another embodiment, the invention is a semiconductor device comprising a semiconductor die and an encapsulant deposited around the semiconductor die. An interconnect structure is formed over the semiconductor die. The encapsulation system does not have this interconnect structure.

In another embodiment, the invention is a semiconductor device comprising a semiconductor die and an encapsulant deposited around the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die.

50‧‧‧Electronic devices

52‧‧‧Printed circuit board (PCB)

54‧‧‧Signal lines

56‧‧‧bonded wire package

58‧‧‧Flip chip

60‧‧‧Pellet Array (BGA)

62‧‧‧Bump wafer carrier (BCC)

64‧‧‧Double-row package (DIP)

66‧‧‧ Platform Grid Array (LGA)

68‧‧‧Multi-chip module (MCM)

70‧‧‧Four-sided flat leadless package (QFN)

72‧‧‧Four-sided flat package

74‧‧‧Semiconductor grains

76‧‧‧Contact pads

78‧‧‧ intermediate carrier

80‧‧‧Conductor leads

82‧‧‧bonding line

84‧‧‧Encapsulation

88‧‧‧Semiconductor grains

90‧‧‧ Carrier

92‧‧‧Adhesive materials

94‧‧‧bonding line

96‧‧‧Contact pads

98‧‧‧Contact pads

100‧‧‧Molded compounds (encapsulated)

102‧‧‧Contact pads

104‧‧‧Bumps

106‧‧‧ intermediate carrier

108‧‧‧Active area

110‧‧‧Bumps

112‧‧‧Bumps

114‧‧‧ signal line

116‧‧‧Molded compound (encapsulated body)

120‧‧‧Semiconductor wafer

122‧‧‧Base substrate material

124‧‧‧Semiconductor grains (components)

126‧‧ ‧ cutting road

128‧‧‧Semiconductor wafer

130‧‧‧Base substrate material

132‧‧‧Semiconductor grains (members)

134‧‧‧ cutting road

136‧‧‧Back (non-active surface)

138‧‧‧Active surface

140‧‧‧conductive layer (node) (contact pad)

142‧‧‧First insulation (protection) layer

144‧‧‧Edge (sidewall)

145‧‧ ‧ laser

146‧‧‧ saw blade (laser cutting tool)

148‧‧‧ Sidewall (side surface)

150‧‧‧ Carrier (temporary substrate)

152‧‧‧Interface layer (double-sided tape)

156‧‧‧Reconstituted wafer

157‧‧‧ gap

158‧‧‧Reconstituted wafer

160‧‧‧Processing equipment

162‧‧‧Control system

164‧‧‧Molded compounds (encapsulated)

166‧‧‧Back surface

168‧‧‧ surface

170‧‧‧ Conductive layer

172‧‧‧Insulation (protection) layer

174‧‧‧ ball (bump)

176‧‧‧Stacked interconnect structures

180‧‧‧ saw blade (laser cutting tool)

182‧‧‧eWLCSP

184‧‧‧ side surface

190‧‧‧eWLCSP

194‧‧‧Bump bottom metallization (UBM)

196‧‧‧Back protective layer

200‧‧‧Semiconductor wafer

202‧‧‧Base substrate material

204‧‧‧Semiconductor die (member)

206‧‧‧ cutting road

208‧‧‧ edge (sidewall)

210‧‧‧Back (non-active surface)

212‧‧‧Active surface

214‧‧‧ Conductive layer (node) (contact pad)

216‧‧‧First insulation (protective) layer

218‧‧ ‧ laser

220‧‧‧ saw blade (laser cutting tool)

222‧‧‧ side surface

230‧‧‧ Carrier (temporary substrate)

232‧‧‧Interface layer (double-sided tape)

240‧‧‧Reconstituted wafer

244‧‧·Molding compound (encapsulated body)

246‧‧‧ Back surface

248‧‧‧ surface

250‧‧‧ Conductive layer

260‧‧‧Insulation (protective layer)

262‧‧‧ ball (bump)

264‧‧‧Stacked interconnect structures

270‧‧‧ saw blade (laser cutting tool)

272‧‧‧eWLCSP

274‧‧‧eWLCSP

276‧‧‧Back protective layer

290‧‧‧Semiconductor wafer

292‧‧‧Base substrate material

294‧‧‧Semiconductor die (member)

296‧‧‧ cutting road

300‧‧‧Semiconductor wafer

302‧‧‧Base substrate material

304‧‧‧Semiconductor die (member)

306‧‧‧Cut Road

310‧‧‧Back (non-active surface)

312‧‧‧Active surface

314‧‧‧ Conductive layer (node) (contact pad)

316‧‧‧First insulation (protective) layer

318‧‧‧Laser

322‧‧‧Saw Blade (Laser Cutting Tool)

324‧‧‧ Sidewall (side surface)

330‧‧‧ Carrier (temporary substrate)

332‧‧‧Interface layer (double-sided tape)

334‧‧‧ surface

336‧‧‧Reconstituted wafer

338‧‧‧Reconstituted wafer

340‧‧‧Processing equipment

342‧‧‧Control system

344‧‧‧Encapsulation (molding compound)

345‧‧‧grinding machine

346‧‧‧ Back surface

347‧‧‧Back surface

348‧‧‧ surface

349‧‧‧Back protective layer

350‧‧‧Insulation (protection) layer

352‧‧‧ openings

354‧‧‧ Conductive layer

356‧‧‧Insulation (protection) layer

358‧‧‧ openings

360‧‧‧ Conductive layer

362‧‧‧ ball (bump)

366‧‧‧Stacked interconnect structures

370‧‧‧Saw Blade (Laser Cutting Tool)

372‧‧‧eWLCSP

380‧‧‧eWLCSP

384‧‧‧eWLCSP

386‧‧‧eWLCSP

388‧‧‧eWLCSP

410‧‧‧Insulation

414‧‧‧ Conductive layer

416‧‧‧Insulation (protection) layer

418‧‧‧ openings

420‧‧‧ saw blade (laser cutting tool)

422‧‧‧ side surface

430‧‧‧ Carrier

432‧‧‧Interface

436‧‧‧Reconstituted wafer

438‧‧‧Encapsulation (molding compound)

440‧‧‧Back surface

442‧‧‧ Grinder

444‧‧‧Back surface

448‧‧‧ surface

460‧‧‧ Conductive layer

462‧‧‧ ball (bump)

466‧‧‧Stacked interconnect structures

470‧‧‧Saw Blade (Laser Cutting Tool)

472‧‧‧eWLCSP

480‧‧‧eWLCSP

482‧‧‧eWLCSP

484‧‧‧Back protective layer

486‧‧‧eWLCSP

488‧‧‧eWLCSP

490‧‧‧eWLCSP

500‧‧‧Semiconductor wafer

502‧‧‧Base substrate material

504‧‧‧Semiconductor die (member)

506‧‧‧ cutting road

508‧‧‧Back (non-active surface)

510‧‧‧Active surface

512‧‧‧conductive layer (node) (contact pad)

514‧‧‧Edge (sidewall)

516‧‧‧First insulation (protection) layer

520‧‧‧Laser

522‧‧‧ openings

530‧‧‧Groove (channel)

532‧‧‧Saw Blade (Laser Cutting Tool)

540‧‧‧Saw Blade (Laser Cutting Tool)

542‧‧‧ side surface (sidewall)

544‧‧‧ gap

560‧‧‧ Carrier (temporary substrate)

562‧‧‧Interface layer (double-sided tape)

564‧‧‧ surface

566‧‧‧Reconstituted wafer

570‧‧‧Encapsulation (molding compound)

572‧‧‧ surface

580‧‧‧Insulation (protection) layer

582‧‧‧ openings

584‧‧‧ Conductive layer

590‧‧‧Insulation (protection) layer

592‧‧‧ ball (bump)

594‧‧‧Fan-in-the-shelf interconnect structure

596‧‧‧Back grinding belt

600‧‧‧grinding machine

602‧‧‧ Back surface

610‧‧‧Cut tape

620‧‧‧ saw blade (laser cutting tool)

622‧‧‧eWLCSP

630‧‧‧eWLCSP

632‧‧‧Interconnect structure

640‧‧‧eWLCSP

642‧‧‧ Conductive layer

644‧‧‧Stacked interconnect structures

D‧‧‧Distance

D1‧‧‧ distance

D2‧‧‧ distance

D3‧‧‧ distance

D4‧‧‧ distance

D5‧‧‧ distance

D6‧‧‧Distance

D7‧‧‧ distance

D8‧‧‧ distance

D9‧‧‧Distance

D10‧‧‧Distance

D12‧‧‧ distance

D14‧‧‧ distance

D15‧‧‧Distance

D16‧‧‧ distance

D18‧‧‧Distance

D20‧‧‧ thickness (distance)

D21‧‧‧ thickness

D22‧‧‧ thickness

D24‧‧‧Distance

L1‧‧‧ length

L2‧‧‧ length

L3‧‧‧ length

L4‧‧‧ length

W1‧‧‧Width

W2‧‧‧Width

W3‧‧‧Width

W4‧‧‧Width

Figure 1 depicts a printed circuit board (PCB) having different types of packages mounted to its surface; Figures 2a-2c depict further details of a representative semiconductor package mounted to the PCB; Figure 3 depicts a semiconductor wafer having a plurality of semiconductor dies separated by scribe lines; FIGS. 4a-4m depict a process for forming a reconstituted or embedded wafer level wafer size package (eWLCSP); FIG. 5 depicts an eWLCSP, wherein The semiconductor die has exposed sidewalls and a back surface; FIG. 6 depicts an eWLCSP having a back protective layer; and FIGS. 7a-7i depict another process for forming an eWLCSP having a thin sidewall encapsulation; Figure 8 depicts an eWLCSP having a backside protective layer and a thin sidewall encapsulation; Figures 9a-9p depict a process for forming an eWLCSP; and Figure 10 depicts an encapsulation having sidewalls over the semiconductor die. Body and a back cover The protective layer eWLCSP; FIG. 11 depicts an eWLCSP having a back protective layer; FIG. 12 depicts an eWLCSP having an encapsulant over the sidewalls and back surface of the semiconductor die; FIG. 13 depicts The eWLCSP of the encapsulant over the back surface of the semiconductor die; FIG. 14 depicts an eWLCSP wherein the semiconductor die has exposed sidewalls and a back surface; FIGS. 15a-15k depict an alternative to forming an eWLCSP Process; Figure 16 depicts an eWLCSP having an encapsulant over the sidewalls and back surface of the semiconductor die; Figure 17 depicts an encapsulant having a back surface over the semiconductor die eWLCSP; Figure 18 depicts an eWLCSP having an encapsulant over the sidewall and a backside protective layer; Figure 19 depicts an eWLCSP having a backside protective layer; Figure 20 depicts another having an overlying sidewall The encapsulant and a back protective layer of eWLCSP; FIG. 21 depicts an eWLCSP in which a semiconductor die has exposed sidewalls and a back surface. FIGS. 22a-22m depict a formation having a sidewall on the semiconductor die. Encapsulation And a process having an exposed back surface eWLCSP; FIG. 23 depicts an eWLCSP having an encapsulant over the sidewall of the semiconductor die and having an exposed back surface; Figure 24 depicts an eWLCSP having an encapsulant over the sidewalls of the semiconductor die, an exposed back surface, and a bump bottom metallization (UBM).

The invention is described in one or more embodiments in the following description of the drawings, wherein the same reference numerals represent the same or similar elements. Although the present invention has been described in terms of the best mode for the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to be The accompanying claims, and the equivalents, modifications and equivalents

Semiconductor components are typically fabricated using two complex processes: front-end manufacturing and back-end manufacturing. Front-end fabrication involves the formation of a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. For example, the active electrical components of the transistor and the diode have the ability to control the flow of current. For example, passive electrical components of capacitors, inductors, and resistors produce a relationship between the voltage and current necessary to perform circuit functions.

The passive and active components are formed on the surface of the semiconductor wafer by a series of processing steps including doping, deposition, lithography, etching, and planarization. Doping is carried into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material in the active device by dynamically changing the conductivity of the semiconductor material in response to an electric field or base current. The electro-crystalline system comprises regions of different types and degrees of doping that are configured to enable the transistor to increase or limit the flow of current when an electric field or base current is applied.

Active and passive components are formed by layers of materials having different electrical properties. The layers can be formed by a variety of deposition techniques, some of which are determined by the type of material being deposited. For example, thin film deposition may involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is typically patterned to form an active member, a passive member, or a portion of an electrical connection between the members.

Back end fabrication refers to cutting or singulation of a finished wafer into individual semiconductor dies, and then packaging the semiconductor dies for structural support and environmental isolation. To singulate the semiconductor die, the wafer is scribed and truncated along non-functional areas of the wafer, referred to as scribe lines or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnecting with other system components. A contact pad formed over the semiconductor die is then attached to the contact pads within the package. The electrical connections can be made using solder bumps, stud bumps, conductive paste, or wire bonding. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and the functionality of the semiconductor device is made available to other system components.

1 depicts an electronic device 50 having a wafer carrier substrate or a printed circuit board (PCB) 52 in which a plurality of semiconductor packages are mounted over its surface. Depending on the application, electronic device 50 can have one type of semiconductor package, or multiple types of semiconductor packages. Different types of semiconductor packages are shown in Figure 1 for purposes of illustration.

Electronic device 50 can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device 50 can be a sub-component of a larger system. For example, electronic device 50 can be part of a mobile phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, the electronic device 50 can be a display card, a network interface card or other signal processing card that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, an application specific integrated circuit (ASIC), a logic circuit, an analog circuit, a radio frequency (RF) circuit, a discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices can be shortened to achieve higher densities.

In FIG. 1, PCB 52 provides a general substrate for structural support and electrical interconnection of a semiconductor package mounted on the PCB. The electrically conductive signal lines 54 are formed over a surface of the PCB 52 or within the layers by evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal line 54 provides electrical communication between each of the semiconductor package, the mounted components, and other external system components. Line 54 also provides power and ground connections to each semiconductor package.

In some embodiments, a semiconductor device has two package levels. The first level of packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate carrier. The second level of packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may have only the package of the first level, wherein the die is directly mechanically and electrically mounted to the PCB.

For purposes of illustration, a plurality of types of first level packages including bond wire packages 56 and flip chips 58 are shown on PCB 52. In addition, a ball grid array (BGA) 60, a bump wafer carrier (BCC) 62, a dual row package (DIP) 64, a platform grid array (LGA) 66, a multi-chip module (MCM) 68, and a four-sided flat are included. Pin package (QFN) 70, and the number of quad flat packs 72 Two types of second level packaging are shown mounted on PCB 52. Depending on the needs of the system, any combination of semiconductor packages and other electronic components configured in any combination of package types of the first and second levels can be connected to the PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Since semiconductor packages include complex functions, electronic devices can be fabricated using less expensive components and streamlined processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in lower costs for the consumer.

2a-2c show an exemplary semiconductor package. Figure 2a depicts further details of the DIP 64 mounted on the PCB 52. The semiconductor die 74 includes an active region including an analog or digital circuit, the analog or digital circuits being implemented as active components and passively formed within the die and electrically interconnected according to the electrical design of the die. The component, the conductive layer, and the dielectric layer. For example, the circuit can include one or more of a transistor, a diode, an inductor, a capacitor, a resistor, and other circuit elements formed in an active region of the semiconductor die 74. The contact pad 76 is one or more layers of conductive materials such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), and is electrically connected to the semiconductor. Circuit elements within die 74. During assembly of the DIP 64, the semiconductor die 74 is mounted to an intermediate carrier 78 using a gold eutectic layer or an adhesive material such as a thermal epoxy or epoxy. The package main system comprises an insulating encapsulant such as a polymer or ceramic. Conductor leads 80 and bond wires 82 provide electrical interconnections between semiconductor die 74 and PCB 52. An encapsulant 84 is deposited over the package for contaminating the environmental protection of the semiconductor die 74 or bond wires 82 by preventing moisture and particulates from entering the package.

Figure 2b depicts further details of the BCC 62 mounted on the PCB 52. The semiconductor die 88 is mounted on the carrier 90 using an underfill or epoxy adhesive material 92. Bond wire 94 provides a first level of package interconnection between contact pads 96 and 98. A molding compound or encapsulant 100 is deposited over the semiconductor die 88 and bonding wires 94 to provide physical support and electrical isolation to the device. The contact pads 102 are formed over a surface of the PCB 52 using a suitable metal deposition process such as electrolytic plating or electroless plating to avoid oxidation. Contact pad 102 is electrically coupled to one or more conductive signal lines 54 in PCB 52. Bumps 104 are formed between contact pads 98 of BCC 62 and contact pads 102 of PCB 52.

In Figure 2c, the semiconductor die 58 is mounted to the intermediate carrier 106 with the package of the first level of a flip chip type facing down. The active region 108 of the semiconductor die 58 includes an analog or digital circuit implemented as an active device, a passive component, a conductive layer, and a dielectric layer formed in accordance with the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit components within the active region 108. The semiconductor die 58 is electrically and mechanically coupled to the carrier 106 through the bumps 110.

The BGA 60 is electrically and mechanically coupled to the PCB 52 using bumps 112 using a BGA type second level package. The semiconductor die 58 is electrically coupled to the conductive signal line 54 in the PCB 52 through the bumps 110, the signal lines 114, and the bumps 112. A molding compound or encapsulant 116 is deposited over the semiconductor die 58 and the carrier 106 to provide physical support and electrical isolation to the device. The flip chip semiconductor device provides a short conductive path from the active component on the semiconductor die 58 to the conductive traces on the PCB 52 to facilitate signal loss reduction, capacitance reduction, and overall circuit performance. In another embodiment, the semiconductor The die 58 can be directly and mechanically and electrically connected to the PCB 52 using a flip-chip type of first level package under the intermediate carrier 106.

3 shows a semiconductor wafer 120 having a base substrate material 122 such as tantalum, niobium, gallium arsenide, indium phosphide, or tantalum carbide for structural support. As described above, a plurality of semiconductor dies or features 124 separated by a non-active inter-die wafer region or scribe 126 are formed on wafer 120. The scribe line 126 provides a dicing area to singulate the semiconductor wafer 120 into individual semiconductor dies 124. In one embodiment, the semiconductor wafer 120 is 200-300 millimeters (mm) in diameter. In another embodiment, the semiconductor wafer 120 is 100-450 mm in diameter. The semiconductor wafer 120 can have any diameter before the singulated semiconductor wafer becomes the individual semiconductor die 124. The semiconductor die 124 can have any size, and in one embodiment, the semiconductor die 124 can have a size of 10 mm by 10 mm.

The semiconductor wafer 128 is similar to the semiconductor wafer 120 and has a base substrate material 130 such as tantalum, niobium, gallium arsenide, indium phosphide, or tantalum carbide for structural support. As described above, a plurality of semiconductor dies or features 132 separated by a non-active inter-die wafer region or scribe 134 are formed on wafer 128. The scribe line 134 provides a dicing area to singulate the semiconductor wafer 128 into individual semiconductor dies 132. Semiconductor wafer 128 can have the same diameter or a different diameter than semiconductor wafer 120. The semiconductor wafer 128 can have any diameter before the singulated semiconductor wafer becomes the individual semiconductor die 132. In one embodiment, the semiconductor wafer 128 is 200-300 mm in diameter. In another embodiment, the semiconductor wafer 128 is 100-450 mm in diameter. The semiconductor die 132 can have any size, and in one embodiment, the semiconductor die 132 is smaller than the semiconductor die 124 and has a size of 5 mm by 5 mm.

4a-4k depict a process for forming a fan-in reconstituted or embedded wafer level wafer size package (eWLCSP) in relation to FIGS. 1 and 2a-2c. 4a is a cross-sectional view showing a portion of a semiconductor wafer 120. Each semiconductor die 124 has a back or non-active surface 136 and an active surface 138 comprising an analog or digital circuit implemented to be formed within the die and based on the die Active components, passive components, conductive layers, and dielectric layers that are functionally and functionally electrically interconnected. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in active surface 138 to implement analog circuits such as DSP, ASIC, memory, or other signal processing circuits or Digital circuit. Semiconductor die 124 may also include IPDs such as inductors, capacitors, and resistors for RF signal processing.

A conductive layer 140 is formed over the active surface 138 by PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 140 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 140 operates as a contact pad that is electrically connected to circuitry on active surface 138. As shown in FIG. 4a, the conductive layer 140 can be formed as a contact pad that is disposed side by side with a first distance apart from the edge or sidewall 144 of the semiconductor die 124. Alternatively, the conductive layer 140 may be formed as a contact pad biased in a plurality of columns such that a contact pad of a first column is disposed a first distance apart from an edge 144 of the semiconductor die 124, and the first and the first A row of staggered second columns of contact pads are disposed a second distance apart from the edge 144 of the semiconductor die 124.

A first insulating or protective layer 142 is formed over the semiconductor die 124 and the conductive layer 140 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 142 includes one or more layers of cerium oxide (SiO2), cerium nitride (Si3N4), and nitrogen. Cerium oxide (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), cerium oxide (HfO2), benzocyclobutene (BCB), polyimine (PI), polybenzoxazole ( PBO), polymer, or other dielectric material having similar structural and insulating properties. In one embodiment, the insulating layer 142 is a low temperature curing photosensitive dielectric polymer with or without an insulating filler that cures at less than 200 degrees Celsius (° C.). The insulating layer 142 covers and provides protection to the active surface 138. The insulating layer 142 is conformally applied over the conductive layer 140 and the active surface 138 of the semiconductor die 124 and does not extend over the edge or sidewall 144 of the semiconductor die 124 or exceeds one of the semiconductor die 124. Coverage area. In other words, the peripheral region of an adjacent semiconductor die 124 of the semiconductor die 124 does not have the insulating layer 142. A portion of the insulating layer 142 is removed by an LDA using a laser 145 or through an etching process of a patterned photoresist layer to expose the conductive layer 140 through the insulating layer 142 and provide for subsequent electrical interconnection.

The semiconductor wafer 120 is electrically tested and inspected as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on the semiconductor wafer 120. The software can be utilized in automated optical analysis of the semiconductor wafer 120. The visual inspection method can utilize, for example, a scanning electron microscope, high intensity or ultraviolet light, or a metallographic microscope. The semiconductor wafer 120 is characterized by a structure including warpage, thickness variation, surface particles, irregularities, cracks, delamination, and discoloration.

Active and passive components within the semiconductor die 124 are tested at the wafer level for electrical performance and circuit function. Each semiconductor die 124 is tested for functional and electrical parameters using a probe or other test device. A probe system is used to electrically contact the nodes or contact pads 140 on each of the semiconductor dies 124 and provide electrical stimulation to the contact pads. The semiconductor die 124 is responsive to the electrical stimuli, which is measured and compared to a pre- The response of the period to test the function of the semiconductor die. These electrical tests may include circuit function, lead integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, critical current, leakage current, and operating parameters specific to the type of component. The inspection and electrical testing of the semiconductor wafer 120 is such that the passed semiconductor die 124 is designated as a well-known die (KGD) for use in a semiconductor package.

In FIG. 4b, semiconductor wafer 120 is singulated into individual semiconductor dies 124 through scribe lines 126, along a sidewall or side surface 148 of base substrate material 122 using a saw or laser cutting tool 146. The semiconductor wafer 120 is singulated along a portion of the base substrate material 122 within the dicing region 126 by a thin cut along the base substrate side surface 148 to allow a portion of the base substrate material 122 to remain set. On sidewall 144 of semiconductor die 124. The thin cut is slightly larger than the semiconductor die 124 by a distance D between the semiconductor sidewall 144 and along the base substrate side surface 148. The base substrate material 122 over the sidewall 144 of the semiconductor die 124 is ruptured by reducing the dielectric material to strengthen the device during recombination and subsequent singulation processes. In an embodiment, the distance D between the sidewall 144 and the base substrate side surface 148 is at least 10 microns (μm). In another embodiment, the distance D between the sidewall 144 and the base substrate side surface 148 ranges from 14 to 36 [mu]m. Similarly, semiconductor wafer 128 is singulated into individual semiconductor dies 132 through scribe lines 134 using a saw blade or laser cutting tool 146. Individual semiconductor dies 124 and 132 can be inspected and electrically tested for identification of KGD after singulation.

4c is a cross-sectional view showing a portion of a carrier or temporary substrate 150 comprising a sacrificial substrate material such as tantalum, polymer, tantalum oxide, glass, or other suitable low cost rigid material. Used for structural support. One or two-sided tape 152 It is formed on the carrier 150 to serve as a temporary adhesive bonding film, an etch stop layer, or a heat release layer.

The carrier 150 is a standardized carrier having a capacity of a plurality of semiconductor crystal grains, and can accommodate semiconductor dies of various sizes that are singulated from semiconductor wafers having arbitrary diameters. For example, the carrier 150 may be a circular panel having a diameter of 305 mm or more, or may be a rectangular panel having a length of 300 mm or more and a width of 300 mm or more. Carrier 150 can have a surface area that is greater than the surface area of semiconductor wafer 120 or 128. In one embodiment, semiconductor wafer 120 has a diameter of 300 mm and includes semiconductor die 124 having a length of 10 mm and a width of 10 mm. In one embodiment, semiconductor wafer 128 has a diameter of 200 mm and includes semiconductor die 132 having a length of 5 mm and a width of 5 mm. The carrier 150 can accommodate 10 mm by 10 mm of semiconductor die 124 and 5 mm by 5 mm of semiconductor die 132. The carrier 150 carries the number of semiconductor dies 124 having a number of semiconductor dies 132 of 5 mm by 5 mm greater than 10 mm by 10 mm. In another embodiment, semiconductor dies 124 and 132 are of the same size. Carrier 150 is standardized in size and shape to accommodate semiconductor dies of any size. A larger carrier reduces the manufacturing cost of the semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit.

Semiconductor packaging and processing equipment is designed and configured for the size of the semiconductor die and carrier being processed. To further reduce manufacturing costs, the size of the carrier 150 is independent of the size of the semiconductor die 124 or 132 and is selected independently of the size of the semiconductor wafers 120 and 128. In other words, the carrier 150 has a fixed or standardized size that can accommodate semiconductor dies of various sizes that are singulated from one or more semiconductor wafers 120 or 128. 124 and 132. In one embodiment, the carrier 150 is circular having a diameter of 330 mm. In another embodiment, the carrier 150 is a rectangle having a width of 560 mm and a length of 600 mm.

The size and size of the standardized carrier (carrier 150) is selected during the design of the processing device to facilitate the development of a manufacturing line that is uniform for all back-end semiconductor fabrication of semiconductor devices. The carrier 150 is dimensionally fixed regardless of the size and type of semiconductor package to be fabricated. For example, the semiconductor die 124 may have a size of 10 mm by 10 mm and be disposed on a standardized carrier 150. Alternatively, the semiconductor die 124 may have a size of 20 mm by 20 mm and be disposed on the same standardized carrier 150. Thus, the standardized carrier 150 can process semiconductor dies 124 and 132 of any size, which allows subsequent semiconductor processing equipment to be standardized to a common carrier, i.e., regardless of die size or incoming wafer size. of. The semiconductor package device can be designed and configured for a standard carrier that utilizes a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 150 reduces manufacturing costs and capital risk by reducing or eliminating the need for a dedicated semiconductor production line based on die size or incoming wafer size. A flexible manufacturing line can be implemented by selecting a predetermined carrier size for use with semiconductor dies of any size from all semiconductor wafers.

In Figure 4d, the semiconductor die 124 from Figure 4b is oriented with the insulating layer 142 oriented toward the carrier 150 and mounted to the carrier 150 and the interface layer 152 using, for example, a pick and place operation. Semiconductor die 124 is mounted to interface layer 152 of carrier 150 to form reconstituted or reconfigured wafer 156. In an embodiment, the insulating layer 142 is embedded within the interface layer 152. For example, the active surface 138 of the semiconductor die 124 may be flush with the surface 154 of the interface layer 152. Faceted. In another embodiment, the insulating layer 142 is mounted over the interface layer 152 such that the active surface 138 of the semiconductor die 124 is offset from the interface layer 152.

4e shows the semiconductor die 124 mounted to the interface layer 152 of the carrier 150 to form a reconstituted or reconfigured wafer 156. Reconstituted wafer 156 can be processed into many types of semiconductor packages, including fan-in wafer level wafer size packages (WLCSP), eWLCSP, fan-out WLCSP, flip chip packages, (PoP), for example, stacked packages (PoP) (3D) package, or other semiconductor package. In one embodiment, the semiconductor die 124 is disposed on the carrier 150 in a high density configuration, i.e., 300 [mu]m or less, for processing the fan-in device. A semiconductor die 124 separated by a gap 157 having a distance D1 between the semiconductor dies 124 is disposed over the carrier 150. The distance D1 between the semiconductor dies 124 is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the distance D1 between the semiconductor dies 124 is 50 μm or less. In another embodiment, the distance D1 between the semiconductor dies 124 is 100 μm or less. The distance D1 between the semiconductor dies 124 on the carrier 150 is optimized for manufacturing the semiconductor packages at the lowest unit cost.

4f shows a plan view of a reconstituted wafer 156 in which semiconductor die 124 is mounted to carrier 150 or over carrier 150. The carrier 150 is of a standardized shape and size and thus constitutes a standardized carrier. The carrier 150 has a capacity for semiconductor dies of various sizes and numbers that are singulated from semiconductor wafers of various sizes. In one embodiment, the carrier 150 is rectangular in shape and has a width W1 of 560 mm and a length L1 of 600 mm. In another embodiment, the carrier 150 is rectangular in shape and has a width W1 of 330 mm and a length L1 of 330 mm. In another In the embodiment, the carrier 150 is circular in shape and has a diameter of 330 mm.

The number of semiconductor dies 124 disposed over the carrier 150 is a function of the size of the semiconductor die 124 and the distance D1 between the semiconductor dies 124 within the structure of the reconstituted wafer 156. The number of semiconductor dies 124 mounted to the carrier 150 can be greater than, less than, or equal to the number of semiconductor dies 124 that are singulated from the semiconductor wafer 120. The larger surface area carrier 150 accommodates more semiconductor die 124 and reduces manufacturing costs because each reconstituted wafer 156 processes more semiconductor die 124. In one example, semiconductor wafer 120 has a diameter of 300 mm, and a number of approximately 600 individual 10 mm by 10 mm semiconductor dies 124 are formed on semiconductor wafer 120. The semiconductor die 124 is singulated from one or more semiconductor wafers 120. The carrier 150 is, for example, a length L1 which is prepared to have a standard width W1 of 560 mm and a standard of 600 mm. The carrier 150 having a width W1 of 560 mm is sized to accommodate a quantity of about 54 semiconductor dies 124 having a size of 10 mm by 10 mm and spaced apart by a distance D1 of 200 μm across the width W1 of the carrier 150. The carrier 150 having a length L1 of 600 mm is sized to accommodate a quantity of about 58 semiconductor dies 124 having a size of 10 mm by 10 mm and a distance D1 of 200 μm across the length L1 of the carrier 150. Thus, the width W1 of the carrier 150 multiplied by the length L1 of the surface area accommodates an amount of about 3,000 semiconductor dies 124 having a size of 10 mm by 10 mm and a gap of 200 μm between the semiconductor dies 124 or a distance D1. The semiconductor die 124 can be placed on the carrier 150 at a gap or distance D1 between the semiconductor die 124 of less than 200 μm to increase the density of the semiconductor die 124 on the carrier 150 and further reduce the processing of the semiconductor die 124. the cost of.

An automated pick and place device is used depending on the number of semiconductor dies 124 and The reconstituted wafer 156 is sized and sized according to the size of the carrier 150. For example, the semiconductor die 124 is selected to have a size of 10 mm by 10 mm. The carrier 150 has a size of, for example, a width W1 of 560 mm and a length L1 of 600 mm. The automated equipment is programmed with the dimensions of semiconductor die 124 and carrier 150 to facilitate processing of reconstituted wafer 156. After singulating the semiconductor wafer 120, a first semiconductor die 124 is selected by the automated pick and place device. A first semiconductor die 124 is mounted to the carrier 150 at a location determined by the programmable automated pick-and-place device on the carrier 150. A second semiconductor die 124 is selected by the automated pick and place device, placed on the carrier 150, and disposed in a first column on the carrier 150. The distance D1 between adjacent semiconductor dies 124 is programmed into the automated pick and place apparatus and is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the gap 157 or distance D1 between adjacent semiconductor dies 124 on the carrier 150 is 200 μm. A third semiconductor die 124 is selected by the automated pick and place device, placed on the carrier 150, and disposed in the first column on the carrier 150. The pick and place operation is repeated until about 54 semiconductor dies 124 of a first column are disposed across the width W1 of the carrier 150.

Another semiconductor die 124 is selected by the automated pick and place device, placed on the carrier 150, and disposed in a second column of the carrier 150 adjacent the first column. The distance D1 between adjacent columns of semiconductor dies 124 is preselected and programmed into the automated pick and place apparatus. In one embodiment, the distance D1 between the semiconductor die 124 of a first column and the semiconductor die 124 of a second column is 200 μm. The pick and place operation is repeated until approximately 58 columns of semiconductor die 124 are disposed across the length L1 of the carrier 150. The standardized carrier (having a width W1 of 560 mm and a carrier 150 of length L1 of 600 mm) Approximately 10 rows and 58 columns of 10 mm by 10 mm semiconductor die 124 are accommodated for a total of about 3,000 semiconductor die 124 disposed on carrier 150. The pick and place operation is repeated until the carrier 150 is partially or completely filled with the semiconductor die 124. The automated pick and place apparatus can mount semiconductor dies 124 of any size on the carrier 150 to form a reconstituted wafer 156 under a standardized carrier such as carrier 150. The reconstituted wafer 156 can then be processed using a backend processing device that is standardized for the carrier 150.

4g shows a plan view of a reconstituted wafer 158 in which semiconductor die 132 is mounted to carrier 150 or over carrier 150. As with the reconstituted wafer 156 being used, the same standardized carrier 150, or a standardized carrier having the same dimensions as the carrier 150, is used to process the reconstituted wafer 158. Any configuration of semiconductor grains on a reconstituted wafer can be supported by carrier 150. The number of semiconductor dies 132 disposed over the carrier 150 is a function of the size of the semiconductor die 132 and the distance D2 between the semiconductor dies 132 within the structure of the reconstituted wafer 158. The number of semiconductor dies 132 mounted to the carrier 150 can be greater than, less than, or equal to the number of semiconductor dies 132 that are singulated from the semiconductor wafer 128. The larger surface area carrier 150 accommodates more semiconductor die 132 and reduces manufacturing costs because each reconstituted wafer 158 processes more semiconductor die 132.

In one example, semiconductor wafer 128 has a diameter of 200 mm, and an amount of about 1,000 individual 5 mm by 5 mm semiconductor dies 132 are formed on semiconductor wafer 128. Semiconductor die 132 is singulated from one or more semiconductor wafers 128. The carrier 150 is, for example, a length L1 which is prepared to have a standard width W1 of 560 mm and a standard of 600 mm. The carrier 150 having a width W1 of 560 mm is sized to accommodate an amount of about 107 sizes and intervals of 5 mm by 5 mm across the width W1 of the carrier 150. A semiconductor die 132 having a distance D2 of 200 μm is opened. The carrier 150 having a length L1 of 600 mm is sized to accommodate a number of about 115 semiconductor dies 132 having a size of 5 mm by 5 mm and a distance D2 spaced apart by 200 μm across the length L1 of the carrier 150. Thus, the width W1 of the carrier 150 multiplied by the length L1 of the surface area accommodates approximately 12,000 semiconductor dies 132 having a size of 5 mm by 5 mm and spaced apart by a distance D2 of 200 μm. The semiconductor die 132 can be placed on the carrier 150 at a gap of less than 200 μm or a distance D2 between the semiconductor dies 132 to increase the density of the semiconductor die 132 on the carrier 150 and further reduce the processing of the semiconductor crystal. The cost of the pellets 132.

An automated pick and place apparatus is used to prepare the reconstituted wafer 158 according to the number and size of the semiconductor dies 132 and according to the size of the carrier 150. For example, the semiconductor die 132 is selected to have a size of 5 mm by 5 mm. The carrier 150 has a size of, for example, a width W1 of 560 mm and a length L1 of 600 mm. The automated equipment is programmed with the dimensions of semiconductor die 132 and carrier 150 to facilitate processing of reconstituted wafer 158. After singulating the semiconductor wafer 128, a first semiconductor die 132 is selected by the automated pick and place device. A first semiconductor die 132 is mounted to carrier 150 in a position on carrier 150 that is determined by the programmable automated pick-and-place device. A second semiconductor die 132 is selected by the automated pick and place device, placed on the carrier 150, and disposed in a first column on the carrier 150. The distance D2 between adjacent semiconductor dies 132 is programmed into the automated pick and place apparatus and is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the gap or distance D2 between adjacent semiconductor dies 132 on the carrier 150 is 200 [mu]m. A third semiconductor die 132 is selected by the automated pick and place device, placed on the carrier 150, and disposed in the first column on the carrier 150. The pick and place operation The system is repeated until a column of about 107 semiconductor dies 132 is disposed across the width W1 of the carrier 150.

Another semiconductor die 132 is selected by the automated pick and place apparatus, placed on the carrier 150, and disposed in a second column of the carrier 150 adjacent the first column. The distance D2 between adjacent columns of semiconductor die 132 is pre-selected and programmed into the automated pick-and-place device. In one embodiment, the distance D2 between the semiconductor die 132 of a first column and the semiconductor die 132 of a second column is 200 μm. The pick and place operation is repeated until approximately 115 columns of semiconductor die 132 are disposed across the length L1 of the carrier 150. The standardized carrier (having a width W1 of 560 mm and a carrier 150 of length L1 of 600 mm) accommodates approximately 107 rows and 115 columns of 5 mm by 5 mm semiconductor die 132 for a total of approximately 12,000 semiconductor die 132 disposed at On the carrier 150. The pick and place operation is repeated until the carrier 150 is partially or completely filled with the semiconductor die 132. The automated pick and place apparatus can mount semiconductor dies of any size on the carrier 150 to form a reconstituted wafer 158 under a standardized carrier such as carrier 150. The reconstituted wafer 158 can be processed using the same carrier 150 and the same backend processing equipment used to process the reconstituted wafer 156.

Both the reconstituted wafer 156 from Figure 4f and the reconstituted wafer 158 from Figure 4g use the same carrier 150, or both reconstituted wafers 156 and 158 use a carrier of the same standardized size. The processing equipment designed for the back end processing of the reconstituted wafers is standardized for the carrier 150, and is thus capable of processing the reconstituted wafer of any configuration formed on the carrier 150 and placed on the carrier 150 Semiconductor dies of any size. Because the reconstituted wafers 156 and 158 all use the same standardized carrier 150, the reconstituted wafers can be processed on the same manufacturing line. Thus, one of the standardized carriers (carriers 150) is intended to simplify Equipment needed to make semiconductor packages.

In another example, the reconstituted wafer 158 includes semiconductor dies 124 and 132, wherein each of the semiconductor dies 124 and 132 have the same size, and the semiconductor dies are derived from semiconductor crystals having different diameters. Round 120 and 128. The semiconductor wafer 120 has a diameter of 450 mm, and an amount of about 2,200 individual 8 mm by 8 mm semiconductor dies 124 are formed on the semiconductor wafer 120. The semiconductor die 124 having a size of 8 mm by 8 mm is singulated from one or more semiconductor wafers 120. The semiconductor wafer 128 has a diameter of 300 mm, and an amount of about 900 individual 8 mm by 8 mm semiconductor dies 132 are formed on the semiconductor wafer 128. The semiconductor die 132 is singulated from the semiconductor wafer 128. The carrier 150 is, for example, prepared to have a standard width 560 of 560 mm and a standard length L1 of 600 mm. The carrier 150 having a width W1 of 560 mm is sized to accommodate a number of about 69 semiconductor dies 124 having a size of 8 mm by 8 mm and a distance D1 or D2 spaced apart by 100 μm across the width W1 of the carrier 150. Or 132. The carrier 150 having a length L1 of 560 mm is sized to accommodate a number of about 74 semiconductor dies 124 having a size of 8 mm by 8 mm and a distance D1 or D2 spaced apart by 100 μm across the length L1 of the carrier 150. Or 132. The surface area of the width W1 of the carrier 150 multiplied by the length L1 accommodates about 5,000 semiconductor dies 124 or 132 having a size of 8 mm by 8 mm and a distance D1 or D2 spaced apart by 100 μm. The semiconductor dies 124 and 132 may be placed on the carrier 150 at a gap of less than 100 μm or a distance D1 or D2 between the semiconductor dies 124 or 132 to increase the semiconductor dies 124 on the carrier 150 and The density of 132 further reduces the cost of processing semiconductor dies 124 and 132.

Automated pick and place equipment is used according to the number of semiconductor dies 124 and 132 The reconstituted wafer 158 is prepared in an amount and size and according to the size of the carrier 150. After singulating the semiconductor wafer 128, a first semiconductor die 124 or 132 is selected by the automated pick and place device. The 8 mm by 8 mm semiconductor die 124 or 132 may be derived from a semiconductor wafer 120 having a diameter of 450 mm or from a semiconductor wafer 128 having a diameter of 300 mm. Alternatively, the 8 mm by 8 mm semiconductor die may be derived from another semiconductor wafer having a different diameter. A first semiconductor die 124 or 132 is mounted to the carrier 150 in a position determined by the programmable automated pick and place device on the carrier 150. A second semiconductor die 124 or 132 is selected by the automated pick and place device, placed on the carrier 150, and disposed in a first column on the carrier 150. The distance D1 or D2 between adjacent semiconductor dies 124 or 132 is programmed into the automated pick and place apparatus and is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the gap 157 or the distance D1 or D2 between adjacent semiconductor dies 124 or 132 on the carrier 150 is 100 μm. The pick and place operation is repeated until approximately 69 semiconductor dies 124 or 132 of a column are disposed across the width W1 of the carrier 150.

Another semiconductor die 124 or 132 is selected by the automated pick and place device, placed on the carrier 150, and disposed in a second column of the carrier 150 adjacent the first column. In one embodiment, the distance D1 or D2 between the semiconductor dies 124 or 132 of a first column and the semiconductor dies 124 or 132 of a second column is 100 μm. The pick and place operation is repeated until approximately 74 columns of semiconductor dies 124 or 132 are disposed across the length L1 of the carrier 150. The standardized carrier (having a width W1 of 560 mm and a carrier 150 of length L1 of 600 mm) accommodates about 69 rows and 74 columns of 8 mm by 8 mm semiconductor dies 124 and 132 for a total of about 5,000 semiconductor dies 124. It is disposed on the carrier 150. The pick and place operation is This is repeated until the carrier 150 is partially or completely filled with the semiconductor die 124 or 132. Thus, the reconstituted wafer 158 can include semiconductor dies 124 and 132 that are singulated from semiconductor wafers of any size. The size of the carrier 150 is independent of the dimensions of the semiconductor dies 124 and 132 and is independent of the dimensions of the semiconductor wafers 120 and 128. The reconstituted wafer 158 can be processed using the same carrier 150 and the same backend processing equipment used to process the reconstituted wafer 156. For a reconstituted wafer having semiconductor dies of the same size that are singulated from different sized incoming wafers, the standardized carrier 150 allows the same material to be used for each reconstituted wafer. Thus, the bill of materials for a reconstituted wafer 156 or 158 on the carrier 150 remains fixed. A consistent and predictable bill of materials allows for cost analysis and planning for improved semiconductor packaging.

In another embodiment, a reconstituted wafer 158 includes various semiconductor grain sizes disposed on the carrier 150. For example, a 10 mm by 10 mm semiconductor die 124 is mounted to the carrier 150, and a 5 mm by 5 mm semiconductor die 132 is mounted to the carrier 150 to form a reconstituted wafer 158. The reconstituted wafer contains semiconductor dies of various sizes on the same reconstituted wafer. In other words, a portion of the reconstituted wafer 158 includes semiconductor dies of one size, and another portion of the reconstituted wafer contains semiconductor dies of another size. The reconstituted wafer 158 comprising simultaneously different sized semiconductor dies 124 and 132 on the carrier 150 utilizes the same back end as the reconstituted wafer 156 having a uniform sized semiconductor die disposed over the carrier 150. Process the device for processing.

In summary, carrier 150 has a capacity for semiconductor dies of various sizes and numbers that are singulated from semiconductor wafers of various sizes. The size of the carrier 150 does not vary with the size of the semiconductor die being processed. Standardized vector 150) is fixed in size and can accommodate semiconductor dies of various sizes. The size of the standardized carrier 150 is independent of the size of the semiconductor die or semiconductor wafer. More small semiconductor dies can be mounted on the carrier 150 than larger semiconductor dies. The number of semiconductor dies 124 or 132 mounted on the carrier 150 varies with the size of the semiconductor dies 124 or 132 and the spacing or distance D1 or D2 between the semiconductor dies 124 or 132. For example, carrier 150 having a length L1 and a width W1 is such that the number of semiconductor dies 132 that accommodate 5 mm by 5 mm above the surface area of carrier 150 is greater than the number of semiconductor dies 124 of 10 mm by 10 mm above the surface area of carrier 150. The size and shape of the carrier 150 remains fixed and independent of the size of the semiconductor die 124 or 132, or the semiconductor wafer 120 or 128 from which the singulated semiconductor die 124 or 132 are derived. The carrier 150 utilizes a common set of processing equipment to utilize the different sized semiconductor dies 124 and 132 from different sized semiconductor wafers 120 and 128 to provide resiliency to fabricate the reconstituted wafers 156 and 158 into many different types of semiconductors. Package.

Figure 4h shows a process for fabricating a semiconductor package using carrier 150. Processing device 160 is used to perform backend processes on semiconductor dies, such as deposition of encapsulants and insulating layers, deposition of conductive layers, bump bonding, reflow, marking, singulation, and other backend processes . Processing device 160 is designed for the size and shape of a standardized carrier such as carrier 150. The processing device 160 is compatible with the carrier 150 because the mechanical and electrical components of the processing device 160 are customized for the standardized size and shape of the carrier 150.

Processing device 160 is controlled by control system 162. Control system 162 can be a software program or algorithm that is used to configure processing device 160 in accordance with the size and shape of the semiconductor die on carrier 150. Control system 162 is programmed and customized. In order for the processing device 160 to process each of the different reconstituted wafers, such as reconstituted wafers 156 and 158, formed on the standardized carrier 150.

By standardizing the size of the carrier 150, the processing device 160 can remain fixed because the size of the carrier 150 does not vary with the size of the semiconductor die and the size of the semiconductor wafer. Control system 162 is directed to using various algorithms for each reconstituted wafer on carrier 150. For example, control system 162 can be utilized to optimize spacing during initial pick and place operations of semiconductor die 124 on carrier 150. The specifications of the reconstituted wafer 156 are input to the control system 162. Control system 162 is programmed to control processing device 160 to pick up individual semiconductor dies 124 and place semiconductor dies 124 over carrier 150 at a distance D1 to form reconstituted wafer 156. The reconstituted wafer 156 is, for example, a carrier 150 that includes a semiconductor die 124 of 10 mm by 10 mm and a standard size of width W1 and length L1. Processing device 160 is configured with control system 162 to perform a backend process on reconstituted wafer 156 on carrier 150. Control system 162 manages processing device 160 to perform deposition and other fabrication steps in accordance with the 10 mm by 10 mm sized semiconductor die 124 and standard sized carrier 150.

Control system 162 allows processing device 160 to be customized for each reconstituted wafer on standardized carrier 150. Processing device 160 does not need to be reconstructed for different sized semiconductor dies. After processing the reconstituted wafer 156, the processing device 160 is prepared to process another reconstituted wafer having the same or different semiconductor grain sizes and spacing on the carrier 150. The specifications of the reconstituted wafer 158 are input to the control system 162. Control system 162 is programmed to control processing device 160 to pick up individual semiconductor dies 132 and place semiconductor dies 132 over carrier 150 at a distance D2 to form reconstituted wafer 158. The reconstituted wafer 158 includes, for example, a 5 mm by 5 mm semiconductor die 132 and a carrier 150 of a standard size of width W1 and length L1. Processing device 160 is configured to utilize control system 162 to perform a backend process on reconstituted wafer 158 on carrier 150. Control system 162 manages processing device 160 to perform deposition and other fabrication steps in accordance with the 5 mm by 5 mm sized semiconductor die 132 and standard sized carrier 150.

The processing device 160 remains fixed regardless of whether the processing device 160 is processing the reconstituted wafer 156 or 158, or other reconstituted wafer on the standardized carrier 150. Control system 162 is programmable and processing device 160 is readily adapted to any reconstituted wafer using carrier 150. Accordingly, the mechanical and physical characteristics of the processing device 160 are designed to take into account the physical characteristics of the standardized carrier 150, while the processing device 160 can also be programmed with the control system 162 for any configuration of the semiconductor die on the carrier 150. Execute the process.

Processing device 160 is used to fabricate various semiconductor packages from a reconstituted wafer on carrier 150. For example, processing device 160 can be utilized to process reconstituted wafer 156 or 158 into a fan-in WLCSP, a recombination or eWLCSP, a fan-out WLCSP, a flip chip package, a 3D package such as PoP, or other semiconductor package. Control system 162 is used to modify and control the operation of processing device 160 to perform back end manufacturing steps in accordance with the semiconductor package to be fabricated. Accordingly, processing device 160 can be utilized to fabricate each of the semiconductor packages described herein. Processing device 160 can be utilized across a plurality of product manufacturing lines that share carrier 150 of the same size. Thus, the cost associated with changes in the size of the semiconductor die, the size of the semiconductor wafer, and the type of semiconductor package can be reduced. The investment risk in the processing device 160 is reduced because the design of the processing device 160 is simplified in the case where the carrier 150 is standardized.

In Figure 4i, an encapsulant or molding compound 164 is printed using a paste, Transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicator is deposited over semiconductor die 124 and carrier 150. The encapsulant 164 can be a polymer composite such as an epoxy with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulant 164 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. In another embodiment, the encapsulant 164 is an insulating or dielectric deposited by printing, spin coating, spray coating, vacuum or pressure lamination under or without heating, or other suitable process deposition. a layer comprising one or more layers of photosensitive low-curing temperature dielectric resist, photosensitive composite resist, laminated compound film, insulating paste with filler, solder mask resist film, liquid or particulate molding compound Polyimine, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg, or other dielectric materials having similar insulating and structural properties. In one embodiment, the encapsulant 164 is a low temperature curing photosensitive dielectric polymer with or without an insulating filler that cures at less than 200 °C.

In particular, the encapsulant 164 is disposed along the side surface 148 of the base substrate. The encapsulant 164 also covers the back surface 136 of the semiconductor die 124. In an embodiment, the encapsulant 164 is opaque and dark or black in color. Encapsulant 164 can be utilized for laser marking reconstituted wafer 156 for alignment and singulation. The encapsulant 164 can be thinned in a subsequent back grinding step. The encapsulant 164 can also be deposited such that the encapsulant 164 is coplanar with the back surface 136 of the semiconductor die 124 and thus does not cover the back surface 136. A surface 168 of the encapsulant 164 opposite the back surface 166 of the encapsulant 164 is disposed over the carrier 150 and the interface layer 152 such that the surface 168 of the encapsulant 164 can be the active surface of the semiconductor die 124 138 coplanar.

In Figure 4j, the carrier 150 and the interface layer 152 are chemically etched, mechanically Stripping, chemical mechanical planarization (CMP), mechanical polishing, thermal baking, UV light, laser scanning, or wet stripping to remove the insulating layer 142, the conductive layer 140, and the encapsulation Surface 168 of body 164.

A conductive layer 170 is formed over the insulating layer 142 and the conductive layer 140 by a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 170 can be one or more layers of Al, Cu, Sn, titanium (Ti), Ni, Au, Ag, or other suitable electrically conductive material. A portion of conductive layer 170 extends horizontally along insulating layer 142 and parallel to active surface 138 of semiconductor die 124 to laterally redistribute the electrical interconnect to conductive layer 140. Conductive layer 170 operates as a redistribution layer (RDL) for the electrical signals of semiconductor die 124. The conductive layer 170 is formed over a footprint of the semiconductor die 124 and does not extend beyond the footprint of the semiconductor die 124 to over the encapsulant 164. In other words, the peripheral region of an adjacent semiconductor die 124 of the semiconductor die 124 does not have the conductive layer 170, and thus the encapsulant 164 remains exposed. In one embodiment, the conductive layer 170 is formed by a sidewall 144 of the semiconductor die 124 at a distance D3 and at a distance D3 of at least 1 μm. A portion of the conductive layer 170 is electrically connected to the conductive layer 140. Other portions of conductive layer 170 are electrically or electrically isolated depending on the connection of semiconductor die 124.

In FIG. 4k, an insulating or protective layer 172 is formed over the insulating layer 142 and the conductive layer 170 by PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 172 may be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. In one embodiment, the insulating layer 172 is a photosensitive dielectric polymer that cures at a low temperature of less than 200 °C. In one embodiment, the insulating layer 172 is formed within the footprint of the semiconductor die 124 and does not extend beyond the semiconductor crystal. The coverage of the particles 124 is above the encapsulant 164. In other words, the peripheral region of an adjacent semiconductor die 124 of the semiconductor die 124 does not have the insulating layer 172, and thus the encapsulant 164 remains exposed. In another embodiment, an insulating layer 172 is formed over the insulating layer 142, the semiconductor die 124, and the encapsulant 164. A portion of the insulating layer 172 is removed by an etching process using a patterned photoresist layer or by an LDA to form an opening to expose the conductive layer 170.

A conductive bump material is deposited over the conductive layer 170 by an evaporation, electrolytic plating, electroless plating, ball dropping, or screen printing process. In one embodiment, the bump material is deposited using a ball drop stencil, i.e., no mask is required. The bump material may be Al, Sn, Ni, Au, Ag, lead (Pb), Bi, Cu, solder, and combinations thereof with an optional fluxing solvent. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is bonded to the conductive layer 170 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 174. In some applications, bumps 174 are reflowed a second time to improve electrical contact to conductive layer 170. The bumps 174 can also be bonded to the conductive layer 170 by compression bonding or thermocompression bonding. Bumps 174 represent a type of interconnect structure that can be formed over conductive layer 170. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects. The laser mark can be performed before or after the formation of the bump or after the removal of the carrier 150.

The insulating layer 172, the conductive layer 170, and the bumps 174 collectively form a stacked interconnect structure 176 formed over the semiconductor die 124 and within a footprint of the semiconductor die 124. The peripheral region of an adjacent semiconductor die 124 of the semiconductor die 124 does not have an interconnect structure 176, and thus the encapsulant 164 remains exposed. The stacked interconnect structure 176 can include There is only one RDL or conductive layer such as conductive layer 170, and an insulating layer such as insulating layer 172. Additional insulating layers and RDL may be formed over the insulating layer 172 prior to forming the bumps 174 to provide additional vertical and horizontal electrical connections across the package in accordance with the design and function of the semiconductor die 124.

In FIG. 41, semiconductor die 124 is singulated into individual eWLCSPs 182 using a saw blade or laser cutting tool 180. The reconstituted wafer 156 is singulated along the side surface 184 through the encapsulant 164 and the base substrate material 122 to remove the encapsulant 164 from the sides of the semiconductor die 124 and from the sides of the semiconductor die 124 A portion of the base substrate material 122 is removed. Thus, the base substrate material 122 is cut or singulated twice during the formation of the eWLCSP 182, once at the wafer level and once at the reconstituted wafer level. Therefore, the dielectric materials are less prone to cracking and the reliability of the eWLCSP 182 is improved.

A portion of the base substrate material 122 remains disposed along the sides of the semiconductor die 124 after singulation. The thickness of the base substrate material 122 of the adjacent semiconductor die 124 is at least 1 μm. In other words, a distance D4 between the side surface 184 of the semiconductor die 124 and the sidewall 144 is at least 1 μm. The eWLCSP 182 was electrically tested before or after the singulation.

4m shows an eWLCSP 182 having an encapsulant covering the back surface 136 of the semiconductor die 124 after singulation. The semiconductor die 124 is electrically coupled to the bumps 174 through the conductive layers 140 and 170 for interconnection through the exterior of the interconnect structure 176. The interconnect structure 176 does not extend beyond a footprint of the semiconductor die 124 and thus forms a fan-in package. The encapsulant 164 is maintained over the back surface 136 of the semiconductor die 124. The encapsulant 164 over the back surface 136 of the semiconductor die 124 eliminates the need for a backside protective layer or backside layer Therefore, thereby reducing the cost of the eWLCSP 182. The encapsulant 164 is completely removed from the sides of the semiconductor die 124 during singulation to expose the side surface 184 of the base substrate material 122. In one embodiment, the eWLCSP 182 has a size of approximately 4.445 mm in length x 3.875 mm in width having a pitch of 0.35-0.50 mm for the bumps 174. In another embodiment, the eWLCSP 182 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 182 is fabricated by forming a reconstituted wafer on a standardized carrier 150 using equipment designed for a single standardized carrier size, which reduces equipment and material costs for the eWLCSP 182. The eWLCSP 182 is manufactured in a larger amount using a standardized carrier 150, thereby simplifying the process and reducing unit cost.

FIG. 5 shows an eWLCSP 190 having an exposed back surface 136 and sidewalls 184. The semiconductor die 124 is electrically connected to the bumps 174 through the conductive layers 140 and 170 for interconnection through the exterior of the interconnect structure 176. The interconnect structure 176 does not extend beyond a footprint of the semiconductor die 124 and thus forms a fan-in package. The encapsulant 164 is completely removed from the back surface 136 of the semiconductor die 124 during a lapping operation. The encapsulant 164 is completely removed from the sides of the semiconductor die 124 during singulation to expose the side surface 184 of the base substrate material 122. In one embodiment, the eWLCSP 190 has a dimension of approximately 4.4 mm in length x 3.9 mm in width with a pitch of 0.35-0.50 mm for the bumps 174. The eWLCSP 190 is fabricated by forming a reconstituted wafer on a standardized carrier 150 using equipment designed for a single standardized carrier size, which reduces the cost of equipment and materials for the eWLCSP 190. The eWLCSP 190 is manufactured in a larger amount using a standardized carrier 150, thereby simplifying the process and reducing unit cost.

Figure 6 shows a bumped bottom metallization (UBM) 194, back protective layer 196, and an alternative eWLCSP 192 of the exposed side surface 184. A conductive layer 194 is formed in the exposed portion of the conductive layer 170 by PVD, CVD, evaporation, electrolytic plating, electroless plating, or other suitable metal deposition process after final repassivation. Above and above the insulating layer 172. Conductive layer 194 can be Al, Cu, Sn, Ni, Au, Ag, W, or other suitable electrically conductive material. Conductive layer 194 is a UBM that is electrically connected to conductive layers 170 and 140. UBM 194 can be a stack of multiple metals with an adhesion layer, a barrier layer, and a seed or wetting layer. The adhesive layer is formed over the conductive layer 170 and may be Ti, titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer is formed over the adhesive layer and may be Ni, NiV, platinum (Pt), palladium (Pd), TiW, Ti, or chromium copper (CrCu). The barrier layer prevents Cu from diffusing into the active surface 138 of the semiconductor die 124. The seed layer is formed over the barrier layer and may be Cu, Ni, NiV, Au, or Al. UBM 194 provides a low resistance interconnect to conductive layer 170, as well as a solder diffusion barrier and a seed layer for solder wettability.

The semiconductor die 124 is electrically connected to the bumps 174 through the conductive layers 140, 170, and 194 for interconnection through the exterior of the interconnect structure 176. Conductive layers 170 and 194 and insulating layers 142 and 172 do not extend beyond a footprint of semiconductor die 124 and thus form a fan-in package. A backside insulating layer or backside protective layer 196 is formed over the back surface 136 of the semiconductor die 124 for mechanical protection and protection against degradation due to exposure to photons from light or other radiation. The back protective layer 196 comprises one or more layers of photosensitive low curing temperature dielectric resistors, photosensitive composite resists, laminated compound films, resin matrix composite sheets with filler or fiberglass fabric, with fillers and fiberglass fabrics. Resin matrix composite sheet, insulating paste with filler, solder mask resist film, liquid molding compound, particle molding A compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg, or other dielectric material having similar insulating and structural properties. The backside protective layer 196 is deposited by printing, spin coating, spray coating, vacuum or pressure lamination with or without heating, or other suitable process. In one embodiment, the backside protective layer 196 is a low temperature curing photosensitive dielectric polymer with or without an insulating filler that cures at less than 200 °C. Backside protective layer 196 provides mechanical protection to semiconductor die 124 and is protected from light. In an embodiment, the backside protective layer 196 has a thickness ranging from about 5 to 150 [mu]m. Alternatively, the backside protective layer 196 is a metal layer such as a Cu foil applied to a back side of the eWLCSP 192. The backside protective layer 196 contacts the back surface 136 of the semiconductor die 124 to conduct heat from the semiconductor die 124 and improve the thermal performance of the device.

The encapsulant 164 is completely removed from the sides of the semiconductor die 124 during singulation to expose the side surface 184 of the base substrate material 122. In one embodiment, the eWLCSP 192 has a dimension of approximately 4.4 mm in length x 3.9 mm in width with a pitch of 0.35-0.50 mm for the bumps 174. In another embodiment, the eWLCSP 192 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 192 is fabricated by forming a reconstituted wafer on a standardized carrier 150 using equipment designed for a single standardized carrier size, which reduces the cost of equipment and materials for the eWLCSP 192. The eWLCSP 192 is manufactured in a larger amount using a standardized carrier 150, thereby simplifying the process and reducing unit cost.

Figures 7a-7i depict, in relation to Figures 1 and 2a-2c, a process for forming a reconstituted or recessed fan-in WLCSP or eWLCSP having a thin sidewall encapsulation. FIG. 7a is a cross-sectional view showing a portion of a semiconductor wafer 200. Semiconductor wafer 200 includes a structure for The supported base substrate material 202 is, for example, tantalum, niobium, gallium arsenide, indium phosphide, or tantalum carbide. A plurality of semiconductor dies or features 204 are formed on wafer 200 by a non-active inter-die wafer region or scriber 206 as described above. The scribe line 206 provides a dicing area to singulate the semiconductor wafer 200 into individual semiconductor dies 204. Semiconductor die 204 has edges or sidewalls 208. In one embodiment, the semiconductor wafer 200 is 200-300 mm in diameter. In another embodiment, the semiconductor wafer 200 is 100-450 mm in diameter. The semiconductor wafer 200 can have any diameter before the singulated semiconductor wafer becomes the individual semiconductor dies 204.

Each semiconductor die 204 has a back or non-active surface 210 and an active surface 212 including analog or digital circuitry that is implemented to be formed within the semiconductor die 204 and in accordance with the semiconductor die 204. Electrical design and functional electrical interconnection of active components, passive components, conductive layers, and dielectric layers. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in active surface 212 to implement analog circuits such as DSPs, ASICs, memories, or other signal processing circuits or Digital circuit. Semiconductor die 204 may also include IPDs such as inductors, capacitors, and resistors for RF signal processing.

A conductive layer 214 is formed over the active surface 212 using PVD, CVD, electrolytic plating, an electroless plating process, or other suitable metal deposition process. Conductive layer 214 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 214 operates as a contact pad that is electrically connected to circuitry on active surface 212. As shown in FIG. 7a, conductive layer 214 can be formed as contact pads disposed side by side at a first distance from edge 208 of semiconductor die 204. Alternatively, the conductive layer 214 can be formed in multiple columns The biased contact pads are such that a contact pad of a first column is disposed a first distance apart from an edge 208 of the semiconductor die 204, and a contact pad of the second column interleaved with the first column is separated by a semiconductor crystal The edge 208 of the grain 204 is disposed a second distance.

A first insulating or protective layer 216 is formed over the semiconductor die 204 and the conductive layer 214 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 216 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer, or other dielectric material having similar structural and insulating properties. The insulating layer 216 covers and provides protection to the active surface 212. The insulating layer 216 is conformally applied over the conductive layer 214 and the active surface 212 of the semiconductor die 204 and does not extend over the edge 208 of the semiconductor die 204 or beyond a footprint of the semiconductor die 204. . The peripheral region of an adjacent semiconductor die 204 of the semiconductor die 204 does not have an insulating layer 216. A portion of the insulating layer 216 is removed by an LDA using the laser 218 or through an etching process of a patterned photoresist layer to expose the conductive layer 214 through the insulating layer 216 and provide electrical for subsequent use. interconnection.

The semiconductor wafer 200 is electrically tested and inspected as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on the semiconductor wafer 200. The software can be utilized in automated optical analysis of the semiconductor wafer 200. The visual inspection method can utilize, for example, a scanning electron microscope, high intensity or ultraviolet light, or a metallographic microscope. The semiconductor wafer 200 is characterized by a structure including warpage, thickness variation, surface fine particles, irregularities, cracks, delamination, and discoloration.

The active and passive components within the semiconductor die 204 are tested at the wafer level for electrical performance and circuit function. Each semiconductor die 204 utilizes a probe or its It tests the device to test for functional and electrical parameters. A probe system is used to electrically contact the nodes or contact pads 214 on each of the semiconductor dies 204 and provide electrical stimulation to the contact pads. The semiconductor die 204 is responsive to the electrical stimuli, which are measured and tested for the function of the semiconductor die 204 as compared to an expected response. These electrical tests may include circuit function, lead integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, critical current, leakage current, and operating parameters specific to the type of component. Inspection and electrical testing of the semiconductor wafer 200 is such that the passed semiconductor die 204 is labeled as KGD for a semiconductor package.

In FIG. 7b, semiconductor wafer 200 is singulated into individual semiconductor dies 204 by a saw blade or laser cutting tool 220 through dicing streets 206. The semiconductor wafer 200 is singulated along a portion of the base substrate material 202 within the dicing region 206 by dicing along the side surface 222 of the base substrate to allow a portion of the base substrate material 202 to remain disposed in the semiconductor die. On the side wall 208 of the 204. The thickness of the base substrate material 202 of the adjacent semiconductor die 204 is at least 1 μm. In other words, the distance D5 between the side wall 208 and the side surface 222 of the base substrate is at least 1 μm. Individual semiconductor dies 204 can be inspected and electrically tested for identification of KGD after singulation.

Figure 7c shows a carrier comprising a sacrificial base material such as tantalum, polymer, tantalum oxide, glass, or other suitable low cost rigid material for supporting the structure or a portion of the temporary substrate 230. Cross-sectional view. A face layer or double-sided tape 232 is formed over the carrier 230 as a temporary adhesive bonding film, an etch stop layer, or a heat release layer. The semiconductor die 204 from FIG. 7b is oriented under the active surface 212 toward the carrier 230, such as by a pick and place operation, to the carrier 230 and the interface layer 232.

Carrier 230 can be a circular or rectangular panel (greater than 300 mm) having a capacity for a plurality of semiconductor dies 204. The carrier 230 can have a surface area greater than the surface area of the semiconductor wafer 200. A larger carrier reduces the manufacturing cost of the semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or carrier being processed.

In order to further reduce the manufacturing cost, the size of the carrier 230 is selected regardless of the size of the semiconductor die 204 or the size of the semiconductor wafer 200. In other words, the carrier 230 has a fixed or standardized size that can accommodate semiconductor dies 204 of various sizes that are singulated from one or more semiconductor wafers 200. In one embodiment, the carrier 230 is circular with a diameter of 330 mm. In another embodiment, the carrier 230 is a rectangle having a width of 560 mm and a length of 600 mm. The semiconductor die 204 may have a size of 10 mm by 10 mm that is disposed on a standardized carrier 230. Alternatively, the semiconductor die 204 may have a size of 20 mm by 20 mm, which is disposed on the same standardized carrier 230. Thus, the standardized carrier 230 can process semiconductor dies 204 of any size, which allows subsequent semiconductor processing equipment to be standardized to a common carrier, i.e., independent of die size or incoming wafer size. The semiconductor package device can be designed and configured for a standard carrier that utilizes a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 230 reduces manufacturing costs and capital risk by reducing or eliminating the need for a dedicated semiconductor production line based on die size or incoming wafer size. A flexible manufacturing line can be implemented by selecting a predetermined carrier size for use with semiconductor dies of any size from all semiconductor wafers.

7d shows a plan view of a reconstituted wafer 240 in which semiconductor die 204 is disposed over carrier 230. Carrier 230 is a standardized shape and size having a capacity for semiconductor dies of various sizes and numbers that are singulated from semiconductor wafers of various sizes. In one embodiment, the carrier 230 is rectangular in shape and has a width W2 of 560 mm and a length L2 of 600 mm. The number of semiconductor dies 204 mounted to the carrier 230 may be greater than the number of semiconductor dies 204 that are singulated from the semiconductor wafer 200. The larger surface area carrier 230 accommodates more semiconductor die 204 and reduces manufacturing costs because each reconstituted wafer 240 processes more semiconductor die 204.

The standardized carrier 230 is fixed in size and can accommodate semiconductor dies of various sizes. The size of the standardized carrier 230 is independent of the size of the semiconductor die or semiconductor wafer. More small semiconductor dies can be mounted on the carrier 230 than larger semiconductor dies. For example, the carrier 230 is accommodating a number of 5 mm by 5 mm grains above the surface area of the carrier 230 that is larger than the number of grains of 10 mm by 10 mm above the surface area of the carrier 230.

For example, a semiconductor die 204 having a size of 10 mm by 10 mm is disposed on the carrier 230 at a distance D6 of 200 μm between adjacent semiconductor dies 204. The number of semiconductor dies 204 that are singulated from the semiconductor wafer 200 is about 600 semiconductor dies, wherein the semiconductor wafer 200 has a diameter of 300 mm. The number of 10 mm by 10 mm semiconductor dies 204 that can be mounted on the carrier 230 is more than 3,000 semiconductor dies. Alternatively, the semiconductor die 204 having a size of 5 mm by 5 mm is disposed on the carrier 230 at a distance D6 of 200 μm between adjacent semiconductor dies 204. In the case where the semiconductor wafer 200 has a diameter of 200 mm, the semiconductor singulated from the semiconductor wafer 200 The number of grains 204 is approximately 1,000 semiconductor grains. The number of 5 mm by 5 mm semiconductor dies 204 that can be mounted on the carrier 230 is more than 12,000 semiconductor dies.

The size of the carrier 230 does not vary with the size of the semiconductor die being processed. The number of semiconductor dies 204 mounted on the carrier 230 varies with the size of the semiconductor dies 204 and the spacing or distance D6 between the semiconductor dies 204. The size and shape of the carrier 230 remains fixed and is independent of the size of the semiconductor die 204 or the semiconductor wafer 200 from which the semiconductor die 204 is singulated. Carrier 230 and reconstituted wafer 240 utilize a common set of processing equipment, such as from processing device 160 of FIG. 4h, to provide resiliency to fabricate many different semiconductor die 204 having different sizes of semiconductor wafers 200 from different sizes. Type of semiconductor package.

In Figure 7e, an encapsulant or molding compound 244 is deposited on the semiconductor using a paste printing, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicator. Above the die 204 and the carrier 230. The encapsulant 244 can be a polymer composite such as an epoxy with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulant 244 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. In another embodiment, the encapsulant 244 is an insulation or deposited by printing, spin coating, spray coating, vacuum or pressure lamination under or without heating, or other suitable process. a dielectric layer comprising one or more layers of photosensitive low-curing temperature dielectric resistors, photosensitive composite resists, laminated compound films, insulating pastes with fillers, solder mask resist films, liquid or particulate molding compounds Polyimine, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg, or other dielectric materials having similar insulating and structural properties. In an embodiment, the encapsulant 244 is a A low temperature curing photosensitive dielectric polymer with or without an insulating filler cured at less than 200 °C.

In particular, the encapsulant 244 is disposed along the side surface 222 of the base substrate. The encapsulant 244 also covers the back surface 210 of the semiconductor die 204. In one embodiment, the encapsulant 244 is opaque and dark or black in color. The encapsulant 244 can be utilized with the laser-marked reconstituted wafer 240 for alignment and singulation. The encapsulant 244 can be thinned in a subsequent back grinding step. The encapsulant 244 can also be deposited such that a back surface 246 of the encapsulant is coplanar with the back surface 210 of the semiconductor die 204 and thus does not cover the back surface 210. A surface 248 of the encapsulant 244 opposite the back surface 246 is disposed over the carrier 230 and the interface layer 232 such that the surface 248 of the encapsulant 244 can be coplanar with the active surface 212 of the semiconductor die 204.

In FIG. 7f, the carrier 230 and the interface layer 232 are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, hot baking, UV light, laser scanning, or wet stripping, The insulating layer 216, the conductive layer 214, and the surface 248 of the encapsulant 244 are exposed.

A conductive layer 250 is formed over the insulating layer 216 and the conductive layer 214 by a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. Conductive layer 250 can be one or more layers of Al, Cu, Sn, Ti, Ni, Au, Ag, or other suitable electrically conductive material. A portion of conductive layer 250 extends horizontally along insulating layer 216 and parallel to active surface 212 of semiconductor die 204 to laterally redistribute the electrical interconnect to conductive layer 214. Conductive layer 250 operates as an RDL for the electrical signal of semiconductor die 204. The conductive layer 250 is formed over a footprint of the semiconductor die 204 and does not extend beyond the footprint of the semiconductor die 204 to over the encapsulant 244. In other words, semi-guide The peripheral region of an adjacent semiconductor die 204 of the bulk die 204 does not have a conductive layer 250. In one embodiment, the conductive layer 250 is formed within a footprint of the semiconductor die 204 and spaced apart from the edge or sidewall 208 of the semiconductor die 204 by a distance D7 of at least 1 μm. A portion of the conductive layer 250 is electrically connected to the conductive layer 214. Other portions of conductive layer 250 are electrically or electrically isolated depending on the connection of semiconductor die 204.

In FIG. 7g, an insulating or protective layer 260 is formed over the insulating layer 216 and the conductive layer 250 by PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 260 may be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. In one embodiment, the insulating layer 260 is a photosensitive dielectric polymer that cures at a low temperature of less than 200 °C. In one embodiment, the insulating layer 260 is formed over the insulating layer 216, the semiconductor die 204, and extends beyond the footprint of the semiconductor die 204 by a distance D8 of 1 μm or greater, to the encapsulant 244. Above surface 248. The insulating layer 260 covers the interface between the semiconductor die 204 and the encapsulant 244 to protect the interface during processing and to improve the reliability of the device. A portion of the insulating layer 260 is removed by an etching process using a patterned photoresist layer or by LDA to form an opening to expose the conductive layer 250.

A conductive bump material is deposited over the conductive layer 250 by a vapor deposition, electrolytic plating, electroless plating, ball dropping, or screen printing process. In one embodiment, the bump material is deposited using a ball drop stencil, i.e., no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with an optional fluxing solvent. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is attached using a suitable attachment or bonding process The conductive layer 250 is bonded. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 262. In some applications, bumps 262 are reflowed a second time to improve electrical contact to conductive layer 250. The bumps 262 can also be compression bonded or thermocompression bonded to the conductive layer 250. Bumps 262 represent a type of interconnect structure that can be formed over conductive layer 250. The interconnect structure can also use bond wires, conductive pastes, stud bumps, micro bumps, or other electrical interconnects. The laser mark can be performed before or after the formation of the bump or after the removal of the carrier 230.

The insulating layer 260, the conductive layer 250, and the bumps 262 collectively form a stacked interconnect structure 264 formed over the semiconductor die 204 and the encapsulant 244. Alternatively, the stacked interconnect structures 264 are fully formed within a footprint of the semiconductor die 204. The stacked interconnect structure 264 can include only one RDL or conductive layer, such as conductive layer 250, and an insulating layer, such as insulating layer 260. Additional insulating layers and RDL may be formed over insulating layer 260 prior to forming bumps 262 to provide additional vertical and horizontal electrical connections across the package in accordance with the design and function of semiconductor die 204.

In Figure 7h, semiconductor die 204 is singulated into individual eWLCSPs 272 using a saw blade or laser cutting tool 270. The reconstituted wafer 240 is singulated by the encapsulant 244. After singulation, a portion of the encapsulant 244 is maintained along the sides of the semiconductor die 204. The eWLCSP 272 was electrically tested before or after singulation.

In FIG. 7i, an eWLCSP 272 having an encapsulant formed over the back surface 210 and sidewalls 208 of the semiconductor die 204 is shown. Semiconductor die 204 is electrically coupled to bumps 262 through conductive layers 214 and 250 for interconnection through the exterior of interconnect structure 264. The conductive layer of interconnect structure 264 does not extend beyond a footprint of semiconductor die 204, and thus Form a fan-in package. The insulating layer 260 covers the interface between the semiconductor die 204 and the encapsulant 244 to protect the interface during processing and to improve the reliability of the device. After an optional grinding operation, the encapsulant 244 is maintained over the back surface 210 of the semiconductor die 204. The encapsulant 244 is maintained over the side surface 222 of the base substrate for mechanical protection of the semiconductor die 204 and to protect against degradation due to exposure to photons from light or other radiation. Thus, the encapsulant 244 is formed over the five sides of the semiconductor die 204, that is, over the side surfaces 222 of the four base substrates and over the back surface 210. The encapsulant 244 over the back surface 210 of the semiconductor die 204 eliminates the need for a backside protective layer or backside layer, thereby reducing the cost of the eWLCSP 272.

The thickness of the encapsulant 244 for the eWLCSP 272 over the side surface 222 of the base substrate is less than 150 μm. In one embodiment, the eWLCSP 272 has a size of 4.595 mm in length x 4.025 mm in width x 0.470 mm in height and a pitch of 0.4 mm for the bumps 262, wherein the semiconductor die 204 It has a length of 4.445 mm and a width of 3.875 mm. In another embodiment, the thickness of the encapsulant 244 above the side surface 222 of the base substrate is 75 [mu]m or less. The eWLCSP 272 has a size of 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and a pitch of 0.5 mm for the bumps 262, wherein the semiconductor die 204 has a length. 6.0 mm × 6.0 mm in width × 0.470 mm in height. In yet another embodiment, the eWLCSP 272 has a size of 5.92 mm in length x 5.92 mm in width x 0.765 mm in height and a pitch of 0.5 mm for the bumps 262, wherein the semiconductor die The 204 series has a size of 5.75 mm in length × 5.75 mm in width × 0.535 mm in height. In another embodiment, the thickness of the encapsulant 244 above the side surface 222 of the base substrate is 25 [mu]m or less. In yet another implementation In an example, the eWLCSP 272 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 272 is fabricated by forming a reconstituted wafer on a standardized carrier 230 using equipment designed for a single standardized carrier size, which reduces equipment and material costs for the eWLCSP 272. The eWLCSP 272 is manufactured in a larger amount using a standardized carrier 230, thereby simplifying the process and reducing unit cost.

FIG. 8 shows an eWLCSP 274 having an encapsulant over sidewall 208 of semiconductor die 204 after singulation and having a backside protective layer 276. Semiconductor die 204 is electrically coupled to bumps 262 through conductive layers 214 and 250 for interconnection through the exterior of interconnect structure 264. The conductive layer of interconnect structure 264 does not extend beyond a footprint of semiconductor die 204 and thus forms a fan-in package. The insulating layer 260 covers the interface between the semiconductor die 204 and the encapsulant 244 to protect the interface during processing and to improve the reliability of the device. A backside insulating layer or backside protective layer 276 is formed over the back surface 210 of the semiconductor die 204 for mechanical protection and protection against degradation due to exposure to photons from light or other radiation. The back protective layer 276 is one or more layers of photosensitive low curing temperature dielectric resistors, photosensitive composite resists, laminated compound films, resin matrix composite sheets with filler or fiberglass fabric, with fillers and fiberglass fabrics. Resin matrix composite sheet, insulating paste with filler, solder mask resist film, liquid molding compound, particle molding compound, polyimine, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, pre Dip, or other dielectric material with similar insulating and structural properties. The backside protective layer 276 is deposited by printing, spin coating, spray coating, vacuum or pressure lamination with or without heating, or other suitable process. In one embodiment, the backside protective layer 276 is a low temperature cured photosensitive medium that cures at less than 200 ° C with or without an insulating filler. Electrical polymer. Backside protective layer 276 provides mechanical protection to semiconductor die 204 and is protected from light. In an embodiment, the backside protective layer 276 has a thickness ranging from about 5 to 150 [mu]m. Alternatively, the backside protective layer 276 is a metal layer such as a Cu foil that is applied to a back side of the reconstituted wafer 240. The backside protective layer 276 contacts the back surface 210 of the semiconductor die 204 to conduct heat from the semiconductor die 204 and improve the thermal performance of the device.

The encapsulant 244 covers the side surface 222 of the base substrate to protect the semiconductor die 204 from degradation due to exposure to photons from light or other radiation. The thickness of the encapsulant 244 for the eWLCSP 274 on the side surface 222 of the base substrate is less than 150 μm. In one embodiment, the eWLCSP 274 has a size of 4.595 mm in length x 4.025 mm in width x 0.470 mm in height and a pitch of 0.4 mm for the bumps 262, wherein the semiconductor die 204 It has a length of 4.445 mm and a width of 3.875 mm. In another embodiment, the thickness of the encapsulant 244 above the side surface 222 of the base substrate is 75 [mu]m or less. The eWLCSP 274 has a size of 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and a pitch of 0.5 mm for the bumps 262, wherein the semiconductor die 204 has a length. 6.0 mm × 6.0 mm in width × 0.470 mm in height. In yet another embodiment, the eWLCSP 274 has a size of 5.92 mm in length x 5.92 mm in width x 0.765 mm in height and a pitch of 0.5 mm for the bumps 262, wherein the semiconductor die The 204 series has a size of 5.75 mm in length × 5.75 mm in width × 0.535 mm in height. In another embodiment, the thickness of the encapsulant 244 above the side surface 222 of the base substrate is 25 [mu]m or less. In yet another embodiment, the eWLCSP 274 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 274 utilizes equipment designed for a single standardized carrier size, with a standardized carrier 230 A reconstituted wafer is formed to be fabricated, which reduces the cost of equipment and materials for the eWLCSP 274. The eWLCSP 274 is manufactured in a larger amount using a standardized carrier 230, thereby simplifying the process and reducing unit cost.

Figures 9a-9p depict a process for forming a recombination or embedded fan-in WLCSP in relation to Figures 1 and 2a-2c. Figure 9a shows a semiconductor wafer 290 having a base substrate material 292 such as tantalum, niobium, gallium arsenide, indium phosphide, or tantalum carbide for structural support. A plurality of semiconductor dies or features 294 separated by a non-active inter-die wafer region or scribe 296 as described above are formed on wafer 290. The scribe line 296 provides a dicing area to singulate the semiconductor wafer 290 into individual semiconductor dies 294. The semiconductor wafer 290 can have any diameter before the single granulated semiconductor wafer becomes the individual semiconductor die 294. In one embodiment, the semiconductor wafer 290 is 200-300 mm in diameter. In another embodiment, the semiconductor wafer 290 is 100-450 mm in diameter. The semiconductor die 294 can have any size, and in one embodiment, the semiconductor die 294 has a size of 10 mm by 10 mm.

FIG. 9a also shows a semiconductor wafer 300 that is similar to semiconductor wafer 290. The semiconductor wafer 300 includes a base substrate material 302 such as tantalum, niobium, gallium arsenide, indium phosphide, or tantalum carbide for structural support. A plurality of semiconductor dies or features 304 separated by a non-active inter-die wafer region or scribe 306 as described above are formed on wafer 300. The scribe line 306 provides a dicing area to singulate the semiconductor wafer 300 into individual semiconductor dies 304. Semiconductor wafer 300 can have the same diameter or a different diameter than semiconductor wafer 290. The semiconductor wafer 300 can have any diameter before the single granulated semiconductor wafer becomes the individual semiconductor die 304. In one embodiment, the semiconductor wafer 300 is 200-300 mm in diameter. In another embodiment, the semiconductor wafer 300 is 100-450 mm in diameter. The semiconductor die 304 can have any size, and in one embodiment, the semiconductor die 304 is smaller than the semiconductor die 294 and has a size of 5 mm by 5 mm.

FIG. 9b is a cross-sectional view showing a portion of a semiconductor wafer 290. Each semiconductor die 294 has a back or non-active surface 310 and an active surface 312 comprising an analog or digital circuit implemented to be formed within the die and based on the electrical properties of the die Active components, passive components, conductive layers, and dielectric layers that are designed and functionally electrically interconnected. For example, the circuit can include one or more transistors, diodes, and other circuit components formed in active surface 312 to implement analog circuits such as DSPs, ASICs, memories, or other signal processing circuits or Digital circuit. Semiconductor die 294 may also include IPDs such as inductors, capacitors, and resistors for RF signal processing.

A conductive layer 314 is formed over the active surface 312 by PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 314 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 314 operates as a contact pad that is electrically connected to circuitry on active surface 312. As shown in FIG. 9b, the conductive layer 314 can be formed as a contact pad disposed side by side with a first distance apart from the edge of the semiconductor die 294. Alternatively, the conductive layer 314 can be formed as a contact pad biased in a plurality of columns such that a contact pad of a first column is disposed a first distance apart from an edge of the semiconductor die 294, and the first and the first The contact pads of the second column of staggered columns are disposed at a second distance from the edge of the semiconductor die 294.

A first insulating or protective layer 316 is formed over the semiconductor die 294 and conductive layer 314 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 316 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer, or other dielectric materials having similar structural and insulating properties. In one embodiment, the insulating layer 316 is a low temperature curing photosensitive dielectric polymer that cures at less than 200 ° C with or without an insulating filler. The insulating layer 316 covers and provides protection to the active surface 312. A portion of insulating layer 316 is removed by an LDA using laser 318 or through an etching process of a patterned photoresist layer to expose conductive layer 314 through surface 320 of insulating layer 316 and provide for subsequent use. Electrical interconnection.

The semiconductor wafer 290 is electrically tested and inspected as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on semiconductor wafer 290. Software can be utilized in automated optical analysis of semiconductor wafer 290. The visual inspection method can utilize, for example, a scanning electron microscope, high intensity or ultraviolet light, or a metallographic microscope. The semiconductor wafer 290 is characterized by a structure including warpage, thickness variation, surface particles, irregularities, cracks, delamination, and discoloration.

The active and passive components within the semiconductor die 294 are tested at the wafer level for electrical performance and circuit function. Each semiconductor die 294 is tested for functional and electrical parameters using a probe or other test device. A probe system is used to electrically contact the nodes or contact pads 314 on each of the semiconductor dies 294 and provide electrical stimulation to the contact pads. The semiconductor die 294 is responsive to the electrical stimuli, which are measured and compared to an expected response to test the function of the semiconductor die. These electrical tests may include circuit function, lead integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, critical current, leakage current, and operating parameters specific to the type of component. Inspection and electrical testing of the semiconductor wafer 290 enables the passed semiconductor die 294 to be labeled as KGD for a semiconductor package.

In FIG. 9c, semiconductor wafer 290 is singulated through dicing streets 296 by a saw blade or laser cutting tool 322 into individual semiconductor dies 294 having sidewalls or side surfaces 324. Similarly, the semiconductor wafer 300 from FIG. 9a is singulated into individual semiconductor dies 304 by a saw blade or laser cutting tool 322 through a dicing street 306. Individual semiconductor dies 294 and 304 can be inspected and electrically tested for identification of KGD after singulation.

Figure 9d is a cross-sectional view showing a portion of a carrier or temporary substrate 330 comprising a sacrificial substrate material such as tantalum, polymer, tantalum oxide, glass, or other suitable low cost rigid material. Used for structural support. A face layer or double-sided tape 332 is formed over the carrier 330 as a temporary adhesive bonding film, an etch stop layer, or a heat release layer.

The carrier 330 is a standardized carrier having a capacity of a plurality of semiconductor dies, and can accommodate semiconductor dies of various sizes that are singulated from semiconductor wafers having arbitrary diameters. For example, the carrier 330 may be a circular panel having a diameter of 305 mm or more, or may be a rectangular panel having a length of 300 mm or more and a width of 300 mm or more. Carrier 330 can have a surface area greater than the surface area of semiconductor wafer 290 or 300. In one embodiment, semiconductor wafer 290 has a diameter of 300 mm and includes semiconductor die 294 having a length of 10 mm and a width of 10 mm. In one embodiment, semiconductor wafer 300 has a diameter of 200 mm and includes semiconductor die 304 having a length of 5 mm and a width of 5 mm. The carrier 330 can accommodate 10 mm by 10 mm of semiconductor die 294 and 5 mm by 5 mm of semiconductor die 304. The number of 5 mm by 5 mm semiconductor dies 304 carried by the carrier 330 is greater than the number of semiconductor dies 294 of 10 mm by 10 mm. In another embodiment, semiconductor dies 294 and 304 have the same dimensions. Carrier 330 It is standardized in size and shape to accommodate semiconductor dies of any size. A larger carrier reduces the manufacturing cost of the semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit.

Semiconductor packaging and processing equipment is designed and configured for the size of the semiconductor die and carrier being processed. To further reduce manufacturing costs, the size of the carrier 330 is independent of the size of the semiconductor die 294 or 304 and is selected independently of the size of the semiconductor wafers 290 and 300. In other words, carrier 330 has a fixed or standardized size that can accommodate semiconductor dies 294 and 304 of various sizes that are singulated from one or more semiconductor wafers 290 or 300. In one embodiment, the carrier 330 has a circular shape with a diameter of 330 mm. In another embodiment, the carrier 330 is a rectangle having a width of 560 mm and a length of 600 mm.

The size and size of the standardized carrier (carrier 330) is selected during the design of the processing device to facilitate the development of a manufacturing line that is uniform for all back-end semiconductor fabrication of semiconductor devices. The carrier 330 remains fixed in size regardless of the size and type of semiconductor package to be fabricated. For example, the semiconductor die 294 can have a size of 10 mm by 10 mm and is disposed on a standardized carrier 330. Alternatively, the semiconductor die 294 may have a size of 20 mm by 20 mm and be disposed on the same standardized carrier 330. Thus, the standardized carrier 330 can process semiconductor dies 294 and 304 of any size, which allows subsequent semiconductor processing devices to be standardized to a common carrier, i.e., regardless of die size or incoming wafer size. The semiconductor package device can be designed and configured for a standard carrier that utilizes a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 330 is reduced or eliminated for the size of the wafer or the size of the incoming wafer. Demand for dedicated semiconductor production lines to reduce manufacturing costs and capital risks. A flexible manufacturing line can be implemented by selecting a predetermined carrier size for use with semiconductor dies of any size from all semiconductor wafers.

In Figure 9e, the semiconductor die 294 from Figure 9c is oriented with the insulating layer 316 oriented toward the carrier 330, mounted to the carrier 330 and the interface layer 332 using, for example, a pick and place operation. Semiconductor die 294 is mounted to interface layer 332 of carrier 330 to form a reconstituted or reconfigured wafer 336. In an embodiment, insulating layer 316 is embedded within interface layer 332. For example, the active surface 312 of the semiconductor die 294 can be coplanar with the surface 334 of the interface layer 332. In another embodiment, insulating layer 316 is mounted over interface layer 332 such that active surface 312 of semiconductor die 294 is biased relative to interface layer 332.

The reconstituted wafer 336 can be processed into many types of semiconductor packages, including fan-in WLCSP, recombination or eWLCSP, fan-out WLCSP, flip chip package, 3D package such as PoP, or other semiconductor packages. The reconstituted wafer 336 is configured according to the specifications of the resulting semiconductor package. In one embodiment, the semiconductor die 294 is disposed on the carrier 330 in a high density configuration, i.e., 300 [mu]m or less, for processing the fan-in device. A semiconductor die 294 separated by a gap or distance D9 between the semiconductor dies 294 is disposed over the carrier 330. The distance D9 between the semiconductor dies 294 is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the distance D9 between the semiconductor dies 294 is 50 [mu]m or less. In another embodiment, the distance D9 between the semiconductor dies 294 is 100 μm or less. The distance D9 between the semiconductor dies 294 on the carrier 330 is optimized for manufacturing the semiconductor packages at the lowest unit cost.

9f shows a plan view of a reconstituted wafer 336 in which semiconductor die 294 is mounted to carrier 330 or over carrier 330. The carrier 330 is of a standardized shape and size and thus constitutes a standardized carrier. Carrier 330 has a capacity for semiconductor dies of various sizes and numbers that are singulated from semiconductor wafers of various sizes. In an embodiment, the carrier 330 is rectangular in shape and has a width W3 of 560 mm and a length L3 of 600 mm. In another embodiment, the carrier 330 is rectangular in shape and has a width W3 of 330 mm and a length L3 of 330 mm. In another embodiment, the carrier 330 is circular in shape and has a diameter of 330 mm.

The number of semiconductor dies 294 disposed over the carrier 330 depends on the size of the semiconductor die 294 and the distance D9 between the semiconductor dies 294 within the structure of the reconstituted wafer 336. The number of semiconductor dies 294 mounted to the carrier 330 can be greater than, less than, or equal to the number of semiconductor dies 294 that are singulated from the semiconductor wafer 290. The larger surface area carrier 330 accommodates more semiconductor grains 294 and reduces manufacturing costs because each reconstituted wafer 336 processes more semiconductor grains 294. In one example, semiconductor wafer 290 has a diameter of 300 mm, and an amount of about 600 individual 10 mm by 10 mm semiconductor dies 294 are formed on semiconductor wafer 290. Semiconductor die 294 is singulated from one or more semiconductor wafers 290. The carrier 330 is, for example, a length L3 which is prepared to have a standard width W3 of 560 mm and a standard of 600 mm. The carrier 330 having a width W3 of 560 mm is sized to accommodate a number of semiconductor dies 294 having a size of 10 mm by 10 mm and a distance D9 of 200 μm spaced across the width W3 of the carrier 330. The carrier 330 having a length L3 of 600 mm is sized to accommodate a number of approximately 58 sizes having a size of 10 mm by 10 mm and spaced apart by a distance of 200 μm across the length L3 of the carrier 330. Semiconductor die 294. Thus, the width W3 of the carrier 330 multiplied by the length L3 of the surface area accommodates an amount of about 3,000 semiconductor dies 294 having a size of 10 mm by 10 mm and a gap of 200 μm or distance D9 between the semiconductor dies 294. Semiconductor dies 294 may be placed on carrier 330 at a gap of less than 200 [mu]m or distance D9 between semiconductor dies 294 to increase the density of semiconductor dies 294 on carrier 330 and further reduce processing of semiconductor crystals. The cost of the grain 294.

An automated pick and place apparatus is used to prepare the reconstituted wafer 336 according to the number and size of the semiconductor dies 294 and according to the size of the carrier 330. For example, the semiconductor die 294 is selected to have a size of 10 mm by 10 mm. The carrier 330 has a size of, for example, a standard of 560 mm width W3 and 600 mm length L3. The automated equipment is programmed with the dimensions of semiconductor die 294 and carrier 330 to facilitate processing of reconstituted wafer 336. After singulating the semiconductor wafer 290, a first semiconductor die 294 is selected by the automated pick and place device. A first semiconductor die 294 is mounted to the carrier 330 in a position determined by the programmable automated pick and place device on the carrier 330. A second semiconductor die 294 is selected by the automated pick and place device, placed on the carrier 330, and disposed in a first column on the carrier 330. The distance D9 between adjacent semiconductor dies 294 is programmed into the automated pick and place apparatus and is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the gap or distance D9 between adjacent semiconductor dies 294 on carrier 330 is 200 [mu]m. A third semiconductor die 294 is selected by the automated pick and place device, placed on the carrier 330, and disposed on the carrier 330 at a distance D9 of 200 μm apart from an adjacent semiconductor die 294. In a column. The pick and place operation is repeated until a first column of approximately 54 semiconductor dies 294 is across the width W3 of the carrier 330 is set to stop.

Another semiconductor die 294 is selected by the automated pick and place device, placed on carrier 330, and disposed in a second column of carrier 330 adjacent to the first column. The distance D9 between the adjacent rows of semiconductor dies 294 is pre-selected and programmed into the automated pick-and-place device. In one embodiment, the distance D9 between the semiconductor die 294 of a first column and the semiconductor die 294 of a second column is 200 μm. The pick and place operation is repeated until approximately 58 columns of semiconductor dies 294 are disposed across the length L3 of the carrier 330. The standardized carrier (having a width W3 of 560 mm and a carrier 330 of length L3 of 600 mm) accommodates approximately 54 rows and 58 columns of 10 mm by 10 mm semiconductor die 294 for a total of approximately 3,000 semiconductor die 294 disposed at On the carrier 330. The pick and place operation is repeated until the carrier 330 is partially or completely filled with the semiconductor die 294. The automated pick and place apparatus can mount semiconductor dies of any size on the carrier 330 to form a reconstituted wafer 336 under a standardized carrier such as carrier 330. The reconstituted wafer 336 can then be processed using a backend processing device that is standardized for the carrier 330.

Figure 9g shows a plan view of a reconstituted wafer 338 in which the semiconductor die 304 is mounted to the carrier 330 or over the carrier 330. As with the reconstituted wafer 336, the same standardized carrier 330, or a standardized carrier having the same dimensions as the carrier 330, is used to process the reconstituted wafer 338. Any configuration of semiconductor dies on a reconstituted wafer can be supported by carrier 330. The number of semiconductor dies 304 disposed over the carrier 330 depends on the size of the semiconductor dies 304 and the distance D10 between the semiconductor dies 304 within the structure of the reconstituted wafer 338. The number of semiconductor dies 304 mounted to the carrier 330 may be greater than, less than, or equal to the semiconductor singulated from the semiconductor wafer 300. The number of grains 304. The larger surface area carrier 330 accommodates more semiconductor die 304 and reduces manufacturing costs because each reconstituted wafer 338 processes more semiconductor die 304.

In one example, semiconductor wafer 300 has a diameter of 200 mm, and an amount of about 1,000 individual 5 mm by 5 mm semiconductor dies 304 are formed on semiconductor wafer 300. Semiconductor die 304 is singulated from one or more semiconductor wafers 300. The carrier 330 is, for example, a length L3 which is prepared to have a standard width W3 of 560 mm and a standard of 600 mm. The carrier 330 having a width W3 of 560 mm is sized to accommodate a number of about 70 semiconductor dies 304 having a width D3 across the width of the carrier 330 having a size of 5 mm by 5 mm and a distance D10 spaced apart by 200 μm. The carrier 330 having a length L3 of 600 mm is sized to accommodate a number of about 115 semiconductor dies 304 having a size L5 of 5 mm by 5 mm across the length L3 of the carrier 330 and spaced apart by a distance D10 of 200 μm. Thus, the width W3 of the carrier 330 multiplied by the length L3 of the surface area accommodates approximately 12,000 semiconductor dies 304 having a size of 5 mm by 5 mm and spaced apart by a distance D10 of 200 μm. The semiconductor die 304 can be placed on the carrier 330 at a gap of less than 200 μm or a distance D10 between the semiconductor dies 304 to increase the density of the semiconductor die 304 on the carrier 330 and further reduce processing of the semiconductor crystal. The cost of the pellets 304.

An automated pick and place apparatus is used to prepare the reconstituted wafer 338 based on the number and size of the semiconductor dies 304 and according to the dimensions of the carrier 330. For example, the semiconductor die 304 is selected to have a size of 5 mm by 5 mm. The carrier 330 has a size of, for example, a width W3 of 560 mm and a length L3 of 600 mm. The automated equipment is programmed with the dimensions of semiconductor die 304 and carrier 330 to facilitate processing of reconstituted wafer 338. After singulating the semiconductor wafer 300, a first semiconductor die 304 is applied by the automated pick and place device. select. A first semiconductor die 304 is mounted to the carrier 330 in a position on the carrier 330 that is determined by the programmable automated pick-and-place device. A second semiconductor die 304 is selected by the automated pick and place device, placed on carrier 330, and disposed in a first column on carrier 330 at a distance D10 from first semiconductor die 304. The distance D10 between adjacent semiconductor dies 304 is programmed into the automated pick and place apparatus and is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the gap or distance D10 between adjacent semiconductor dies 304 on the carrier 330 is 200 [mu]m. A third semiconductor die 304 is selected by the automated pick and place device, placed on the carrier 330, and disposed in the first column on the carrier 330. The pick and place operation is repeated until approximately 107 semiconductor dies 304 of a column are disposed across the width W3 of the carrier 330.

Another semiconductor die 304 is selected by the automated pick and place device, placed on carrier 330, and disposed in a second column of carrier 330 adjacent to the first column. The distance D10 between adjacent rows of semiconductor dies 304 is preselected and programmed into the automated pick and place apparatus. In one embodiment, the distance D10 between the semiconductor die 304 of a first column and the semiconductor die 304 of a second column is 200 μm. The pick and place operation is repeated until approximately 115 columns of semiconductor die 304 are disposed across the length L3 of the carrier 330. The standardized carrier (having a width W3 of 560 mm and a carrier 330 of length L3 of 600 mm) accommodates approximately 107 rows and 115 columns of 5 mm by 5 mm semiconductor die 304 for a total of approximately 12,000 semiconductor die 304 disposed at On the carrier 330. The pick and place operation is repeated until the carrier 330 is partially or completely filled with the semiconductor die 304. The automated pick and place apparatus can mount semiconductor dies of any size on the carrier 330 to form a reconstituted wafer 338 under a standardized carrier such as carrier 330. Reconstituted wafer 338 can be utilized and used The same carrier 330 of the reconstituted wafer 336 and the same back end processing equipment are processed for processing.

Both the reconstituted wafer 336 from Figure 9f and the reconstituted wafer 338 from Figure 9g use the same carrier 330 or a carrier of the same standardized size for both reconstituted wafers 336 and 338. The processing equipment designed for the back end processing of the reconstituted wafers is standardized for the carrier 330, thereby being able to process any configuration of the reconstituted wafer formed on the carrier 330, and being placed on the carrier 330. Semiconductor dies of any size. Because both reconstituted wafers 336 and 338 use the same standardized carrier 330, the reconstituted wafers can be processed on the same manufacturing line. Thus, one of the purposes of the standardized carrier 330 is to simplify the equipment required to fabricate a semiconductor package.

In another example, the reconstituted wafer 338 includes semiconductor dies 294 and 304, wherein each of the semiconductor dies 294 and 304 have the same size, and the semiconductor dies are derived from semiconductor crystals having different diameters. Round 290 and 300. The semiconductor wafer 290 has a diameter of 450 mm, and an amount of about 2,200 individual 8 mm by 8 mm semiconductor dies 294 are formed on the semiconductor wafer 290. The semiconductor die 294 having a size of 8 mm by 8 mm is singulated from one or more semiconductor wafers 290. In addition, the semiconductor wafer 300 has a diameter of 300 mm, and an amount of about 900 individual 8 mm by 8 mm semiconductor dies 304 are formed on the semiconductor wafer 300. The semiconductor die 304 having a size of 8 mm by 8 mm is singulated from one or more semiconductor wafers 300. The carrier 330 is, for example, prepared to have a standard width 560 of 560 mm and a standard length L3 of 600 mm. The carrier 330 having a width W3 of 560 mm is sized to accommodate a semiconductor die 294 having a size of about 8 mm by 8 mm spaced apart by a distance of D9 or D10 spaced apart by a distance of 100 μm across the width W3 of the carrier 330. Or 304. Carrier 330 having a length of 560 mm L3 is made in size A semiconductor die 294 or 304 having a size of 8 mm by 8 mm spaced apart by a distance of about 100 distances D9 or D10 spaced apart by 100 μm is accommodated across the length L3 of the carrier 330. The width W3 of the carrier 330 multiplied by the length L3 of the surface area accommodates about 5,000 semiconductor dies 294 or 304 having a size of 8 mm by 8 mm spaced apart by a distance D9 or D10 of 100 μm. Semiconductor dies 294 and 304 may be placed on carrier 330 at a gap of less than 100 [mu]m or distance D9 or D10 between semiconductor dies 294 or 304 to increase the density of semiconductor dies 294 and 304 on carrier 330. And further reducing the cost of processing the semiconductor dies 294 and 304.

An automated pick and place apparatus is used to prepare the reconstituted wafer 338 based on the number and size of the semiconductor dies 294 and 304 and according to the size of the carrier 330. After singulating the semiconductor wafer 300, a first semiconductor die 294 or 304 is selected by the automated pick and place device. The 8 mm by 8 mm semiconductor die 294 or 304 may be derived from a semiconductor wafer 290 having a diameter of 450 mm or from a semiconductor wafer 300 having a diameter of 300 mm. Alternatively, the 8 mm by 8 mm semiconductor die is derived from another semiconductor wafer having a different diameter. A first semiconductor die 294 or 304 is mounted to the carrier 330 in a position on the carrier 330 that is determined by the programmed automated pick-and-place device. A second semiconductor die 294 or 304 is selected by the automated pick and place device, placed on the carrier 330, and disposed in a first column on the carrier 330. The distance D9 or D10 between adjacent semiconductor dies 294 or 304 is programmed into the automated pick and place apparatus and is selected according to the design and specifications of the semiconductor package to be processed. In an embodiment, the gap or distance D9 or D10 between adjacent semiconductor dies 294 or 304 on the carrier 330 is 100 μm. The pick and place operation is repeated until approximately 69 semiconductor dies 294 or 304 of a column are disposed across the width W3 of the carrier 330.

Another semiconductor die 294 or 304 is selected by the automated pick and place device, placed on carrier 330, and disposed in a second column of carrier 330 adjacent to the first column. In one embodiment, the distance D9 or D10 between the semiconductor dies 294 or 304 of a first column and the semiconductor dies 294 or 304 of a second column is 100 μm. The pick and place operation is repeated until approximately 74 columns of semiconductor dies 294 or 304 are disposed across the length L3 of the carrier 330. The standardized carrier (having a width W3 of 560 mm and a carrier 330 of length L3 of 600 mm) accommodates approximately 69 rows and 74 columns of 8 mm by 8 mm semiconductor dies 294 and 304 for a total of approximately 5,000 semiconductor dies 294 It is disposed on the carrier 330. The pick and place operation is repeated until the carrier 330 is partially or completely filled with the semiconductor die 294 or 304. Thus, reconstituted wafer 338 can include semiconductor dies 294 and 304 that are singulated from semiconductor wafers of any size. The size of the carrier 330 is independent of the size of the semiconductor dies 294 and 304 and is independent of the dimensions of the semiconductor wafers 290 and 300. Reconstituted wafer 338 can be processed using the same carrier 330 and the same backend processing equipment as used to process reconstituted wafer 336. For reconstituted wafers having the same size semiconductor die that are singulated from different sized incoming wafers, the standardized carrier 330 allows the same material to be used for each reconstituted wafer. Thus, the bill of materials for a reconstituted wafer 336 or 338 on the carrier 330 remains fixed. A consistent and predictable bill of materials allows for cost analysis and planning for improved semiconductor packaging.

In another embodiment, a reconstituted wafer 338 includes various semiconductor grain sizes disposed on the carrier 330. For example, a 10 mm by 10 mm semiconductor die 294 is mounted to the carrier 330, and a 5 mm by 5 mm semiconductor die 304 is mounted to the carrier 330 to form a reconstituted wafer 338. The reconstituted wafer contains half of various sizes on the same reconstituted wafer Conductor grain. In other words, a portion of the reconstituted wafer 338 includes semiconductor dies of one size, and another portion of the reconstituted wafer contains semiconductor dies of another size. A reconstituted wafer 338 comprising simultaneously different sized semiconductor dies 294 and 304 on carrier 330 utilizes and is used to process another reconstituted wafer 336 having uniform sized semiconductor dies disposed over carrier 330. The same backend processing device is used to process it.

In summary, the carrier 330 has a capacity for semiconductor dies of various sizes and numbers that are singulated from semiconductor wafers of various sizes. The size of the carrier 330 does not vary with the size of the semiconductor die being processed. The standardized carrier (carrier 330) is fixed in size and can accommodate semiconductor dies of various sizes. The size of the standardized carrier 330 is independent of the size of the semiconductor die or semiconductor wafer. More small semiconductor dies can be mounted on the carrier 330 than larger semiconductor dies. The number of semiconductor dies 294 or 304 mounted on the carrier 330 varies with the size of the semiconductor dies 294 or 304 and the spacing or distance D9 or D10 between the semiconductor dies 294 or 304. For example, carrier 330 having a length L3 and a width W3 accommodates a greater number of 5 mm by 5 mm semiconductor die 304 than semiconductor surface 294 of 10 mm by 10 mm over the surface area of carrier 330 over the surface area of carrier 330. . For example, carrier 330 holds approximately 3,000 10 mm by 10 mm semiconductor dies, or approximately 12,000 5 mm by 5 mm semiconductor dies. The size and shape of the carrier 330 remains fixed and independent of the size of the semiconductor die 294 or 304 or the semiconductor wafer 290 or 300 from which the semiconductor die 294 or 304 is singulated. The carrier 330 provides resiliency to fabricate the reconstituted wafers 336 and 338 using a common set of processing equipment into many different types of semiconductors having different sized semiconductor dies 294 and 304 from different sized semiconductor wafers 290 and 300. Package.

Figure 9h shows a process for fabricating a semiconductor package using carrier 330. Processing device 340 is used to perform backend processes on semiconductor dies, such as deposition of encapsulants and insulating layers, deposition of conductive layers, bump bonding, reflow, marking, singulation, and other backend processes . Processing device 340 is designed for the size and shape of a standardized carrier such as carrier 330. Processing device 340 is compatible with carrier 330 because the mechanical and electrical components of processing device 340 are customized for the standardized size and shape of carrier 330.

Processing device 340 is controlled by control system 342. Control system 342 can be a software program or algorithm that is used to configure processing device 340 based on the size and shape of the semiconductor die on carrier 330. Control system 342 is programmed and customized for processing device 340 to process each of the different reconstituted wafers formed on standardized carrier 330, such as reconstituted wafers 336 and 338.

By standardizing the size of the carrier 330, the processing device 340 can remain fixed because the size of the carrier 330 does not change with the size of the semiconductor die and the size of the semiconductor wafer. Control system 342 uses various algorithms for each reconstituted wafer on carrier 330. For example, control system 342 can be utilized to optimize the spacing on carrier 330 during the initial pick and place operation of semiconductor die 294. The specifications of the reconstituted wafer 336 are entered into the control system 342. Control system 342 is programmed to control processing device 340 to pick up individual semiconductor dies 294 and place semiconductor dies 312 over carrier 330 at a distance D9 to form recombined wafer 336. The reconstituted wafer 336 includes, for example, a semiconductor die 294 of 10 mm by 10 mm and a standard size carrier 330 of width W3 and length L3. Processing device 340 is configured to utilize control system 342 to perform a backend process on reconstituted wafer 336 on carrier 330. Control system 342 manages processing device 340 to follow the 10 mm by 10 mm ruler The in-line semiconductor die 294 and the standard sized carrier 330 perform deposition and other fabrication steps.

Control system 342 allows processing device 340 to be customized for each reconstituted wafer on standardized carrier 330. Processing device 340 does not need to be reconstructed for a different size of semiconductor die. After processing the reconstituted wafer 336, processing device 340 is prepared to process another reconstituted wafer having the same or different semiconductor grain sizes and spacings on carrier 330. The specifications of the reconstituted wafer 338 are entered into the control system 342. Control system 342 is programmed to control processing device 340 to pick up individual semiconductor dies 304 and place semiconductor dies 304 onto carrier 330 at a distance D10 to form reconstituted wafer 338. The reconstituted wafer 338 includes, for example, a 5 mm by 5 mm semiconductor die 304 and a standard sized carrier 330 having a width W3 and a length L3. Processing device 340 is configured to utilize control system 342 to perform a backend process on reconstituted wafer 338 on carrier 330. Control system 342 manages processing device 340 to perform deposition and other fabrication steps in accordance with the 5 mm by 5 mm sized semiconductor die 304 and standard sized carrier 330.

Processing device 340 remains fixed regardless of whether processing device 340 processes reconstituted wafers 336 or 338, or other reconstituted wafers on standardized carrier 330. Control system 342 is programmable and processing device 340 is readily adaptable to any reconstituted wafer using carrier 330. Accordingly, the mechanical and physical characteristics of the processing device 340 are designed to take into account the physical characteristics of the standardized carrier 330, while the processing device 340 is also programmable with the control system 342 for any configuration of the semiconductor die on the carrier 330. Execute the process.

Processing device 340 is used to fabricate various semiconductor packages from a reconstituted wafer on carrier 330. For example, processing device 340 can be utilized to process reconstituted wafer 336 or 338 It becomes a fan-in WLCSP, recombination or eWLCSP, fan-out WLCSP, flip chip package, 3D package such as PoP, or other semiconductor package. Control system 342 is used to perform the back end manufacturing steps in accordance with the semiconductor package to be fabricated to modify and control the operation of processing device 340. Accordingly, processing device 340 can be utilized to fabricate each of the semiconductor packages described herein. Processing device 340 can be utilized across a plurality of product manufacturing lines that share carrier 330 of the same size. Thus, the cost associated with changes in the size of the semiconductor die, the size of the semiconductor wafer, and the type of semiconductor package can be reduced. The investment risk in the processing device 340 is reduced because in the case where the carrier 330 is standardized, the design of the processing device 340 is simplified.

In Figure 9i, an encapsulant or molding compound 344 is deposited on a semiconductor using a paste printing, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicator. Above the die 294 and the carrier 330. The encapsulant 344 can be a polymer composite such as an epoxy with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulant 344 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. In another embodiment, the encapsulant 344 is an insulation or deposited by printing, spin coating, spray coating, vacuum or pressure lamination under heating or without heating, or other suitable process. a dielectric layer comprising one or more layers of a photosensitive low curing temperature dielectric resistor, a photosensitive composite resist, a laminated compound film, an insulating paste with a filler, a solder mask resist film, a liquid or particle molding A compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg, or other dielectric material having similar insulating and structural properties. In one embodiment, the encapsulant 344 is a low temperature curing photosensitive dielectric polymer that cures at less than 200 ° C with or without an insulating filler.

In particular, the encapsulant 344 is disposed along the side surface 324 of the semiconductor die 294 and thus covers each side surface 324 of the semiconductor die 294. Thus, the encapsulant 344 covers or contacts at least four surfaces of the semiconductor die 294, that is, the four side surfaces 324 of the semiconductor die 294. The encapsulant 344 also covers the back surface 310 of the semiconductor die 294. The encapsulant 344 protects the semiconductor die 294 from degradation due to exposure to photons from light or other radiation. In one embodiment, the encapsulant 344 is opaque and dark or black in color. Figure 9i shows a composite substrate or reconstituted wafer 336 covered by an encapsulation 344. The encapsulant 344 can be utilized with a laser marked reconstituted wafer 336 for alignment and singulation. The encapsulant 344 is formed over the back surface 310 of the semiconductor die 294 and may be thinned in a subsequent backgrinding step. The encapsulant 344 can also be deposited such that the encapsulant 344 is coplanar with the back surface 310 and thus does not cover the back surface 310 of the semiconductor die 294.

In Figure 9j, a back surface 346 of the encapsulant 344 utilizes a grinder 345 to perform a lapping operation to planarize and reduce a thickness of the encapsulant 344. A chemical etch can also be utilized to remove and planarize the encapsulant 344 and form a flat back surface 347. In one embodiment, a thickness of the encapsulant 344 is maintained overlying the back surface 310 of the semiconductor die 294. In one embodiment, the thickness of the encapsulant 344 remaining over the back surface 310 of the semiconductor die 294 after deposition or back grinding ranges from about 170 to 230 μm or less. In another embodiment, the thickness of the encapsulant 344 remaining over the back surface 310 of the semiconductor die 294 ranges from about 5 to 150 [mu]m. A surface 348 of the encapsulant 344 opposite the back surface 346 is disposed over the carrier 330 and the interface layer 332 such that the surface 348 of the encapsulant 344 can be coplanar with the active surface 312 of the semiconductor die 294.

Figure 9k depicts an alternative backgrinding step in which the encapsulant 344 is finished All are removed from the back surface 310 of the semiconductor die 294. After the polishing operation in Figure 9k is completed, the back surface 310 of the semiconductor die 294 is exposed. A thickness of the semiconductor die 294 can also be reduced by the back grinding operation. In one embodiment, the semiconductor die 294 has a thickness of 225-305 [mu]m or less. After the back grinding step, a cleaning process is performed to remove contamination from the back surface 310 of the semiconductor die 294 and from the back surface of the reconstituted wafer 336. The cleaning process is a wet or dry cleaning process that is performed prior to application of a backside protective layer. The cleaning process improves adhesion of the backside protective layer to the reconstituted wafer 336.

In FIG. 91, an insulating layer, a protective layer or a back protective layer 349 is formed over the encapsulant 344 and the back surface 310 of the semiconductor die 294 after completion of the back grinding step in FIG. 9k. The back protective layer 349 is one or more layers of photosensitive low curing temperature dielectric resistor, photosensitive composite resist, laminated compound film, resin matrix composite sheet with filler or glass fiber fabric, with filler and glass fiber fabric. Resin matrix composite sheet, insulating paste with filler, solder mask resist film, liquid molding compound, particle molding compound, polyimine, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, pre Dip, or other dielectric material with similar insulating and structural properties. The backside protective layer 349 is deposited by printing, spin coating, spray coating, vacuum or pressure lamination with or without heating, or other suitable process. In one embodiment, the backside protective layer 349 is a low temperature curing photosensitive dielectric polymer that cures at less than 200 ° C with or without an insulating filler. The backside protective layer 349 is a backside protective layer and provides mechanical protection to the semiconductor die 294 and is protected from light. In an embodiment, the backside protective layer 349 has a thickness ranging from about 5 to 150 [mu]m. Alternatively, the backside protective layer 349 is a metal layer such as a Cu foil applied to a back side of the reconstituted wafer 336. Back protection layer 349 is in contact with semiconductor The back surface 310 of the die 294 conducts heat from the semiconductor die 294, thereby improving the thermal performance of the device.

The carrier 330 and the interface layer 332 are removed by chemical etching, mechanical peeling, CMP, mechanical polishing, thermal baking, UV light, laser scanning, or wet stripping to expose the insulating layer 316, Conductive layer 314, and surface 348 of encapsulant 344.

In FIG. 9m, an insulating or protective layer 350 is formed over the insulating layer 316 and the conductive layer 314 by PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 350 may be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. In one embodiment, the insulating layer 350 is a photosensitive dielectric polymer that cures at a low temperature of less than 200 °C. In one embodiment, the insulating layer 350 is formed within the footprint of the semiconductor die 294 and does not extend beyond the footprint of the semiconductor die 294 to over the surface 348 of the encapsulant 344. In other words, the peripheral region of an adjacent semiconductor die 294 of the semiconductor die 294 does not have the insulating layer 350. In another embodiment, an insulating layer 350 is formed over the insulating layer 316, the semiconductor die 294, and the surface 348 of the encapsulant 344, and one of the insulating layers 350 is over the surface 348 of the encapsulant 344. Part of it is removed by an etching process using a patterned photoresist layer or by LDA. A portion of insulating layer 350 is removed by an etching process using a patterned photoresist layer or by LDA to form opening 352 to expose conductive layer 314.

In FIG. 9n, a conductive layer 354 is formed over the insulating layer 350 and the conductive layer 314 by a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. . Conductive layer 354 can be one or more layers of Al, Cu, Sn, Ti, Ni, Au, Ag, or other suitable electrically conductive material. A portion of the conductive layer 354 is along The insulating layer 350 extends horizontally parallel to the active surface 312 of the semiconductor die 294 to laterally redistribute the electrical interconnect to the conductive layer 314. Conductive layer 354 operates as an RDL for the electrical signal of semiconductor die 294. Conductive layer 354 is formed over a footprint of semiconductor die 294 and does not extend beyond the footprint of semiconductor die 294 to over surface 348 of encapsulant 344. In other words, the peripheral region of an adjacent semiconductor die 294 of semiconductor die 294 does not have conductive layer 354 such that surface 348 of an encapsulant 344 remains exposed from conductive layer 354. A portion of conductive layer 354 is electrically connected to conductive layer 314. Other portions of conductive layer 354 are electrically or electrically isolated depending on the connection of semiconductor die 294.

An insulating or protective layer 356 is formed over the insulating layer 350 and the conductive layer 354 by PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 356 may be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. In one embodiment, the insulating layer 356 is a photosensitive dielectric polymer that cures at a low temperature of less than 200 °C. In one embodiment, the insulating layer 356 is formed within the footprint of the semiconductor die 294 and does not extend beyond the footprint of the semiconductor die 294 to over the encapsulant 344. In other words, the peripheral region of an adjacent semiconductor die 294 of the semiconductor die 294 is free of the insulating layer 356 such that the surface 348 of the encapsulant 344 remains exposed from the insulating layer 356. In another embodiment, the insulating layer 356 is formed over the insulating layer 316, the semiconductor die 294, and the encapsulant 344, and a portion of the insulating layer 350 above the encapsulant 344 is utilized by a The etching process of the patterned photoresist layer is removed by LDA. A portion of insulating layer 350 is removed by an etching process using a patterned photoresist layer or by LDA to form opening 358 to expose conductive layer 354.

In Figure 9o, after the final passivation, a conductive layer 360 is utilized. PVD, CVD, evaporation, electrolytic plating, electroless plating, or other suitable metal deposition process is formed over the exposed portions of conductive layer 354 and over insulating layer 356. Conductive layer 360 can be Al, Cu, Sn, Ni, Au, Ag, W, or other suitable electrically conductive material. Conductive layer 360 is a UBM that is electrically connected to conductive layers 354 and 314. UBM 360 can be a stack of multiple metals with an adhesive layer, a barrier layer, and a seed or wetting layer. The adhesive layer is formed over the conductive layer 354 and may be Ti, TiN, TiW, Al or Cr. The barrier layer is formed over the adhesive layer and may be Ni, NiV, Pt, Pd, TiW, Ti or CrCu. The barrier layer inhibits Cu from diffusing into the active surface 312 of the semiconductor die 294. The seed layer is formed over the barrier layer and may be Cu, Ni, NiV, Au, or Al. UBM 360 provides a low resistance interconnect to conductive layer 354, as well as a solder diffusion barrier and a seed layer for solder wettability.

A conductive bump material is deposited over conductive layer 360 by an evaporation, electrolytic plating, electroless plating, ball dropping, or screen printing process. In one embodiment, the bump material is deposited using a ball drop stencil, i.e., no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with an optional fluxing solvent. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is bonded to conductive layer 360 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 362. In some applications, bumps 362 are reflowed a second time to improve electrical contact to conductive layer 360. The bumps 362 can also be compression bonded or thermocompression bonded to the conductive layer 360. Bumps 362 represent a type of interconnect structure that can be formed over conductive layer 360. The interconnect structure can also use bonding wires, conductive paste, stud bumps, micro bumps, or It is another electrical interconnection. The laser mark can be performed before or after the formation of the bump or after the removal of the carrier 330.

Insulation layers 350 and 356, conductive layers 354 and 360, and bumps 362 collectively form a stacked interconnect structure 366 formed over semiconductor die 294 and within a footprint of semiconductor die 294. The peripheral region of an adjacent semiconductor die 294 of semiconductor die 294 does not have interconnect structure 366 such that surface 348 of encapsulant 344 remains exposed from interconnect structure 366. The stacked interconnect structure 366 can include only one RDL or conductive layer, such as conductive layer 354, and an insulating layer, such as insulating layer 350. Additional insulating layers and RDL may be formed over insulating layer 356 prior to forming bumps 362 to provide additional vertical and horizontal electrical connections across the package in accordance with the design and function of semiconductor die 294.

In Figure 9p, the semiconductor die 294 is singulated into individual eWLCSPs 372 by a saw blade or laser cutting tool 370 through the encapsulant 344. The eWLCSP 372 was electrically tested before or after singulation. The reconstituted wafer 336 is singulated into an eWLCSP 372 to leave a thin layer of encapsulant 344 over the side surface 324 of the semiconductor die 294. Alternatively, the reconstituted wafer 336 is singulated to completely remove the encapsulant 344 from the side surface 324.

FIG. 10 shows an eWLCSP 372 having an encapsulant over sidewalls 324 of semiconductor die 294 and a backside protection layer 349 over back surface 310 of semiconductor die 294 after singulation. The semiconductor die 294 is electrically coupled to the bumps 362 through the conductive layers 314, 354, and 360 for interconnecting the exterior of the interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. A back protective layer 349 is formed over the back surface 310 of the semiconductor die 294 for mechanical protection and protection Protection against deterioration due to exposure to photons from light or other radiation.

The encapsulant 344 covers the side surface 324 of the semiconductor die 294 to protect the semiconductor die 294 from degradation due to exposure to photons from light or other radiation. For eWLCSP 372, the thickness of the encapsulant 344 above the side surface 324 is less than 150 [mu]m. In one embodiment, the eWLCSP 372 has a dimension of 4.595 mm in length x 4.025 mm in width x 0.470 mm in height and a pitch of 0.4 mm for the bumps 362, wherein the semiconductor die 294 It has a length of 4.445 mm and a width of 3.875 mm. In another embodiment, the thickness of the encapsulant 344 over the side surface 324 of the semiconductor die 294 is 75 [mu]m or less. The eWLCSP 372 has a size of 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and a pitch of 0.5 mm for the bumps 362, wherein the semiconductor die 294 has a length. 6.0 mm × 6.0 mm in width × 0.470 mm in height. In yet another embodiment, the eWLCSP 372 has a size of 5.92 mm in length x 5.92 mm in width x 0.765 mm in height and a pitch of 0.5 mm for the bumps 362, wherein the semiconductor die The 294 series has a size of 5.75 mm in length x 5.75 mm in width x 0.535 mm in height. In another embodiment, the thickness of the encapsulant 344 over the side surface 324 of the semiconductor die 294 is 25 [mu]m or less. In yet another embodiment, the eWLCSP 372 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 372 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 330, which reduces the cost of equipment and materials for the eWLCSP 372. The eWLCSP 372 is manufactured in a larger amount using a standardized carrier 330, thereby simplifying the process and reducing unit cost.

Figure 11 shows a pattern having a top surface 310 of semiconductor die 294. The backside protective layer 349 and the exposed sidewalls 324 of the semiconductor die 294 are replaced by an eWLCSP 380. Semiconductor die 294 is electrically coupled to bumps 362 through conductive layers 314, 354, and 360 for interconnecting the exterior of interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. A backside protective layer 349 is formed over the back surface 310 of the semiconductor die 294 for mechanical protection and protection against degradation due to exposure to photons from light or other radiation. The encapsulant 344 is completely removed from the side surface 324 of the semiconductor die 294 during singulation to expose the side surface 324. The length and width of the eWLCSP 380 are the same as the length and width of the semiconductor die 294. In one embodiment, the eWLCSP 380 has a dimension of approximately 4.4 mm in length x 3.9 mm in width with a pitch of 0.35-0.50 mm for the bumps 362. In another embodiment, the eWLCSP 380 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 380 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 330, which reduces the cost of equipment and materials for the eWLCSP 380. The eWLCSP 380 is manufactured in a larger amount using a standardized carrier 330, thereby simplifying the process and reducing unit cost.

FIG. 12 shows another eWLCSP 384 in which an encapsulation system is formed over the back surface 310 and sidewalls 324 of the semiconductor die 294. Semiconductor die 294 is electrically coupled to bumps 362 through conductive layers 314, 354, and 360 for interconnecting the exterior of interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. After the lapping operation shown in FIG. 9j, the encapsulant 344 is maintained over the back surface 310 of the semiconductor die 294. After singulation, the encapsulant 344 is maintained over the side surface 324 of the semiconductor die 294 for mechanical protection and protection from exposure to light or It is the deterioration caused by other emitted photons. Thus, the encapsulant 344 is formed over the five sides of the semiconductor die 294, that is, over the four side surfaces 324 and above the back surface 310. The encapsulant 344 over the back surface 310 of the semiconductor die 294 eliminates the need for a backside protective layer or backside layer, thereby reducing the cost of the eWLCSP 384.

For eWLCSP 384, the thickness of the encapsulant 344 above the side surface 324 is less than 150 [mu]m. In one embodiment, the eWLCSP 384 has a dimension of 4.595 mm in length x 4.025 mm in width x 0.470 mm in height and a pitch of 0.4 mm for the bumps 362, wherein the semiconductor die 294 It has a length of 4.445 mm and a width of 3.875 mm. In another embodiment, the thickness of the encapsulant 344 over the side surface 324 of the semiconductor die 294 is 75 [mu]m or less. The eWLCSP 384 has a size of 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and a pitch of 0.5 mm for the bumps 362, wherein the semiconductor die 294 has length over 6.0 mm × 6.0 mm in width × 0.470 mm in height. In yet another embodiment, the eWLCSP 384 has a size of 5.92 mm in length x 5.92 mm in width x 0.765 mm in height and a pitch of 0.5 mm for the bumps 362, wherein the semiconductor die The 294 series has a size of 5.75 mm in length x 5.75 mm in width x 0.535 mm in height. In another embodiment, the thickness of the encapsulant 344 above the side surface 324 of the semiconductor die 294 is 25 [mu]m or less. In yet another embodiment, the eWLCSP 384 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 384 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 330, which reduces the cost of equipment and materials for the eWLCSP 384. The eWLCSP 384 is manufactured in a larger amount using a standardized carrier 330, thereby simplifying the process and reducing unit cost.

Figure 13 shows another eWLCSP 386 having a back encapsulant and exposed sidewalls. Semiconductor die 294 is electrically coupled to bumps 362 through conductive layers 314, 354, and 360 for interconnecting the exterior of interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. After the lapping operation shown in FIG. 9j, the encapsulant 344 is maintained over the back surface 310 of the semiconductor die 294. The encapsulant 344 over the back surface 310 of the semiconductor die 294 eliminates the need for a backside protective layer or backside layer, thereby reducing the cost of the eWLCSP 386. During singulation, the encapsulant 344 is completely removed from the side surface 324 of the semiconductor die 294 to expose the side surface 324. The length and width of the eWLCSP 386 are the same as the length and width of the semiconductor die 294. In one embodiment, the eWLCSP 386 has a size of approximately 4.445 mm in length x 3.875 mm in width, having a pitch of 0.35-0.50 mm for the bumps 362. In another embodiment, the eWLCSP 386 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 386 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 330, which reduces the cost of equipment and materials for the eWLCSP 386. The eWLCSP 386 is manufactured in a larger amount using a standardized carrier 330, thereby simplifying the process and reducing unit cost.

FIG. 14 shows another eWLCSP 388 having an exposed back surface 310 of semiconductor die 294 and sidewalls 324. Semiconductor die 294 is electrically coupled to bumps 362 through conductive layers 314, 354, and 360 for interconnecting the exterior of interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulant 344 is completely removed from the back surface 310 of the semiconductor die 294 during the lapping operation shown in Figure 9k. The encapsulant 344 is completely from the side surface 324 of the semiconductor die 294 during singulation. It is removed to expose the side surface 324. In eWLCSP 388, no encapsulant 344 remains covering a surface of semiconductor die 294. The length and width of the eWLCSP 388 are the same as the length and width of the semiconductor die 294. In one embodiment, the eWLCSP 388 has a dimension of approximately 4.4 mm in length x 3.9 mm in width with a pitch of 0.35-0.50 mm for the bumps 362. The eWLCSP 388 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 330, which reduces the cost of equipment and materials for the eWLCSP 388. The eWLCSP 388 is manufactured in a larger amount using a standardized carrier 330, thereby simplifying the process and reducing unit cost.

Figures 15a-15k depict a process for forming a recombination or embedded fan-in WLCSP in relation to Figures 1 and 2a-2c. Continuing from Figure 9b, Figure 15a shows a cross-sectional view of a portion of a semiconductor wafer 290. Conductive layer 314 is formed over active surface 312 of semiconductor die 294. An insulating layer 316 is formed over the active surface 312 and the conductive layer 314, wherein the openings are formed through the insulating layer 316 to expose the conductive layer 314.

In FIG. 15a, an insulating layer 410 is formed over the insulating layer 316 and the conductive layer 314. The insulating layer 410 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. The insulating layer 410 is deposited by PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable process. In one embodiment, the insulating layer 410 is a photosensitive dielectric polymer that cures at a low temperature of less than 200 °C. In an embodiment, insulating layer 410 is formed over insulating layer 316, semiconductor die 294, and overlying semiconductor material 292 outside of a footprint of semiconductor die 294. In other words, the peripheral region of an adjacent semiconductor die 294 of the semiconductor die 294 includes an insulating layer 410. A portion of the insulating layer 410 is formed by an exposure or development process, LDA, Etching, or other suitable process, is removed to form openings 412 to expose conductive pads 314.

In FIG. 15b, a conductive layer 414 is formed on the insulating layer 410 and the conductive layer 314 by a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. on. Conductive layer 414 can be one or more layers of Al, Cu, Sn, Ti, Ni, Au, Ag, or other suitable electrically conductive material. A portion of conductive layer 414 extends horizontally along insulating layer 410 and parallel to active surface 312 of semiconductor die 294 to laterally redistribute the electrical interconnect to conductive layer 314. Conductive layer 414 operates as an RDL for the electrical signal of semiconductor die 294. Conductive layer 414 is formed over a footprint of semiconductor die 294 and does not extend beyond the footprint of semiconductor die 294. In other words, the peripheral region of an adjacent semiconductor die 294 of the semiconductor die 294 does not have a conductive layer 414. A portion of conductive layer 414 is electrically connected to conductive layer 314. Other portions of conductive layer 414 are electrically or electrically isolated depending on the connection of semiconductor die 294.

An insulating or protective layer 416 is formed over the insulating layer 410 and the conductive layer 414 by PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 416 may be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. In one embodiment, the insulating layer 416 is a photosensitive dielectric polymer that cures at a low temperature of less than 200 °C. In an embodiment, insulating layer 416 is formed over semiconductor die 294 and overlying semiconductor semiconductor material 292 outside of a footprint of semiconductor die 294. In another embodiment, the insulating layer 416 is formed within the footprint of the semiconductor die 294 and does not extend beyond the footprint of the semiconductor die 294. A portion of the insulating layer 416 is removed by an etching process using a patterned photoresist layer or by LDA Divide to form opening 418 to expose conductive layer 414.

In FIG. 15c, semiconductor wafer 290 is singulated into individual semiconductor dies 294 by dicing 296 using a saw or laser cutting tool 420. The semiconductor wafer 290 is also singulated by the insulating layer 316, the insulating layer 410, and the insulating layer 416 to form sidewalls or side surfaces 422. Side surface 422 includes sidewalls of semiconductor die 294 and insulating layers 316, 410, and 416. Individual semiconductor dies 294 can be inspected and electrically tested for identification of KGD after singulation.

In Figure 15d, the semiconductor die 294 from Figure 15c is mounted to the carrier 430 and the interface layer 432, for example, using a pick and place operation with the active surface 312 oriented toward the carrier 430. Semiconductor die 294 is mounted to interface layer 432 of carrier 430 to form a reconstituted or reconfigured wafer 436.

Carrier 430 can be a circular or rectangular panel (greater than 300 mm) having a capacity for a plurality of semiconductor dies 294. Carrier 430 can have a surface area greater than the surface area of semiconductor wafer 290 or 300. A larger carrier reduces the manufacturing cost of the semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or carrier being processed.

To further reduce manufacturing costs, the size of the carrier 430 is selected independently of the size of the semiconductor die 294 or the size of the semiconductor wafers 290 and 300. In other words, carrier 430 has a fixed or standardized size that can accommodate semiconductor dies 294 of various sizes that are singulated from one or more semiconductor wafers 290 and 300. In one embodiment, the carrier 430 is circular with a diameter of 330 mm. In another embodiment, the carrier 430 has a 560 mm The width and the rectangle of the length of 600mm. The semiconductor die 294 can have a size of 10 mm by 10 mm that is disposed on a standardized carrier 430. Alternatively, the semiconductor die 294 can have a size of 20 mm by 20 mm that is disposed on the same standardized carrier 430. Thus, the standardized carrier 430 can process semiconductor dies 294 of any size, which allows subsequent semiconductor processing devices to be standardized to a common carrier, i.e., independent of die size or incoming wafer size. The semiconductor package device can be designed and configured for a standard carrier that utilizes a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 430 reduces manufacturing costs and capital risk by reducing or eliminating the need for a dedicated semiconductor production line based on die size or incoming wafer size. A flexible manufacturing line can be implemented by selecting a predetermined carrier size for use with semiconductor dies of any size from all semiconductor wafers.

The reconstituted wafer 436 can be processed into many types of semiconductor packages including fan-in WLCSP, recombination or eWLCSP, fan-out WLCSP, flip chip package, 3D package such as PoP, or other semiconductor package. The reconstituted wafer 436 is configured according to the specifications of the resulting semiconductor package. In one embodiment, the semiconductor die 294 is disposed on the carrier 430 in a high density configuration, i.e., 300 [mu]m or less, for processing the fan-in device. The semiconductor die 294 is disposed over the carrier 430 with a gap or distance D12 between the semiconductor dies 294. The distance D12 between the semiconductor dies 294 is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the distance D12 between the semiconductor dies 294 is 50 μm or less. In another embodiment, the distance D12 between the semiconductor dies 294 is 100 μm or less. Inter-semiconductor on carrier 430 The distance D12 between the dies 294 is optimized for manufacturing the semiconductor packages at the lowest unit cost.

Figure 15e shows a plan view of a reconstituted wafer 436 in which semiconductor die 294 is disposed over carrier 430. Carrier 430 is a standardized shape and size having a capacity for semiconductor dies of various sizes and numbers that are singulated from semiconductor wafers of various sizes. In an embodiment, the carrier 430 is rectangular in shape and has a width W4 of 560 mm and a length L4 of 600 mm. The number of semiconductor dies 294 mounted to the carrier 430 can be greater than, less than, or equal to the number of semiconductor dies 294 that are singulated from the semiconductor wafer 290. The larger surface area carrier 430 accommodates more semiconductor grains 294 and reduces manufacturing costs because each reconstituted wafer 436 processes more semiconductor grains 294.

The standardized carrier (carrier 430) is fixed in size and can accommodate semiconductor dies of various sizes. The size of the standardized carrier 430 is independent of the size of the semiconductor die or semiconductor wafer. More small semiconductor dies can be mounted on the carrier 430 than larger semiconductor dies. For example, carrier 430 holds a greater number of 5 mm by 5 mm grains than the number of 10 mm by 10 mm grains above the surface area of carrier 430 over the surface area of carrier 430.

For example, a semiconductor die 294 having a size of 10 mm by 10 mm is disposed on the carrier 430 at a distance D12 of 200 μm between adjacent semiconductor dies 294. The number of semiconductor dies 294 that are singulated from the semiconductor wafer 290 is about 600 semiconductor dies, wherein the semiconductor wafer 290 has a diameter of 300 mm. The number of 10 mm by 10 mm semiconductor dies 294 that can be mounted on carrier 430 is about 3,000 semiconductor dies. Alternatively, the semiconductor die 294 having a size of 5 mm by 5 mm is disposed on the carrier 430 at a distance D12 of 200 μm between adjacent semiconductor dies 294. In the case where the semiconductor wafer 290 has a diameter of 200 mm, the number of semiconductor dies 294 that are singulated from the semiconductor wafer 290 is about 1,000 semiconductor dies. The number of 5 mm by 5 mm semiconductor dies 294 that can be mounted on carrier 430 is about 12,000 semiconductor dies.

The size of the carrier 430 does not vary with the size of the semiconductor die being processed. The number of semiconductor dies 294 disposed on the carrier 430 varies with the size of the semiconductor dies 294 and the spacing or distance D12 between the semiconductor dies 294. The size and shape of the carrier 430 remains fixed and independent of the size of the semiconductor die 294 or the semiconductor wafer 290 from which the semiconductor die 294 is singulated. Carrier 430 and reconstituted wafer 436 provide resiliency to fabricate many different semiconductor die 294 having different sizes of semiconductor wafers 290 from different sizes using a common processing device such as processing device 340 from Figure 9h. Type of semiconductor package.

In Figure 15f, an encapsulant or molding compound 438 is deposited on the semiconductor using a paste printing, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicator. Above the die 294 and the carrier 430. The encapsulant 438 can be a polymer composite such as an epoxy with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulant 438 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. In another embodiment, the encapsulant 438 is an insulation or deposited by printing, spin coating, spray coating, vacuum or pressure lamination under heating or without heating, or other suitable process. a dielectric layer comprising one or more layers of a photosensitive low curing temperature dielectric resistor, a photosensitive composite resist, a laminated compound film, Insulating paste with filler, solder mask resist film, liquid or particulate molding compound, polyimine, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg, or the like Dielectric materials of insulating and structural properties. In one embodiment, the encapsulant 438 is a low temperature curing photosensitive dielectric polymer that cures at less than 200 ° C with or without an insulating filler.

In particular, the encapsulant 438 is disposed along the side surface 422 of the semiconductor die 294 and thus covers each side surface 422 of the semiconductor die 294 and the insulating layers 316, 410, and 416. Thus, the encapsulant 438 covers or contacts at least four surfaces of the semiconductor die 294, that is, the four side surfaces 422 of the semiconductor die 294. The encapsulant 438 also covers the back surface 310 of the semiconductor die 294. The encapsulant 438 protects the semiconductor die 294 from degradation due to exposure to photons from light or other radiation. In one embodiment, the encapsulant 438 is opaque and dark or black in color. Encapsulant 438 can be utilized for laser marking reconstituted wafer 436 for alignment and singulation. In another embodiment, the encapsulant 438 is deposited such that the encapsulant 438 is coplanar with the back surface 310 of the semiconductor die 294 and thus does not cover the back surface 310.

In Figure 15g, a back surface 440 of the encapsulant 344 is milled 442 to perform a polishing operation to planarize and reduce a thickness of the encapsulant 438. A chemical etch can also be utilized to remove and planarize the encapsulant 438 and form a flat back surface 444. In one embodiment, a thickness of the encapsulant 438 is maintained overlying the back surface 310 of the semiconductor die 294. In another embodiment, the back surface 310 of the semiconductor die 294 is exposed during the back grinding step. A thickness of the semiconductor die 294 can also be reduced by the polishing operation. In one embodiment, the semiconductor die 294 has a thickness of 225 to 305 [mu]m or less.

Figure 15h shows a reconstituted wafer 436 covered by an encapsulant 438. In one embodiment, the thickness of the encapsulant 438 remaining over the back surface 310 of the semiconductor die 294 after deposition or backgrinding ranges from about 170 to 230 [mu]m or less. In another embodiment, the thickness of the encapsulant 438 remaining over the semiconductor die 294 of the back surface 310 ranges from about 5 to 150 [mu]m. A surface 448 of the encapsulant 438 opposite the back surface 440 is disposed over the carrier 430 and the interface layer 432.

In FIG. 15i, the carrier 430 and the interface layer 432 are removed by chemical etching, mechanical peeling, CMP, mechanical grinding, hot baking, UV light, laser scanning, or wet stripping, The insulating layer 416, the conductive layer 414, and the surface 448 of the encapsulant 438 are exposed.

In FIG. 15j, after final re-passivation, a conductive layer 460 is formed by PVD, CVD, evaporation, electrolytic plating, electroless plating, or other suitable metal deposition process to form an exposed layer 414. Above the portion and above the insulating layer 416. Conductive layer 460 can be Al, Cu, Sn, Ni, Au, Ag, W, or other suitable electrically conductive material. Conductive layer 460 is a UBM that is electrically connected to conductive layers 414 and 314. UBM 460 can be a stack of multiple metals with an adhesion layer, a barrier layer, and a seed or wetting layer. The adhesive layer is formed over the conductive layer 414 and may be Ti, TiN, TiW, Al or Cr. The barrier layer is formed over the adhesive layer and may be Ni, NiV, Pt, Pd, TiW, Ti or CrCu. The barrier layer inhibits Cu from diffusing into the active surface 312 of the semiconductor die 294. The seed layer is formed over the barrier layer and may be Cu, Ni, NiV, Au or Al. UBM 460 provides a low resistance interconnect to conductive layer 414, as well as a solder diffusion barrier and a seed layer for solder wettability.

A conductive bump material utilizes an evaporation, electrolytic plating, and electroless electricity A plating, ball drop, or screen printing process is deposited over the conductive layer 460. In one embodiment, the bump material is deposited using a ball drop stencil, i.e., no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with an optional fluxing solvent. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is bonded to conductive layer 460 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 462. In some applications, bumps 462 are reflowed a second time to improve electrical contact to conductive layer 460. The bumps 462 can also be compression bonded or thermocompression bonded to the conductive layer 460. Bump 462 represents a type of interconnect structure that can be formed over conductive layer 460. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects. The laser mark can be performed before or after the formation of the bump or after the removal of the carrier 430.

The insulating layers 410 and 416, the conductive layers 414 and 460, and the bumps 462 all form a stacked interconnect structure 466 formed over the semiconductor die 294 and within a footprint of the semiconductor die 294. The peripheral region of an adjacent semiconductor die 294 of semiconductor die 294 does not have interconnect structure 466, and surface 448 of encapsulant 438 remains exposed from interconnect structure 466. The stacked interconnect structure 466 can include only one RDL or conductive layer, such as conductive layer 414, and an insulating layer, such as insulating layer 410. Additional insulating layers and RDL may be formed over insulating layer 416 prior to forming bumps 462 to provide additional vertical and horizontal electrical connections across the package depending on the design and function of semiconductor die 294.

In Figure 15k, the semiconductor die 294 is singulated into individual eWLCSPs 472 by a saw blade or laser cutting tool 470 through the encapsulant 438. Reconstituted wafer 436 It is singulated into eWLCSP 472 to leave a thin layer of encapsulant 438 over side surface 422 of semiconductor die 294 and insulating layers 316, 410 and 416. Alternatively, the reconstituted wafer 436 is singulated to completely remove the encapsulant 438 from the side surface 422. The eWLCSP 472 was electrically tested before or after singulation.

FIG. 16 shows an eWLCSP 472 having an encapsulant formed over the back surface 310 and sidewalls 422 of the semiconductor die 294. Semiconductor die 294 is electrically coupled to bumps 462 through conductive layers 314, 414, and 460 for interconnecting the exterior of interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. After the lapping operation shown in Figure 15g, the encapsulant 438 is maintained over the back surface 310 of the semiconductor die 294. The encapsulant 438 is maintained over the side surface 422 of the semiconductor die 294 and over the insulating layers 316, 410 and 416 for mechanical protection and protection against degradation due to exposure to photons from light or other radiation. . Thus, the encapsulant 438 is formed over the five sides of the semiconductor die 294, that is, over the four side surfaces 422 and above the back surface 310. The encapsulant 438 over the back surface 310 of the semiconductor die 294 eliminates the need for a backside protective layer or backside layer, thereby reducing the cost of the eWLCSP 472.

For eWLCSP 472, the thickness of the encapsulant 438 above the side surface 422 is less than 150 [mu]m. In one embodiment, the eWLCSP 472 has a size of 4.595 mm in length x 4.025 mm in width x 0.470 mm in height and a pitch of 0.4 mm for the bumps 462, wherein the semiconductor die 294 It has a length of 4.445 mm and a width of 3.875 mm. In another embodiment, the thickness of the encapsulant 438 above the side surface 324 of the semiconductor die 294 is 75 μm or less. The eWLCSP 472 has a size of 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and one for the bump 462. A pitch of 0.5 mm in which the semiconductor die 294 has a size of 6.0 mm in length × 6.0 mm in width × 0.470 mm in height. In yet another embodiment, the eWLCSP 472 has a size of 5.92 mm in length x 5.92 mm in width x 0.765 mm in height and a pitch of 0.5 mm for the bumps 462, wherein the semiconductor die The 294 series has a size of 5.75 mm in length x 5.75 mm in width x 0.535 mm in height. In another embodiment, the thickness of the encapsulant 438 above the side surface 422 is 25 [mu]m or less. In yet another embodiment, the eWLCSP 472 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 472 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 430, which reduces the cost of equipment and materials for the eWLCSP 472. The eWLCSP 472 is manufactured in a larger amount using a standardized carrier 430, thereby simplifying the process and reducing unit cost.

17 shows another eWLCSP 480 having an encapsulation 438 over the back surface 310 of the semiconductor die 294 and exposed sidewalls 422 of the semiconductor die 294. Semiconductor die 294 is electrically coupled to bumps 462 through conductive layers 314, 414, and 460 for interconnecting the exterior of interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. After the lapping operation shown in Figure 15g, the encapsulant 438 is maintained over the back surface 310 of the semiconductor die 294. The encapsulant 438 over the back surface 310 of the semiconductor die 294 eliminates the need for a backside protective layer or backside layer, thereby reducing the cost of the eWLCSP 480. The encapsulant 438 is completely removed from the side surface 422 of the semiconductor die 294 and the insulating layers 316, 410, and 416 during singulation to expose the side surface 422. The length and width of the eWLCSP 480 are the same as the length and width of the semiconductor die 294. In one embodiment, the eWLCSP 480 has a thickness of approximately 4.445 mm over the length. The 3.875 mm size has a pitch of 0.35-0.50 mm for the bumps 462. In another embodiment, the eWLCSP 480 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 480 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 430, which reduces the cost of equipment and materials for the eWLCSP 480. The eWLCSP 480 is manufactured in a larger amount using a standardized carrier 430, thereby simplifying the process and reducing unit cost.

Figure 18 shows an eWLCSP 482 having an encapsulant over the sidewall 422 of the semiconductor die 294 and a backside protective layer 484 after singulation. Semiconductor die 294 is electrically coupled to bumps 462 through conductive layers 314, 414, and 460 for interconnecting the exterior of interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulant 438 is completely removed from the back surface 310 of the semiconductor die 294. A backside insulating layer or backside protective layer 484 is formed over the back surface 310 of the semiconductor die 294 for mechanical protection and protection against degradation due to exposure to photons from light or other radiation. The back protective layer 484 comprises one or more layers of photosensitive low curing temperature dielectric resistors, photosensitive composite resists, laminated compound films, resin matrix composite sheets with filler or fiberglass fabric, with fillers and fiberglass fabrics. Resin matrix composite sheet, insulating paste with filler, solder mask resist film, liquid molding compound, particle molding compound, polyimine, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, pre Dip, or other dielectric material with similar insulating and structural properties. Backside protective layer 484 is deposited by printing, spin coating, spray coating, vacuum or pressure lamination with or without heating, or other suitable process. In one embodiment, the backside protective layer 484 is a low temperature curing photosensitive medium that cures at less than 200 ° C with or without an insulating filler. Electrical polymer. Backside protective layer 484 provides mechanical protection to semiconductor die 294 and is protected from light. In an embodiment, the backside protective layer 484 has a thickness ranging from about 5 to 150 [mu]m. Alternatively, the backside protective layer 484 is a metal layer, such as a Cu foil, applied to a back side of the reconstituted wafer 436. The backside protective layer 484 contacts the back surface 310 of the semiconductor die 294 to conduct heat from the semiconductor die 294 and improve the thermal performance of the device.

The encapsulant 438 covers the side surface 422 of the semiconductor die 294 to protect the semiconductor die 294 from degradation due to exposure to photons from light or other radiation. For eWLCSP 482, the thickness of the encapsulant 438 above the side surface 422 is less than 150 [mu]m. In one embodiment, the eWLCSP 482 has a size of 4.595 mm in length x 4.025 mm in width x 0.470 mm in height and a pitch of 0.4 mm for the bumps 462, wherein the semiconductor die 294 It has a length of 4.445 mm and a width of 3.875 mm. In another embodiment, the thickness of the encapsulant 438 above the side surface 422 is 75 [mu]m or less. The eWLCSP 482 has a size of 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and a pitch of 0.5 mm for the bump 462, wherein the semiconductor die 294 has a length. 6.0 mm × 6.0 mm in width × 0.470 mm in height. In yet another embodiment, the eWLCSP 482 has a size of 5.92 mm in length x 5.92 mm in width x 0.765 mm in height and a pitch of 0.5 mm for the bumps 462, wherein the semiconductor die The 294 series has a size of 5.75 mm in length x 5.75 mm in width x 0.535 mm in height. In another embodiment, the thickness of the encapsulant 438 above the side surface 422 is 25 [mu]m or less. In yet another embodiment, the eWLCSP 482 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 482 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 430. This reduces the cost of equipment and materials used for eWLCSP 482. The eWLCSP 482 is manufactured in a larger amount using a standardized carrier 430, thereby simplifying the process and reducing unit cost.

Figure 19 shows an alternative eWLCSP 488 having a backside protective layer 484 and exposed sidewalls 422. Semiconductor die 294 is electrically coupled to bumps 462 through conductive layers 314, 414, and 460 for interconnecting the exterior of interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulant 438 is completely removed from the back surface 310 of the semiconductor die 294. A backside insulating layer or backside protective layer 484 is formed over the back surface 310 of the semiconductor die 294 for mechanical protection and protection against degradation due to exposure to photons from light or other radiation. The encapsulant 438 is completely removed from the side surface 324 of the semiconductor die 294 during singulation to expose the side surface 422. The length and width of the eWLCSP 488 are the same as the length and width of the semiconductor die 294. In one embodiment, the eWLCSP 488 has a dimension of approximately 4.4 mm in length x 3.9 mm in width having a pitch of 0.35-0.50 mm for the bumps 462. In another embodiment, the eWLCSP 488 can be formed to have a length of 14 mm and a width of 14 mm. The eWLCSP 488 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 430, which reduces the cost of equipment and materials for the eWLCSP 488. The eWLCSP 488 is manufactured in a larger amount using a standardized carrier 430, thereby simplifying the process and reducing unit cost.

Figure 20 shows an eWLCSP 486 similar to eWLCSP 482, but without a conductive layer 460. Bumps 462 are formed directly on conductive layer 414. The bump material is bonded to conductive layer 414 using a suitable attachment or bonding process. In an embodiment, the bump material The material is reflowed by heating the material beyond its melting point to form a ball or bump 462. In some applications, bumps 462 are reflowed a second time to improve electrical contact to conductive layer 414. The bumps 462 can also be compression bonded or thermocompression bonded to the conductive layer 414. Bump 462 represents a type of interconnect structure that can be formed over conductive layer 414. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects.

Semiconductor die 294 is electrically coupled to bumps 462 through conductive layers 314 and 414 for interconnection through the exterior of interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulant 438 is completely removed from the back surface 310 of the semiconductor die 294. A backside protective layer 484 is formed over the back surface 310 of the semiconductor die 294 for mechanical protection and protection against degradation due to exposure to photons from light or other radiation. The encapsulant 438 covers the side surface 422 of the semiconductor die 294 to protect the semiconductor die 294 from degradation due to exposure to photons from light or other radiation. For the eWLCSP 486, the thickness of the encapsulant 438 above the side surface 422 is less than 150 [mu]m. The eWLCSP 486 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 430, which reduces the cost of equipment and materials for the eWLCSP 486. The eWLCSP 486 is manufactured in a larger amount using a standardized carrier 430, thereby simplifying the process and reducing unit cost.

21 shows another eWLCSP 490 having an exposed back surface 310 and sidewalls 422 of semiconductor die 294. Semiconductor die 294 is electrically coupled to bumps 462 through conductive layers 314, 414, and 460 for interconnecting the exterior of interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulant 438 is completely from the back surface of the semiconductor die 294 during the lapping operation shown in Figure 15g. 310 was removed. The encapsulant 438 is completely removed from the side surface 422 of the semiconductor die 294 during singulation to expose the side surface 422. The length and width of the eWLCSP 490 are the same as the length and width of the semiconductor die 294. In one embodiment, the eWLCSP 490 has a dimension of approximately 4.4 mm in length x 3.9 mm in width having a pitch of 0.35-0.50 mm for the bumps 462. The eWLCSP 490 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 430, which reduces the cost of equipment and materials for the eWLCSP 490. The eWLCSP 490 is manufactured in a larger amount using a standardized carrier 430, thereby simplifying the process and reducing unit cost.

Figures 22a-22m relate to Figures 1 and 2a-2c depicting a process for forming a fan-in eWLCSP having an encapsulant over the sidewalls of the semiconductor die and having an exposed back surface. 22a is a cross-sectional view showing a portion of a semiconductor wafer 500 having a base substrate material 502, such as tantalum, niobium, gallium arsenide, indium phosphide, or tantalum carbide, for structural use. support. A plurality of semiconductor dies or features 504 separated by a non-active inter-die wafer region or scribe 506 are formed over wafer 500. The scribe line 506 provides a dicing area to singulate the semiconductor wafer 500 into individual semiconductor dies 504. In one embodiment, the semiconductor wafer 500 is 200-300 mm in diameter. In another embodiment, the semiconductor wafer 500 is 100-450 mm in diameter. The semiconductor wafer 500 may have any diameter before the singulated semiconductor wafer 500 becomes an individual semiconductor die 504.

Each semiconductor die 504 has a back or non-active surface 508 and an active surface 510 comprising an analog or digital circuit implemented to be formed within the die and based on the die Active components, passive components, conductive layers, and dielectric layers that are electrically connected and functionally interconnected. For example, the circuit can include a formation on the active surface 510 One or more transistors, diodes, and other circuit components within the system to implement analog or digital circuits such as DSPs, ASICs, memories, or other signal processing circuits. Semiconductor die 504 may also include IPDs such as inductors, capacitors, and resistors for RF signal processing.

A conductive layer 512 is formed over the active surface 510 by PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 512 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 512 operates as a contact pad that is electrically connected to circuitry on active surface 510. As shown in FIG. 22a, the conductive layer 512 can be formed as a contact pad that is spaced apart from each other by a first distance or a sidewall 514 of the semiconductor die 504. Alternatively, the conductive layer 512 can be formed as a contact pad biased in a plurality of columns such that the contact pads of a first column are disposed a first distance apart from the edge 514 of the semiconductor die 504, and the first and the first A row of staggered second columns of contact pads are disposed a second distance apart from the edge 514 of the semiconductor die 504.

A first insulating or protective layer 516 is formed over the semiconductor die 504 and conductive layer 512 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 516 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer, or other dielectric material having similar structural and insulating properties. In one embodiment, the insulating layer 516 is a low temperature curing photosensitive dielectric polymer that cures at less than 200 ° C with or without an insulating filler. The insulating layer 516 covers and provides protection to the active surface 510. The insulating layer 516 is conformally applied over the conductive layer 512 and the active surface 510 of the semiconductor die 504 and does not extend over the edge 514 of the semiconductor die 504 or exceeds a coverage of the semiconductor die 504. Area. An adjacent semiconductor die of semiconductor die 504 There is no insulating layer 516 in the peripheral region of 504. A portion of the insulating layer 516 is removed by an LDA utilizing the laser 520 or by an etching process through a patterned photoresist layer to form an opening 522 in the insulating layer 516. Opening 522 is through insulating layer 516 to expose conductive layer 512 and is provided for subsequent electrical interconnection.

The semiconductor wafer 500 is electrically tested and inspected as part of a quality control process. Manual visual inspection and automated optical systems are used to perform inspections on the semiconductor wafer 500. The software can be utilized in automated optical analysis of the semiconductor wafer 500. The visual inspection method can utilize, for example, a scanning electron microscope, high intensity or ultraviolet light, or a metallographic microscope. The semiconductor wafer 500 is characterized by a structure including warpage, thickness variation, surface particles, irregularities, cracks, delamination, and discoloration.

Active and passive components within the semiconductor die 504 are tested at the wafer level for electrical performance and circuit function. Each semiconductor die 504 is tested for functional and electrical parameters using a probe or other test device. A probe system is used to electrically contact the nodes or contact pads 512 on each of the semiconductor dies 504 and provide electrical stimulation to the contact pads. The semiconductor die 504 is responsive to the electrical stimuli, which are measured and compared to an expected response to test the function of the semiconductor die. These electrical tests may include circuit function, lead integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, critical current, leakage current, and operating parameters specific to the type of component. Inspection and electrical testing of the semiconductor wafer 500 enables the passed semiconductor die 504 to be designated as KGD for a semiconductor package.

In Figure 22b, a groove or channel 530 is cut into the base substrate material 502 within the scribe line 506 using a saw or laser cutting tool 532. The trench 530 is surrounded by a semi-conductive The peripheral region of the bulk crystal grains 504 extends. The width of the trench 530 is less than the width of the scribe line 506. In one embodiment, the saw blade 532 is selected to have a width that is less than a width of the cutting track 506. The saw blade 532 has a width that is less than about 1 [mu]m across the width of the cutting track 506. The width of the saw blade 532 is such that the trench 530 can be formed by being spaced apart from the edge 514 of the semiconductor die 504 by a distance D14. In one embodiment, the distance D14 between the trench 530 and the edge 514 is 0.5 [mu]m or larger. In another embodiment, the scribe line 506 is more than 1 [mu]m wider than the groove 530 or the saw blade 532. The trench 530 is partially formed through the base substrate material 502 and has a depth of 150 μm or less. In one embodiment, trench 530 has a depth of 60 [mu]m or less. The saw blade 532 is selected to have a particle size ranging from 1,500 to 3,500. The formation of trenches 530 constitutes a first dicing in a single granulation process for the steps of semiconductor wafer 500.

In FIG. 22c, semiconductor wafer 500 is singulated by dicing streets 506 using a saw or laser cutting tool 540 to separate semiconductor wafers 500 into individual semiconductor dies 504. The semiconductor wafer 500 is singulated by the trench 530 and transmitted through the base substrate material 502 in the scribe line 506. In one embodiment, the saw blade 540 is selected to have a particle size similar to the saw blade 532, i.e., having a particle size ranging from 1,500 to 3,500. In another embodiment, the saw blade 540 is selected to have a grain size that is thicker than the saw blade 532. A portion of the base substrate material 502 is removed by the saw blade 540 while leaving a portion of the trench 530 and the base substrate material 502 within the scribe line 506. A portion of the base substrate material 502 is maintained disposed on the sidewall 514 of the semiconductor die 504. The base substrate material 502 forms a seal ring around the semiconductor die 504.

In one embodiment, the saw blade 540 has a width that is less than the width of the saw blade 532 or less than the width of the groove 530. A width of the saw blade 540 is less than a width of the saw blade 532 At least 5 μm, and after singulation, a portion of the trench 530 remains in a peripheral region of the semiconductor die 504. The singulation of a second and thinner diced semiconductor wafer 500 produces a step cut or gap 544 formed in the base substrate material 502. The notch 544 is maintained in the base substrate material 502 in a peripheral region of the semiconductor die 504 by the use of a saw blade 540 that is thinner than the saw blade 532, through the singulation nature of the trench 530. In an embodiment, a distance D15 between the edge of the trench 530 and the side surface 542 is about 2.5 [mu]m. In another embodiment, the distance D15 is at least 0.5-1 [mu]m. The notches 544 extend along the four sides of the semiconductor die 504. In yet another embodiment, the trench 530 is completely removed such that the distance D15 is 0 [mu]m. A full laser cut or stealth laser cut is used to singulate across the entire width of the trench 530 through the trench 530. The singulation through the trenches 530 constitutes a second dicing in a single granulation process for the steps of the semiconductor wafer 500.

In an alternate embodiment, the grooves 530 are used for alignment inspection during singulation. The saw blade 540 has a width similar to the width of the saw blade 532 or a width similar to the groove 530. During singulation with a saw blade or laser cutting tool 540, a portion of the base substrate material 502 is within the scribe line 506 and removed within the trench 530. The singulation of the semiconductor wafer 500 using a saw blade 540 having a width similar to the saw blade 532 produces a flat sidewall 542. The trench 530 is completely removed during the singulation because the saw blade 540 is removed from the base substrate material 502 below the trench 530. The surface of the base substrate material 502 can be visually inspected to check the alignment of the singulated cut. After singulation with a similarly sized saw blade 540, a step or gap remaining in the base substrate material 502 indicates the alignment offset of the saw blade 540.

Figure 22d shows a carrier comprising a sacrificial base material such as tantalum, polymer, niobium oxide, glass, or other suitable low cost rigid material for structural support Or a temporary substrate 560. A via or double-sided tape 562 is formed over the carrier 560 as a temporary adhesive bonding film, etch stop layer, or heat release layer. With the insulating layer 516 oriented toward the carrier 560, the semiconductor die 504 is mounted to the carrier 560 and the interface layer 562 using, for example, a pick and place operation. Semiconductor die 504 is disposed over surface 564 of interface layer 562 and over carrier 560 to form a reconstituted or reconfigured wafer 566. In an embodiment, insulating layer 516 is embedded within interface layer 562. For example, active surface 510 of semiconductor die 504 is coplanar with surface 564 of interface layer 562. In another embodiment, the insulating layer 516 is mounted over the interface layer 562 such that the active surface 510 of the semiconductor die 504 is offset from the interface layer 562.

Carrier 560 can be a circular or rectangular panel having a capacity for a plurality of semiconductor dies 504. In one embodiment, carrier 560 is a 12 inch wafer. In another embodiment, carrier 560 is a panel having a width of 300 mm and a length of 300 mm. Carrier 560 can have a surface area that is greater than the surface area of semiconductor wafer 500. A larger carrier reduces the manufacturing cost of the semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. In another embodiment, carrier 560 is a standardized shape and size for the capacitance of various sizes and numbers of semiconductor dies that are singulated from semiconductor wafers of various sizes. The standardized carrier 560 is fixed in size and can accommodate semiconductor dies of various sizes. For example, the standardized carrier 560 is rectangular in shape and has a width of 560 mm and a length of 600 mm. The size of the standardized carrier 560 is independent of the size of the semiconductor die 504 or the semiconductor wafer 500. More small semiconductor dies can be mounted on the carrier 560 than larger semiconductor dies. For example, compared to the number of 10 mm by 10 mm grains above the surface area of the carrier 560, Carrier 560 accommodates a greater number of 5 mm by 5 mm grains above the surface area of carrier 560. Thus, the standardized carrier 560 can process semiconductor dies 504 of any size, which allows subsequent semiconductor processing devices to be standardized to a common carrier, i.e., regardless of die size or incoming wafer size. The semiconductor package device can be designed and configured for a standard carrier that utilizes a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 560 reduces manufacturing costs and capital risk by reducing or eliminating the need for a dedicated semiconductor production line based on die size or incoming wafer size. A flexible manufacturing line can be implemented by selecting a predetermined carrier size for use with semiconductor dies of any size from all semiconductor wafers.

Figure 22e shows a reconstituted wafer 566 having semiconductor dies 504 disposed over carrier 560. The reconstituted wafer 566 can be processed into many types of semiconductor packages including fan-in WLCSP, recombination or eWLCSP, fan-out WLCSP, flip chip package, 3D package such as PoP, or other semiconductor package. The reconstituted wafer 566 is configured according to the specifications of the resulting semiconductor package. In one embodiment, the semiconductor die 504 is disposed on the carrier 560 in a high density configuration, i.e., 500 [mu]m or less, for processing the fan-in device. A semiconductor die 504 that is separated by a gap between semiconductor dies 504 or a distance D16 is disposed over carrier 560. The distance D16 between the semiconductor dies 504 is selected according to the design and specifications of the semiconductor package to be processed. In one embodiment, the distance D16 between the semiconductor dies 504 is 500 μm or less. The distance D16 between the semiconductor dies 504 on the carrier 560 is optimized for manufacturing the semiconductor packages at the lowest unit cost.

An encapsulant or molding compound 570 is deposited onto the semiconductor die 504 by a paste printing, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicator. And around and above the carrier 560 and the interface layer 562. The encapsulant 570 can be a polymer composite such as an epoxy with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulant 570 is non-conductive and environmentally protects the semiconductor device from external elements and contaminants. In another embodiment, the encapsulant 570 is an insulation or deposited by printing, spin coating, spray coating, vacuum or pressure lamination under heating or without heating, or other suitable process. a dielectric layer comprising one or more layers of a photosensitive low curing temperature dielectric resistor, a photosensitive composite resist, a laminated compound film, an insulating paste with a filler, a solder mask resist film, a liquid or particle molding A compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg, or other dielectric material having similar insulating and structural properties. In one embodiment, the encapsulant 570 comprises a filler having a size of 55 [mu]m or less. In another embodiment, the encapsulant 570 comprises a filler having a size of 30 μm or less. In yet another embodiment, the encapsulant 570 is a low temperature curing photosensitive dielectric polymer that cures at less than 200 ° C with or without an insulating filler.

In particular, the encapsulant 570 is disposed along the side surface 542 and into the gap 544 to be disposed in a peripheral region of the semiconductor die 504. The encapsulant 570 is filled into the gap 544 and surrounds the four sidewalls of the semiconductor die 504. A surface 572 of the encapsulant 570 is coplanar with the active surface 510 of the semiconductor die 504. The encapsulant 570 also covers the back surface 508 of the semiconductor die 504. In one embodiment, a thickness of the encapsulant between the back surface 508 of the semiconductor die 504 and the back surface 574 of the encapsulant 570 is 50 μm or greater. Back of capsule 570 Surface 574 is thinned in a subsequent back grinding step. Alternatively, the encapsulant 570 is deposited such that the back surface 574 of the encapsulant 570 is coplanar with the back surface 508 of the semiconductor die 504 such that the encapsulant 570 does not cover the back surface 508.

In FIG. 22f, the carrier 560 and the interface layer 562 are removed by chemical etching, mechanical peeling, CMP, mechanical polishing, thermal baking, UV light, laser scanning, or wet stripping. The insulating layer 516, the conductive layer 512, and the surface 572 of the encapsulant 570 are exposed. The reconstituted wafer 566 is maintained in wafer form or in the form of a panel and constitutes a fan-in substrate. A thermal annealing process is applied to the reconstituted wafer 566 to facilitate outgassing. In one embodiment, the thermal annealing is performed for 30 minutes at 200 ° C or higher.

An insulating or protective layer 580 is formed over the insulating layer 516 and the conductive layer 512 by PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 580 may be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. In one embodiment, insulating layer 580 is a photosensitive dielectric polymer that cures at a low temperature of less than 200 °C. The insulating layer 580 is formed within the footprint of the semiconductor die 504 and does not extend beyond the footprint of the semiconductor die 504 onto the encapsulant 570. In other words, the peripheral region of an adjacent semiconductor die 504 of the semiconductor die 504 does not have an insulating layer 580 such that the encapsulant 570 remains exposed relative to the insulating layer 580. In another embodiment, an insulating layer 580 is formed over the insulating layer 516, the semiconductor die 504, and over the encapsulant 570.

A portion of insulating layer 580 is removed by an etching process using a patterned photoresist layer or by LDA to form opening 582 to expose conductive layer 512. An opening 582 is formed over the conductive layer 512 to provide electrical connection to the conductive layer 512. In a In an embodiment, opening 582 is formed to expose conductive layer 512 and a portion of insulating layer 516. The insulating layer 580 is completely removed from above the conductive layer 512. The insulating layer 580 does not overlap the conductive layer 512 and does not overlap the opening 522 in the insulating layer 516 over the conductive layer 512. Conductive layer 512 does not have an insulating layer 580. In another embodiment, the opening 582 is formed to expose the conductive layer 512 while leaving a portion of the insulating layer 580 disposed to contact the conductive layer 512. The insulating layer 580 is formed within the opening 522 in the insulating layer 516 over the conductive layer 512. The insulating layer 580 extends into the opening 522 in the insulating layer 516 and over the conductive layer 512.

In FIG. 22g, a conductive layer 584 is formed over the insulating layer 580 and the conductive layer 512 by a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolytic plating, and electroless plating. . Conductive layer 584 can be one or more layers of Al, Cu, Sn, Ti, Ni, Au, Ag, or other suitable electrically conductive material. A portion of conductive layer 584 extends horizontally along insulating layer 580 and parallel to active surface 510 of semiconductor die 504 to laterally redistribute the electrical interconnect to conductive layer 512. Conductive layer 584 operates as an RDL for the electrical signal of semiconductor die 504. The conductive layer 584 is formed over a footprint of the semiconductor die 504 and does not extend beyond the footprint of the semiconductor die 504 or over the encapsulant 570. In other words, the peripheral region of an adjacent semiconductor die 504 of the semiconductor die 504 does not have a conductive layer 584 such that the encapsulant 570 remains exposed relative to the conductive layer 584. In an embodiment, conductive layer 584 is formed to reach edge 514 of semiconductor die 504 and does not extend beyond the active region of semiconductor die 504. In another embodiment, the conductive layer 584 is formed by a distance DF from the edge 514 of the semiconductor die 504, wherein the distance D18 is greater than 0 [mu]m. A portion of the conductive layer 584 is electrically connected to the conductive layer 512. Other portions of conductive layer 584 are electrically or electrically isolated depending on the connection of semiconductor die 504.

In FIG. 22h, an insulating or protective layer 590 is formed over the insulating layer 580 and the conductive layer 584 by PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 590 may be one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating and structural properties. In an embodiment, the insulating layer 590 comprises the same material as the insulating layer 580. In another embodiment, the insulating layer 590 comprises a material different from the insulating layer 580, such as a material having a higher or lower coefficient of thermal expansion (CTE). In another embodiment, the insulating layer 590 is a photosensitive dielectric polymer that cures at a low temperature of less than 200 °C.

The insulating layer 590 is formed within the footprint of the semiconductor die 504 and does not extend beyond the footprint of the semiconductor die 504 beyond the edge 514 or over the encapsulant 570. The peripheral region of an adjacent semiconductor die 504 of the semiconductor die 504 does not have an insulating layer 590 such that the encapsulant 570 remains exposed relative to the insulating layer 590. In another embodiment, the insulating layer 590 is formed over the semiconductor die 504 and over a footprint of the semiconductor die 504 to the base substrate material 502 and does not extend to the encapsulant 570. on. An insulating layer 590 is formed over the base substrate material 502 around the semiconductor die 504 while the encapsulation system remains exposed relative to the insulating layer 590. In yet another embodiment, an insulating layer 590 is formed over the insulating layer 580, the semiconductor die 504, and the encapsulant 570. A portion of the insulating layer 590 is removed by an etching process using a patterned photoresist layer or by an LDA to form an opening to expose the conductive layer 584.

A conductive bump material is deposited over conductive layer 584 by an evaporation, electrolytic plating, electroless plating, ball dropping, or screen printing process. In one embodiment, the bump material is deposited using a ball drop stencil, i.e., no mask is required. The The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with an optional fluxing solvent. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is bonded to conductive layer 584 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 592. In some applications, bumps 592 are reflowed a second time to improve electrical contact to conductive layer 584. The bump 592 can also be compression bonded or thermocompression bonded to the conductive layer 584. Bump 592 represents a type of interconnect structure that can be formed over conductive layer 584. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects.

Insulating layers 580 and 590, conductive layer 584, and bumps 592 collectively form a fan-in bulk interconnect structure 594 formed over semiconductor die 504 and within a footprint of semiconductor die 504. The peripheral region of an adjacent semiconductor die 504 of the semiconductor die 504 does not have an interconnect structure 594 such that the encapsulant 570 remains exposed relative to the interconnect structure 594. Thus, interconnect structure 594 forms a fan-in interconnect structure. The stacked interconnect structure 594 can include only one RDL or conductive layer, such as conductive layer 584, and an insulating layer, such as insulating layer 590. Additional insulating layers and RDL may be formed over insulating layer 590 prior to forming bumps 592 to provide additional vertical and horizontal electrical connections across the package in accordance with the design and function of semiconductor die 504.

In FIG. 22i, a backgrinding tape 596 is applied over the active surface 510 of the semiconductor die 504 and overlies the interconnect structure 594 and bumps 592 of the reconstituted wafer 566. The reconstituted wafer 566 can be mounted to a support table with the back grinding strip 596 oriented toward the support table. A portion of the encapsulant 570 is from the back surface 574, optionally by utilizing the grinder 600 Back grinding, or removal by CMP, etching process, or LDA. The back grinding operation removes the encapsulant 570 from the back surface 508 of the semiconductor die 504 to reduce warpage of the reconstituted wafer 566. In one embodiment, the backgrinding operation completely removes the encapsulant 570 from above the semiconductor die 504 to expose the back surface 508 of the semiconductor die 504. After back grinding, a back surface 602 of the encapsulant 570 is coplanar with the back surface 508 of the semiconductor die 504. After the back grinding operation, the reconstituted wafer 566 has a reduced thickness. In an embodiment, a portion of the back surface 508 of the semiconductor die 504 is removed during the backgrinding operation to thin the semiconductor die 504. In one embodiment, the semiconductor die 504 has a thickness of 500 μm or less. Laser markings can be applied directly to the back surface 508 of the semiconductor die 504 for alignment and singulation.

In Figure 22j, a mounting strip, dicing tape, or support carrier 610 is applied to a back surface of the reconstituted wafer 566. The dicing tape 610 provides support to the reconstituted wafer 566 during subsequent fabrication steps and during singulation into individual semiconductor packages. Backgrinding tape 596 is removed from reconstituted wafer 566 as it is mounted to dicing tape 610.

In Figure 22k, the reconstituted wafer 566 is singulated into individual eWLCSPs 622 using a saw or laser cutting tool 620. The reconstituted wafer 566 is passed through the encapsulant 570 and passed through the dicing tape 610 to be singulated. The saw blade 620 does not cut through the base substrate material 502 of the semiconductor die 504. Since the reconstituted wafer 566 is singulated by the encapsulant 570 rather than passing through the base substrate material 502, the base substrate material 502 is less prone to cracking and breaking. The saw blade 620 is selected to have a width that is less than a gap between adjacent semiconductor dies 504. In one embodiment, the saw blade 620 is at least 20 [mu]m narrower than the gap between adjacent semiconductor dies 504. In another embodiment, the saw blade 620 is compared to the adjacent semiconductor die 504. The gap between them is narrow by 40-100 μm. Since the saw blade 620 is narrower than the gap between the dies 504, the encapsulant 570 remains covered to the side surface 542 after singulation of the reconstituted wafer 566. The thickness of the encapsulant 570 disposed over the surface 542 is shown as a thickness or distance D20. In one embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 is 0.5 [mu]m or greater. In another embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 ranges from 5 to 50 [mu]m. In yet another embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 is at least 10 [mu]m. Reconstituted wafer 566 can also be singulated using a single granulation process similar to the steps of the process illustrated in Figures 22b-22c. A groove is formed through the encapsulant 570 using a saw or laser cutting tool. The trench extends partially through the encapsulant 570 between the semiconductor dies 504. The groove constitutes a first cut in the single granulation process of the step. The reconstituted wafer 566 is singulated by a second cut in the single granulation process of the step, through the grooves in the encapsulant 570, to completely separate the individual eWLCSPs 622. After the singulation of the reconstituted wafer 566, the dicing tape 610 is removed from the eWLCSP 622.

Figure 221 shows an eWLCSP 622 having an encapsulant 570 covering a side surface 542 after singulation. Semiconductor die 504 is electrically coupled to bumps 592 through conductive layers 512 and 584 for interconnection through the exterior of interconnect structure 594. The electrical interconnections of interconnect structure 594 do not extend beyond a footprint of semiconductor die 504 and thus form a fan-in package. The process of fabricating the eWLCSP 622 improves yield by reducing the defects of the semiconductor die 504 by passing through a one-step single granulation process and the use of an encapsulant 570 that covers the sidewalls of the semiconductor die 504. The step cutting used during the singulation of the semiconductor wafer 500 reduces cracking and fracture of the active surface 510 of the semiconductor die 504. Trench 530 is formed prior to singulation of semiconductor wafer 500 to facilitate control of cracking and fracture of semiconductor die 504. Gap in the base substrate material 502 544 can also be utilized for alignment during singulation of semiconductor wafer 500. The single granulation process for the steps of the semiconductor wafer 500 improves yield by reducing damage to the semiconductor die 504.

The encapsulant 570 provides sidewall protection over the four sides of the semiconductor die 504 to mechanically strengthen the semiconductor die 504. The encapsulant 570 covers the side surface 542 and covers the base substrate material 502 surrounding the edge 514 of the semiconductor die 504. The encapsulant 570 protects the semiconductor die 504 during back grinding and singulation. The encapsulant 570 is singulated to separate the individual eWLCSPs 622 without passing through the base substrate material 502 or the semiconductor grains 504 for singulation. The encapsulant 570 disposed over the side surface 542 reduces cracking and fracture of the base substrate material 502 and the semiconductor die 504. In one embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 is 0.5 [mu]m or greater. In another embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 ranges from 5 to 50 [mu]m. Semiconductor die 504 is surrounded by a ring of base substrate material 502 around edge 514 of semiconductor die 504. The semiconductor die 504 and the base substrate material 502 are surrounded by a ring of an encapsulant 570. The ring of the encapsulant 570 has a thickness D22 between the notch 544 in the base substrate material 502 and the outer edge of the eWLCSP 622. In an embodiment, the thickness D22 is at least 0.5 μm.

The encapsulant 570 is removed from the back surface 508 of the semiconductor die 504 during the backgrinding process to reduce the thickness of the eWLCSP 622. The semiconductor die 504 is thinned during back grinding to reduce warpage of the eWLCSP 622. In one embodiment, the semiconductor die 504 has a thickness D21 of 500 μm or less. The reduced thickness of the encapsulant 570 and the semiconductor die 504 improves the reliability of the eWLCSP 622 after mounting the eWLCSP 622 to a substrate such as a PCB.

The eWLCSP 622 is a fan-in package with sidewall protection to strengthen the semiconductor die 504 without the need for a backside protective layer. The eWLCSP 622 can be manufactured at a lower cost without a back protection layer. Moreover, the exposed back surface 508 of the semiconductor die 504 allows for inspection of the semiconductor die 504 for crack and broken vision. The eWLCSP 622 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 560, which reduces the cost of equipment and materials for the eWLCSP 622. The eWLCSP 622 is manufactured in a larger amount using a standardized carrier 560, thereby simplifying the process and reducing unit cost.

Figure 22m shows a plan view of a back surface of the eWLCSP 622. The back surface 508 of the semiconductor die 504 is exposed from the encapsulant 570. The semiconductor die 504 is surrounded by a ring of an encapsulant 570 that covers the four side surfaces of the semiconductor die 504. In one embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 is 0.5 [mu]m or greater. In another embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 ranges from 5 to 50 [mu]m. The encapsulant 570 disposed over the side surface 542 reduces cracking and fracture of the base substrate material 502 and the semiconductor die 504. The encapsulant 570 improves yield by reducing damage to the semiconductor die 504 during processing and singulation into the eWLCSP 622.

23 shows an eWLCSP 630 having an encapsulant 570 over the sidewalls of the semiconductor die 504 and having an exposed back surface 508. Semiconductor die 504 is electrically coupled to bumps 592 through conductive layers 512 and 584 for interconnection through the exterior of interconnect structure 632. The electrical interconnections of interconnect structure 632 do not extend beyond a footprint of semiconductor die 504 and thus form a fan-in package. An insulating layer 590 is formed over the conductive layer 584 and the insulating layer 580. In addition, the insulating layer 590 of the eWLCSP 630 extends beyond a footprint of the semiconductor die 504 to cover A portion of the encapsulant 570 in a peripheral region of the semiconductor die 504. The insulating layer 590 is in contact with the surface 572 of the encapsulant 570 and extends over the encapsulant 570 by a distance D24 wherein the distance D24 is greater than 0 [mu]m. The overlap of insulating layer 590 with encapsulant 570 provides an improved seal between semiconductor die 504 and encapsulant 570. Since the insulating layer 590 extends over the encapsulant 570, the reliability of the eWLCSP 622 is improved.

The process of fabricating the eWLCSP 630 improves yield by reducing the defects of the semiconductor die 504 by passing through a one-step single granulation process and the use of an encapsulant 570 that covers the sidewalls of the semiconductor die 504. The step cutting used during the singulation of the semiconductor wafer 500 reduces cracking and fracture of the active surface 510 of the semiconductor die 504. Trench 530 is formed prior to singulation of semiconductor wafer 500 to facilitate control of cracking and fracture of semiconductor die 504. The notches 544 in the base substrate material 502 can also be utilized for alignment during singulation of the semiconductor wafer 500. The single granulation process for the steps of the semiconductor wafer 500 improves yield by reducing damage to the semiconductor die 504.

The encapsulant 570 provides sidewall protection over the four sides of the semiconductor die 504 to mechanically strengthen the semiconductor die 504. Semiconductor die 504 is surrounded by a ring of base substrate material 502 around edge 514 of semiconductor die 504. The semiconductor die 504 and the base substrate material 500 are surrounded by a ring of an encapsulant 570. The ring of the encapsulant 570 has a thickness D22 between the notch 544 in the base substrate material 502 and the outer edge of the eWLCSP 630. In an embodiment, the thickness D22 is at least 0.5 μm. The encapsulant 570 covers the side surface 542 and covers the base substrate material 502 that surrounds the edge 514 of the semiconductor die 504. The encapsulant 570 protects the semiconductor die 504 during back grinding and singulation. The encapsulant 570 is singulated to separate the individual eWLCSP 630 without passing through the substrate material 502 or The semiconductor die 504 is singulated. The encapsulant 570 disposed over the side surface 542 reduces cracking and fracture of the base substrate material 502 and the semiconductor die 504. In one embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 is 0.5 [mu]m or greater. In another embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 ranges from 5 to 50 [mu]m.

The encapsulant 570 is removed from the back surface 508 of the semiconductor die 504 during the back grinding process to reduce the thickness of the eWLCSP 630. The semiconductor die 504 is thinned during back grinding to reduce warpage of the eWLCSP 630. In one embodiment, the semiconductor die 504 has a thickness D21 of 500 μm or less. The reduced thickness of the encapsulant 570 and the semiconductor die 504 improves the reliability of the eWLCSP 630 after mounting the eWLCSP 630 to a substrate such as a PCB.

The eWLCSP 630 is a fan-in package with sidewall protection to strengthen the semiconductor die 504 without the need for a backside protective layer. The eWLCSP 630 can be manufactured at a lower cost without a back cover. Moreover, the exposed back surface 508 of the semiconductor die 504 allows for inspection of the semiconductor die 504 for crack and broken vision. The eWLCSP 630 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 560, which reduces the cost of equipment and materials for the eWLCSP 630. The eWLCSP 630 is manufactured in a larger amount using a standardized carrier 560, thereby simplifying the process and reducing unit cost.

Figure 24 shows an encapsulant having an overlying sidewall of a semiconductor die, an exposed back surface, and a UBM's eWLCSP 640. A conductive layer 642 is formed on the exposed portion of conductive layer 584 by PVD, CVD, evaporation, electrolytic plating, electroless plating, or other suitable metal deposition process after final repassivation, and In the insulation layer Above 590. Conductive layer 642 can be Al, Cu, Sn, Ni, AU, Ag, W, or other suitable electrically conductive material. Conductive layer 642 is a UBM that is electrically connected to conductive layers 584 and 512. UBM 642 can be a stack of multiple metals with an adhesion layer, a barrier layer, and a seed or wetting layer. The adhesive layer is formed over the conductive layer 584 and may be Ti, TiN, TiW, Al, or Cr. The barrier layer is formed over the adhesive layer and may be Ni, NiV, Pt, Pd, TiW, Ti, or CrCu. The barrier layer inhibits Cu from diffusing into the active surface 510 of the semiconductor die 504. The seed layer is formed over the barrier layer and may be Cu, Ni, NiV, AU, or Al. UBM 642 provides a low resistance interconnect to conductive layer 584, as well as a solder diffusion barrier and a seed layer for solder wettability.

A conductive bump material is deposited over conductive layer 642 using an evaporation, electrolytic plating, electroless plating, ball dropping, or screen printing process. In one embodiment, the bump material is deposited using a ball drop stencil, i.e., no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof with an optional fluxing solvent. For example, the bump material can be eutectic Sn/Pb, high lead solder, or lead free solder. The bump material is bonded to conductive layer 642 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material beyond its melting point to form a ball or bump 592. In some applications, bumps 592 are reflowed a second time to improve electrical contact to conductive layer 642. The bump 592 can also be compression bonded or thermocompression bonded to the conductive layer 642. Bump 592 represents a type of interconnect structure that can be formed over conductive layer 642. The interconnect structure can also use bond wires, conductive pastes, stud bumps, microbumps, or other electrical interconnects.

Insulation layers 580 and 590, conductive layers 584 and 642, and bumps 592 are all The body constitutes an interconnect structure 644 formed over the semiconductor die 504 and deposited within a footprint of the semiconductor die 504. The peripheral region of an adjacent semiconductor die 504 of semiconductor die 504 does not have interconnect structure 644 such that surface 572 of encapsulant 570 remains exposed relative to interconnect structure 644. The stacked interconnect structure 644 can include only one RDL or conductive layer, such as conductive layer 584, and an insulating layer, such as insulating layer 580. Additional insulating layers and RDL may be formed over insulating layer 580 prior to forming bumps 592 to provide additional vertical and horizontal electrical connections across the package depending on the design and function of semiconductor die 504.

The process of fabricating the eWLCSP 640 improves yield by reducing the defects of the semiconductor die 504 by passing through a single granulation process of one step and the use of an encapsulant 570 that covers the sidewalls of the semiconductor die 504. The step cutting used during the singulation of the semiconductor wafer 500 reduces cracking and fracture of the active surface 510 of the semiconductor die 504. Trench 530 is formed prior to singulation of semiconductor wafer 500 to facilitate control of cracking and fracture of semiconductor die 504. The notches 544 in the base substrate material 502 can also be utilized for alignment during singulation of the semiconductor wafer 500. The single granulation process for the steps of the semiconductor wafer 500 improves yield by reducing damage to the semiconductor die 504.

The encapsulant 570 provides sidewall protection over the four sides of the semiconductor die 504 to mechanically strengthen the semiconductor die 504. Semiconductor die 504 is surrounded by a ring of base substrate material 502 around edge 514 of semiconductor die 504. The encapsulant 570 covers the side surface 542 and covers the base substrate material 502 that surrounds the edge 514 of the semiconductor die 504. The encapsulant 570 protects the semiconductor die 504 during back grinding and singulation. The encapsulant 570 is singulated to separate the individual eWLCSP 640 without singulation through the base substrate material 502 or the semiconductor die 504. The encapsulant 570 disposed over the side surface 542 lowers the base substrate The material 502 and the semiconductor die 504 are cracked and broken. In one embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 is 0.5 [mu]m or greater. In another embodiment, the thickness D20 of the encapsulant 570 above the side surface 542 ranges from 5 to 50 [mu]m.

The encapsulant 570 is removed from the back surface 508 of the semiconductor die 504 during the backgrinding process to reduce the thickness of the eWLCSP 640 and expose the back surface 508 of the semiconductor die 504. The semiconductor die 504 is thinned during back grinding to reduce warpage of the eWLCSP 640. In one embodiment, the semiconductor die 504 has a thickness D21 of 500 μm or less. The reduced thickness of the encapsulant 570 and the semiconductor die 504 improves the reliability of the eWLCSP 640 after mounting the eWLCSP 640 to a substrate such as a PCB.

The eWLCSP 640 is a fan-in package with sidewall protection to strengthen the semiconductor die 504 without the need for a backside protective layer. The eWLCSP 640 can be manufactured at a lower cost without a back cover. Moreover, the exposed back surface 508 of the semiconductor die 504 allows for inspection of the semiconductor die 504 for crack and broken vision. The eWLCSP 640 is fabricated using a device designed for a single standardized carrier size by forming a reconstituted wafer on a standardized carrier 560, which reduces the cost of equipment and materials for the eWLCSP 640. The eWLCSP 640 is manufactured in a larger amount using a standardized carrier 560, thereby simplifying the process and reducing unit cost.

Although one or more embodiments of the present invention have been described in detail, those skilled in the art will recognize that modifications and adaptations can be made to those embodiments without departing from the scope of the following claims. The scope of the invention.

Claims (15)

A method of fabricating a semiconductor device, comprising: disposing a semiconductor die; forming a notch surrounding the semiconductor die; disposing the semiconductor die on a carrier, the notch being oriented toward the carrier; above the semiconductor die And surrounding and depositing an encapsulant into the gap, and the semiconductor die is on the carrier; and forming an interconnect structure over the semiconductor die and within a footprint of the semiconductor die. The method of claim 1, further comprising: arranging the plurality of semiconductor dies on a carrier prior to depositing the encapsulant, wherein a distance between the semiconductor dies is on the carrier It is 500 micrometers (μm) or smaller. The method of claim 1, further comprising: disposing a semiconductor wafer including the plurality of semiconductor dies and a base semiconductor material; separating the semiconductor crystals by singulating the semiconductor wafer through the gap grain. The method of claim 1, further comprising singulating through the encapsulant while leaving an encapsulant disposed on a sidewall of the semiconductor die. The method of claim 4, wherein the singulating through the encapsulation further comprises: partially forming a groove through the encapsulation; and transmitting the groove in the encapsulation Single granulation. A method of fabricating a semiconductor device, comprising: disposing a semiconductor die; forming a notch in a peripheral region of an active surface of the semiconductor die; depositing an encapsulant on a back surface of the semiconductor die, surrounding the semiconductor crystal The side surface of the grain enters the gap; and a fan-in interconnect structure is formed over the semiconductor die. The method of claim 6, further comprising removing a portion of the encapsulant from the back surface of the semiconductor die or the side surface of the semiconductor die. The method of claim 6, further comprising: disposing a semiconductor wafer including the plurality of semiconductor dies and a base semiconductor material; and singulating the semiconductor wafer through the gap to separate the semiconductors Grain. The method of claim 6, further comprising singulating through the encapsulant while leaving an encapsulant disposed on a sidewall of the semiconductor die. The method of claim 9, wherein the singulation through the encapsulation further comprises: partially forming a groove through the encapsulation; and transmitting the groove in the encapsulation Single granulation. A semiconductor device comprising: a semiconductor die comprising a notch formed in a peripheral region of the semiconductor die; An encapsulant deposited around the semiconductor die and entering the gap; and a fan-in interconnect structure formed over the semiconductor die. The semiconductor device of claim 11, wherein the fan-in interconnect structure further comprises: an insulating layer formed over the semiconductor die; and a conductive layer formed over the insulating layer and Within a footprint of the semiconductor die. The semiconductor device of claim 12, wherein the insulating layer extends over the encapsulant. The semiconductor device of claim 11, wherein the encapsulation system covers a sidewall of the semiconductor die. The semiconductor device of claim 14, wherein the encapsulation system covering the sidewall of the semiconductor die comprises a thickness of 50 micrometers (μm) or less.