CN112885793A - Chip packaging structure and manufacturing method thereof - Google Patents
Chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN112885793A CN112885793A CN202110270310.5A CN202110270310A CN112885793A CN 112885793 A CN112885793 A CN 112885793A CN 202110270310 A CN202110270310 A CN 202110270310A CN 112885793 A CN112885793 A CN 112885793A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 103
- 229910000679 solder Inorganic materials 0.000 claims abstract description 78
- 238000005520 cutting process Methods 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims description 32
- 239000002184 metal Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 15
- 238000003466 welding Methods 0.000 claims description 6
- 238000005253 cladding Methods 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 230000009471 action Effects 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 3
- 230000003628 erosive effect Effects 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 230000006872 improvement Effects 0.000 description 8
- 230000032798 delamination Effects 0.000 description 7
- 239000000463 material Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000007888 film coating Substances 0.000 description 2
- 238000009501 film coating Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- -1 photoetching Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
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- 238000005260 corrosion Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
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- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
Abstract
The invention provides a chip packaging structure and a manufacturing method thereof.A cutting channel is exposed on an insulating layer and a solder mask layer which are arranged along the side edge of a chip substrate and are retracted inwards, on one hand, when each chip is cut and separated, the silicon substrate part of the wafer can be directly cut, the insulating layer and the solder mask layer are prevented from being cut, and therefore, microcracks are prevented from being formed at the edges of the two layers due to cutting action; on the other hand, the insulating layer and the solder mask layer form a complete continuous film layer structure on the surface of the substrate, and the situation that stress is generated on one side in a cut film layer and cannot be compensated is avoided. The solder mask layer extends to the outside of the insulating layer, the coating insulating layer is combined with the substrate, and the protective insulating layer can be completely sealed, so that the erosion of water vapor and the like to the insulating layer is slowed down, meanwhile, the partial stress of the solder mask layer can be directly borne by the substrate, and when no layering occurs between the solder mask layer and the substrate, the insulating layer can only receive a small amount of stress.
Description
Technical Field
The invention relates to the technical field of packaging, in particular to a chip packaging structure and a manufacturing method thereof.
Background
Based on the material characteristics of each layer of material of the chip packaging structure, such as film forming defects, compactness, thermal expansion coefficient and the like, different stresses are generated inside each layer of material and among each layer of material, wherein the stress influence of the material used by the solder mask layer is the largest, and particularly, the stress changes more severely in the cold and hot impact process of the chip reliability test. The chip substrate silicon material and the insulating layer are relatively fragile materials, and are most prone to delamination in the stress change process.
In the prior art, an insulating layer and a solder mask layer which completely cover a wafer are usually formed on the surface of the wafer, and then the wafer is cut to obtain single chips. The chip obtained by the method has the advantages that on one hand, due to the cutting, inevitable microcracks are generated at the edge of the chip, on the other hand, the film layer is disconnected from the edge of the chip, the stress is not compensated by the other side, and the stress applied to the edge of the chip substrate is larger, so that when the delamination occurs, the chip substrate or the insulating layer which starts from the edge of the chip usually extends inwards.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a manufacturing method thereof.
The invention provides a chip packaging structure, wherein the chip comprises a substrate, an insulating layer, a metal wiring layer and a solder mask layer, wherein the substrate is provided with a first surface, a second surface opposite to the first surface and a plurality of side surfaces for connecting the first surface and the second surface, the first surface of the substrate is sequentially provided with the insulating layer, the metal wiring layer and the solder mask layer, the solder mask layer is provided with a welding bulge electrically connected with the metal wiring layer, the chip packaging structure is characterized in that,
the edge of the insulating layer and the edge of the solder mask layer are respectively retracted inwards along the side surface of the substrate by a first distance a and a second distance b, wherein b is more than or equal to 0nm and less than a;
the insulating layer is located inside the solder mask layer, the solder mask layer is located the part in the insulating layer outside covers the basement, and the cladding insulating layer side.
As a further improvement of the invention, the side surface of the substrate is provided with grooves which are inwards sunken along the first surface of the substrate, and the grooves are distributed along the length direction of the side surface of the substrate.
As a further improvement of the invention, the trench forms a step structure on the side surface of the substrate, the step structure is provided with a trench side wall surface and a trench bottom surface, and a third distance c is arranged between the top end of the trench side wall surface and the side surface of the substrate on the same side of the trench side wall surface, wherein c is less than or equal to b.
As a further improvement of the present invention, a buffer layer is provided between the insulating layer and the metal wiring layer.
As a further improvement of the present invention, the second surface of the substrate is provided with a pad, the first surface of the substrate is provided with a through hole extending toward the second surface of the substrate, the bottom of the through hole exposes the pad, and the metal wiring layer extends to the pad along the sidewall of the through hole and is electrically connected with the pad.
The invention also provides a manufacturing method of the chip packaging structure, which comprises the following steps:
providing a wafer, wherein the wafer is provided with a first surface and a second surface which are opposite, a plurality of chip substrates are arrayed on the wafer, and cutting channels are distributed between the adjacent substrates;
forming insulating layers on the first surfaces of the substrates, forming the insulating layers on each substrate at intervals, and retracting the edges of the insulating layers on each substrate inwards by a first distance a along the cutting path;
sequentially forming a metal wiring layer and a solder mask layer on the insulating layer, forming the solder mask layers on each substrate at intervals, wherein the edge of each solder mask layer on each substrate is inwards retracted by a second distance b along the cutting channel, b is more than or equal to 0nm and less than a, and the part of each solder mask layer, which is positioned on the outer side of the insulating layer, covers the substrate and coats the side edge of the insulating layer;
forming a through hole exposing the metal wiring layer on the solder mask layer, and forming a welding bulge electrically connected with the metal wiring layer in the through hole;
and cutting the wafer along the cutting channels to obtain a plurality of independent chip packaging structures.
As a further improvement of the present invention, before "forming an insulating layer on the first surface of the substrate", the method further comprises the steps of:
and forming a full groove above the cutting channel on the first surface of the wafer, wherein the width of the full groove is greater than that of the cutting channel.
As a further improvement of the invention, the full trench has a trench sidewall surface and a trench bottom surface, a third distance c is arranged between the top end of the trench sidewall surface and the edge of the scribe line on the same side of the trench sidewall surface, wherein c is less than or equal to b, and the trench bottom surface at least completely exposes the scribe line.
As a further improvement of the present invention, "forming a metal wiring layer and a solder resist layer on the insulating layer in this order" further includes the steps of:
and forming a buffer layer on the insulating layer.
As a further improvement of the present invention, "forming an insulating layer on the first surface of the substrate" further comprises the steps of:
and forming a through hole extending towards the second surface of the wafer on the first surface of the wafer, wherein the bottom of the through hole exposes out of the welding pad arranged on the second surface of the wafer.
The invention has the beneficial effects that: the insulating layer and the solder mask layer which are inwards retracted along the side edge of the chip substrate are arranged, and the insulating layer and the solder mask layer are exposed out of a cutting channel in an uncut wafer, so that on one hand, when each chip is cut and separated, the silicon substrate part of the wafer can be directly cut, the insulating layer and the solder mask layer are prevented from being cut, and microcracks are prevented from being formed at the edges of the two layers due to cutting action; on the other hand, the insulating layer and the solder mask layer form a complete continuous film layer structure on the surface of the substrate, and the situation that stress is generated on one side in a cut film layer and cannot be compensated is avoided.
The solder mask extends to the outer side of the insulating layer, wraps the insulating layer and is combined with the substrate, on one hand, the solder mask can completely seal and protect the insulating layer, so that the erosion of water vapor and the like to the insulating layer is slowed down; on the other hand, partial stress of the solder mask layer can be directly borne by the substrate, and when no delamination occurs between the solder mask layer and the substrate, the insulating layer can only bear a small amount of stress, so that the reliability of the chip packaging structure is further improved.
Drawings
Fig. 1 is a schematic diagram of a chip package structure according to an embodiment of the invention.
Fig. 2 is a schematic diagram of the chip package structure before being cut and separated according to an embodiment of the invention.
Fig. 3 is an enlarged schematic view at a in fig. 1.
Fig. 4 is a schematic diagram of a chip package structure according to a second embodiment of the invention.
Fig. 5 is a schematic diagram of the chip package structure before being cut and separated according to the second embodiment of the invention.
Fig. 6 is an enlarged schematic view at B in fig. 4.
Fig. 7 is a schematic diagram of a chip package structure in the third embodiment of the invention.
Fig. 8 is a schematic diagram of the chip package structure before being cut and separated according to the third embodiment of the invention.
Fig. 9 is an enlarged schematic view at C in fig. 7.
Fig. 10 is an enlarged schematic view at D in fig. 8.
Fig. 11 is a schematic diagram illustrating a manufacturing process of a chip package structure according to an embodiment of the invention.
Fig. 12 to 16 are schematic diagrams illustrating steps of a manufacturing process of a chip package structure according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more clear, the technical solutions of the present application will be clearly and completely described below with reference to the detailed description of the present application and the accompanying drawings. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
For convenience in explanation, the description herein uses terms indicating relative spatial positions, such as "upper," "lower," "rear," "front," and the like, to describe one element or feature's relationship to another element or feature as illustrated in the figures. The term spatially relative position may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "above" other elements or features would then be oriented "below" or "above" the other elements or features. Thus, the exemplary term "below" can encompass both a spatial orientation of below and above.
As shown in fig. 1 to 10, the present invention provides a chip package structure, the chip includes a substrate 1 having a first surface 11, a second surface 12 opposite to the first surface 11, and a side surface 13 connecting the first surface 11 and the second surface 12, an insulating layer 2, a metal wiring layer 3, and a solder resist layer 4 are sequentially disposed on the first surface 11 of the substrate 1, and a solder bump 6 electrically connected to the metal wiring layer 3 is disposed on the solder resist layer 4.
The chip can be an MEMS chip or an image sensor chip, and the like, and according to different chip types, the chip can also be provided with a structure such as a protective cover plate 5, and the protective cover plate 5 is attached to the second surface 12 of the substrate 1.
According to the chip type, in some embodiments, the second surface 12 of the chip substrate 1 is provided with a pad, the first surface 11 of the substrate 1 is provided with a through hole extending towards the second surface 12 thereof, the bottom of the through hole exposes the pad, and the metal wiring layer 3 extends along the sidewall of the through hole to the pad and is electrically connected with the pad.
Further, in some embodiments, a buffer layer 7 may be further disposed between the buffer layer 7 and the metal wiring layer to relieve stress between the insulating layer 2 and the metal wiring layer 3.
As shown in fig. 2, the chip is obtained by cutting and separating a wafer 1', the wafer 1' has a first surface and a second surface opposite to each other, that is, corresponding to a first surface 11 and a second surface 12 of a chip substrate 1, a plurality of chip substrates 1 are arrayed on the wafer 1', cutting streets 8 are distributed between adjacent chip substrates 1, and after a subsequent packaging process and a subsequent test are completed, the wafer is cut and separated along the cutting streets 8 to obtain a single chip. It should be noted that the scribe line 8 between two adjacent chip substrates 1 is only a margin area reserved between the two chip substrates 1 for dicing, and there is no actual boundary line between the scribe line 8 and the chip substrates 1 on both sides.
Since a certain loss inevitably exists when the wafer 1 'is cut by laser or mechanical means, the scribe line 8 has a certain width d, that is, the width of a scribe line when the wafer 1' is cut along the scribe line 8.
The edge of the insulating layer 2 and the edge of the solder mask layer 4 are respectively retracted inwards along the side surface 13 of the substrate 1 by a first distance a and a second distance b, wherein b is more than or equal to 0nm and less than a. Namely, a first distance a is formed between the side surface of the chip insulation layer 2 and the side surface 13 of the substrate 1 on the same side of the chip insulation layer, and a second distance b is formed between the side surface of the solder mask layer 4 and the side surface 13 of the substrate 1 on the same side of the chip insulation layer.
It should be noted that, when the chip is not cut and separated from the wafer 1', the first distance a and the second distance b are distances between the edge of the insulating layer 2 and the edge of the solder resist layer 4 and the edge of the adjacent scribe line 8.
In the manufacturing process, the insulating layer 2 and the solder resist layer 4 are formed on the wafer 1' at intervals by a mask plate corresponding to the shapes of the insulating layer 2 and the solder resist layer 4. The insulating layer 2 is positioned in the solder mask layer 4, and the part of the solder mask layer 4 positioned on the outer side of the insulating layer 2 covers the substrate 1 and covers the side edge of the insulating layer 2.
As shown in fig. 1 to 3, in the first embodiment, the second length b is 0nm, that is, the side surface of the solder mask layer 4 is flush with the side surface 13 of the substrate 1, and at this time, it is preferable that in the uncut wafer 1', the solder mask layers 4 on the adjacent chip substrates 1 are spaced apart and have the same width as the width of the scribe line 8, so that the solder mask layers 4 are exposed out of the scribe line 8, on one hand, when each chip is cut and separated, the silicon substrate portion of the wafer 1' can be directly cut, and the insulating layer 2 and the solder mask layer 4 are prevented from being cut, so as to avoid the formation of micro cracks at the edges of the two layers due to the cutting action; on the other hand, the insulating layer 2 and the solder resist layer 4 form a complete continuous film structure on the surface of the substrate 1, and the situation that stress is generated on one side in a cut film layer and cannot be compensated does not occur.
Moreover, the solder mask layer 4 extends to the outer side of the insulating layer 2, covers the insulating layer 2 and is combined with the substrate 1, on one hand, the solder mask layer 4 can completely seal and protect the insulating layer 2, so that the corrosion of water vapor and the like to the insulating layer 2 is slowed down; on the other hand, partial stress of the solder mask layer 4 can be directly borne by the substrate 1, and when no delamination occurs between the solder mask layer 4 and the substrate 1, the insulating layer 2 is only subjected to a small amount of stress, so that the reliability of the chip packaging structure is further improved.
In addition, since the second length b is smaller than the first length a, i.e., a certain distance is spaced between the edge of the insulating layer 2 and the solder resist layer 4, even when delamination occurs between the substrate 1 and the solder resist layer 4, there is a delamination transition distance, so that the delamination does not easily extend into the inside of the insulating layer 2.
In other embodiments of the first embodiment, when the stress of the solder mask layer 4 is sufficiently low, only the insulating layer 2 may be set back inward to form the insulating layers 2 distributed at intervals, so as to form the complete solder mask layer 4 on the surface of the wafer 1', and the solder mask layer 4 is cut along with the wafer 1' during the cutting process.
As shown in fig. 4 to 6, in the second embodiment, the difference from the first embodiment is that the second length b is greater than 0nm, that is, in the wafer 1' which is not cut and separated, there is a space between the edge of the solder mask layer 4 and the side edge of the substrate 1, and by disposing the edge of the solder mask layer 4 away from the edge of the cutting street 8, the stress of the solder mask layer 4 is not directly applied to the side edge of the substrate 1 to pull the substrate 1 from the side edge.
The first length a and the second length b may be specifically adjusted according to chip size and functional requirements, and are not particularly limited as long as the second length b is smaller than the first length a.
Further, in some embodiments of the present invention, the side 13 of the substrate 1 is provided with grooves 9 recessed inward along the first surface 11 of the substrate 1, and the grooves 9 are distributed along the length of the side 13 of the substrate 1.
As shown in fig. 7 to 10, in the third embodiment, the difference from the second embodiment is that the chip further includes a trench 9, the trench 9 forms a step structure on the side surface 13 of the substrate 1, and the trench 9 has a side wall surface 91 of the trench 9 and a bottom surface 92 of the trench 9, and a third distance c is spaced between the top end of the side wall surface 91 of the trench 9 and the side surface 13 of the substrate 1 on the same side as the top end, where c is not less than b, i.e. the side surface of the solder mask layer 4 is flush with the side wall surface 91 of the trench 9, or the edge of the solder mask layer 4 is recessed inward by a certain.
In the wafer 1 'which is not cut and separated, a full groove 9' covering the cutting path 8 is formed above the cutting path, the full groove 9 'is opened upwards, after a single chip is cut, the full groove 9' is cut along with the chip, and a groove 9 which is opened upwards and opened towards the side edge is formed on the side surface 13 of the substrate 1. The top end of the side wall surface 91 of the single-side groove 9 is spaced from the edge of the scribe line 8 by a third distance c, the width of the opening of the full groove 9 'is d +2c, and the bottom surface 92 of the full groove 9' at least completely exposes the scribe line 8.
The grooves 9 are formed by etching before cutting, the grooves 9 with the width larger than the cutting channel 8 and with certain depth are arranged above the cutting channel 8, the initial position of cutting is lower, partial allowance is reserved on two sides, the strength of the single chip substrate 1 at the corner after cutting can be enhanced, the single chip substrate can bear larger stress, and the reliability of the chip is further enhanced.
Before cutting, the longitudinal section of the trench 9 may be rectangular, or inverted trapezoidal, as long as the scribe line 8 can be exposed, and the depth of the scribe line 8 is not particularly limited and can be adjusted according to the process capability and the chip design space.
As shown in fig. 11, the present invention further provides a method for manufacturing a chip package structure, including the steps of:
s1: as shown in fig. 12, a wafer 1' is provided, the wafer 1' has a first surface 11 and a second surface 12 opposite to each other, a plurality of chip substrates 1 are arranged on the wafer 1', dicing streets 8 are distributed between adjacent chip substrates 1, and the width of each dicing street 8 is d.
Further, in some embodiments of the present invention, the step of forming the trench 9 is further included.
S11: a full trench 9' is formed on the first surface 11 of the wafer 1' above the scribe line 8, and the width of the full trench 9' is greater than that of the scribe line 8.
Specifically, the full trench 9 'is formed by etching, the full trench 9' has a sidewall surface 91 of the trench 9 and a bottom surface 92 of the trench 9, and a third distance c is provided between the top end of the sidewall surface 91 of the full trench 9 'and the edge of the scribe line 8 on the same side as the top end, i.e., after the subsequent cutting, the full trench 9' is cut into the trench 9 on the side surface 13 of the substrate 1.
The top end of the side wall surface 91 of the groove 9 and the side surface 13 of the substrate 1 on the same side of the side wall surface are separated by a third distance c, the width of the upper end surface of the groove 9 is d +2c, at least the cutting path 8 is exposed on the bottom surface 92 of the groove 9, and the longitudinal section of the groove 9 can be rectangular, inverted trapezoid or the like.
Furthermore, after forming the full trench 9 'according to different types of chips, a through hole extending toward the second surface 12 of the wafer 1' is formed on the first surface 11 of the wafer 1', and a pad disposed on the second surface 12 of the wafer 1' is exposed at the bottom of the through hole.
Alternatively, it may also include attaching a protective cover 5 to the second side 12 of the substrate 1.
S2: as shown in fig. 13, the insulating layers 2 are formed on the first surface 11 of the chip substrate 1, the insulating layers 2 are formed on each substrate 1 at intervals, and the edge of the insulating layer 2 on each substrate 1 is inwardly retracted by a first distance a along the scribe line 8.
Specifically, the insulating layer 2 is formed by a vapor deposition technique, and the insulating layer 2 is formed on the substrate 1 by a mask corresponding to the planar shape of the insulating layer 2.
The metal wiring layer 3 is formed by a sequence of processes of metal film coating, photoetching, copper plating, film removing and copper/titanium etching, and the projection of the metal wiring layer 3 in the vertical direction is positioned in the insulating layer 2.
Further, in some embodiments of the present invention, after forming the insulating layer 2, forming a buffer layer 7 on the insulating layer 2 is further included.
S3: as shown in fig. 14, a metal wiring layer 3 and a solder mask layer 4 are sequentially formed on an insulating layer 2, the solder mask layers 4 are independently formed on each substrate 1 at intervals, the edge of the solder mask layer 4 on each substrate 1 is inwardly retracted by a second distance b along a scribe line 8, wherein c is greater than or equal to 0nm and less than or equal to b and less than a, and the part of the solder mask layer 4 located outside the insulating layer 2 covers the substrate 1 and covers the side edge of the insulating layer 2.
Specifically, the method for forming the solder resist layer 4 includes a sequence of processes of deposition, photolithography, electroless plating, and the like, and the solder resist layer 4 is formed on the substrate 1 through a mask corresponding to the planar shape of the solder resist layer 4.
S4: as shown in fig. 15, a through hole exposing the metal wiring layer 3 is opened in the solder resist layer 4, and a solder bump 6 electrically connected to the metal wiring layer 3 is formed in the through hole.
S5: as shown in fig. 16, the wafer 1' is diced along the dicing streets 8 to obtain a plurality of individual chip package structures.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention and is not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention are included in the scope of the present invention.
Claims (10)
1. A chip packaging structure, the chip includes the basement, it has the first surface, the second surface opposite to first surface and connects the multiple sides of the first surface and second surface, there are insulating layer, metal routing layer and solder mask on the first surface of the said basement sequentially, there are welding projections connected electrically to the said metal routing layer on the said solder mask, characterized by that,
the edge of the insulating layer and the edge of the solder mask layer are respectively retracted inwards along the side surface of the substrate by a first distance a and a second distance b, wherein b is more than or equal to 0nm and less than a;
the insulating layer is located inside the solder mask layer, the solder mask layer is located the part in the insulating layer outside covers the basement, and the cladding insulating layer side.
2. The chip package structure according to claim 1, wherein the substrate side surface is provided with grooves recessed inward along the first surface of the substrate, and the grooves are distributed along a length direction of the substrate side surface.
3. The chip package structure according to claim 2, wherein the trench forms a step structure on the side surface of the substrate, the step structure has a trench sidewall surface and a trench bottom surface, and a third distance c is provided between a top end of the trench sidewall surface and the side surface of the substrate on the same side of the trench sidewall surface, where c is not less than b.
4. The chip package structure according to claim 1, wherein a buffer layer is disposed between the insulating layer and the metal wiring layer.
5. The chip package structure according to claim 1, wherein the second surface of the substrate is provided with a pad, the first surface of the substrate is provided with a through hole extending toward the second surface of the substrate, the bottom of the through hole exposes the pad, and the metal wiring layer extends along the sidewall of the through hole to the pad and is electrically connected to the pad.
6. A chip packaging structure manufacturing method is characterized by comprising the following steps:
providing a wafer, wherein the wafer is provided with a first surface and a second surface which are opposite, a plurality of chip substrates are arrayed on the wafer, and cutting channels are distributed between the adjacent substrates;
forming insulating layers on the first surfaces of the substrates, forming the insulating layers on each substrate at intervals, and retracting the edges of the insulating layers on each substrate inwards by a first distance a along the cutting path;
sequentially forming a metal wiring layer and a solder mask layer on the insulating layer, forming the solder mask layers on each substrate at intervals, wherein the edge of each solder mask layer on each substrate is inwards retracted by a second distance b along the cutting channel, b is more than or equal to 0nm and less than a, and the part of each solder mask layer, which is positioned on the outer side of the insulating layer, covers the substrate and coats the side edge of the insulating layer;
forming a through hole exposing the metal wiring layer on the solder mask layer, and forming a welding bulge electrically connected with the metal wiring layer in the through hole;
and cutting the wafer along the cutting channels to obtain a plurality of independent chip packaging structures.
7. The method for manufacturing a chip package structure according to claim 6, further comprising, before the step of forming an insulating layer on the first surface of the substrate:
and forming a full groove above the cutting channel on the first surface of the wafer, wherein the width of the full groove is greater than that of the cutting channel.
8. The method of manufacturing a chip package structure according to claim 7,
the full groove is provided with a groove side wall face and a groove bottom face, a third distance c is arranged between the top end of the groove side wall face and the edge of the cutting channel on the same side of the groove side wall face, wherein c is less than or equal to b, and the cutting channel is at least completely exposed on the groove bottom face.
9. The method for manufacturing a chip package structure according to claim 6, further comprising, before the step of sequentially forming a metal wiring layer and a solder resist layer on the insulating layer:
and forming a buffer layer on the insulating layer.
10. The method for manufacturing a chip package structure according to claim 6, further comprising the step of, before forming the insulating layer on the first surface of the substrate:
and forming a through hole extending towards the second surface of the wafer on the first surface of the wafer, wherein the bottom of the through hole exposes out of the welding pad arranged on the second surface of the wafer.
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| CN202110270310.5A CN112885793A (en) | 2021-03-12 | 2021-03-12 | Chip packaging structure and manufacturing method thereof |
| PCT/CN2021/128895 WO2022188445A1 (en) | 2021-03-12 | 2021-11-05 | Chip package structure and manufacturing method therefor |
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| CN202110270310.5A CN112885793A (en) | 2021-03-12 | 2021-03-12 | Chip packaging structure and manufacturing method thereof |
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