CN105336685A - Wafer cutting method possessing test pattern - Google Patents
Wafer cutting method possessing test pattern Download PDFInfo
- Publication number
- CN105336685A CN105336685A CN201410348384.6A CN201410348384A CN105336685A CN 105336685 A CN105336685 A CN 105336685A CN 201410348384 A CN201410348384 A CN 201410348384A CN 105336685 A CN105336685 A CN 105336685A
- Authority
- CN
- China
- Prior art keywords
- cutting
- wafer
- chip
- scribe line
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dicing (AREA)
Abstract
The invention discloses a wafer cutting method possessing a test pattern. A copper interconnection test structure circuit and an on-line monitoring pattern are not put into a scribing groove area or the test structure circuit and the on-line monitoring pattern are not put into a scribing groove cutting area so that phenomena of chip collapse lack and stress hierarchy, which are generated because a problem that a thermal stress coefficient difference of copper, silicon oxide and a silicon nitride insulating layer is large because of scalability of the copper during a laser cutting process, are thoroughly avoided. Simultaneously, an extra chip with a high proportion can be acquired. In a technology after copper interconnection is completed, a silicon nitride film layer in the scribing groove area is removed so that only silicon oxide and silicon of a substrate exist in a profile map of the scribing groove area from top to bottom. Effective appearance of miniature cracks of the scribing groove area during a laser scanning process is effectively increased, cutting efficiency can be improved, and a yield of the chip after cutting and a packaging yield are increased.
Description
Technical field
The present invention relates to semiconductor preparation field, be specifically related to a kind of method for cutting wafer with resolution chart.
Background technology
Test is received in order to test online fabrication process parameters and monitor and carry out wafer electric property to chip after technique completing in chip manufacturing proces, relevant test structure is placed in the scribe line area between chip and chip usually, and those skilled in the art are referred to as chip (or claiming wafer) scribe line area.
Meanwhile, the technique of advanced process chip copper-connection adopts the insulating barrier of low-K (low-k) to improve RCdelay (delay) effect usually, and below copper-connection metal level, adopt silicon nitride dielectric layer to prevent the diffusion of copper.Test structure circuit and on-line monitoring pattern are placed on scribe line area, for preventing the residue problem occurring copper in cmp copper process, also dummy hole or the line simulator shape (DummyPattern) of layout not of the same race is placed, to reduce pressure, to prevent the copper of cmp from remaining in the scribe line area without test structure.
Fig. 1 a ~ 1d is the schematic diagram adopting machine cuts; first, wafer 2 is placed on an antiultraviolet adhesive tape 1, and at the surface-coated layer protective layer 3 of wafer 2; then along scribe region, wafer is cut with a cutting tool, wafer 2 is cut into the structure shown in Fig. 1 d.Fig. 2 a ~ 2d is the schematic diagram cut when scribe region arranges line simulator shape; first wafer 2 is placed on an antiultraviolet adhesive tape 1; and at the surface-coated layer protective layer 3 of wafer 2; then adopt laser cutting parameter to define line simulator shape, finally utilize cutting technique by wafer cutting in the structure shown in Fig. 2 d.
But technical staff finds following problem when cutting copper-connection wafer:
Due to the better ductility that copper has, the problem that simultaneously the thermal stress difference of coefficients of copper and silica, silicon nitride dielectric layer is larger, in employing laser cutting scribe line area process, serious collapsing can be there is and lack and chip stress lamination, and badly influence yield and the encapsulation of chip.
As shown in Fig. 3 a ~ 3b, between 4 chip areas (chiparea) 100, be provided with chip scribe line area 102, in chip scribe line area 102, be provided with test structure circuit and on-line monitoring pattern 101.When cutting, need to utilize a cutting tool 103 to cut along cutting zone 102.But at cutting zone 102 owing to being provided with test structure circuit and on-line monitoring pattern 101, and test structure circuit and on-line monitoring pattern 101 are generally copper test suite (Cu-testkey), when cutting, very easily there is serious bursting apart and chip stress lamination, and certain damage be also result in chip, shown in Fig. 3 b.
Therefore, how to avoid the problems referred to above to be the direction that those skilled in the art endeavour to study when cutting chip.
Summary of the invention
The invention discloses a kind of method for cutting wafer with resolution chart, well can solving by method provided by the present invention bursting apart and chip lamination of easily producing when cutting, improving cutting effect, and then boost device yield; Break area area occupied can be reduced simultaneously, therefore can obtain a high proportion of, extra chip.
The technical solution adopted in the present invention is:
There is a method for cutting wafer for resolution chart, wherein, comprise the steps:
Step S1: provide a wafer to be cut, described wafer to be cut arranges some chip areas and test suite, and arranges scribe line area between adjacent described chip area;
Wherein, include a cutting zone in described scribe line area, described test suite is arranged in described chip area, or this test suite is arranged in the region in described scribe line area except described cutting zone;
Step S2: cut along described cutting zone, to be separated by each described chip area, and is tested described chip area by described test suite.
The above-mentioned method for cutting wafer with resolution chart, wherein, described method is applied in the back-end process of metal interconnected technique.
The above-mentioned method for cutting wafer with resolution chart, wherein, described test suite is metal interconnected test structure circuit and on-line monitoring pattern.
The above-mentioned method for cutting wafer with resolution chart, wherein, described metal interconnected test structure circuit is copper-connection test structure circuit.
The above-mentioned method for cutting wafer with resolution chart, wherein, described scribe line area surface is provided with insulation material layer.
The above-mentioned method for cutting wafer with resolution chart, wherein, described insulation material layer is silicon nitride layer.
The above-mentioned method for cutting wafer with resolution chart, wherein, when described test suite is arranged in described scribe line area, described test suite is positioned at the top of described insulation material layer.
The above-mentioned method for cutting wafer with resolution chart, wherein, adopts machine cuts or laser cutting to cut.
The above-mentioned method for cutting wafer with resolution chart, wherein, the width of described scribe line area is 8um ~ 200um.
The above-mentioned method for cutting wafer with resolution chart, wherein, is provided with integrated circuit in described chip area.
The present invention proposes the test structure circuit of copper-connection and on-line monitoring pattern no longer to put into scribe line area or scribe line and is cut region and does not place test structure circuit and on-line monitoring pattern, thus avoid problem larger because of the thermal stress difference of coefficients of the ductility of copper, copper and silica, silicon nitride dielectric layer in laser cutting process thoroughly, and the chip produced collapses scarce, stress lamination.And because the test structure circuit of copper-connection and on-line monitoring pattern no longer put into scribe line area, can scribe line area be designed less, therefore can obtain a high proportion of, extra chip.In technique after copper-connection completes, the silicon nitride film layer of scribe line area is removed, thus the profile that can obtain scribe line area sees the silicon of only silica and substrate from top to bottom, while the effective appearance effectively improving scribe line area micro-cracks in laser scanning process, yield and the encapsulation rate of finished products of cutting efficiency and the rear chip of cutting can also be improved further.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.
Fig. 1 a ~ 1d is the schematic flow sheet adopting traditional machine cuts in prior art;
Fig. 2 a ~ 2d is to the schematic flow sheet that low K wafer cuts in prior art;
Fig. 3 a is the schematic diagram of test suite distribution in prior art;
Fig. 3 b is the schematic diagram after cutting;
The layout of the test pattern that Fig. 4 a ~ 4b provides for the embodiment of the present invention one and the rear schematic diagram of cutting;
The layout of the test pattern that Fig. 5 a ~ 5b provides for the embodiment of the present invention two and the rear schematic diagram of cutting;
Fig. 6 is the tendency chart obtaining different chip count after selecting the scribe line area with different in width to cut.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:
The invention provides a kind of method for cutting wafer with resolution chart, be applied in the back-end process of copper wiring technique, concrete comprises the steps:
Step S1 a: first wafer to be cut is provided, this wafer to be cut includes some chip areas and test suite, in chip area, be provided with integrated circuit, all arranges scribe line area between adjacent chip area, wherein, in scribe line area, a cutting zone is also included; Wherein, test suite is arranged in chip area, or is arranged in scribe line area and not overlapping with cutting zone.Therefore, when test suite is arranged in chip area, then scribe line area can all as cutting zone; When test suite is arranged in scribe line area, then scribe line area removes test suite with exterior domain then for cutting zone.
In the present invention, the width of scribe line area is 8um ~ 200um; Test suite is copper-connection test structure circuit and on-line monitoring pattern, and the lower surface of test suite is provided with insulation material layer, and preferably, this insulation material layer is silicon nitride film, and then copper can be avoided to produce diffusion thus cause damage to underlying device.
Step S2: cut along cutting zone, to be separated by the chip area on wafer, and tests described chip area by test suite.In a particular embodiment of the present invention, machine cuts or laser cutting can be adopted according to demand to cut, do not repeat them here.
The present invention does not place the test suite of copper-connection by the cutting zone test suite of copper-connection no longer being put into scribe line area or scribe line, and then avoids when cutting, due to the adverse effect that copper test suite is present in and then causes cutting; Adopt technical scheme provided by the present invention owing to being arranged on beyond scribe line area by test suite simultaneously, and then the width of scribe line area can be reduced, reducing of scribe line area width, means and can place more chip area of the same area, thus minimizing cost, and increase economic efficiency.
The present invention is described further to provide two embodiments also to come by reference to the accompanying drawings below,
Embodiment one:
First one wafer to be cut is provided, 4a is depicted as the partial schematic diagram of this wafer to be cut, comprise multiple chip area 100 (being illustrated as 4 chip areas) spaced apart, be provided with scribe line area 102 between each chip area 100, scribe line area 102 comprises cutting zone 104 and test suite 101.Wherein, test suite 101 is test structure circuit and the on-line monitoring pattern of copper-connection, and its main material is copper; And the lower surface of test suite 101 is provided with insulation material layer, preferably, this insulation material layer is silicon nitride film, to be used for avoiding copper produce diffusion downwards thus cause damage to device.
In this embodiment, cutting zone 104 and test suite 101 do not form overlap, and then make when cutting along cutting zone 104, can not be formed with the test suite 101 of copper-connection and contact, thus also just avoid due to copper ductility and and silicon nitride film between stress relation thus cause fracture to burst apart or lamination, improve cutting effect, and improve product yield, as shown in Figure 4 b, when adopting this embodiment to cut, because the test suite of copper-connection is not overlapping with cutting zone 104, therefore when cutting, cutting effect can not be affected due to the effect of copper, can ensure to cut the intact fracture of rear formation one.
Embodiment two:
First provide a wafer to be cut, 5a is depicted as the partial schematic diagram of this wafer to be cut, comprises multiple chip area 100 spaced apart, is provided with scribe line area 102 between adjacent chips region 100.Each chip area 100 is provided with test suite 101 away from the edge of scribe line area 102, test suite 101 is test structure circuit and the on-line monitoring pattern of copper-connection, its material is copper, and the lower surface of test suite 101 is provided with one deck insulation material layer, preferably, this insulation material layer is silicon nitride film, to be used for avoiding copper produce diffusion downwards thus cause damage to device.
Because the test suite 101 in the present invention is not arranged in scribe line area 102, therefore can directly whole scribe line area 102 be cut as cutting zone, therefore the width of scribe line area 102 can suitably be reduced, then the reduction of the width of scribe line area 102 then means the reduction of depletion region, a high proportion of, extra chip can be obtained, reduce and produce and increase economic efficiency.Further, due to test suite 101 is arranged on chip position place, therefore when cutting along scribe line area 102, the adverse effect that also can not cause due to the effect of test suite 101 thus to cut surface.
Two forms are provided below and 6 are further detailed by reference to the accompanying drawings, such as standing chip scale is 580X580 (um), be that the scribe line area of 20um, 60um, 80um is cut respectively with width, and add up the number of chips obtained after dicing, related data is as follows:
Table 1
Table 2
By table 1 and table 2 and by reference to the accompanying drawings 6 can obviously find out, along with the reduction of scribe line area width, the chip count obtained after cutting also increases gradually, please refer to table 2 simultaneously, when the width of scribe line area is decreased to 20um, its chip count obtained is 79426, compares to want many 20.9%, the chip count obtained after greatly improving cutting with the chip count 65690 that scribe line area width is obtained for 80um carries out cutting.Meanwhile, adopt the less scribe line area of width to cut, the chip size specification that the chip size obtained also more is near the mark, this is conducive to the yield and the encapsulation rate of finished products that improve cutting efficiency and the rear chip of cutting.
In sum, owing to present invention employs above technical scheme, the present invention is cut region does not place test structure circuit and on-line monitoring pattern by the test structure circuit of copper-connection and on-line monitoring pattern no longer being put into scribe line area or scribe line, because the test structure circuit of copper-connection and on-line monitoring pattern no longer put into scribe line area, can scribe line area be designed less (lower than 60um), therefore can obtain a high proportion of, extra chip; In technique simultaneously after copper-connection completes, the silicon nitride film layer of scribe line area is removed, thus the profile that can obtain scribe line area sees the silicon of only silica and substrate from top to bottom, while the effective appearance effectively improving scribe line area micro-cracks in laser scanning process, also can improve yield and the encapsulation rate of finished products of cutting efficiency and the rear chip of cutting.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (9)
1. there is a method for cutting wafer for resolution chart, it is characterized in that, comprise the steps:
Step S1: provide a wafer to be cut, described wafer to be cut arranges some chip areas and test suite, and arranges scribe line area between adjacent described chip area;
Wherein, include a cutting zone in described scribe line area, described test suite is arranged in described chip area, or this test suite is arranged in the region in described scribe line area except described cutting zone;
Step S2: cut along described cutting zone, to be separated by each described chip area, and is tested described chip area by described test suite.
2. have the method for cutting wafer of resolution chart as claimed in claim 1, it is characterized in that, described method is applied in the back-end process of metal interconnected technique.
3. have the method for cutting wafer of resolution chart as claimed in claim 1, it is characterized in that, described test suite is metal interconnected test structure circuit and on-line monitoring pattern.
4. have the method for cutting wafer of resolution chart as claimed in claim 3, it is characterized in that, described metal interconnected test structure circuit is copper-connection test structure circuit.
5. have the method for cutting wafer of resolution chart as claimed in claim 1, it is characterized in that, the surface of described test suite is provided with insulation material layer.
6. have the method for cutting wafer of resolution chart as claimed in claim 5, it is characterized in that, described insulation material layer is silicon nitride layer.
7. there is the method for cutting wafer of resolution chart as claimed in claim 1, it is characterized in that, adopt machine cuts or laser cutting to cut.
8. have the method for cutting wafer of resolution chart as claimed in claim 1, it is characterized in that, the width of described scribe line area is 8um ~ 200um.
9. there is the method for cutting wafer of resolution chart as claimed in claim 1, it is characterized in that, in described chip area, be provided with integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410348384.6A CN105336685A (en) | 2014-07-21 | 2014-07-21 | Wafer cutting method possessing test pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410348384.6A CN105336685A (en) | 2014-07-21 | 2014-07-21 | Wafer cutting method possessing test pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105336685A true CN105336685A (en) | 2016-02-17 |
Family
ID=55287124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410348384.6A Pending CN105336685A (en) | 2014-07-21 | 2014-07-21 | Wafer cutting method possessing test pattern |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105336685A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206350A (en) * | 2016-08-08 | 2016-12-07 | 武汉新芯集成电路制造有限公司 | The bonding Tachistoscope method and system of optional position on a kind of product wafer |
| CN108133928A (en) * | 2017-12-25 | 2018-06-08 | 豪威科技(上海)有限公司 | Scribe line and imaging sensor wafer |
| CN109216178A (en) * | 2018-09-13 | 2019-01-15 | 普冉半导体（上海）有限公司 | A kind of design method of silicon chip size package scribe line |
| WO2024066218A1 (en) * | 2022-09-28 | 2024-04-04 | 长鑫存储技术有限公司 | Mask and layout method therefor, and typesetting pattern of chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101297394A (en) * | 2005-11-10 | 2008-10-29 | 株式会社瑞萨科技 | Semiconductor device manufacturing method and semiconductor device |
| CN101459180A (en) * | 2007-11-12 | 2009-06-17 | 英飞凌科技股份公司 | Wafer and a method of dicing a wafer |
| CN101770992A (en) * | 2008-12-30 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor chip protection structure and semiconductor chip |
| CN102810517A (en) * | 2011-06-03 | 2012-12-05 | Nxp股份有限公司 | Semiconductor wafer and method of producing the same |
-
2014
- 2014-07-21 CN CN201410348384.6A patent/CN105336685A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101297394A (en) * | 2005-11-10 | 2008-10-29 | 株式会社瑞萨科技 | Semiconductor device manufacturing method and semiconductor device |
| CN101459180A (en) * | 2007-11-12 | 2009-06-17 | 英飞凌科技股份公司 | Wafer and a method of dicing a wafer |
| CN101770992A (en) * | 2008-12-30 | 2010-07-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor chip protection structure and semiconductor chip |
| CN102810517A (en) * | 2011-06-03 | 2012-12-05 | Nxp股份有限公司 | Semiconductor wafer and method of producing the same |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206350A (en) * | 2016-08-08 | 2016-12-07 | 武汉新芯集成电路制造有限公司 | The bonding Tachistoscope method and system of optional position on a kind of product wafer |
| CN106206350B (en) * | 2016-08-08 | 2019-04-30 | 武汉新芯集成电路制造有限公司 | The bonding Tachistoscope method and system of any position on a kind of product wafer |
| CN108133928A (en) * | 2017-12-25 | 2018-06-08 | 豪威科技(上海)有限公司 | Scribe line and imaging sensor wafer |
| CN108133928B (en) * | 2017-12-25 | 2020-04-10 | 豪威科技(上海)有限公司 | Scribing groove and image sensor wafer |
| CN109216178A (en) * | 2018-09-13 | 2019-01-15 | 普冉半导体（上海）有限公司 | A kind of design method of silicon chip size package scribe line |
| WO2020052584A1 (en) * | 2018-09-13 | 2020-03-19 | 普冉半导体（上海）有限公司 | Design method for scribe line of silicon wafer level package |
| WO2024066218A1 (en) * | 2022-09-28 | 2024-04-04 | 长鑫存储技术有限公司 | Mask and layout method therefor, and typesetting pattern of chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8368180B2 (en) | Scribe line metal structure | |
| KR101469331B1 (en) | Scribe lines in wafers | |
| US7952167B2 (en) | Scribe line layout design | |
| US8692357B2 (en) | Semiconductor wafer and processing method therefor | |
| CN105336685A (en) | Wafer cutting method possessing test pattern | |
| US9472509B2 (en) | Dummy metal structure and method of forming dummy metal structure | |
| US8039367B2 (en) | Scribe line structure and method for dicing a wafer | |
| US10643911B2 (en) | Scribe line structure | |
| US8987734B2 (en) | Semiconductor wafer, semiconductor process and semiconductor package | |
| US8293581B2 (en) | Semiconductor chip with protective scribe structure | |
| US20110193200A1 (en) | Semiconductor wafer chip scale package test flow and dicing process | |
| US20120286397A1 (en) | Die Seal for Integrated Circuit Device | |
| US20140094019A1 (en) | Wafer processing method | |
| CN107516655A (en) | Scribe line test structure and method of testing | |
| CN104752325A (en) | Semiconductor device and forming method thereof and method for improving cutting yield of wafer | |
| US20150048373A1 (en) | Method and layout for detecting die cracks | |
| CN102496602B (en) | Chip cutting method | |
| KR20090034788A (en) | Integrated circuit package system including die having relieved active region | |
| CN109904119B (en) | Preparation method of chip | |
| US7250670B2 (en) | Semiconductor structure and fabricating method thereof | |
| CN100477175C (en) | Semiconductor structure and manufacturing method thereof | |
| US9196508B2 (en) | Method for producing three-dimensional integrated circuit structure | |
| CN103137584B (en) | The TSV encapsulating structure of semiconductor chip and method for packing thereof | |
| US7320930B2 (en) | Multi-elevation singulation of device laminates in wafer scale and substrate processing | |
| CN113921500A (en) | Packaging method of silicon wafer level scribing groove |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160217 |
|
| RJ01 | Rejection of invention patent application after publication |