CN109216178A - A kind of design method of silicon chip size package scribe line - Google Patents
A kind of design method of silicon chip size package scribe line Download PDFInfo
- Publication number
- CN109216178A CN109216178A CN201811069368.8A CN201811069368A CN109216178A CN 109216178 A CN109216178 A CN 109216178A CN 201811069368 A CN201811069368 A CN 201811069368A CN 109216178 A CN109216178 A CN 109216178A
- Authority
- CN
- China
- Prior art keywords
- scribe line
- design method
- size package
- chip size
- silicon chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 52
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 19
- 239000010703 silicon Substances 0.000 title claims abstract description 19
- 238000013461 design Methods 0.000 title claims abstract description 17
- 238000012544 monitoring process Methods 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 description 13
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of design methods of silicon chip size package scribe line, comprising: several regions are selected in the array of the chip of wafer；Process monitoring figure is concentrated into the region of selection, the wafer forms a scribe line between two adjacent chips in carrying out silicon wafer grade encapsulating products process.The process monitoring figure of scribe line can be placed into chip interior by the present invention, to guarantee the clean of scribe line, reduce sliver risk.
Description
Technical field
The present invention relates to semiconducter IC field, in particular to a kind of design method of silicon chip size package scribe line.
Background technique
In silicon chip size package (WLCSP) product processing of 8 cun of traditional wafers, one can be spaced apart between two chips
Scribe line, scribing groove width is from 25-80um etc..Fab can place process monitoring figure 1, this some processes in scribe line
The figure of monitoring has metal wiring layer and metallic vias, be easy to cause chip sliver when final encapsulation scribing.
WLCSP product is scribing again after test, due to surveying after scribing without whole, due to existing in current scribing sheet groove structures
The figure of process monitoring often will cause the sliver in scribing processes, and sliver is difficult to be found, and have in the terminal use of time
The failure of certain probability.
Summary of the invention
The object of the present invention is to provide a kind of design methods of silicon chip size package scribe line, by the process monitoring figure of scribe line
Shape is placed into chip interior, to guarantee the clean of scribe line, reduces sliver risk.
In order to achieve the goal above, the present invention is achieved by the following technical solutions:
A kind of design method of silicon chip size package scribe line, its main feature is that, comprising:
Several regions are selected in the array of the chip of wafer；
Process monitoring figure is concentrated into the region of selection.
The wafer forms a scribing between two adjacent chips in carrying out silicon wafer grade encapsulating products process
Slot.
The design method further comprises:
Remove the process monitoring figure that is placed in scribe line so that do not placed in the scribe line any band metal wiring layer and
The data of metallic vias.
The width of the scribe line is between 45 microns to 80 microns.
The wafer is 8 inches or 12 inches.
Compared with prior art, the present invention having the advantage that
1, the process monitoring figure of scribe line is placed into chip interior, to guarantee the clean of scribe line, guaranteeing can in scribing
The sliver risk of energy substantially reduces.
2, guarantee the integrality of monitoring parameter figure.
3, have a wide range of application, the wafer of 8 inches or 12 inches can be used for simultaneously.
Detailed description of the invention
Fig. 1 is scribe line and process monitoring figure laying method in the prior art
Fig. 2 is a kind of flow chart of the design method of silicon chip size package scribe line of the present invention；
Fig. 3 is scribe line of the present invention and process monitoring figure displacement structure figure.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Below in conjunction with FIG. 1 to FIG. 3, technical solution of the present invention is described in detail with specifically embodiment.Below this
Several specific embodiments can be combined with each other, may be no longer superfluous in some embodiments for the same or similar concept or process
It states.
As shown in Figure 1, 2, a kind of design method of silicon chip size package scribe line, comprising:
Several regions are selected in the array of the chip of wafer；
Process monitoring figure 1 is concentrated into the region of selection.
It should be noted that select several regions to refer to pre-selects several regions in the master chip of wafer, region can
To determine according to the structure of the distribution of chip or wafer, specifically, one piece of region can choose as subsequent process monitoring
The placement region of figure.
Fig. 3 shows scribe line of the present invention and process monitoring figure displacement structure figure, as shown in figure 3, the wafer exists
It carries out forming a scribe line between two adjacent chips in silicon chip size package (WLCSP) product processing.Two neighboring stroke
Width between film trap is SXAnd SY, SXAnd SYWidth be 45 μm -80 μm, the scribing for laser, etching or blade.
In a particular embodiment, the design method further include: the process monitoring figure being placed in scribe line is removed, so that
Any data with metal wiring layer and metallic vias are not placed in the scribe line.
Described is concentrated into process monitoring figure in the region of selection specifically: will originally be placed in scribe line
In technique figure be placed in chip region vacant in advance.
Scribing finally is packaged to wafer, obtains corresponding each chip product and the chip with process monitoring figure
Region abandons the chip area.
The wafer according to an embodiment of the present invention for being applied to 8 inches is described in conjunction with attached drawing, 3 above.Further, this hair
It is bright to be applied to 12 inch wafers.
In conclusion a kind of design method of silicon chip size package scribe line of the present invention, by the process monitoring figure of scribe line
It is placed into chip interior, to guarantee that the clean and process monitoring parameter of scribe line is complete, reduces sliver risk.
It should be noted that, in this document, the relational terms (if present) such as " first ", " second ", " third " is only
Only it is used to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying these realities
There are any actual relationship or orders between body or operation.It should be understood that the term used in this way is in the appropriate case
Can be interchanged, so as to the embodiment of the present invention described herein, such as can in addition to those of illustrate or describe herein with
Outer sequence is implemented.In addition, the terms "include", "comprise", " having " or its any other variant are intended to nonexcludability
Include so that include a series of elements process, method, article or terminal device not only include those elements, and
It and further include other elements that are not explicitly listed, or further include for this process, method, article or terminal device institute
Intrinsic element.In the absence of more restrictions, the element limited by sentence " including ... " or " including ... ", not
There is also other elements in process, method, article or the terminal device for including the element for exclusion.In addition, herein
In, " being greater than ", " being less than ", " being more than " etc. are interpreted as not including this number；" more than ", " following ", " within " etc. be interpreted as including this
Number.
It is discussed in detail although the contents of the present invention have passed through above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read above content, for of the invention
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (5)
1. a kind of design method of silicon chip size package scribe line characterized by comprising
Several regions are selected in the array of the chip of wafer；
Process monitoring figure is concentrated into the region of selection.
2. the design method of silicon chip size package scribe line as described in claim 1, which is characterized in that the wafer is carrying out
In silicon wafer grade encapsulating products process, a scribe line is formed between two adjacent chips.
3. the design method of silicon chip size package scribe line as described in claim 1, which is characterized in that the design method into
One step includes:
Remove the process monitoring figure that is placed in scribe line so that do not placed in the scribe line any band metal wiring layer and
The data of metallic vias.
4. the design method of silicon chip size package scribe line as described in claim 1, which is characterized in that the width of the scribe line
Degree is between 45 microns to 80 microns.
5. the design method of silicon chip size package scribe line as described in claim 1, which is characterized in that the wafer is 8 English
It is very little or 12 inches.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811069368.8A CN109216178A (en) | 2018-09-13 | 2018-09-13 | A kind of design method of silicon chip size package scribe line |
| PCT/CN2019/105337 WO2020052584A1 (en) | 2018-09-13 | 2019-09-11 | Design method for scribe line of silicon wafer level package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811069368.8A CN109216178A (en) | 2018-09-13 | 2018-09-13 | A kind of design method of silicon chip size package scribe line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109216178A true CN109216178A (en) | 2019-01-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811069368.8A Pending CN109216178A (en) | 2018-09-13 | 2018-09-13 | A kind of design method of silicon chip size package scribe line |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109216178A (en) |
| WO (1) | WO2020052584A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020052584A1 (en) * | 2018-09-13 | 2020-03-19 | 普冉半导体（上海）有限公司 | Design method for scribe line of silicon wafer level package |
| WO2022077502A1 (en) * | 2020-10-16 | 2022-04-21 | 华为技术有限公司 | Wafer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070293020A1 (en) * | 2006-06-20 | 2007-12-20 | Infineon Technologies Ag | Singulating semiconductor wafers to form semiconductor chips |
| CN102810517A (en) * | 2011-06-03 | 2012-12-05 | Nxp股份有限公司 | Semiconductor wafer and method of producing the same |
| US20140264767A1 (en) * | 2013-03-14 | 2014-09-18 | Infineon Technologies Ag | Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip |
| CN105336685A (en) * | 2014-07-21 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Wafer cutting method possessing test pattern |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216178A (en) * | 2018-09-13 | 2019-01-15 | 普冉半导体（上海）有限公司 | A kind of design method of silicon chip size package scribe line |
-
2018
- 2018-09-13 CN CN201811069368.8A patent/CN109216178A/en active Pending
-
2019
- 2019-09-11 WO PCT/CN2019/105337 patent/WO2020052584A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070293020A1 (en) * | 2006-06-20 | 2007-12-20 | Infineon Technologies Ag | Singulating semiconductor wafers to form semiconductor chips |
| CN102810517A (en) * | 2011-06-03 | 2012-12-05 | Nxp股份有限公司 | Semiconductor wafer and method of producing the same |
| US20140264767A1 (en) * | 2013-03-14 | 2014-09-18 | Infineon Technologies Ag | Wafer, Integrated Circuit Chip and Method for Manufacturing an Integrated Circuit Chip |
| CN105336685A (en) * | 2014-07-21 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Wafer cutting method possessing test pattern |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020052584A1 (en) * | 2018-09-13 | 2020-03-19 | 普冉半导体（上海）有限公司 | Design method for scribe line of silicon wafer level package |
| WO2022077502A1 (en) * | 2020-10-16 | 2022-04-21 | 华为技术有限公司 | Wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020052584A1 (en) | 2020-03-19 |
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| PB01 | Publication | ||
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| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: Room 504, 560 Shengxia Road, Pudong New Area, Shanghai 200000 Applicant after: Praran semiconductor (Shanghai) Co.,Ltd. Address before: Room 503-504, 560 Midsummer Road, China (Shanghai) Free Trade Pilot Area, Pudong New Area, Shanghai 201210 Applicant before: PUYA SEMICONDUCTOR (SHANGHAI) Co.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190115 |
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| RJ01 | Rejection of invention patent application after publication |