WO2022077502A1

WO2022077502A1 - Wafer

Info

Publication number: WO2022077502A1
Application number: PCT/CN2020/121683
Authority: WO
Inventors: 刘新荣; 蔡振华; 周庆萍
Original assignee: 华为技术有限公司
Priority date: 2020-10-16
Filing date: 2020-10-16
Publication date: 2022-04-21
Also published as: CN116250068A

Abstract

Embodiments of the present application provide a wafer, relating to the technical field of chips, which can solve the problem that the thickness of an opaque film layer in an incomplete exposure unit cannot be completely monitored and controlled. The wafer comprises a first exposure unit and a second exposure unit; said second exposure unit is located at the outer periphery of said wafer; the number of chips in said second exposure unit is smaller than the number of chips in said first exposure unit; the wafer further comprises: first process monitoring patterns; at least one of said first process monitoring patterns is arranged on the area of each chip in said second exposure unit and/or on the dicing path around each of said chips; the second exposure unit comprises at least two chips.

Description

a wafer

technical field

The present application relates to the field of chip technology, and in particular, to a wafer.

Background technique

In the process of wafer fabrication, process monitoring is an important link, which can feedback the pros and cons of the processing technology in real time. Process monitoring includes overlay accuracy, feature size, film thickness, and electrical properties.

Among them, the performance of the chip in the wafer is closely related to the thickness of the film layer in the chip, so it is necessary to monitor the thickness of the film layer in real time during the production process of the wafer, and adjust the process parameters according to the monitoring results, so as to make the film thickness meet the design requirements. At present, the process monitoring method of the film thickness of the metal layer is to set a long process monitoring pattern formed synchronously with the metal layer in the exposure unit (shot) processed by the mask on the wafer, and use the process monitoring pattern to monitor the metal layer. The film thickness of the layers is monitored. Since projection exposure usually uses the same mask to sequentially expose multiple exposure units on the wafer, the position of the process monitoring pattern in the exposure unit is relatively fixed. For an incomplete exposure unit located at the edge of the wafer, due to the process The position of the monitoring pattern may not be on the wafer, so the incomplete exposure unit may not include the process monitoring pattern, so that the film thickness of the metal layer in the incomplete exposure unit cannot be completely monitored.

SUMMARY OF THE INVENTION

The embodiments of the present application provide a wafer, which can solve the problem that the thickness of an opaque film layer in an incomplete exposure unit cannot be fully monitored.

To achieve the above object, the application adopts the following technical solutions:

An embodiment of the present application provides a wafer, the wafer includes a first exposure unit and a second exposure unit; the second exposure unit is located at the periphery of the wafer, and both the first exposure unit and the second exposure unit are performed once using a mask The area covered by exposure on the wafer; the number of chips in the second exposure unit is smaller than the number of chips in the first exposure unit; the wafer further includes: a first process monitoring pattern; the first process monitoring pattern is used to monitor opaque parts in the chip. The thickness of the film layer, and the first process monitoring pattern is arranged on the same layer as the opaque film layer; at least one first process monitoring pattern is provided on the area of each chip and/or the dicing lane around each chip in the second exposure unit ; The second exposure unit includes at least two chips. Since at least one first process monitoring pattern is provided on the area of each chip and/or the dicing lane around each chip in the second exposure unit, each second exposure unit is correspondingly provided with the first process monitoring pattern, Therefore, the thickness of the opaque film layer in the chip included in each second exposure unit can be monitored by the first process monitoring pattern in the second exposure unit, so that the opaqueness of the second exposure unit in the wafer can be monitored. The thickness of the film layer is fully monitored. In addition, the embodiments of the present application can be compatible with the current wafer processing technology without increasing the complexity of the process.

In a possible implementation manner, at least one first process monitoring pattern is provided on an area of each chip in the first exposure unit and/or a dicing lane around each chip. Here, the thickness of the opaque film layer in the first exposure unit may be monitored using one or more first process monitoring patterns in the first exposure unit.

In a possible implementation manner, the wafer further includes a second process monitoring pattern; a second process monitoring pattern located on the dicing lane is correspondingly set in each first exposure unit; the second process monitoring pattern is used to monitor the first exposure The thickness of the opaque film layer in the chip included in the unit, and the second process monitoring pattern is arranged in the same layer as the opaque film layer; wherein, the area of the second process monitoring pattern is larger than the area of the first process monitoring pattern. Here, the thickness of the opaque film layer in the first exposure unit may be monitored by using the second process monitoring pattern in the first exposure unit. In addition, the second process monitoring pattern can also be used as a standard to determine whether the thickness of the opaque film layer in the first exposure unit obtained by using the first process monitoring pattern is accurate.

In a possible implementation manner, the wafer further includes a second process monitoring pattern; a second process monitoring pattern located on the dicing lane is correspondingly set in each second exposure unit; the second process monitoring pattern is used to monitor the second exposure The thickness of the opaque film layer in the chip included in the unit, and the second process monitoring pattern is arranged in the same layer as the opaque film layer; wherein, the area of the second process monitoring pattern is larger than the area of the first process monitoring pattern. The technical effect of the second process monitoring pattern set in the second exposure unit is the same as that of the second process monitoring pattern set in the first exposure unit, and reference may be made to the above-mentioned embodiments, which will not be repeated here.

In a possible implementation manner, the first process monitoring pattern includes a first bounding frame and a plurality of parallel shading bars arranged in the first bounding frame. A plurality of shading strips arranged in parallel are equivalent to a grating. The diffraction spectrum of the grating is measured and recorded, and the diffraction spectrum is fitted by a computer to obtain the thickness of the shading strips, that is, the thickness of the opaque film layer arranged on the same layer.

In a possible implementation manner, the directions of the light shielding bars in the first process monitoring pattern corresponding to two adjacent opaque film layers are perpendicular to each other. In this way, the mutual influence of the first process monitoring patterns of two adjacent layers when monitoring the thickness of the corresponding opaque film layers can be avoided.

In a possible implementation manner, the second process monitoring graph includes a second bounding box and a plurality of second process monitoring sub-graphs arranged in sequence within the second bounding box; wherein, each second process monitoring sub-graph Including a plurality of shading strips arranged in parallel. Each second process monitoring sub-pattern is equivalent to a grating. The diffraction spectrum of the grating is measured and recorded, and the diffraction spectrum is fitted by a computer to obtain the thickness of the shading bars in the second process monitoring sub-pattern, that is, the same layer setting can be obtained. The thickness of the opaque film layer.

In a possible implementation manner, the directions of the light shielding bars in the second process monitoring sub-pattern corresponding to two adjacent opaque film layers are perpendicular to each other. In this way, the mutual influence of the second process monitoring patterns of two adjacent layers when monitoring the thickness of the corresponding opaque film layers can be avoided.

In a possible implementation manner, the shape of the first bounding frame is a polygon or a circle.

In a possible implementation manner, a first process monitoring pattern is provided on each dicing lane around the chip. In this way, the thickness of the opaque film layer in the chip can be monitored by using a plurality of first process monitoring patterns on each dicing lane around the chip, so as to ensure the accuracy of the thickness of the obtained opaque film layer.

Description of drawings

1 is a schematic structural diagram of a wafer according to an embodiment of the present application;

2 is a schematic structural diagram of a process monitoring graph provided by the prior art;

3 is a schematic structural diagram of an exposure unit provided by the prior art;

4a is a schematic diagram of the positional relationship between a first process monitoring pattern and a second exposure unit according to an embodiment of the present application;

4b is a schematic diagram of the positional relationship between another first process monitoring pattern and a second exposure unit provided by an embodiment of the present application;

5 is a schematic diagram of the positional relationship between another first process monitoring pattern and a second exposure unit provided by an embodiment of the application;

6 is a schematic structural diagram of a first process monitoring graph provided by an embodiment of the present application;

7 is a schematic structural diagram of a multi-layer first process monitoring pattern provided by an embodiment of the present application;

8 is a positional relationship diagram of a second exposure unit, a first process monitoring pattern, and a second process monitoring pattern provided by an embodiment of the present application;

9 is a schematic structural diagram of a second process monitoring graph provided by an embodiment of the present application;

10 is a schematic structural diagram of an N-layer second process monitoring pattern provided by an embodiment of the application;

11a is a schematic diagram of the positional relationship between a first process monitoring pattern and a first exposure unit provided by an embodiment of the application;

FIG. 11b is a schematic diagram of the positional relationship between another first process monitoring pattern and a first exposure unit according to an embodiment of the present application;

11c is a schematic diagram of the positional relationship between still another first process monitoring pattern and the first exposure unit provided by the embodiment of the application;

12 is a schematic diagram of the positional relationship between a second process monitoring pattern and a first exposure unit provided by an embodiment of the application;

13 is a schematic diagram of a positional relationship between a first exposure unit, a first process monitoring pattern, and a second process monitoring pattern according to an embodiment of the present application.

Reference number:

10-wafer; 100-exposure unit; 100a-first exposure unit (complete exposure unit); 100b-first exposure unit (incomplete exposure unit); 101-cut lane; 102-process monitoring pattern; 1021- Process monitoring sub-graphic; 1022-bounding box; 103-first process monitoring graphic; 1031-shading bar; 1032-first limiting box; 104-second process monitoring graphic; 1041-second process monitoring sub-graphic; 1042-th Two bounding boxes.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art.

Hereinafter, the terms "first", "second", etc. are only used for convenience of description, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as "first", "second", etc., may expressly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality" means two or more, and "at least one" means one or more.

It should be noted that, in this application, words such as "exemplary" or "for example" are used to represent examples, illustrations or illustrations. Any embodiment or design described in this application as "exemplary" or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present the related concepts in a specific manner.

It should be understood that in the manufacturing process of the wafer, it is often necessary to form a specific pattern on the material film layer of the wafer through a photolithography process. The photolithography process includes an exposure process, and the exposure process may also be called a photocopying process. . Exposure processes generally include contact exposure, proximity exposure, and projection exposure. Due to the high exposure accuracy of projection exposure, projection exposure is mainly used in the current exposure process, especially for the production of miniaturized chips, projection exposure has become the mainstream. The reticle used in projection exposure (also known as a mask) can only cover a small square area on the wafer at one time (the coverage area of the reticle can be a square or a rectangle), and after exposing one area, move it to an adjacent area. The next area continues to be exposed, covering the entire wafer through S-shaped scanning or stepper exposure. For a certain product, the effective area of each exposure is fixed and repeated in the up, down, left, and right directions of the wafer. The area of each exposure is called shot, and the area covered by each exposure or the area covered by each exposure can also be called the exposure unit. In projection exposure, each reticle is aligned with the previous reticle, and the exposure area requires high-precision coincidence. Since the circuit of each chip (also called die) is the same, the pattern on the photomask is the same. In this way, the number of chips in the shot is reasonably designed, and the entire wafer is sequentially exposed several times through the photomask. After that, the exposure of the whole wafer can be realized. And because only one mask is needed, the cost can be well controlled, and efficiency can be taken into account at the same time by rationally designing the number of chips in the area covered by the mask.

As shown in FIG. 1 , since the shape of the wafer 10 is circular, in the exposure process when the wafer 10 is fabricated, in addition to the complete exposure unit 100a, the edge of the wafer 10 also includes incomplete exposure units 100a. Exposure unit 100b. The chips in the complete exposure unit 100a in FIG. 1 are denoted by "1", and the chips in the incomplete exposure unit 100b are denoted by "2". In the prior art, the process monitoring method for the film thickness of the metal layer in the wafer 10 is to set a long process monitoring pattern in an exposure unit 100 . As shown in FIG. 2 , the strip-shaped process monitoring graphic in the prior art (for example, the strip-shaped process monitoring graphic may be a pad line) 102 includes a bounding box 1022 and is disposed within the bounding box 1022 A plurality of process monitoring sub-patterns 1021 arranged in sequence in one direction. FIG. 2 illustrates N process monitoring sub-graphs 1021 . Since the process monitoring graphic 102 in the prior art is a long striped graphic including a plurality of process monitoring sub-graphics 1021, the area of the process monitoring graphic 102 is relatively large, so only one process monitoring graphic 102 can be set in one exposure unit 100 .

Based on the above-mentioned projection exposure process, since projection exposure usually uses the same mask to sequentially expose multiple exposure units on the wafer, the position of the process monitoring pattern 102 set in each exposure unit 100 is the same. For the exposure unit 100b with an incomplete edge of the circle 10, since the incomplete exposure unit 100b has fewer chips than the complete exposure unit 100a, the process monitoring pattern 102 may not be set in some incomplete exposure units 100b. As an example, as shown in FIG. 3 , the exposure unit 100 includes 3*2 (ie, 3 rows and 2 columns) chips, and strips are arranged on the dicing lanes 101 under the chips in the first row and the first column of each exposure unit 100 Shaped process monitoring graph 102. However, for the incomplete exposure unit 100b that does not include the chips in the first row and the first column, since the process monitoring pattern 102 is not set in the incomplete exposure unit 100b, the metal in the incomplete exposure unit 100b cannot be The film thickness of the layers is monitored for the process. Therefore, the existing film thickness process monitoring method can only monitor the process of the complete exposure unit 100a. For the exposure unit 100b with an incomplete edge of the wafer 10, because some incomplete exposure units 100b are not provided with process monitoring graphics Therefore, the prior art cannot completely monitor the film thickness of the metal layer at the edge of the wafer 10 .

Based on this, an embodiment of the present application provides a wafer 10, as shown in FIG. 1, comprising: an exposure unit 100, the exposure unit 100 includes a first exposure unit 100a and a second exposure unit 100b; the second exposure unit 100b is located on the wafer In the periphery of 10, the first exposure unit 100a and the second exposure unit 100b are both areas covered on the wafer 10 by one exposure using a mask; the number of chips in the second exposure unit 100b is smaller than the number of chips in the first exposure unit 100a. quantity.

Here, the second exposure unit 100b is located at the periphery of the wafer 10, which means that the second exposure unit 100b has no other exposure units in at least one direction around the second exposure unit 100b. Referring to Fig. 1, for example, the second exposure unit 100b has no other exposure units to the right and above it. For another example, the second exposing unit 100b' has no other exposing units to the left and above thereof.

It should be noted that, in the embodiment of the present application, the chips in the first exposure unit 100a are represented by "1", and the chips in the second exposure unit 100b are represented by "2". In FIG. 1 , there may still be incomplete chips on the side of the chip 2 , and the incomplete chips are not shown in FIG. 1 .

Here, since the number of chips in the second exposure unit 100b is smaller than the number of chips in the first exposure unit 100a, the second exposure unit 100b may be called an incomplete exposure unit 100b, and the first exposure unit 100a may be called a complete exposure unit The exposure unit 100a of the second exposure unit 100b lacks some chips relative to the first exposure unit 100a.

In addition, in order to improve exposure efficiency, the first exposure unit 100a includes chips with m rows and n columns, wherein m≧2, n≧2, and m and n are both positive integers. For example, the first exposure unit 100a includes 3*2 chips, that is, includes 3 rows and 2 columns of chips. For another example, the first exposure unit 100a includes 10*8 chips, that is, includes 10 rows and 8 columns of chips.

As shown in FIGS. 4 a , 4 b and 5 , the wafer 10 provided by the embodiment of the present application further includes: a first process monitoring pattern 103 , the first process monitoring pattern 103 is used to monitor the thickness of the opaque film layer in the chip, and The first process monitoring pattern 103 is disposed on the same layer as the opaque film layer. Wherein, at least one first process monitoring pattern 103 is provided on an area of each chip and/or a dicing lane around each chip in the second exposure unit 100b; the second exposure unit 100b includes at least two chips.

The above-mentioned "opaque film layer" can be, for example, a metal layer or an opaque insulating layer, and the material of the insulating layer is, for example, black resin or non-conductive graphite.

Here, for the second exposure unit 100b including only one chip, at least one first process monitoring pattern 103 is provided on the area of the chip in the second exposure unit 100b and/or the dicing lane around the chip.

It should be understood that after the wafer 10 is fabricated, in order to separate multiple chips in the wafer 10, the wafer 10 needs to be cut. Therefore, the wafer 10 includes a dicing lane 101 disposed between two adjacent chips. The wafer 10 is diced along the dicing lane 101 at the same time.

Here, the wafer 10 includes a plurality of chips and dicing lines 101 for separating the plurality of chips, and the area occupied by each chip is referred to as the area of the chip.

It should be noted that, for the setting position of the first process monitoring pattern 103, as shown in FIG. 4a, at least one first process monitoring pattern 103 is set in the region of each chip in the second exposure unit 100b, that is, the first process monitoring pattern 103 is set to A process monitoring pattern 103 is arranged inside the chip; as shown in FIG. 4b, at least one first process monitoring pattern 103 is arranged on the dicing lane 101 around each chip in the second exposure unit 100b; of course, it can also be As shown in FIG. 5 , each chip in the second exposure unit 100b is not only provided with at least one first process monitoring pattern 103 in the area where the chip is located, but also provided with at least one first process monitoring pattern 101 on the dicing line 101 around the chip Graphics 103.

It should be understood that the first process monitoring pattern 103 is disposed on the cutting line 101 , that is, the first process monitoring pattern 103 is completely located on the cutting line 101 . For the dicing road 101 between two adjacent chips, the first process monitoring pattern 103 on the dicing road 101 can be regarded as the first process monitoring pattern 103 set on the dicing road 101 around one of the chips, or can be regarded as The first process monitoring pattern 103 provided on the dicing line 101 around the other chip.

In addition, a first process monitoring pattern 103 may be provided on at least one dicing line 101 of the plurality of dicing lines 101 around the chip. In some embodiments, a first process monitoring pattern 103 is disposed on each of the plurality of scribe lines 101 around the chip. For example, there are four dicing lanes 101 around the chip, and the first process monitoring patterns 103 are set on the four dicing lanes 101. In this way, the plurality of first process monitoring patterns 103 on each dicing lane 101 around the chip can be used. The thickness of the opaque film layer in the chip is monitored to ensure the accuracy of the thickness of the resulting opaque film layer.

Here, the first process monitoring pattern 103 is arranged on the dicing road 101. Since the material on the dicing road 101 is removed after the wafer 10 is cut into chips, the first process monitoring pattern 103 can be prevented from occupying the chip. design space.

It should be understood that the first process monitoring pattern 103 set in the above-mentioned wafer 10 should not affect the circuit design and function of the chip.

On this basis, the first process monitoring pattern 103 and the opaque film layer are arranged in the same layer, that is, the first process monitoring pattern 103 and the opaque film layer are produced simultaneously, so that the first process monitoring pattern 103 and the opaque film layer are produced simultaneously. of the same material and of the same thickness.

It should be noted that, when the wafer 10 includes multiple opaque film layers, for the opaque film layer whose thickness needs to be monitored, the first process monitoring pattern 103 can be produced while the opaque film layer is produced, and after the production is completed After the opaque film layer and the first process monitoring pattern 103, since at least one first process monitoring pattern 103 is provided on the area of each chip and/or the dicing lane 101 around each chip in the second exposure unit 100b, therefore Each second exposure unit 100b corresponds to at least one first process monitoring pattern 103, so that the opaque film in the second exposure unit 100b can be obtained by using at least one first process monitoring pattern 103 in the second exposure unit 100b Determine whether the thickness of the obtained opaque film meets the design requirements, if not, adjust the process according to the thickness of the obtained opaque film, so that the thickness of the opaque film meets the design requirements .

In some embodiments, as shown in FIG. 6 , the structure of the first process monitoring pattern 103 includes a first confinement frame 1032 and a plurality of light shielding bars 1031 arranged in parallel in the first confinement frame 1032 .

Here, the first confinement frame 1032 and the light-shielding strip 1031 are made of the same material and are fabricated simultaneously.

In some embodiments, the shape of the first bounding box 1032 is a polygon or a circle. Polygons are, for example, squares or hexagons.

Since the structure of the first process monitoring pattern 103 includes a plurality of light shielding bars 1031 arranged in parallel, the first process monitoring pattern 103 is equivalent to a grating. The specific process of "using at least one first process monitoring pattern 103 in the second exposure unit 100b to obtain the thickness of the opaque film layer in the second exposure unit 100b" is as follows: the opaque film layer is synchronized with the first process monitoring pattern 103 After the production is completed, look for the first process monitoring pattern 103, align the first process monitoring pattern 103, measure and record the diffraction spectrum of the grating, and use the computer to fit the diffraction spectrum to obtain the thickness of the shading strip 1031, that is, the first process. The thickness of the monitoring pattern 103, and the thickness of the first process monitoring pattern 103 and the monitored opaque film layer are the same, that is, the thickness of the opaque film layer can be obtained.

In addition, when the opaque film layer in the second exposure unit 100b is disposed in the same layer as the plurality of first process monitoring patterns 103, one of the first process monitoring patterns 103 in the second exposure unit 100b can be used to obtain the first process monitoring pattern 103 in the second exposure unit 100b. The thickness of the opaque film layer; it is also possible to obtain a plurality of thickness values of the opaque film layer in the second exposure unit 100b by using a plurality of first process monitoring patterns 103 in the second exposure unit 100b, respectively, and then compare the plurality of thickness values. The average value is taken to obtain the thickness of the opaque film layer in the second exposure unit 100b, which can improve the accuracy of the obtained thickness of the opaque film layer.

In addition, exemplarily, the opaque film layer and the first process monitoring pattern 103 can be fabricated according to the following steps. First, an insulating film is formed; then, the insulating film is patterned to form an insulating layer, and the insulating layer includes a first groove, multiple two parallel strip-shaped second grooves and a third groove surrounding the second groove, where the first groove and the orthographic projection of the opaque film layer to be formed on the substrate completely overlap; Opaque film such as metal film; next, remove the metal film outside the first groove, the second groove and the third groove, that is, form a metal layer in the first groove, and form a metal line in the second groove , a first confinement frame 1032 is formed in the third groove, and a plurality of metal lines arranged in parallel and the first confinement frame 1032 surrounding the metal lines constitute the first process monitoring pattern 103 . It should be understood that the depths of the first groove, the second groove and the third groove should be greater than or equal to the thickness of the designed metal thin film.

It should be noted that, when the wafer 10 includes a multi-layered opaque film layer, a multi-layered first process monitoring pattern 103 may be provided, and one layer of the first process monitoring pattern 103 is used to monitor the The thickness of an opaque film layer was monitored. In order to avoid a large space occupied by the first process monitoring patterns 103 , in some embodiments, the spaces occupied by the multi-layer first process monitoring patterns 103 overlap.

On this basis, in the case where the wafer 10 includes a multi-layered opaque film layer and a multi-layered first process monitoring pattern 103, in order to avoid using the first process monitoring pattern 103 to obtain an opaque layer arranged in the same layer When the thickness of the film layer is 100%, the two adjacent first process monitoring patterns 103 corresponding to the two adjacent opaque film layers influence each other, so in some embodiments, the first process corresponding to the adjacent two opaque film layers The directions of the light shielding bars 1031 in the monitoring pattern 103 are not parallel. Further, in order to improve the accuracy of the thickness of the obtained opaque film layers, in some examples, as shown in FIG. 7 , the shading bars 1031 in the first process monitoring pattern 103 corresponding to two adjacent opaque film layers are directions are perpendicular to each other.

FIG. 7 illustrates the six-layer first process monitoring pattern 103, which are the first layer first process monitoring pattern 103a, the second layer first process monitoring pattern 103b, the third layer first process monitoring pattern 103c, and the fourth layer first process monitoring pattern 103c, respectively. A process monitoring pattern 103d, a first process monitoring pattern 103e on the fifth layer, and a first process monitoring pattern 103f on the sixth layer.

An embodiment of the present application provides a wafer 10, the wafer 10 includes a first exposure unit 100a and a second exposure unit 100b; the second exposure unit 100b is located at the periphery of the first exposure unit 100a, the first exposure unit 100a and the second exposure unit 100b The exposure units 100b are all areas covered on the wafer 10 by one exposure using a mask; the number of chips in the second exposure unit 100b is smaller than the number of chips in the first exposure unit 100a. The wafer 10 further includes a first process monitoring pattern 103, the first process monitoring pattern 103 is used to monitor the thickness of the opaque film layer in the chip, and the first process monitoring pattern 103 and the opaque film layer are arranged in the same layer; the second exposure unit At least one first process monitoring pattern 103 is disposed on the area of each chip in 100b and/or the dicing lane 101 around each chip; the second exposure unit 100b includes at least two chips. Compared with the prior art in which a long process monitoring pattern 102 is set in one exposure unit 100, since the second exposure unit 100b has fewer chips than the first exposure unit 100a, some of the second exposure units 100b may have fewer chips. The process monitoring pattern 102 is not provided, so that the film thickness of the second exposure unit 100b in the wafer 10 cannot be completely monitored. At least one first process monitoring pattern 103 is provided on the dicing lanes 101 around each chip, so each second exposure unit 100b is correspondingly provided with the first process monitoring pattern 103, so the chips included in each second exposure unit 100b The thickness of the opaque film layer in the wafer 10 can be monitored by the first process monitoring pattern 103 in the second exposure unit 100b, so that the thickness of the opaque film layer in the second exposure unit 100b in the wafer 10 can be monitored. Full monitoring. In addition, the embodiments of the present application can be compatible with the current processing technology of the wafer 10 without increasing the complexity of the process.

In some embodiments, as shown in FIG. 8 , the wafer 10 further includes a second process monitoring pattern 104; a second process monitoring pattern 104 located on the dicing lane 101 is correspondingly provided in each second exposure unit 100b; The process monitoring pattern 104 is used to monitor the thickness of the opaque film layer in the chip included in the second exposure unit 100b, and the second process monitoring pattern 104 is arranged in the same layer as the opaque film layer; wherein, the area of the second process monitoring pattern 104 is larger than The first process monitors the area of the pattern 103 .

Here, for the setting position of the second process monitoring pattern 104, the circuit design and function in the chip are not affected.

It should be understood that, since the second exposure unit 100b is an incomplete exposure unit, the second exposure unit 100b has less chips than the first exposure unit 100a, and the position of the second process monitoring pattern 104 in the second exposure unit 100b is fixed , so the second process monitoring pattern 104 may not be set in some of the second exposure units 100b. By way of example, referring to FIG. 8 , the exposure unit 100 includes chips in 3 rows and 2 columns, and a dicing line 101 is arranged between the chips in the first row and the first column and the chips in the second row and the first column in the second exposure unit 100b. 2. Process monitoring graph 104. For the second exposure unit 100b that does not include the chips in the first row and the first column and the chips in the second row and the first column, the second process monitoring pattern 104 is not provided.

When the second exposure unit 100b includes the second process monitoring pattern 104, the second process monitoring pattern 104 can be used to monitor the thickness of the opaque film layer in the second exposure unit 100b, and the first process monitoring pattern 103 can also be used to monitor the thickness of the opaque film layer in the second exposure unit 100b. The thickness of the opaque film layer in the second exposure unit 100b.

It should be noted that, the second process monitoring graph 104 in the embodiment of the present application may be the same as the process monitoring graph 102 in the prior art. On this basis, since the method of monitoring the thickness of the opaque film layer by using the process monitoring pattern 102 is very mature, in this embodiment of the present application, the second exposure unit 100b includes the first process monitoring pattern 103 and the second process monitoring pattern 103 . When the pattern 104 is used, the second process monitoring pattern 104 can be used as a standard to determine whether the thickness of the opaque film layer in the second exposure unit 100b obtained by using the first process monitoring pattern 103 is accurate. Specifically, if the thickness of the opaque film layer in the second exposure unit 100b obtained by using the first process monitoring pattern 103 and the second process monitoring pattern 104 does not meet the design requirements, the process needs to be adjusted so that the opaque film layer The thickness meets the design requirements. If the thickness of the opaque film layer in the second exposure unit 100b obtained by using the second process monitoring pattern 104 does not meet the design requirements, and the thickness of the opaque film layer in the second exposure unit 100b obtained by using the first process monitoring pattern 103 The thickness meets the design requirements; or, the thickness of the opaque film layer in the second exposure unit 100b obtained by using the second process monitoring pattern 104 meets the design requirements, while the opaque film layer in the second exposure unit 100b obtained by using the first process monitoring pattern 103 The thickness of the film layer does not meet the design requirements. At this time, it is necessary to adjust or modify the thickness of the opaque film layer in the second exposure unit 100b obtained by using the first process monitoring pattern 103, so as to make it different from the method using the first process monitoring pattern 103. The thickness of the opaque film layer in the second exposure unit 100b obtained from the two process monitoring patterns 104 is the same.

In some embodiments, as shown in FIG. 9 , the second process monitoring graph 104 includes a second bounding box 1042 and a plurality of second process monitoring sub-graphs 1041 arranged in sequence within the second bounding box 1042 ; The second process monitoring sub-pattern 1041 includes a plurality of shading bars 1031 arranged in parallel.

It should be noted that the light shielding bars 1031 in each of the second process monitoring sub-graphics 1041 in the second process monitoring graph 104 are parallel.

In some embodiments, the shape of the second bounding box 1042 is a polygon or a circle. Polygons are, for example, squares or hexagons.

Here, one or more second process monitoring sub-patterns 1041 in the second process monitoring pattern 104 may be used to monitor the thickness of the opaque film layer disposed on the same layer as the second process monitoring pattern 104 . Each second process monitoring sub-pattern 1041 is equivalent to a grating, and the method for obtaining the thickness of the opaque film layer using the second process monitoring sub-pattern 1041 is the same as the method for obtaining the thickness of the opaque film layer using the first process monitoring pattern 103 above. , you can refer to the above, which will not be repeated here.

In addition, the manufacturing method of each second process monitoring sub-pattern 1041 in the second process monitoring pattern 104 may refer to the above-mentioned manufacturing method of the first process monitoring pattern 103, which will not be repeated here.

In addition, when the wafer 10 includes a multi-layered opaque film layer, a multi-layered second process monitoring pattern 104 can be provided, and one layer of the second process monitoring pattern 104 is used for the opaque layer disposed on the same layer. The thickness of the film layer was monitored.

On this basis, in the case where the wafer 10 includes a multi-layered opaque film layer and a multi-layered second process monitoring pattern 104, in order to avoid using the second process monitoring pattern 104 to obtain an opaque layer arranged in the same layer When the thickness of the adjacent two opaque film layers corresponds to the two second process monitoring patterns 104, the two adjacent layers of the second process monitoring pattern 104 affect each other. The directions of the shading bars 1031 in the monitoring pattern 104 are not parallel. Further, in order to improve the accuracy of the thickness of the obtained opaque film layers, in some examples, the directions of the light shielding bars 1031 in the second process monitoring pattern 104 corresponding to two adjacent opaque film layers are perpendicular to each other.

In the case where the wafer 10 includes the second process monitoring patterns 104 arranged in multiple layers, in order to avoid a large space occupied by the second process monitoring patterns 104 , in some embodiments, the multi-layer second process monitoring patterns 104 are The space occupied overlaps.

In some embodiments, if the thickness of the N opaque film layers in the chip needs to be monitored, as shown in FIG. 10 , the second process monitoring pattern 104 disposed on the same layer as the first opaque film layer includes N The second process monitoring sub-pattern 1041a arranged in sequence; the second process monitoring sub-pattern 104 arranged in the same layer as the second opaque film layer includes N-1 second process monitoring sub-patterns 1041b arranged in sequence, the second process monitoring sub-pattern 1041b. The shading bars in the pattern 1041b and the shading bars in the second process monitoring sub-pattern 1041a are not parallel (for example, perpendicular to each other), and the space occupied by the N-1 second process monitoring sub-patterns 1041b arranged in sequence is the same as that of the N-1 The space occupied by the second process monitoring sub-graphics 1041a arranged in sequence overlaps; the second process monitoring graphics 104 arranged on the same layer as the third opaque film layer includes N-2 second process monitoring sub-graphics 1041c arranged in sequence, The light-shielding bars in the second process monitoring sub-pattern 1041c and the light-shielding bars in the second process monitoring sub-pattern 1041b are not parallel (for example, perpendicular to each other), and the space occupied by the N-2 second process monitoring sub-patterns 1041c arranged in sequence It overlaps with the space occupied by the N-2 second process monitoring sub-patterns 1041b arranged in sequence; and so on, the second process monitoring pattern 104 arranged in the same layer as the N-2 opaque film layer includes three sequentially arranged sub-patterns 104 . The second process monitoring sub-pattern 1041d; the second process monitoring pattern 104 arranged on the same layer as the N-1th opaque film layer includes two second process monitoring sub-patterns 1041e arranged in sequence. In the second process monitoring sub-pattern 1041e The shading strips are not parallel (for example, perpendicular to each other) with the shading strips in the second process monitoring sub-pattern 1041d, and the space occupied by the two second process monitoring sub-patterns 1041e is the same as the space occupied by the two second process monitoring sub-patterns 1041d. The space overlaps; the second process monitoring pattern 104 set on the same layer as the Nth opaque film layer includes a second process monitoring sub-pattern 1041f, the shading bar in the second process monitoring sub-pattern 1041f and the second process monitoring sub-pattern 1041f The shading bars in the pattern 1041e are not parallel (for example, perpendicular to each other), and the second process monitoring sub-pattern 1041f overlaps with the space occupied by one second process monitoring sub-pattern 1041e.

Based on the above, for the first exposure unit 100 a in the wafer 10 , the following three methods can be used to set the process monitoring pattern, so as to monitor the thickness of the opaque film layer in the chip included in the first exposure unit 100 a.

method one:

As shown in FIGS. 11 a , 11 b and 11 c , at least one first process monitoring pattern 103 is disposed on the area of each chip and/or the dicing lane around each chip in the first exposure unit 100 a .

Here, as shown in FIG. 11a, at least one first process monitoring pattern 103 is provided in the area of each chip in the first exposure unit 100a, that is, the first process monitoring pattern 103 is arranged inside the chip; or As shown in FIG. 11b, at least one first process monitoring pattern 103 is provided on the dicing lane 101 around each chip in the first exposure unit 100a; of course, as shown in FIG. 11c, in the first exposure unit 100a Each of the chips is not only provided with at least one first process monitoring pattern 103 in the region where the chip is located, but also provided with at least one first process monitoring pattern 103 on the dicing line 101 around the chip.

In some embodiments, the sum of the number of the first process monitoring patterns 103 provided on the area of any chip in the wafer 10 and the dicing lanes 101 around the chip and the area of another chip and the dicing lanes 101 around the chip The number of the first process monitoring patterns 103 set on the wafer is the same, and the position of the first process monitoring patterns 103 set on the area of any chip in the wafer 10 and the dicing lane 101 around the chip relative to the chip is the same as that of the other chip. The position of the first process monitoring pattern 103 set on the area and the dicing line 101 around the chip is the same relative to the chip. The above "any chip" and "another chip" may both refer to the chip in the first exposure unit 100a; they may also both refer to the chip in the second exposure unit 100b; of course, one may also be the chip in the first exposure unit 100a. chip, and the other is the chip in the second exposure unit 100b.

It should be noted that, because the area of any chip in the wafer 10 and the number of the first process monitoring patterns 103 set on the dicing road 101 around the chip are combined with the area of another chip and the dicing road 101 around the chip The number of the first process monitoring patterns 103 set on the wafer is the same, and the position of the first process monitoring patterns 103 set on the area of any chip in the wafer 10 and the dicing lane 101 around the chip relative to the chip is the same as that of the other chip. The position of the area and the first process monitoring pattern 103 set on the dicing road 101 around the chip is the same relative to the chip, so the area of any chip and the first process monitoring pattern 103 set on the dicing road 101 around the chip are at the same time. After moving up, down, left or right, it can completely overlap the area of another chip and the first process monitoring pattern 103 set on the dicing line 101 around the chip.

For example, referring to FIG. 4a and FIG. 11a, a first process monitoring pattern 103 is provided in the center area of each chip. For another example, referring to FIG. 4b and FIG. 11b, eight first process monitoring patterns 103 are arranged on the dicing lanes 101 around each chip, and the eight first process monitoring patterns 103 are respectively located on the four sides of the chip, two adjacent to each other. The first process monitoring patterns 103 on the overlapping sides of the two chips also overlap.

In the embodiment of the present application, since the area of any chip in the wafer 10 and the number of the first process monitoring patterns 103 set on the dicing road 101 around the chip are combined with the area of another chip and the dicing road around the chip The sum of the numbers of the first process monitoring patterns 103 set on the 101 is the same, and the position of the first process monitoring patterns 103 set on the area of any chip in the wafer 10 and the dicing lane 101 around the chip relative to the chip is the same as that of the other chip. The region of a chip and the first process monitoring pattern 103 set on the dicing lane 101 around the chip are at the same position relative to the chip, so during the manufacturing process of the wafer 10, the same mask can be used to manufacture the first exposure unit 100a and the first process monitoring pattern 103 in the second exposure unit 100b, reducing the production cost.

Method two:

As shown in FIG. 12 , the wafer further includes a second process monitoring pattern 104; a second process monitoring pattern 104 located on the dicing lane 101 is correspondingly set in each first exposure unit 100a; the second process monitoring pattern 104 is used for monitoring The thickness of the opaque film layer in the chip included in the first exposure unit 100a, and the second process monitoring pattern 104 is arranged in the same layer as the opaque film layer; wherein, the area of the second process monitoring pattern 104 is larger than that of the first process monitoring pattern 103. area.

It should be noted that, for the structure and manufacturing method of the second process monitoring pattern 104, reference may be made to the foregoing embodiments, and details are not described herein again.

way three

As shown in FIG. 13 , at least one first process monitoring pattern 103 is provided on the area of each chip and/or on the dicing lane around each chip in the first exposure unit 100a, and each first exposure unit 100a is correspondingly provided with A second process monitoring pattern 104 is located on the scribe line 101 .

Since the first exposure unit 100a includes the first process monitoring pattern 103 and the second process monitoring pattern 104, the first process monitoring pattern 103 can be used to monitor the thickness of the opaque film layer in the first exposure unit 100a, and the second process can also be used The monitoring pattern 104 monitors the thickness of the opaque film layer in the first exposure unit 100a.

In some embodiments, the first exposure unit 100a includes a second process monitoring pattern 104 , and the second exposure unit 100b includes a first process monitoring pattern 103 . In this case, the thickness of the opaque film layer in the first exposure unit 100a can be monitored using the second process monitoring pattern 104, and the thickness of the opaque film layer in the second exposure unit 100b can be monitored using the first process monitoring pattern 103. Since the first exposure unit 100a is a complete exposure unit, each first exposure unit 100a is provided with the second process monitoring pattern 104, so the second process monitoring pattern 104 can be used to monitor the opaque film in the first exposure unit 100a. The thickness of the layer is completely monitored, and the thickness of the opaque film layer in the first exposure unit 100a can be detected by using a second process monitoring pattern 104, which improves the detection efficiency. However, in the second exposure unit 100b, at least one first process monitoring pattern 103 is set on the area of each chip and/or on the dicing lane 101 around each chip, so each second exposure unit 100b is correspondingly provided with a first process monitoring pattern 103. The process monitoring pattern 103 can thus ensure complete monitoring of the thickness of the opaque film layers in each second exposure unit 100b.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention. should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

A wafer, characterized in that, comprising:

a first exposure unit and a second exposure unit; wherein the second exposure unit is located at the periphery of the wafer; the number of chips in the second exposure unit is smaller than the number of chips in the first exposure unit;

The wafer also includes: a first process monitoring pattern;

Wherein, at least one of the first process monitoring patterns is provided on an area of each chip and/or a dicing lane around each chip in the second exposure unit; the second exposure unit includes at least two chips .
The wafer according to claim 1, wherein at least one of the first process monitoring patterns is provided on an area of each chip in the first exposure unit and/or a dicing lane around each chip .
The wafer according to claim 1 or 2, characterized in that, the wafer further comprises a second process monitoring pattern; each of the first exposure units is correspondingly provided with a second process monitoring pattern located on a dicing lane graphics;

Wherein, the area of the second process monitoring pattern is larger than the area of the first process monitoring pattern.
The wafer according to any one of claims 1-3, characterized in that, the wafer further comprises a second process monitoring pattern; each of the second exposure units is correspondingly provided with one of the first 2. Process monitoring graphics;

The second process monitoring pattern is used to monitor the thickness of the opaque film layer in the chip included in the second exposure unit, and the second process monitoring pattern is arranged in the same layer as the opaque film layer;

Wherein, the area of the second process monitoring pattern is larger than the area of the first process monitoring pattern.
The wafer according to claim 1 or 2, wherein the first process monitoring pattern comprises a first confinement frame and a plurality of light-shielding bars arranged in parallel in the first confinement frame.
The wafer according to claim 5, wherein the directions of the light-shielding bars in the first process monitoring pattern corresponding to two adjacent opaque film layers are perpendicular to each other.
The wafer according to claim 3 or 4, wherein the second process monitoring pattern comprises a second bounding box and a plurality of second process monitoring sub-patterns arranged in sequence within the second bounding box ;

Wherein, each of the second process monitoring sub-patterns includes a plurality of shading bars arranged in parallel.
The wafer according to claim 7, wherein directions of the light-shielding bars in the second process monitoring sub-pattern corresponding to two adjacent opaque film layers are perpendicular to each other.
The wafer according to claim 5, wherein the shape of the first confinement frame is a polygon or a circle.
The wafer according to claim 1 or 2, wherein the first process monitoring pattern is provided on each of the dicing lanes around the chip.