CN210429826U

CN210429826U - Power semiconductor device

Info

Publication number: CN210429826U
Application number: CN201921347175.4U
Authority: CN
Inventors: 郭依腾; 史波
Original assignee: Gree Electric Appliances Inc of Zhuhai
Current assignee: Gree Electric Appliances Inc of Zhuhai
Priority date: 2019-08-16
Filing date: 2019-08-16
Publication date: 2020-04-28
Anticipated expiration: 2029-08-16

Abstract

The application relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a novel structure. The power semiconductor device comprises a back metal layer, a substrate, an epitaxial layer and a front structure which are sequentially stacked from bottom to top, wherein the back metal layer is connected with the epitaxial layer through metal arranged in the substrate. In the preparation process of the power semiconductor device, the substrate does not need to be thinned, and the back electrode is led out by adopting a lead hole technology. On the basis of not influencing the welding process and the electrical property of the power semiconductor device, the thinning process is cancelled, the substrate is kept as a support, the risk of fragments in the thinning process and the subsequent sheet manufacturing process is avoided, and the cost is saved.

Description

Power semiconductor device

Technical Field

The application relates to the technical field of power semiconductor devices, in particular to a power semiconductor device with a novel structure.

Background

In order to ensure the on-resistance or voltage drop of the chip, the chip manufacturing process in the prior art performs back thinning treatment on the wafer after the front process is completed. With the continuous development of chip manufacturing technology, the thickness of a chip is continuously reduced, and with the thinner chip thickness, the wafer is damaged by the reduction process, so that abnormal problems such as wafer fragments, corner loss and the like are caused, and the higher and higher fragment rate is brought, particularly with the continuous increase of the size of the wafer, the wafer fragment rate also rises linearly, so that a great deal of cost is wasted; in addition, the stress of the wafer is changed by the thinning process, and the subsequent packaging and the like have reliability problems due to insufficient stress release.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem mentioned above or at least partially solve the technical problem mentioned above, the present application provides a power semiconductor device.

According to the power semiconductor device of the embodiment of the application, the power semiconductor device comprises a back metal layer, a substrate, an epitaxial layer and a front structure which are sequentially stacked from bottom to top, wherein the back metal layer is connected with the epitaxial layer through metal arranged in the substrate.

Furthermore, a through lead hole is formed in the substrate, and metal for connecting the back metal layer and the epitaxial layer is filled in the lead hole.

Further, the front structure includes at least one of a source electrode, a drain electrode, a gate electrode, an oxide layer, a field plate, and a passivation layer.

Further, the substrate includes one of a SiC substrate, a Si substrate, a sapphire substrate, and a GaN substrate.

Further, the lead holes are uniformly distributed in the range of the tube core original cell area of the power semiconductor device.

Furthermore, the metal is made of tungsten, and the metal is filled in the lead hole through a tungsten plug process.

Further, the back metal layer is formed on the substrate in a padding mode.

Furthermore, the material of the back metal layer is Al, Ti, Ni or Ag.

Furthermore, the lead hole is formed by etching in the substrate through a dry etching process or a wet etching process.

According to the power semiconductor device provided by the technical scheme, the substrate is not thinned, and the back electrode is led out by adopting a lead hole technology. On the basis of not influencing the welding process and the electrical property of the power semiconductor device, the thinning process is cancelled, the substrate is kept as a support, the risk of fragments in the thinning process and the subsequent sheet manufacturing process is avoided, and the cost is saved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, serve to provide a further understanding of the application and to enable other features, objects, and advantages of the application to be more apparent. The drawings and their description illustrate the embodiments of the invention and do not limit it. In the drawings:

FIG. 1 is a schematic diagram of a prior art power semiconductor device;

fig. 2 is a schematic structural diagram of a power semiconductor device according to an embodiment of the present disclosure;

fig. 3 to 8 are schematic structural diagrams corresponding to steps of a method for manufacturing a GaN power semiconductor device according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In this application, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation.

Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In the production practice, technicians find that, in order to ensure the on-resistance or voltage drop of a chip, the power semiconductor device manufacturing process in the prior art performs back thinning treatment on a wafer after the front process is completed. As shown in fig. 1, the substrate of the thinned power semiconductor device is removed and directly connected to the epitaxial layer through the back metal layer. The thinning process of the power semiconductor device shown in fig. 1 may damage a wafer, resulting in abnormal problems such as wafer fragments, corner chipping, etc., which may lead to higher and higher fragment rates, and particularly, as the size of the wafer is continuously increased, the wafer fragment rate is also increased linearly, which causes a great amount of cost waste; in addition, the stress of the wafer is changed by the thinning process, and the subsequent packaging and the like have reliability problems due to insufficient stress release.

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the thicknesses of layers and regions are exaggerated for convenience of description, and the sizes shown do not represent actual sizes. Although these figures do not reflect the actual dimensions of the device exactly, they do reflect the mutual positions of the regions and the constituent structures, in particular the upper and lower and adjacent relationships between the constituent structures. Referring to the drawings, which are schematic illustrations of idealized embodiments of the present invention, the illustrated embodiments of the present invention should not be considered limited to the particular shapes of regions illustrated in the drawings, but rather include resulting shapes, such as manufacturing-induced variations. Also in the following description, the term substrate will be used to be understood to include semiconductor substrates being processed, possibly including other thin film layers fabricated thereon.

As shown in fig. 3 to 8, the present embodiment discloses a method for manufacturing a power semiconductor device, which includes the following steps:

step 1: as shown in fig. 3, a substrate 2 is provided, an epitaxial layer 3 is formed on the substrate 2, and the fabrication of the front structure 4 of the power semiconductor device is completed.

The substrate 2 includes, but is not limited to, a SiC substrate, a Si substrate, a sapphire substrate, or a GaN substrate, among others. The epitaxial layer 3 may be formed by a chemical vapor deposition process, such as MOCVD. The epitaxial layer 3 may be n-type or p-type, and may be specifically set as needed, and the thickness of the epitaxial layer 3 may also be specifically set as needed, for example, the typical thickness of the epitaxial layer of a power semiconductor device for a high-speed digital circuit is 0.5 to 5 micrometers, and the typical thickness of the epitaxial layer for a silicon power device is 50 to 100 micrometers.

Step 2: and etching the back surface of the substrate 2, and etching the whole substrate 2 till the epitaxial layer 3 to form a lead hole 5.

The step may specifically include:

first, as shown in fig. 3, a protective film is attached to the front surface of the power semiconductor device having completed the front surface structure 4 to protect the front surface structure 4 of the power semiconductor device from scratches, stains, and the like of the front surface when the back surface of the power semiconductor device is handled. Preferably, the protective film includes, but is not limited to, a blue film, a UV film, a white film, or a dry film.

Then, the back surface of the substrate 2 in the structure shown in fig. 3 is cleaned, and the contamination and the excess film layer on the back surface of the substrate 2 are cleaned, so that the structure shown in fig. 4 is obtained.

Then, coating a photoresist on the back surface of the substrate 2, removing the photoresist at the lead hole position through a photolithography process to form a window, and exposing the substrate 2, thereby obtaining the structure shown in fig. 5.

Then, the substrate 2 in the area not covered by the photoresist is removed by etching, the whole substrate 2 is etched through to the epitaxial layer 3, and the lead holes 6 are made, so that the structure shown in fig. 6 is obtained. The etching process for forming the lead hole 6 may be a dry etching process or a wet etching process

Finally, after the substrate 2 is etched, the remaining photoresist and the protective film attached to the front surface are removed, so as to obtain the structure shown in fig. 7.

In this step, the positions of the lead holes 6 are uniformly distributed in the range of the cell area (cell area) of the die to ensure that no potential difference exists on the back surface, and the number of the lead holes 6 is preferably to ensure that the total area of the lead holes 6 on the back surface is larger than or equal to that of the lead holes on the front surface, so that the current conduction bottleneck is avoided.

And step 3: as shown in fig. 8, the wiring hole 6 is filled with metal 5, and a back metal layer 1 is formed on the back surface of the substrate 2 by pad-forming, and the alloy is annealed to wire the epitaxial layer 3 to the back metal layer 1 through the metal 5. Since the substrate 2 is usually relatively thick, the metal 6 in the via hole 6 is preferably filled with tungsten by using a tungsten plug process, and the material of the back metal layer 1 may include, but is not limited to, at least one of Al, Ti, Ni and Ag.

And 4, step 4: and packaging the device through a packaging process to finish the preparation of the power semiconductor device.

The method for processing the power semiconductor device according to the above embodiment may further include other necessary steps, and the implementation manner and the sequence of the corresponding steps can be known to those skilled in the art, and will not be described in detail herein.

As shown in fig. 2 and 8, the embodiment of the present application provides a power semiconductor device manufactured by the manufacturing process provided in the above embodiment, which includes a back metal layer 1, a substrate 2, an epitaxial layer 3, and a front structure 4 stacked in sequence from bottom to top, where the back metal layer 1 is connected to the epitaxial layer 3 through a metal 5 disposed in the substrate 2. As shown in the figure, a through lead hole 6 is formed in the substrate 2, and the metal 5 for connecting the back metal layer 1 and the epitaxial layer 3 is filled in the lead hole 6.

Wherein the front side structure 4 includes, but is not limited to, at least one of a source electrode, a drain electrode, a gate electrode, an oxide layer, a field plate, and a passivation layer.

The power semiconductor device according to the above embodiment may further include other necessary components or structures, and the corresponding arrangement positions and connection relationships may refer to the power semiconductor device in the prior art, and the connection relationships, operation and operation principles of the structures that are not described are known to those skilled in the art and will not be described in detail herein.

Some embodiments in this specification are described in a progressive or parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

The foregoing is merely a detailed description of the invention that enables those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The power semiconductor device is characterized by comprising a back metal layer (1), a substrate (2), an epitaxial layer (3) and a front structure (4) which are sequentially stacked from bottom to top, wherein the back metal layer (1) is connected with the epitaxial layer (3) through a metal (5) arranged in the substrate (2).

2. The power semiconductor device according to claim 1, wherein a lead hole (6) is formed through the substrate (2), and a metal (5) for connecting the back metal layer (1) and the epitaxial layer (3) is filled in the lead hole (6).

3. Power semiconductor device according to claim 1, characterized in that the front side structure (4) comprises at least one of a source electrode, a drain electrode, a gate electrode, an oxide layer, a field plate and a passivation layer.

4. The power semiconductor device according to claim 1, wherein the substrate (2) comprises one of a SiC substrate, a Si substrate, a sapphire substrate, and a GaN substrate.

5. A power semiconductor device according to claim 2, characterized in that the lead holes (6) are evenly distributed over the area of the die cell area of the power semiconductor device.

6. The power semiconductor device according to claim 2, wherein the metal (5) is made of tungsten, and the metal (5) is filled in the lead hole (6) by a tungsten plug process.

7. The power semiconductor device according to claim 1, characterized in that the back metal layer (1) is formed on the substrate (2) by means of pad deposition.

8. The power semiconductor device according to claim 1, wherein the material of the back metal layer (1) is Al, Ti, Ni or Ag.

9. A power semiconductor device according to claim 2, characterized in that the lead hole (6) is etched in the substrate (2) by means of a dry etching process or a wet etching process.