CN102891120B - Wafer encapsulation body and forming method thereof - Google Patents
Wafer encapsulation body and forming method thereof Download PDFInfo
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- CN102891120B CN102891120B CN201110209118.1A CN201110209118A CN102891120B CN 102891120 B CN102891120 B CN 102891120B CN 201110209118 A CN201110209118 A CN 201110209118A CN 102891120 B CN102891120 B CN 102891120B
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Abstract
The present invention provides a kind of wafer encapsulation body and forming method thereof, and this wafer encapsulation body includes: a substrate, has a upper surface and a lower surface; Multiple conductive pads, are positioned under this lower surface of this substrate; One dielectric layer, between described conductive pad; One groove, extends towards this lower surface from this upper surface of this substrate; One hole, extends towards this lower surface of this substrate bottom the one of this groove, and wherein a sidewall of this hole is perpendicular to this lower surface of this substrate and the described conductive pad of exposed portion bottom this sidewall or of this hole; And a conductive layer, it is positioned among this hole and conductive pad described in electrical contact at least. The present invention not only can promote structural reliability, moreover it is possible to increases and wears the conductive path that substrate conducting structure connects.
Description
Technical field
The present invention is related to wafer encapsulation body, and in particular to having the wafer encapsulation body wearing substrate conducting structure (through-substratevia, TSV).
Background technology
Recently, industry is often formed in wafer encapsulation body and wears substrate conducting structure with in response to the result of scaling of wafer and multifunction. For promoting the functional of wafer encapsulation body further, need to manage to promote and wear the conductive path that substrate conducting structure is connected, make wafer encapsulation body after lasting downsizing, remain to that there is highdensity conductive path. Additionally, industry is also needed badly promotes the structural stability wearing substrate conducting structure.
Summary of the invention
The present invention provides a kind of wafer encapsulation body, including: a substrate, there is a upper surface and a lower surface; Multiple conductive pads, are positioned under this lower surface of this substrate; One dielectric layer, between described conductive pad; One groove, extends towards this lower surface from this upper surface of this substrate; One hole, extends towards this lower surface of this substrate bottom the one of this groove, and wherein a sidewall of this hole is perpendicular to this lower surface of this substrate and the described conductive pad of exposed portion bottom this sidewall or of this hole; And a conductive layer, it is positioned among this hole and conductive pad described in electrical contact at least.
Wafer encapsulation body of the present invention, the Upper conductive pad in wherein said conductive pad has at least one opening or groove, and this opening or this groove expose the lower floor's conductive pad in described conductive pad.
Wafer encapsulation body of the present invention, at least one of wherein said conductive pad is incremented by close to the thickness of the part of this hole towards the direction away from this hole.
Wafer encapsulation body of the present invention, wherein at least one of upper surface of described conductive pad is exposed in the bottom of this hole.
Wafer encapsulation body of the present invention, wherein the sidewall of this hole exposes at least one of side of described conductive pad.
Wafer encapsulation body of the present invention, also includes a wall, is arranged under described conductive pad, and wherein this hole further extends among this wall.
Wafer encapsulation body of the present invention, also includes a photoelectric cell, is formed among this substrate.
Wafer encapsulation body of the present invention, also includes one second substrate, be arranged under this lower surface of this substrate with described conductive pad under.
Wafer encapsulation body of the present invention, also includes a photoelectric cell, is formed among this second substrate.
Wafer encapsulation body of the present invention, wherein this hole further extends among this second substrate.
Wafer encapsulation body of the present invention, also includes an insulating barrier, between this conductive layer and this second substrate.
Wafer encapsulation body of the present invention, also includes a wall, is arranged under described second substrate, and wherein this hole further extends among this wall.
Wafer encapsulation body of the present invention, also includes an insulating barrier, between this conductive layer and this second substrate, and between this conductive layer and this wall.
Wafer encapsulation body of the present invention, also includes a welding resisting layer, is positioned on this conductive layer, and at least a part of which one bubble or space are positioned among this welding resisting layer.
The present invention provides the forming method of a kind of wafer encapsulation body, including: a substrate is provided, this substrate has a upper surface and a lower surface, and wherein this substrate includes the multiple conductive pads under this lower surface of this substrate and the dielectric layer between described conductive pad; The depression that this substrate of part extends towards this lower surface is removed with formation from this upper surface of this substrate; Being formed after this depression, removing the hole that this substrate of part extends with this lower surface formed towards this substrate bottom the one of this depression, wherein a sidewall of this hole is perpendicular to this lower surface of this substrate; An insulating barrier is formed on the sidewall of this depression and the sidewall of this hole and bottom; Remove this insulating barrier of part and this dielectric layer of part described conductive pad with exposed portion; And form a conductive layer on the sidewall of this depression and the sidewall of this hole and bottom, this conductive layer described conductive pad in electrical contact.
The forming method of wafer encapsulation body of the present invention, is additionally included on this conductive layer and forms a welding resisting layer, and wherein this welding resisting layer is inserted among this hole, and has at least one bubble or space.
The present invention provides the forming method of a kind of wafer encapsulation body, including: a substrate is provided, this substrate has a first surface and a second surface, and wherein this substrate includes the multiple conductive pads on this first surface of this substrate and the dielectric layer between described conductive pad; On this first surface of this substrate, on described conductive pad and this dielectric layer, a bearing basement is set; This bearing basement of part is removed to form the depression towards this base extension from a upper surface of this bearing basement; After forming this depression, removing this bearing basement of part to form the hole towards this base extension bottom the one of this depression of this bearing basement, wherein a sidewall of this hole is perpendicular to a surface of this bearing basement; An insulating barrier is formed on the sidewall of this depression and the sidewall of this hole and bottom; Remove this insulating barrier of part and this dielectric layer of part described conductive pad with exposed portion; And form a conductive layer on the sidewall of this depression and the sidewall of this hole and bottom, this conductive layer described conductive pad in electrical contact.
The forming method of wafer encapsulation body of the present invention, wherein this hole extends among this substrate, and this conductive layer extends among this substrate.
The forming method of wafer encapsulation body of the present invention, is also included between this substrate and this conductive layer and forms one second insulating barrier.
The forming method of wafer encapsulation body of the present invention, is additionally included on this conductive layer and forms a welding resisting layer, and wherein this welding resisting layer is inserted among this hole, and has at least one bubble or space.
The present invention not only can promote structural reliability, moreover it is possible to increases and wears the conductive path that substrate conducting structure connects.
Accompanying drawing explanation
Figure 1A to Fig. 1 C shows the processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Fig. 2 A to Fig. 2 C shows the partial enlargement processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Fig. 3 A to Fig. 3 C shows the partial enlargement processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Fig. 4 A to Fig. 4 B shows the partial enlargement processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Fig. 5 shows the enlarged fragmentary cross section of wafer encapsulation body according to an embodiment of the invention.
The partial top view of Fig. 6 A to Fig. 6 E display wafer encapsulation body according to embodiments of the present invention.
Fig. 7 shows the profile of wafer encapsulation body according to an embodiment of the invention.
Fig. 8 to Figure 13 shows the processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Figure 14 A to Figure 14 B shows the processing procedure profile of wafer encapsulation body according to another embodiment of the present invention.
Figure 15 A to Figure 15 C shows the partial enlargement processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Figure 16 A to Figure 16 C shows the partial enlargement processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Figure 17 A to Figure 17 C shows the partial enlargement processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Figure 18 A to Figure 18 G shows the processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
Figure 19 A to Figure 19 F shows the processing procedure profile of wafer encapsulation body according to an embodiment of the invention.
What meet in accompanying drawing is simply described as follows:
1: wafer; 3: wafer; 5: substrate; 7: Image Sensor; 9: conductive pad structure; 9A, 9B, 9C: conductive pad; 10A: action zone; 10B: periphery circuit region; 11: dielectric layer; 13: protective layer; 15: bonding layer; 17: carrying wafer; 19: intermediate layer; 21: wall; 23: carrying wafer; 25: perforation; 27: insulating barrier; 30,30A: opening; 32: conductive layer; 34: protective layer; 36,36A, 36B, 36C: insulation windows; 100A: front; 100B: the back side; 100: substrate; 100a, 100b: surface; 102,104: insulating barrier; 106: substrate; 106a: wall; 106b: transparency carrier; 108,112: hole; 110: conductive pad structure; 110a, 110b, 110c: conductive pad; 113,113a, 113b: dielectric layer; 114: conductive layer; 300: substrate; 300a, 300b: surface; 302: element region; 304: insulating barrier; 306: conductive pad structure; 308: wall; 310: bearing basement; 312,312a, 312b: hole; 314: depression; 316: insulating barrier; 318: conductive layer; 320: welding resisting layer; 400: substrate; 400a, 400b: surface; 402: element region; 404: insulating barrier; 406: conductive pad structure; 407: bearing basement; 408: wall; 410: bearing basement; 412a, 412b: hole; 414: depression; 416,417: insulating barrier; 418: conductive layer; 420: welding resisting layer; 602,604,606: opening; 700: wafer; 702: groove; 704: contact hole; A: region; D, D1: the degree of depth; H: perforation; SC: Cutting Road; T: groove; ��: angle.
Detailed description of the invention
Will be detailed below the making of the embodiment of the present invention and occupation mode. So it should be noted that the present invention provides many inventive concepts being available for application, it can multiple specific pattern be implemented. The specific embodiment discussed of being illustrated in literary composition is only the ad hoc fashion of the manufacture and use present invention, is not used to restriction the scope of the present invention. Additionally, be likely in different embodiments use the label repeated or sign. These repeat only for simply clearly describing the present invention, do not represent and have any association between discussed different embodiments and/or structure.Furthermore, when address one first material layer be positioned on one second material layer or on time, directly contact or be separated with the situation of one or more other materials layer including the first material layer and the second material layer.
In the embodiment of the wafer encapsulation body of the present invention, it can be applicable to the various electronic component (electroniccomponents) comprising the integrated circuit such as active component or passive element (activeorpassiveelements), digital circuit or analog circuit (digitaloranalogcircuits), for instance is related to photoelectric cell (optoelectronicdevices), MEMS (MicroElectroMechanicalSystem; MEMS), the physics sensor (PhysicalSensor) that the physical quantity variation such as microfluid system (microfluidicsystems) or utilization heat, light and pressure is measured. Particularly optional use wafer-level packaging (waferscalepackage; WSP) processing procedure is to Image Sensor, light emitting diode (light-emittingdiodes; LEDs), the semiconductor wafer such as solaode (solarcells), radio-frequency (RF) component (RFcircuits), accelerometer (accelerators), gyroscope (gyroscopes), micro-brake (microactuators), surface acoustic wave element (surfaceacousticwavedevices), pressure sensor (processsensors), ink gun (inkprinterheads) or power modules (powermodules) is packaged.
Wherein above-mentioned wafer-level packaging processing procedure refers mainly to after wafer stage completes encapsulation step, cut into independent packaging body again, but, in a specific embodiment, such as separated semiconductor wafer redistribution is carried on wafer one, it is packaged processing procedure again, is also referred to as wafer-level packaging processing procedure. Additionally, above-mentioned wafer-level packaging processing procedure is also applicable to arrange the more wafers with integrated circuit by stacking (stack) mode, to form the wafer encapsulation body of multilevel integration (multi-layerintegratedcircuitdevices).
The wafer encapsulation body of the embodiment of the present invention is mainly through being designed the pattern of multilayer conductive pad respectively, the substrate conducting structure (TSV) of wearing making to be formed in packaging body can be simultaneously in electrical contact with multilayer conductive pad, can promote outside structural reliability, and the conductive path that substrate conducting structure connects is worn in increase.
Figure 1A to Fig. 1 C shows the processing procedure profile of wafer encapsulation body according to an embodiment of the invention. As shown in Figure 1A, it is provided that substrate 100, it has upper surface 100a and lower surface 100b. Substrate 100 such as includes semi-conducting material or ceramic material. In one embodiment, substrate 100 is that semiconductor wafer (being such as Silicon Wafer) is so that carrying out wafer-level packaging. Adopt wafer-level packaging to form wafer encapsulation body to reduce cost and save processing time.
In one embodiment, substrate 100 includes conductive pad structure 110, and it is positioned under the lower surface 100b of substrate 100. So in other embodiments, conductive pad structure 110 can be located among substrate 100. Conductive pad structure 110 is the stacked structure of multiple conductive pad, for instance include the multiple conductive pads being gripped with dielectric layer to each other. The follow-up partial enlargement processing procedure profile by the wafer encapsulation body according to an embodiment of the invention coordinated shown by Fig. 2 A to Fig. 2 C of detailed construction of conductive pad structure 110 explains. In the embodiment of Figure 1A, conductive pad structure 110 is positioned under the lower surface 100b of substrate 100, and and is separated with insulating barrier 102 between the lower surface 100b of substrate 100.Additionally, substrate 106 can be provided with under substrate 100 and conductive pad structure 110. Substrate 106 such as can include insulant. In one embodiment, substrate 106 is the wall being arranged on glass substrate.
Refer to Fig. 2 A, the embodiment of its display Figure 1A is in the enlarged fragmentary cross section at A place, region. Substrate 106 is formed conductive pad 110b, dielectric layer 113, conductive pad 110a and insulating barrier 102. In one embodiment, the conductive pad 110b of the specially designed part to expose under it of the pattern of conductive pad 110a. In one embodiment, conductive pad 110a has at least one opening (or groove) 602, and opening 602 exposes the conductive pad 110b of dielectric layer 113 and underface. That is, in this embodiment, Upper conductive pad (110a) has at least one opening (or groove), and it exposes underlying conductive pad (110b). It should be noted that essence can be seen that conductive pad 110b on " exposing " non-finger vision herein, and refer to that the underface of opening 602 is overlapping with the conductive pad 110b of part.
Then, forming hole in substrate 100, hole extends towards lower surface 100b from the upper surface 100a of substrate 100, and the conductive pad 110b of the conductive pad 110a of hole exposed portion and part. In one embodiment, hole is formed in single etch process. In another embodiment, hole is that segmentation is formed. Hereinafter, will illustrate that segmentation forms the forming process of the hole of the conductive pad 110a of exposed portion and the conductive pad 110b of part.
Such as, refer to Figure 1A, in this embodiment, form the first hole 108 from the upper surface 100a of substrate 100, the first hole 108 extends (that is, extending) towards conductive pad 110a towards conductive pad structure 110. For the embodiment of Figure 1A, the first hole 108 runs through substrate 100, and stops on the insulating barrier 102 between substrate 100 and conductive pad structure 110. Then, the alternative sidewall in the first hole 108 and the formation insulating barrier 104 conductive layer to electrically isolate substrate 100 be subsequently formed in hole on bottom.
Then, as shown in Figure 1B, the second hole 112 is formed from the bottom of the first hole 108. That is, the insulating barrier 104 and 102 of part is removed so that the conductive pad structure 110 of lower section is exposed. Additionally, the second hole 112 also makes conductive pad 110a and 110b expose further. Refer to Fig. 2 B, the embodiment of display Figure 1B is in the enlarged fragmentary cross section at A place, region.
As shown in Figure 2 A and 2 B, the formation of the second hole 112 includes a part for the insulating barrier 102 and dielectric layer 113 under it removing in the opening 602 of conductive pad 110a. In one embodiment, the conductive pad 110a of the sidewall exposed portion of the second hole 112 formed, for instance expose the side of conductive pad 110a, as shown in Figure 2 B. In one embodiment, the conductive pad 110b of the exposed portion, bottom of the second hole 112 formed, for instance expose the upper surface of conductive pad 110b, as shown in Figure 2 B. Owing to the formation of the second hole 112 only relates to removing of isolation material, therefore it can be formed in single etch process. Additionally, selected etchant preferably to the etching speed of dielectric material or insulant more than the etching speed to metal material or conductive material.
As previously described, the conductive pad 110b of the specially designed part to expose under it of the pattern of conductive pad 110a. Therefore, in the process forming the second hole 112, on the whole removal of material is the dielectric material of the insulant in the opening 602 of conductive pad 110a and lower section, thus can form out the second hole 112 in single etch process.
Fig. 6 A shows the partial top view of wafer encapsulation body according to an embodiment of the invention, and it only shows the relativeness of conductive pad 110a and 110b. It should be noted that the use by way of example only of the top view shown in Fig. 6 A, it is not used to limit the embodiment of the embodiment of the present invention. As shown in Figure 6A, having at least one opening 602 in conductive pad 110a, it exposes the conductive pad 110b of lower section. That is, the second hole 112 exposes conductive pad 110a and the 110b that the degree of depth is different.
Then, refer to Fig. 1 C, in the hole that the first hole 108 and the second hole 112 collectively constitute, form conductive layer 114. Referring to Fig. 2 C, the embodiment of its display Fig. 1 C is in the enlarged fragmentary cross section at A place, region. As shown in Figure 2 C, conductive layer 114 extends in the second hole 112 in electrical contact with conductive pad 110a and conductive pad 110b. In one embodiment, conductive layer 114 is securable to have preferably structural stability in the second hole 112, and conductive layer 114 also contacts with conductive pad 110a and conductive pad 110b simultaneously, is connectable to more conductive path. In one embodiment, conductive pad 110a and conductive pad 110b is connected to same electronic component. Owing to conductive layer 114 is simultaneously in electrical contact with conductive pad 110a and conductive pad 110b, it can be ensured that open circuit does not occur the conductive path being connected to this electronic component. In another embodiment, conductive pad 110a and conductive pad 110b is respectively connecting to different electronic components. Different electronic components can be transmitted via conductive pad 110a and conductive pad 110b by conductive layer 114 or be received electronic signal respectively.
The conductive pad structure 110 of the embodiment of the present invention, except can including two conductive pads (110a, 110b), may also include other conductive pads. Fig. 3 A to Fig. 3 C shows the partial enlargement processing procedure profile of wafer encapsulation body according to another embodiment of the present invention, and wherein same or analogous element will adopt same or analogous label to indicate. Additionally, due to embodiment illustrated in fig. 3 is compared with the embodiment of Fig. 2, mainly the design of conductive pad structure 110 is different, and its generation type can refer to the narration corresponding to Figure 1A to Fig. 1 C, below will not be described in great detail.
As shown in Figure 3A, in one embodiment, wafer encapsulation body, except including conductive pad 110a and conductive pad 110b, also includes at least one conductive pad 110c, among its dielectric layer between conductive pad 110a and 110b. As shown in Figure 3A, substrate 106 is formed with conductive pad 110b, dielectric layer 113a, conductive pad 110c, dielectric layer 113b, conductive pad 110a and insulating barrier 102. In one embodiment, the conductive pad 110c of the specially designed part to expose under it of the pattern of conductive pad 110a and conductive pad 110b partly. In one embodiment, conductive pad 110a has at least one opening (or groove) 602, and opening 602 exposes the conductive pad 110b of dielectric layer 113b, the conductive pad 110c of lower section, dielectric layer 113a and lower section. Additionally, the pattern of conductive pad 110c is also designed and having at least one opening (or groove) 604, opening 604 exposes the conductive pad 110b of dielectric layer 113a and lower section.
In other words, the wafer encapsulation body of one embodiment of the invention includes multiple conductive pad (being such as conductive pad 110a, 110c, 110b), and the Upper conductive pad in these conductive pads has at least one opening or groove, expose the lower floor's conductive pad in these conductive pads. Such as, for conductive pad 110a (Upper conductive pad), it has opening 602, and it exposes conductive pad 110c and 110b (underlying conductive pad).Similarly, for conductive pad 110c (Upper conductive pad), it has opening 604, and it exposes conductive pad 110b (underlying conductive pad).
Then, forming hole in substrate 100, hole extends towards lower surface 100b from the upper surface 100a of substrate 100, and the conductive pad 110b of the conductive pad 110c of the conductive pad 110a of hole exposed portion, part and part. In one embodiment, hole is formed in single etch process. In another embodiment, hole is that segmentation is formed.
Similarly, in this embodiment, also can be initially formed the first hole 108 (as shown in Figure 1A), then form the second hole 112 in the bottom of the first hole 108, as shown in Figure 1B. Fig. 3 B shows the enlarged fragmentary cross section near the second hole 112.
Similarly, in the process forming the second hole 112, on the whole removal of material is the dielectric material of the insulant in the opening 602 of conductive pad 110a and lower section, thus can form out the second hole 112 in single etch process.
Fig. 6 B shows the partial top view of wafer encapsulation body according to an embodiment of the invention, and it only shows the relativeness of conductive pad 110a, 110b and 110c. It should be noted that the use by way of example only of the top view shown in Fig. 6 B, it is not used to limit the embodiment of the embodiment of the present invention. As shown in Figure 6B, having at least one opening 602 in conductive pad 110a, it exposes conductive pad 110c and 110b of lower section. Additionally, have at least one opening 604 in conductive pad 110c, it exposes the conductive pad 110b of lower section. That is, the second hole 112 exposes conductive pad 110a, 110c and 110b that the degree of depth is different.
Similarly, as shown in Figure 3 C, being subsequently formed conductive layer 114, it extends in the second hole 112 in electrical contact with conductive pad 110a, 110c and 110b. In one embodiment, conductive layer 114 is securable to have preferably structural stability in the second hole 112, and conductive layer 114 also contacts with conductive pad 110a, 110c and 110b simultaneously, is connectable to more conductive path.
As mentioned above, by the design to conductive pad, the hole simultaneously exposing multiple conductive pad can be formed out in single etch process, the number of the conductive path that the conductive layer (wearing base conductive structure) being subsequently formed in hole connects can be made to increase. Furthermore, the surface profile of the hole owing to being formed is comparatively coarse (the multiple conductive pads different because having the degree of depth), can promote the cohesiveness between conductive layer and hole sidewalls, thus promote the structural stability wearing base conductive structure.
It should be noted that the design of conductive pad can have various forms, it is not limited to the form described in Fig. 6 A to Fig. 6 B. Fig. 6 C to Fig. 6 E display partial top view according to the wafer encapsulation body of the multiple embodiment of the present invention. Similarly, Fig. 6 C to Fig. 6 E also use by way of example only, it is not used to limit the embodiment of the embodiment of the present invention.
As shown in Figure 6 C, in one embodiment, conductive pad 110a has a rectangular aperture 602, and it exposes conductive pad 110c and 110b of lower section. Conductive pad 110c has multiple rectangular aperture 604, and it exposes the conductive pad 110b of lower section.
As shown in Figure 6 D, in another embodiment, conductive pad 110a has a rectangular aperture 602, and it exposes conductive pad 110c and 110b of lower section. Conductive pad 110c has multiple oblong openings 604 (or claiming groove), and it exposes the conductive pad 110b of lower section.
As illustrated in fig. 6e, in another embodiment, conductive pad 110a has a rectangular aperture 602, and it exposes conductive pad 110c and 110b of lower section.Conductive pad 110c has multiple opening 604, includes rectangular aperture and oblong openings (or claiming groove), and it exposes the conductive pad 110b of lower section. As above-mentioned, all visual demand of the shape of the opening of conductive pad, number and distribution and adjust.
Fig. 4 A to Fig. 4 B shows the partial enlargement processing procedure profile of wafer encapsulation body according to an embodiment of the invention, and same or analogous element will indicate with same or analogous label. Wherein, the structure shown in Fig. 4 A is similar to the embodiment of Fig. 3 A, and Main Differences refer to Fig. 4 B.
As above-mentioned, the formation of the second hole 112 includes using single etch process. In a case where, the process of etching formation the second hole 112 may partly remove the conductive pad of both sides. As shown in Figure 4 B, conductive pad 110a and the 110c of part is also etched in the process forming the second hole 112 and removes. In this case, conductive pad 110a is incremented by close to the thickness of the part of hole 112 towards the direction away from hole 112. Similarly, in one embodiment, conductive pad 110c is incremented by close to the thickness of the part of hole 112 towards the direction away from hole 112. Even so, follow-up in the second hole 112 formed conductive layer 114 time, conductive layer 114 still can conductive pad 110a, 110c and 110b in electrical contact. And, based on part conductive pad 110a and 110c be removed, the contact area between conductive layer 114 and conductive pad 110a and 110c also can thus increase, as shown in Figure 4 B.
Fig. 5 shows the enlarged fragmentary cross section of wafer encapsulation body according to an embodiment of the invention. Similarly, in this embodiment, in the process forming the second hole 112, conductive pad 110a and 110b of part is removed. In this case, conductive pad 110a is incremented by close to the thickness of the part of hole 112 towards the direction away from hole 112. Similarly, conductive pad 110b is incremented by close to the thickness of the part of hole 112 towards the direction away from hole 112. Additionally, in this embodiment, conductive pad 110b is specially designed and has opening 605, and it exposes the substrate 106 of lower section. In one embodiment, the second hole 112 can further extend in substrate 106. Such as, in one embodiment, the second hole 112 may extend in the wall of substrate 106.
Fig. 7 shows the profile of wafer encapsulation body according to an embodiment of the invention, and same or analogous element indicates with same or analogous label. In this embodiment, wafer encapsulation body also includes groove 702, and it extends towards lower surface 100b from the upper surface 100a of substrate 100. The bottom of groove 702 is formed with multiple contact hole 704. Contact hole 704 exposes the conductive pad structure 110 under substrate 100. Conductive layer 114 may be along the upper surface 100a of substrate 100, the sidewall of groove 702, the sidewall of contact hole 704 and extend to conductive pad structure 110. Wherein, conductive pad structure 110 can be similar to previously described embodiment and includes multiple conductive pad with special pattern design. Conductive layer 114 can be in electrical contact with the multiple conductive pads exposed along the sidewall of the hole formed. Additionally, in this embodiment, substrate 106 can include transparency carrier 106b and the wall 106a being arranged on. Wall 106a, substrate 100 and transparency carrier 106b can around cavitys. Can arranging wafer 700 in cavity, it can be such as the photosensitive wafer of (but not limited to) or luminescent wafer.
The wafer encapsulation body of the embodiment of the present invention is mainly through being designed the pattern of multilayer conductive pad respectively, the base conductive structure (TSV) of wearing making to be formed in packaging body can be simultaneously in electrical contact with multilayer conductive pad, can promote outside structural reliability, and the conductive path that base conductive structure connects is worn in increase.
Fig. 8 to Figure 13 shows the processing procedure profile of wafer encapsulation body according to an embodiment of the invention. As shown in Figure 8, one wafer 1 is provided, including multiple wafers 3, it it is such as CMOS CIS wafer, wafer includes a substrate 5, be divided into active area 10A and peripheral circuit region 10B according to region, wafer 3 has front 100A and back side 100B, active area 10A and peripheral circuit region 10B and is respectively arranged with Image Sensor 7 and conductive pad structure 9 in the position of front 100A. Substrate 5 such as includes semi-conducting material or ceramic material. In one embodiment, substrate 5 is convenient for wafer-level packaging for semiconductor wafer (being such as Silicon Wafer). Adopt wafer-level packaging to form wafer encapsulation body to reduce cost and save processing time.
In one embodiment, conductive pad structure 9 can be made up of layer of metal, or the stacked structure being made up of multiple conductive pads, for instance includes the multiple conductive pads being gripped with dielectric layer 11 to each other. The detailed construction of conductive pad structure 9 is follow-up will coordinate embodiment explanation. It is said that in general, being positioned at front wafer surface is be covered with a layer wafer protective layer 13, for instance be oxide layer, nitration case or its composite bed, wafer protective layers 13 then may choose whether to form opening on the position of conductive pad structure, and it is determined according to follow-up packing forms.
Referring to Fig. 9, be then engaged in by the front 100A of above-mentioned wafer wafer 1 and form a composition surface on carrying wafer 17, wherein in one embodiment, can be come joint wafer wafer 1 and carrying wafer 17 by bonding layer 15, it is depending on various wafer bond techniques. Therefore, in one embodiment, the conductive pad structure 9 composition surface between the front 100A and carrying wafer 17 of wafer wafer 1 includes an intermediate layer 19, for instance wafer protective layers 13 and/or bonding layer 15. Now the back side 100B of wafer wafer 1 can be bestowed thinning processing procedure, so that light is enough to enter image sensing district from its back side.
Refer to Figure 10, sequentially processing procedure is that another carrying wafer 23 of laminating is in the back side 100B of the substrate 5 of wafer wafer, the wafer being such as made up of materials such as light transmissive material such as glass, a wall 21 can be formed between substrate 5 and carrying wafer 23, in one embodiment, on the active area of substrate 5, between carrying wafer 23 and wall 21, cavity can be formed. Now optional another thinning processing procedure of enforcement, to reduce the thickness of carrying wafer 17.
Refer to Figure 11, the position being connected in the corresponding conductive pad structure of carrying wafer 17 forms a via 25, in this example, it selects etching to form a chamfering, angle, �� is about between more than 90 degree to 92 degree, then compliance forms an insulating barrier 27, for instance be oxide layer or photonasty insulating barrier, photoresistance etc., to extend into via 25 medial wall and bottom from carrying wafer 17.
Refer to Figure 12, the fabrication steps of an exposed conductive pads structure 9 is implemented in its display, to form opening 30 in the bottom of via 25, in the present embodiment, this opening can run through such as intermediate layer 19, the composition surface between two wafers, and be parked in the upper surface of conductive pad structure and/or be communicated to wafer dielectric layer 11 by the conductive pad structure of part, or resting on wall 21 partially or completely through substrate 5 further, relevant above-mentioned processing procedure and structure thereof are by the details will be described later.
Refer to Figure 13, form a conductive layer 32 as being made up of metal material in carrying wafer 17 surface compliance, and extend in sidewalls, bottom and opening 30, constituted a conductive path to contact conductive pad structure.Afterwards, insert packaging protection layer 34, as by solder resist material constitute, then make the outer connecting element such as weld pad being electrically connected conductive layer 32, carry out wafer cutting step to complete the making (not shown) of wafer encapsulation body.
In another embodiment, as shown in Figure 14 A, Figure 14 B, the profile of its another kind of through-hole structure of display and top view. in this example, carrying wafer 17 surface can utilize in advance removes the base material of a part such as modes such as etching steps and forms a groove T with set degree of depth D, in the occasion that carrying wafer 17 is a blank wafer, due to reactive circuit element wherein, therefore the opening of groove T, position or degree of depth elasticity are bigger, groove T can be formed at the position containing Cutting Road SC, simultaneously the scope of groove T can once corresponding multiple conductive pad structure 9, it it is such as whole edge area, then channel bottom is utilized and remove the base material of a part again such as modes such as etching steps and form multiple via H with set degree of depth D1, wherein owing to groove T can be greatly reduced the depth-to-width ratio of via H, therefore the processing procedure difficulty forming above-mentioned opening 30 in the bottom of via H can reduce.
The stacked structure (multilayer conductive pad) of the processing procedure of following description opening 30 and multilayer conductive mat structure 9.
Refer to Figure 15 A, the embodiment of its display Figure 12 or Figure 14 A is in the enlarged fragmentary cross section at the region place of opening 30 and conductive pad 9. Wafer substrates 5 is formed multilayer conductive pad 9A, 9B, interlayer dielectric layer 11 and such as intermediate layer 19, composition surface. In one embodiment, the pattern of Upper conductive pad 9A is specially designed to expose the partially electronically conductive pad 9B of lower floor. In one embodiment, Upper conductive pad 9A has at least one insulation windows 36, the conductive pad 9B immediately below insulation windows 36 is corresponding. Namely, Upper conductive pad 9A synchronizes to be defined out an opening, breach or groove in processing procedure, and is filled by interlayer dielectric layer 11, in this embodiment, insulation windows 36 is overlapping with the underlying conductive pad 9B of part, and insulation windows 36 carries wafer 17 and is previously formed in being formed before via or engage.
Then, with reference to described in Figure 14 A, after forming via H and insulating barrier 27 in the substrate 17 of carrying wafer, bottom via H, remove partial insulative layer 27 and form opening 30, wherein this step can simultaneously or perform following processing procedure in succession, as shown in fig. 15b, including removing intermediate layer 19 to form the surface of insulation windows 36 and part interlayer dielectric layer 11 sidewall and underlying conductive pad 9B to expose Upper conductive pad 9A, such as available lithographic process and the insulating barrier etching selectivity to metal, select suitable etching mode to complete above-mentioned processing procedure.
Afterwards as shown in figure 15 c, conductive layer 32 is formed to be electrically connected one or more layers of conductive pad structure, for instance conductive layer 32 can contact the side of Upper conductive pad and/or the upper surface of underlying conductive pad simultaneously.
Refer to Figure 16 A to Figure 16 C, the processing procedure profile of the conductive pad stacked structure of its display three layers, it Upper conductive pad 9A including there is insulation windows 36A, there is the middle level conductive pad 9B and underlying conductive pad 9C of insulation windows 36B. Wherein insulation windows 36A is more than insulation windows 36B, and both also correspond to the upper surface of underlying conductive pad 9C. In the present embodiment, as shown in figure 16 c, the conductive layer 32 formed can be electrically connected one or more layers of conductive pad structure, for instance conductive layer 32 can contact the upper surface of the side of Upper conductive pad 9A, the upper surface of middle level conductive pad structure 9B and side and/or underlying conductive pad 9C simultaneously.
Then, with reference to described in Figure 17 A to Figure 17 C, the processing procedure profile of the conductive pad stacked structure of its display three layers, its difference with previous embodiment is in that underlying conductive pad 9C also includes an insulation windows 36C, the insulation windows 36B of its insulation windows 36A and middle level conductive pad 9B with Upper conductive pad 9A has corresponding relation, and the insulation windows 36C of another underlying conductive pad 9C is less than insulation windows 36A and 36B.
The step forming opening 30 includes removing intermediate layer 19, insulation windows 36A, 36B, 36C and part interlayer dielectric layer 11 to expose sidewall and the portion of upper surface of multilayer conductive pad, such as available lithographic process and the insulating barrier etching selectivity to metal, suitable etching mode is selected to complete above-mentioned processing procedure, so can increase the contact area of subsequent conductive layer 32 and conductive pad stacked structure, and be conducive to the compliance of conductive layer 32 to be formed.
Wherein according to the characteristic of processing procedure, also optional with wall 21 for barrier layer, remove part silicon base 5 further and form opening 30A, this opening 30A can be in silicon base 5 or expose wall 21. Afterwards as shown in Figure 17 C, form conductive layer 32 to be electrically connected one or more layers of conductive pad structure, or side and/or the upper surface of conductive pad can be contacted simultaneously. Conductive layer 32 can extend into silicon base 5 from opening 30A simultaneously, and in one embodiment, in being formed before conductive layer 32, can separately form an insulating barrier 38 in opening 30A, or such as implement an oxidation step and silicon base 5 in opening 30A forms oxide layer.
Figure 18 A to Figure 18 G shows the processing procedure profile of wafer encapsulation body according to an embodiment of the invention. As shown in Figure 18 A, it is provided that substrate 300, it has surface 300a and 300b. Substrate 300 can be such as semiconductor crystal wafer, such as Silicon Wafer. In one embodiment, in substrate 300, definable has multiple predetermined cuts road SC, and substrate 300 is divided into multiple region by it. In each region, it is formed with at least one element region 302. In one embodiment, element region 302 can include photoelectric cell, for instance is Image Sensor or light-emitting component. Being formed with multiple conductive pad structure 306 on the surface 300a of substrate 300, it is positioned among the insulating barrier 304 (or claiming dielectric layer) on surface 300. Each conductive pad structure 306 can include multiple stacking conductive pad. These stacking conductive pads can be electrically connected to each other (such as, by being formed at the vertical conductive structure between stacked conductive pad). Or, these stacking conductive pads can not be electrically connected each other. In one embodiment, at least one electrical connection element district 302 in these conductive pads. It should be noted that the thickness of insulating barrier 304 and conductive pad structure 306 is actually relatively thin, for clear view thin portion structure, insulating barrier 304 in graphic and the thickness of conductive pad structure 306 amplified and not according to actual ratio.
Then, bearing basement 310 is set in substrate 300. Multiple wall 308 can be provided with between bearing basement 310 and substrate 300. Wall 308 and bearing basement 310 can cross multiple cavity in substrate 300, can include at least one element region 302 under each cavity. Wall 308 can be covered on conductive pad structure 306. Photoelectric cell is included (such as at element region 302, Image Sensor or light-emitting component) embodiment in, can be selected for transparency carrier (such as, glass substrate, quartz base plate or transparent polymer substrate) or to send from element region 302 in order to light entrance element region 302 as bearing basement 310.
As shown in figure 18b, can then selectivity thinning substrate 300 in order to the carrying out of successive process. For example, it is possible to bearing basement 310 is for supporting, from the surface 300b thinning substrate 300 of substrate 300. The thinning processing procedure being suitable for is such as mechanical lapping or cmp.
Then, as shown in figure 18 c, the substrate 300 of part is removed to be formed from the surface 300b of substrate 300 towards the surface 300a depression 314 extended. Such as, photoetching and etch process can be adopted to form depression 314. Depression 314 can be located on multiple conductive pad structures 306 of SC both sides, predetermined cuts road.
As shown in Figure 18 D, then substrate 300 can be removed to form at least one surface 300a towards substrate 300 hole 312a extended from the base section of depression 314. Hole 312a on the whole to it in corresponding conductive pad structure 306. In one embodiment, on the whole the sidewall of hole 312a is perpendicular to the surface 300a of substrate 300. Or, on the whole the sidewall of hole 312a can be perpendicular to the bottom of depression 314. In one embodiment, the generation type of hole 312a is such as photoetching and etch process. Depression 314 can be overlapping with multiple hole 312a. Such as, depression 314 can be overlapping with the hole 312a in the zones of different of Cutting Road SC both sides. Adjacent hole 312a in the same areas that also can divide with Cutting Road SC of depression 314 is overlapping. Such as, depression 314 can be similar to the situation shown in Figure 14 B with the relation of hole 312a.
Then, insulating barrier 316 can be formed on the surface 300b of substrate 300. The material of insulating barrier 316 such as includes oxide, nitride, nitrogen oxides, macromolecular material or aforesaid combination. Insulating barrier 316 can vapour deposition process, thermal oxidation method or rubbing method be formed. In one embodiment, insulating barrier 316 on the whole compliance is positioned on the surface 300b of substrate 300, the sidewall of 314 that caves in, the sidewall of hole 312a and bottom.
Then, as shown in fig. 18e, remove the insulating barrier 316 of part on bottom hole 312a, and be subsequently formed hole 312b. In one embodiment, can such as with photoetching and etch process remove part insulating barrier 304, part conductive pad structure 306 and part wall 308 to form hole 312b. In another embodiment, each conductive pad in conductive pad structure 306 patterns in advance and has the opening that exposes underlying conductive pad. In this case, in the process forming hole 312b, it is only necessary to etching isolation layer 304 is without etching conductive pad. In another embodiment, the conductive pad of hole 312b only exposed portion and do not extend among wall 308.
As shown in fig. 18f, on the surface 300b of substrate 300, patterned conductive layer 318 is then formed. The material of conductive layer 318 such as includes copper, aluminum, nickel, gold, platinum or aforesaid combination. The generation type of conductive layer 318 such as includes physical vapour deposition (PVD), chemical vapour deposition (CVD), rubbing method, plating, electroless plating or aforesaid combination.
Conductive layer 318 can extend towards conductive pad structure 306 along the sidewall of depression 314, the sidewall of hole 312a and the sidewall of hole 312b from the surface 300b of substrate 300, and in electrical contact with conductive pad structure 306.
It should be noted, although in the embodiment of Figure 18 F, the conductive pad of conductive layer 318 three layers in electrical contact, and extend into direct contact interval layer 308 among wall 308 through insulating barrier 304, but the embodiment of the present invention is not limited to this. The hole 312b of the embodiment of the present invention is not limited to extend among wall 308.The conductive layer 318 of the embodiment of the present invention and conductive pad structure 306 also can have and be similar to the structure shown in Fig. 2 C, Fig. 3 C or Fig. 4 B. Additionally, conductive pad structure 306 also can have other changes many. Such as, conductive pad structure 306 can have and is similar to the structure shown in Fig. 6 A to Fig. 6 E.
Continue referring to Figure 18 F, then can form welding resisting layer 320 on the surface 300b of substrate 300. In one embodiment, welding resisting layer 320 can have the opening (not shown) exposing conductive layer 318, and can form conductive structure (not shown) on the conductive layer 318 exposed, for instance soldered ball. In one embodiment, owing to hole (312a and 312b) has on the whole vertical sidewall, therefore the material in order to form welding resisting layer 320 is likely to leave bubble 321 or space in the process insert hole.
Then, multiple wafer encapsulation body separated from one another is formed along the structure shown in predetermined cuts road SC cutting drawing 18F, as shown in Figure 18 G.
Figure 19 A to Figure 19 F shows the processing procedure profile of wafer encapsulation body according to an embodiment of the invention. As shown in Figure 19 A, it is provided that substrate 400, it has surface 400a and 400b. Substrate 400 can be such as semiconductor crystal wafer, such as Silicon Wafer. In one embodiment, in substrate 400, definable has multiple predetermined cuts road SC, and substrate 400 is divided into multiple region by it. In each region, it is formed with at least one element region 402. In one embodiment, element region 402 can include photoelectric cell, for instance is Image Sensor or light-emitting component. Being formed with multiple conductive pad structure 406 on the surface 400a of substrate 400, it is positioned among the insulating barrier 404 (or claiming dielectric layer) on surface 400. Each conductive pad structure 406 can include multiple stacking conductive pad. These stacking conductive pads can be electrically connected to each other (such as, by being formed at the vertical conductive structure between stacked conductive pad). Or, these stacking conductive pads can not be electrically connected each other. In one embodiment, at least one electrical connection element district 402 in these conductive pads. It should be noted that the thickness of insulating barrier 404 and conductive pad structure 406 is actually relatively thin, for clear view thin portion structure, insulating barrier 404 in graphic and the thickness of conductive pad structure 406 amplified and not according to actual ratio.
Then, bearing basement 407 is set on the surface 400a of substrate 400. On the insulating barrier 404 that bearing basement 407 is such as the bond by adhesion coating (not shown) or other patterns and is fixed in substrate 400. In one embodiment, the more or less the same substrate 400 under it of the size and shape of bearing basement 407. In one embodiment, bearing basement 407 is semiconductor wafer, such as Silicon Wafer.
As shown in Figure 19 B, with bearing basement 407 for supporting, from the surface 400b thinning substrate 400 of substrate 400. The thinning processing procedure being suitable for is such as mechanical lapping or cmp.
Then, another bearing basement 410 is set in substrate 400. Multiple wall 408 can be provided with between bearing basement 410 and substrate 400. Wall 408 and bearing basement 410 can cross multiple cavity in substrate 400, can include at least one element region 402 under each cavity. Wall 408 can be covered on conductive pad structure 406. Photoelectric cell is included (such as at element region 402, Image Sensor or light-emitting component) embodiment in, can be selected for transparency carrier (such as, glass substrate, quartz base plate or transparent polymer substrate) or to send from element region 402 in order to light entrance element region 402 as bearing basement 410.In addition, owing to substrate 400 is thinned, therefore only needing the substrate 400 after transparency carrier (bearing basement 410) and thinning without through insulating barrier 404 and conductive pad structure 406 when light is into or out, the into or out of light can be more smooth.
Then, as shown in fig. 19 c, in one embodiment, change with bearing basement 410 for supporting, the bearing basement 407 (such as, photoetching and etch process can be adopted) of part is removed to be formed from the upper surface of bearing basement 407 towards leading the depression 414 that substrate 400 extends from the upper surface of bearing basement 407. Then, the bearing basement 407 of part is removed from the bottom of the depression 414 of bearing basement 407 to form the hole 412a extended towards substrate 400. In one embodiment, on the whole the sidewall of hole 412a is perpendicular to the basal surface of bearing basement 407. Or, on the whole the sidewall of hole 412a can be perpendicular to the bottom of depression 414.
In one embodiment, the generation type of hole 412a is such as photoetching and etch process. Depression 414 can be overlapping with multiple holes. Such as, depression 414 can be overlapping with the hole in the zones of different of Cutting Road SC both sides. Adjacent hole in the same areas that also can divide with Cutting Road SC of depression 414 is overlapping. Such as, depression 414 can be similar to the situation shown in Figure 14 B with the relation of hole.
Then, insulating barrier 416 can be formed on the upper surface of bearing basement 407. The material of insulating barrier 416 such as includes oxide, nitride, nitrogen oxides, macromolecular material or aforesaid combination. Insulating barrier 416 can vapour deposition process, thermal oxidation method or rubbing method be formed. In one embodiment, insulating barrier 416 on the whole compliance is positioned on the upper surface of bearing basement 407, the sidewall of 414 that caves in, the sidewall of hole 412a and bottom.
Then, as shown in Figure 19 D, remove the insulating barrier 416 of part on bottom hole 312a, and be subsequently formed hole 412b. In one embodiment, can such as with photoetching and etch process remove part insulating barrier 404, part conductive pad structure 406 and part wall 408 to form hole 412b. In another embodiment, each conductive pad in conductive pad structure 406 patterns in advance and has the opening that exposes underlying conductive pad. In this case, in the process forming hole 412b, it is only necessary to etching isolation layer 404 is without etching conductive pad. In another embodiment, the conductive pad of hole 412b only exposed portion and do not extend among substrate 400 or wall 408.
As shown in Figure 19 D, in one embodiment, alternative formation patterned insulation layer 417 on the bottom and partial sidewall of hole 412b. Insulating barrier 417 covers the former substrate 400 exposed in hole 412b. Insulating barrier 417 does not cover conductive pad structure 406.
Then, as shown in fig.19e, on the upper surface of bearing basement 407, patterned conductive layer 418 is formed. The material of conductive layer 418 such as includes copper, aluminum, nickel, gold, platinum or aforesaid combination. The generation type of conductive layer 418 such as includes physical vapour deposition (PVD), chemical vapour deposition (CVD), rubbing method, plating, electroless plating or aforesaid combination.
Conductive layer 418 can extend towards conductive pad structure 416 along the sidewall of depression 414, the sidewall of hole 412a and the sidewall of hole 412b from the upper surface of bearing basement 407, and in electrical contact with conductive pad structure 416.
It should be noted, although in the embodiment of Figure 19 E, the conductive pad of conductive layer 418 three layers in electrical contact, and extend into direct contact interval layer 408 among wall 408 through insulating barrier 404, but the embodiment of the present invention is not limited to this.The hole 412b of the embodiment of the present invention is not limited to extend among wall 408. The conductive layer 418 of the embodiment of the present invention and conductive pad structure 406 also can have and be similar to the structure shown in Fig. 2 C, Fig. 3 C or Fig. 4 B. Additionally, conductive pad structure 406 also can have other changes many. Such as, conductive pad structure 406 can have and is similar to the structure shown in Fig. 6 A to Fig. 6 E.
Continue referring to Figure 19 E, then can form welding resisting layer 420 on the upper surface of bearing basement 407. In one embodiment, welding resisting layer 420 can have the opening (not shown) exposing conductive layer 418, and can form conductive structure (not shown) on the conductive layer 418 exposed, for instance soldered ball. In one embodiment, owing to hole (412a and 412b) has on the whole vertical sidewall, therefore in order to form the material of welding resisting layer 420 in the process inserting hole, it is possible to leave bubble 321 or space.
Then, multiple wafer encapsulation body separated from one another is formed along the structure shown in predetermined cuts road SC cutting drawing 19E, as shown in fig. 19f.
The foregoing is only present pre-ferred embodiments; so it is not limited to the scope of the present invention; anyone familiar with this technology; without departing from the spirit and scope of the present invention; can doing on this basis and further improve and change, therefore protection scope of the present invention ought be as the criterion with the scope that following claims defines.
Claims (16)
1. a wafer encapsulation body, it is characterised in that including:
One substrate, has a upper surface and a lower surface;
Stacking multiple conductive pads, are positioned under this lower surface of this substrate, and the centre of the Upper conductive pad in wherein said conductive pad has at least one opening or groove, and this opening or this groove expose the lower floor's conductive pad in described conductive pad;
One dielectric layer, between described conductive pad;
One groove, extends towards this lower surface from this upper surface of this substrate;
One hole, extends towards this lower surface of this substrate bottom the one of this groove, and wherein a sidewall of this hole is perpendicular to this lower surface of this substrate and the described conductive pad of exposed portion bottom this sidewall or of this hole;
One conductive layer, is positioned among this hole and described conductive pad in electrical contact; And
One welding resisting layer, is positioned on this conductive layer, and at least a part of which one bubble or space are positioned among this welding resisting layer.
2. wafer encapsulation body according to claim 1, it is characterised in that at least one of described conductive pad is incremented by close to the thickness of the part of this hole towards the direction away from this hole.
3. wafer encapsulation body according to claim 1, it is characterised in that at least one of upper surface of described conductive pad is exposed in the bottom of this hole.
4. wafer encapsulation body according to claim 1, it is characterised in that the sidewall of this hole exposes at least one of side of described conductive pad.
5. wafer encapsulation body according to claim 1, it is characterised in that also include a wall, is arranged under described conductive pad, and wherein this hole further extends among this wall.
6. wafer encapsulation body according to claim 1, it is characterised in that also include a photoelectric cell, is formed among this substrate.
7. wafer encapsulation body according to claim 1, it is characterised in that also include one second substrate, be arranged under this lower surface of this substrate with described conductive pad under.
8. wafer encapsulation body according to claim 7, it is characterised in that also include a photoelectric cell, is formed among this second substrate.
9. wafer encapsulation body according to claim 7, it is characterised in that this hole further extends among this second substrate.
10. wafer encapsulation body according to claim 9, it is characterised in that also include an insulating barrier, between this conductive layer and this second substrate.
11. wafer encapsulation body according to claim 7, it is characterised in that also include a wall, being arranged under described second substrate, wherein this hole further extends among this wall.
12. wafer encapsulation body according to claim 11, it is characterised in that also include an insulating barrier, between this conductive layer and this second substrate, and between this conductive layer and this wall.
13. the forming method of a wafer encapsulation body, it is characterised in that including:
One substrate is provided, this substrate has a upper surface and a lower surface, wherein this substrate includes the stacking multiple conductive pads under this lower surface of this substrate and the dielectric layer between described conductive pad, the centre of the Upper conductive pad in wherein said conductive pad has at least one opening or groove, and this opening or this groove expose the lower floor's conductive pad in described conductive pad;
The depression that this substrate of part extends towards this lower surface is removed with formation from this upper surface of this substrate;
Being formed after this depression, removing the hole that this substrate of part extends with this lower surface formed towards this substrate bottom the one of this depression, wherein a sidewall of this hole is perpendicular to this lower surface of this substrate;
An insulating barrier is formed on the sidewall of this depression and the sidewall of this hole and bottom;
Remove this insulating barrier of part and this dielectric layer of part described conductive pad with exposed portion;
A conductive layer is formed, this conductive layer described conductive pad in electrical contact on the sidewall of this depression and the sidewall of this hole and bottom; And
Forming a welding resisting layer on this conductive layer, wherein this welding resisting layer is inserted among this hole, and has at least one bubble or space.
14. the forming method of a wafer encapsulation body, it is characterised in that including:
One substrate is provided, this substrate has a first surface and a second surface, wherein this substrate includes the stacking multiple conductive pads on this first surface of this substrate and the dielectric layer between described conductive pad, the centre of the Upper conductive pad in wherein said conductive pad has at least one opening or groove, and this opening or this groove expose the lower floor's conductive pad in described conductive pad;
On this first surface of this substrate, on described conductive pad and this dielectric layer, a bearing basement is set;
This bearing basement of part is removed to form the depression towards this base extension from a upper surface of this bearing basement;
After forming this depression, removing this bearing basement of part to form the hole towards this base extension bottom the one of this depression of this bearing basement, wherein a sidewall of this hole is perpendicular to a surface of this bearing basement;
An insulating barrier is formed on the sidewall of this depression and the sidewall of this hole and bottom;
Remove this insulating barrier of part and this dielectric layer of part described conductive pad with exposed portion;
A conductive layer is formed, this conductive layer described conductive pad in electrical contact on the sidewall of this depression and the sidewall of this hole and bottom; And
Forming a welding resisting layer on this conductive layer, wherein this welding resisting layer is inserted among this hole, and has at least one bubble or space.
15. the forming method of wafer encapsulation body according to claim 14, it is characterised in that this hole extends among this substrate, and this conductive layer extends among this substrate.
16. the forming method of wafer encapsulation body according to claim 15, it is characterised in that be also included between this substrate and this conductive layer and form one second insulating barrier.
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| US9177919B2 (en) * | 2013-11-18 | 2015-11-03 | Xintec Inc. | Chip package and method for forming the same |
| CN111009506B (en) * | 2018-10-08 | 2021-08-03 | 精材科技股份有限公司 | Chip package |
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| CN1779961A (en) * | 2004-10-26 | 2006-05-31 | 三洋电机株式会社 | Semiconductor device and manufacturing method of the same |
| CN101221939A (en) * | 2007-01-11 | 2008-07-16 | 采钰科技股份有限公司 | Package structure for optoelectronic device and fabrication method thereof |
| CN101355069A (en) * | 2007-05-18 | 2009-01-28 | 三星电子株式会社 | Semiconductor packages with through hole silicon and method of fabricating the same |
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| US8823179B2 (en) * | 2008-05-21 | 2014-09-02 | Chia-Lun Tsai | Electronic device package and method for fabricating the same |
| KR20100048610A (en) * | 2008-10-31 | 2010-05-11 | 삼성전자주식회사 | Semiconductor fackage and forming method of the same |
| TWI418002B (en) * | 2009-12-01 | 2013-12-01 | Xintec Inc | Chip package and fabrication method thereof |
| US8525345B2 (en) * | 2010-03-11 | 2013-09-03 | Yu-Lin Yen | Chip package and method for forming the same |
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| CN101221939A (en) * | 2007-01-11 | 2008-07-16 | 采钰科技股份有限公司 | Package structure for optoelectronic device and fabrication method thereof |
| CN101355069A (en) * | 2007-05-18 | 2009-01-28 | 三星电子株式会社 | Semiconductor packages with through hole silicon and method of fabricating the same |
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