CN100485931C - Semiconductor element and its producing method - Google Patents
Semiconductor element and its producing method Download PDFInfo
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- CN100485931C CN100485931C CNB2006100058915A CN200610005891A CN100485931C CN 100485931 C CN100485931 C CN 100485931C CN B2006100058915 A CNB2006100058915 A CN B2006100058915A CN 200610005891 A CN200610005891 A CN 200610005891A CN 100485931 C CN100485931 C CN 100485931C
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- 238000000034 method Methods 0.000 title claims abstract description 80
- 239000004065 semiconductor Substances 0.000 title claims description 64
- 239000000758 substrate Substances 0.000 claims abstract description 125
- 239000003990 capacitor Substances 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims description 108
- 238000002955 isolation Methods 0.000 claims description 45
- 238000004519 manufacturing process Methods 0.000 claims description 37
- 229910021332 silicide Inorganic materials 0.000 claims description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 35
- 229910052751 metal Inorganic materials 0.000 claims description 34
- 239000002184 metal Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 26
- 238000005516 engineering process Methods 0.000 claims description 18
- 230000015572 biosynthetic process Effects 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000012447 hatching Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 230000003340 mental effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
First, the method provides substrate. Cut line on the substrate divides the substrate into at least one chip. Being formed on the substrate, grooves are positioned on prearranged area, where weld pads are to be formed, or on the area between pads and the cut line. Low electrode is formed on sidewall of substrate, and in substrate of base. Dielectric layer of capacitance and up electrode are formed on the substrate. The up electrode is filled in the grooves. Then, being formed on the substrate, the doping area is connected to the low electrode electrically. Afterwards, first weld pad and second weld pad are formed on the substrate. Through the doping area, the low electrode is connected to the first weld pad electrically, and the up electrode is connected to the second weld pad electrically. Since capacitor is formed under pads, or on the substrate between pads and the cut line, the invention reduces area engaged by chip.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of high-voltage semi-conductor electric capacity and its manufacture method.
Background technology
Along with the progress that integrated circuit is made, size of component is constantly dwindled, and metal-oxide semiconductor (MOS) becomes the main element of circuit design.Yet,, therefore be easy to damage because of the intrusion of outside noise because the operating voltage of MOS transistor is more and more little.Industry and educational circles noise prevent bet a large amount of mental and physical efforts on the problem, and obtain many solutions.
When high voltage device is imposed input voltage, also having similar noise problem via input weld pad (Input Pad).For making the stabilized input voltage of high voltage device, can have the capacitor (Capacitor) of big capacitance (Capacitance) with filtered noise in the configuration of input weld pad.Yet this measure meeting increases the cost of design.Another program be adopt with the embedded metal-insulating barrier-metal capacitor of CMOS (Complementary Metal Oxide Semiconductor) (CMOS) process integration (Embedded Metal-Insulator-Metal Capacitor, MIMCapacitor).Yet under the trend that integration promotes, the spendable chip area of capacitor plate (Plate) is forced to reduction, and strengthening day by day of active element function make the quantity of capacitor constantly increase, and these problems are the bottleneck of using MIM capacitor.Since at present MIM capacitor can with dielectric material and pole plate area can't provide enough capacitances (for example need 0.75fF/um to input voltage 18V
2), to deal with the voltage stabilizing problem of input voltage when higher.Therefore, desire to make stabilized input voltage, the mode that embedded MIM capacitor is set has tangible restriction.
Summary of the invention
In view of this, purpose of the present invention is exactly in the manufacture method that proposes a kind of semiconductor element, with the substrate that slot type capacitor is disposed at weld pad below or the zone between weld pad and the line of cut, to reduce capacitor shared space on chip, can be on the chip and increase for the area of other element use.
Another object of the present invention is to propose a kind of semiconductor element, so that the capacitor of tolerable than high input voltage to be provided.
The present invention proposes a kind of semiconductor element, and this semiconductor element is made of substrate, weld pad and slot type capacitor.And this slot type capacitor is made of bottom electrode, top electrode and capacitance dielectric layer.Have many lines of cut in the substrate, line of cut is divided at least one chip with substrate.The neighboring area of chip has a plurality of weld pads.Slot type capacitor is arranged at the zone between weld pad below or weld pad and the line of cut.Bottom electrode is arranged in the sidewall and the bottom of the groove of substrate.Top electrode is positioned in the substrate and fills up groove.Capacitance dielectric layer is between top electrode and bottom electrode, and wherein bottom electrode is electrically connected to first weld pad, and top electrode is electrically connected to second weld pad.
According to the described semiconductor element of the preferred embodiments of the present invention, also comprise a plurality of component isolation structures, those component isolation structures are positioned at this slot type capacitor both sides, so that other semiconductor element in this slot type capacitor and the substrate is isolated.In addition, above-mentioned groove is identical with the degree of depth of these component isolation structures.
According to the described semiconductor element of the preferred embodiments of the present invention, wherein bottom electrode is made of first doped region.The material of capacitance dielectric layer for example is a silica.The material of top electrode for example is a doped polycrystalline silicon.
According to the described semiconductor element of the preferred embodiments of the present invention, also comprise first conductive plunger of the utmost point and second weld pad that Connects Power, and second conductive plunger that connects this bottom electrode and this first weld pad.In addition, the doped region that connects second conductive plunger and bottom electrode in addition.In addition, be arranged in addition first metal silicide layer between the top electrode and first conductive plunger and be arranged at this doped region and this second conductive plunger between second metal silicide layer.
According to the described semiconductor element of the preferred embodiments of the present invention, wherein slot type capacitor can anti-10 volts to 40 volts voltage.
The characteristics of semiconductor element proposed by the invention are for utilizing slot type capacitor, and this slot type capacitor is placed in the substrate between weld pad below or weld pad and the line of cut.Therefore, the area of can the occupying volume not outer chip area of capacitor of the present invention.And, therefore can bear bigger voltage, and can not influence the semiconductor element beyond the component isolation structure because slot type capacitor is formed between the component isolation structure.
The present invention reintroduces a kind of manufacture method of semiconductor element.The method provides substrate earlier.Have many lines of cut in the substrate, substrate is divided at least one chip.Then, in this substrate, form a plurality of component isolation structures and at least one false isolation structure.This false isolation structure is in predetermined zone or the predetermined zone that forms between those weld pads and those lines of cut that forms a plurality of weld pads.Then, remove false isolation structure, in substrate, to form groove.Then, in the substrate of the sidewall of groove and bottom, form bottom electrode, in substrate, form capacitance dielectric layer and top electrode.Wherein, top electrode fills up groove.Afterwards, in substrate, form doped region and be electrically connected bottom electrode, in substrate, form first weld pad and second weld pad.Bottom electrode is electrically connected to first weld pad via assorted district, and top electrode is electrically connected to second weld pad.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the step that wherein forms groove in substrate is that patterned mask layer has the opening emerges part substrate prior to forming patterned mask layer in the substrate.Then, remove the part substrate, and in substrate, form groove.
Manufacture method according to the described semiconductor element of the preferred embodiments of the present invention, the step that wherein forms bottom electrode in the substrate of the sidewall of groove and bottom is for being mask with the patterned mask layer earlier, carry out the inclination angle ion implantation technology, remove patterned mask layer then.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the method that wherein in substrate, forms capacitance dielectric layer comprise thermal oxidation method or chemical vapour deposition technique one of them.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, wherein on prior to substrate, form conductor layer in the step that forms top electrode in the substrate, conductor layer fills up groove, then this conductor layer of patterning.
Manufacture method according to the described semiconductor element of the preferred embodiments of the present invention, after wherein in substrate, forming the step of doped region, also be included in doped region and upper electrode surface and form metal silicide layer, and the method that forms this metal silicide layer is for example for aiming at metal silicide technology voluntarily.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, wherein after forming the step of top electrode in the substrate, the sidewall that also is included in top electrode forms clearance wall.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, wherein in substrate, after the step of formation doped region, also be included in and form interlayer insulating film in the substrate, and in interlayer insulating film, form conductive plunger.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, wherein first weld pad and second weld pad are electrically connected to bottom electrode and top electrode through a little conductive plungers thus respectively.
According to the manufacture method of the described semiconductor element of the preferred embodiments of the present invention, the step that wherein forms component isolation structure and false isolation structure in substrate is prior to forming one deck patterned mask layer in the substrate, to expose the part substrate.Afterwards, remove institute's exposed portions substrate, in substrate, to form a plurality of grooves.Then, in substrate, form a layer insulating, to fill up each groove.Continue it, carry out flatening process, to remove groove insulating barrier in addition.Then, remove patterned mask layer.
The characteristics of the manufacture method of semiconductor element proposed by the invention are carried out Patternized technique for the photomask that only uses a non-key layer (Non-critical Layer), and form the top electrode of capacitor.Therefore, manufacture method provided by the present invention can't increase cost and the degree of difficulty in the manufacturing.And the manufacture method of semiconductor element of the present invention is easy to and the logic CMOS element process integration that generally has STI.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Fig. 1 is the top view of the semiconductor element of the embodiment of the invention.
Fig. 2 is the profile along the hatching I-I ' of Fig. 1.
Fig. 3 A to Fig. 3 F is the manufacturing process profile of the semiconductor element of the embodiment of the invention.
The simple symbol explanation
100: substrate
110: line of cut
120: chip
130: the interior zone of chip 120
140: component isolation structure
150: well region
160: false isolation structure
170: patterned mask layer
180: groove
190: bottom electrode
200: capacitance dielectric layer
210: top electrode
220: clearance wall
230: doped region
240,242: metal silicide layer
250: interlayer dielectric layer
260,270: conductive plunger
280,290: weld pad
300: slot type capacitor
310: the zone
I-I ': hatching
Embodiment
Fig. 1 is the top view of a semiconductor element of the preferred embodiment of the present invention.Please refer to Fig. 1, semiconductor element of the present invention is made of substrate 100, a plurality of weld pad and slot type capacitor 300.Have many lines of cut 110 in the substrate 100, line of cut 110 is divided into a plurality of chips 120 with substrate 100.That is, the zone of dividing out by line of cut 110 be cut out future chip area.The neighboring area of chip 120 has a plurality of weld pads, comprising weld pad 280 and weld pad 290.Slot type capacitor 300 as shown in Figure 2 is arranged at the below of weld pad, or the zone 310 between weld pad and the line of cut 110.Present embodiment is the example explanation with the slot type capacitor 300 that is positioned at weld pad 280 and weld pad 290 belows.
Please continue with reference to Fig. 2, Fig. 2 is the profile along Fig. 1 hatching I-I '.In substrate 100, dispose component isolation structure 140, well region 150, groove 180, interlayer dielectric layer 250, conductive plunger 260, conductive plunger 270, weld pad 280, weld pad 290 and slot type capacitor 300.Slot type capacitor 300 is made of bottom electrode 190, top electrode 210, capacitance dielectric layer 200, clearance wall 220, doped region 230, metal silicide layer 240 and metal silicide layer 242.Substrate 100 for example is the silicon base of P type for conductivity type.The material of weld pad for example is an aluminium alloy.Well region 150 for example is the light doped region of N type.Well region 150 is arranged in the substrate 100 of weld pad 280 and weld pad 290 belows.Component isolation structure 140 for example is a fleet plough groove isolation structure, and is positioned at the both sides of well region 150.Speak by the book, component isolation structure 140 is positioned at slot type capacitor 300 both sides, with other semiconductor element (not illustrating) electrical isolation in slot type capacitor 300 and the substrate 100.Groove 180 is arranged in the well region 150 of weld pad 280 belows, and the degree of depth of groove 180 is identical with component isolation structure 140.Bottom electrode 190 for example is the dense doped region of N type, and is arranged in the sidewall of groove 180 and the substrate 100 of bottom.The material of top electrode 210 is the doped polycrystalline silicon of N type for example, and is arranged in the groove 180.The material of capacitance dielectric layer 200 is a silica for example, and is arranged between bottom electrode 190 and the top electrode 210.Doped region 230 for example is a N type doped region, and doped region 230 is arranged in the well region 150 of weld pad 290 belows, and in abutting connection with bottom electrode 190.The material of interlayer dielectric layer 250 is a boron-phosphorosilicate glass for example, and is positioned at each weld pad below, and covers substrate 100.Conductive plunger 260 for example is a tungsten plug, and conductive plunger 260 is positioned among the interlayer dielectric layer 250, and the Connect Power utmost point 210 and weld pad 280.Conductive plunger 270 for example is a tungsten plug, and conductive plunger 270 is positioned among the interlayer dielectric layer 250, and connecting doped area 230 and weld pad 290.
The material of metal silicide layer 240 for example is tungsten silicide or cobalt silicide, and metal silicide layer 240 is between conductive plunger 270 and doped region 230.The material of metal silicide layer 242 for example is tungsten silicide or cobalt silicide, and metal silicide layer 242 is positioned among the interlayer dielectric layer 250, and connects conductive plunger 260 and top electrode 210.The material of clearance wall 220 for example is silica or silicon nitride, and connects capacitance dielectric layer 200 and interlayer dielectric layer 250.The top electrode 210 of slot type capacitor 300 and bottom electrode 190 be electrical isolation each other.
If weld pad 280 or weld pad 290 externally connects the high pressure input sources, then can design and make slot type capacitor 300 can bear 10 volts to 40 volts voltage, with as partially-filtered Circuit.This filter circuit can be imported in order to stable high voltage.
If other line configuring is arranged in the substrate 100 of weld pad 280 and weld pad 290 belows, then slot type capacitor 300 can not be disposed at hatching I-I ' and locates, therefore, in the substrate 100 in slot type capacitor 300 configurable zones 310 between each weld pad and line of cut 110.In this case, the mode that slot type capacitor 300 is electrically connected weld pad 280 and weld pad 290 will be not only and utilize conductive plunger 260 and conductive plunger 270, reach and must increase other interconnecting lead (Interconnection) within interlayer dielectric layer 250.
It should be noted that semiconductor element proposed by the invention has the following advantages at least:
1. slot type capacitor can be arranged in the substrate between weld pad below or weld pad and the line of cut, and its capacitor design can increase on demand and need not to increase shared substrate surface long-pending, therefore, semiconductor element of the present invention can not take the area of the interior zone 130 of chip 120.
2. because slot type capacitor is formed between the component isolation structure, therefore can bears bigger voltage, and can not influence the semiconductor element beyond the component isolation structure.
The manufacturing process of semiconductor element of the present invention below is described.Fig. 3 A to Fig. 3 F is the manufacturing process profile of semiconductor element of the present invention.At first, please refer to Fig. 3 A, substrate 100 is provided, this substrate 100 for example is the silicon base of conductivity type (Conductivity Type) P type.Formed many lines of cut (not illustrating) in this substrate 100, and substrate 100 has been divided into a plurality of chips (not illustrating).At first, in substrate 100, form one deck patterned mask layer (not illustrating).The material of this patterned mask layer for example is a silicon nitride, and it exposes the predetermined part substrate 100 that forms component isolation structure 140 and false isolation structure 160.Afterwards, remove institute's exposed portions substrate 100, in substrate 100, to form a plurality of grooves (not illustrating).In substrate 100, form a layer insulating (not illustrating) then to fill up these grooves.The material of this insulating barrier for example is a silica, and its formation method for example is a chemical vapour deposition technique.Continue it, carry out flatening process, to remove those grooves this insulating barrier in addition.Flatening process for example is a chemical mechanical milling tech.Afterwards, remove this patterned mask layer, and in substrate 100, form a plurality of component isolation structures 140 and at least one false isolation structure 160 (Dummy isolation structure).This false isolation structure 160 is in the predetermined zone of a plurality of weld pads or the zone between those weld pads and those lines of cut of forming.Then, between component isolation structure 140, form a well region 150.Well region 150 for example is the light doped region of N type, and the formation method of well region 150 for example is an ion implantation.
Then, in substrate 100, form one deck patterned mask layer 170.The material of patterned mask layer 170 for example is photoresist (Photoresist) or silicon nitride, and it covers isolation structure 140, and expose portion substrate 100 and false isolation structure 160.Then, carry out an etch process, removing false isolation structure 160, and in substrate 100, form a groove 180.
Then, please refer to Fig. 3 C, in the substrate 100 of the sidewall of groove 180 and bottom, form a bottom electrode 190.The formation method of bottom electrode 190 is for example for be that mask carries out the inclination angle ion implantation technology to substrate 100 with patterned mask layer 170, and in the substrate 100 of the sidewall of groove 180 and bottom dense doped region of formation, and then remove patterned mask layer 170.This dense doped region is as bottom electrode 190, and the conductivity type of bottom electrode 190 for example is the N type.The method that removes of patterned mask layer 170 is to decide with the material of patterned mask layer 170, if the material of patterned mask layer 170 is a photoresist, the method that then removes for example is an ashing (Ashing) technology; If the material of patterned mask layer 170 is a silicon nitride, the method that then removes for example is a wet etch process.Afterwards, in substrate 100, form one deck capacitance dielectric layer 200.The method that forms capacitance dielectric layer 200 is thermal oxidation method or chemical vapour deposition technique for example, and the material of capacitance dielectric layer 200 for example is a silica.The material of capacitance dielectric layer 200 also can be any dielectric material.
Continue it, please refer to Fig. 3 D, in substrate 100, form a top electrode 210, and top electrode 210 fills up groove 180.The formation method of top electrode 210 for example is to form one deck conductor layer, this conductor layer of patterning and capacitance dielectric layer 200 then in substrate 100.The material of this conductor layer for example is a polysilicon, and the formation method of this conductor layer for example is a chemical vapour deposition technique.The method of patterning conductor layer and capacitance dielectric layer 200 for example is prior to formation one deck patterning photoresist layer in the substrate 100, and the part substrate 100 beyond these patterning photoresist layer covering groove 180 tops and the groove 180.Then, be mask with this patterning photoresist layer, carry out dry etch process, and remove conductor layer and the capacitance dielectric layer 200 that patterning photoresist layer is exposed.This dry etch process proceeds to till the surface that exposes part substrate 100.Then, the sidewall in top electrode 210 forms a clearance wall 220.The formation method of clearance wall 220 is for example for utilizing chemical vapour deposition technique to form one deck silica or silicon nitride in substrate 100, carries out anisotropic etching process again till the surface that exposes substrate 100.
Then, please refer to Fig. 3 E, in substrate 100, form doped region 230, and doped region 230 is electrically connected bottom electrode 190.Doped region 230 for example is a N type doped region, and the formation method of doped region 230 is for example for to carry out an ion implantation technology to substrate 100.This ion implantation technology is that the top electrode 210 of polysilicon mixes to material simultaneously, makes the surfacing of top electrode 210 become doped polycrystalline silicon, therefore has better conductibility (Conductivity).Certainly, the conductivity type of this doped polycrystalline silicon and doped region 230 are all the N type.
Then, in the top surface formation layer of metal silicide layer 240 of doped region 230, and in the top surface formation layer of metal silicide layer 242 of top electrode 210.Metal silicide layer 240 is a cobalt silicide for example with the material of metal silicide layer 242, and metal silicide layer 240 for example is to aim at metal silicide (Self-Aligned Silicide) technology voluntarily with the formation method of metal silicide layer 242.Be a complete capacitor till the structure of Fig. 3 E technology up till now, this capacitor will be electrically connected with extraneous with the metallic conduction connector at subsequent technique.Top electrode 210 will be electrically connected with conductive plunger via metal silicide layer 242.And owing to bottom electrode 190 is electrically connected with doped region 230, so bottom electrode 190 will be electrically connected with conductive plunger via doped region 230 and metal silicide layer 240.Those skilled in the art know that metal silicide has good electrical conductivity, and are intermediary layer material commonly used between metal and the silicon.Therefore, form metal silicide layer 240 here and promptly reducing this capacitor and the extraneous resistance that is electrically connected with the purpose of metal silicide layer 242.
Afterwards, please refer to Fig. 3 F, in substrate 100, form one deck interlayer dielectric layer 250.The material of interlayer dielectric layer 250 for example is a boron-phosphorosilicate glass (BPSG).The formation method of interlayer dielectric layer 250 for example is with ozone (O
3) carry out aumospheric pressure cvd (APCVD) technology with tetraethoxysilane (TEOS) for reacting gas.Then, in interlayer dielectric layer 250, form a plurality of conductive plungers 260 and conductive plunger 270.The bottom of conductive plunger 260 is electrically connected with metal silicide layer 242, and the bottom of conductive plunger 270 is electrically connected with metal silicide layer 240, and conductive plunger 260 comes out in the top of substrate 100 with conductive plunger 270.Therefore, conductive plunger 260 is electrically connected with top electrode 210, and conductive plunger 270 is electrically connected with bottom electrode 190.Conductive plunger 260 for example is a tungsten plug with conductive plunger 270, and conductive plunger 260 is known by industry with the generation type of conductive plunger 270.
Then, in substrate 100, form weld pad 280 and weld pad 290.Weld pad 280 is electrically connected with conductive plunger 260, and weld pad 290 is electrically connected with conductive plunger 270.Therefore, weld pad 280 is electrically connected with top electrode 210, and weld pad 290 is electrically connected with bottom electrode 190.Weld pad 280 for example is an aluminium alloy with the material of weld pad 290.And the formation method of weld pad 280 and weld pad 290 is carried out the photoengraving carving technology more for example for earlier substrate 100 being carried out the sputtering technology of aluminium alloy.Then, carry out existing subsequent technique, to finish the manufacturing of this semiconductor element.This follow-up technology is well known to those skilled in the art, so locate to repeat no more.
Manufacture method that it should be noted that semiconductor element proposed by the invention has the following advantages at least:
1. the technology of the forming process of slot type capacitor and embedded MIM capacitor is similar.This two technology all needs to form a upper conductor material layer in substrate, and the photomask via a non-key layer (Non-criticalLayer) carries out a Patternized technique then, and forms the top electrode of capacitor.Compare with the technology of embedded MIM capacitor, manufacture method provided by the present invention can't increase cost and the degree of difficulty in the manufacturing.
2. the manufacture method of semiconductor element of the present invention is easy to and the logic CMOS element process integration that generally has STI.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (21)
1, a kind of semiconductor element comprises:
Substrate has many lines of cut in this substrate, this substrate is divided at least one chip;
A plurality of weld pads are arranged in the neighboring area of this chip; And
At least one slot type capacitor is arranged at the zone between those weld pad belows or those weld pads and those lines of cut, and this slot type capacitor comprises:
Bottom electrode is arranged at the sidewall and the bottom of the groove in this substrate;
Top electrode is arranged in this substrate and fills up this groove; And
Capacitance dielectric layer is arranged between this top electrode and this bottom electrode, and wherein this bottom electrode is electrically connected to first weld pad, and this top electrode is electrically connected to second weld pad.
2, semiconductor element as claimed in claim 1 also comprises a plurality of component isolation structures, and those component isolation structures are positioned at this slot type capacitor both sides, so that other semiconductor element in this slot type capacitor and the substrate is isolated.
3, semiconductor element as claimed in claim 2, wherein this groove is identical with the degree of depth of those component isolation structures.
4, semiconductor element as claimed in claim 1, wherein this bottom electrode is made of doped region.
5, semiconductor element as claimed in claim 1, wherein the material of this capacitance dielectric layer comprises silica.
6, semiconductor element as claimed in claim 1, wherein the material of this top electrode comprises doped polycrystalline silicon.
7, semiconductor element as claimed in claim 1 also comprises first conductive plunger that connects this top electrode and this second weld pad, and second conductive plunger that connects this bottom electrode and this first weld pad.
8, semiconductor element as claimed in claim 7 also comprises doped region, connects this second conductive plunger and this bottom electrode.
9, semiconductor element as claimed in claim 8 also comprises first metal silicide layer that is arranged between this top electrode and this first conductive plunger, and is arranged at second metal silicide layer between this doped region and this second conductive plunger.
10, semiconductor element as claimed in claim 1, wherein this slot type capacitor can anti-10 volts to 40 volts voltage.
11, a kind of manufacture method of semiconductor element comprises:
Substrate is provided, has many lines of cut in this substrate, this substrate is divided at least one chip;
Form a plurality of component isolation structures and at least one false isolation structure in this substrate, this vacation isolation structure is in predetermined zone or the predetermined zone that forms between those weld pads and those lines of cut that forms a plurality of weld pads;
Remove this vacation isolation structure, in this substrate, to form groove;
In this substrate of the sidewall of this groove and bottom, form bottom electrode;
In this substrate, form capacitance dielectric layer;
Form top electrode in this substrate, this top electrode fills up this groove;
In this substrate, form doped region and be electrically connected this bottom electrode; And
Form first weld pad and second weld pad in this substrate, this bottom electrode is electrically connected to this first weld pad via this doped region, and this top electrode is electrically connected to second weld pad.
12, the manufacture method of semiconductor element as claimed in claim 11 wherein removes this vacation isolation structure, comprises with the step that forms this groove in this substrate:
Form patterned mask layer in this substrate, this patterned mask layer covers those component isolation structures, and this substrate of expose portion and this vacation isolation structure;
Carry out etch process, removing this vacation isolation structure, and in this substrate, form this groove.
13, the manufacture method of semiconductor element as claimed in claim 12, the step that wherein forms this bottom electrode in this substrate of the sidewall of this groove and bottom comprises:
With this patterned mask layer is mask, carries out the inclination angle ion implantation technology; And
Remove this patterned mask layer.
14, the manufacture method of semiconductor element as claimed in claim 11, the method that wherein forms this capacitance dielectric layer in this substrate comprises one of them of thermal oxidation method or chemical vapour deposition technique.
15, the manufacture method of semiconductor element as claimed in claim 11, the step that wherein forms this top electrode in this substrate comprises:
Form conductor layer in this substrate, this conductor layer fills up this groove; And
This conductor layer of patterning.
16, the manufacture method of semiconductor element as claimed in claim 11 wherein after the step of this doped region of formation, also is included in this doped region and this upper electrode surface and forms metal silicide layer in this substrate.
17, the manufacture method of semiconductor element as claimed in claim 16, wherein the method that forms this metal silicide layer in this doped region and this upper electrode surface comprises and aims at metal silicide technology voluntarily.
18, the manufacture method of semiconductor element as claimed in claim 11, wherein after forming the step of this top electrode in this substrate, the sidewall that also is included in this top electrode forms clearance wall.
19, the manufacture method of semiconductor element as claimed in claim 11 wherein after the step of this doped region of formation, also comprises in this substrate:
In this substrate, form interlayer insulating film; And
In this interlayer insulating film, form a plurality of conductive plungers.
20, the manufacture method of semiconductor element as claimed in claim 19, wherein this first weld pad and this second weld pad are electrically connected to this bottom electrode and this top electrode via those conductive plungers respectively.
21, the manufacture method of semiconductor element as claimed in claim 11, the step that wherein forms those component isolation structures and this at least one false isolation structure in this substrate comprises:
In this substrate, form patterned mask layer, to expose this substrate of part;
Remove institute's this substrate of exposed portions, in this substrate, to form a plurality of grooves;
In this substrate, form insulating barrier, to fill up those grooves;
Carry out flatening process, to remove those grooves this insulating barrier in addition; And
Remove this patterned mask layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100058915A CN100485931C (en) | 2006-01-19 | 2006-01-19 | Semiconductor element and its producing method |
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| CNB2006100058915A CN100485931C (en) | 2006-01-19 | 2006-01-19 | Semiconductor element and its producing method |
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| CN100485931C true CN100485931C (en) | 2009-05-06 |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101673311B (en) * | 2008-09-11 | 2011-05-11 | 北京同方微电子有限公司 | Method for optimizing area of mixed signal chip |
| CN103367109A (en) * | 2012-04-11 | 2013-10-23 | 南亚科技股份有限公司 | Manufacturing method of trench capacitor |
| CN108565255B (en) * | 2018-04-09 | 2020-10-30 | 复汉海志(江苏)科技有限公司 | Semiconductor interconnection structure |
| CN111081675B (en) * | 2018-10-18 | 2024-04-12 | 源芯半导体股份有限公司 | Integrated circuit device with insulating capacitor and method of manufacturing the same |
| WO2020235175A1 (en) * | 2019-05-21 | 2020-11-26 | 株式会社村田製作所 | Capacitor |
| CN113497186A (en) | 2020-04-01 | 2021-10-12 | 联华电子股份有限公司 | Parallel capacitor structure and manufacturing method thereof |
| CN112885793A (en) * | 2021-03-12 | 2021-06-01 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure and manufacturing method thereof |
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