TWI658543B - Semiconductor device and method of using a standardized carrier in semiconductor packaging - Google Patents

Semiconductor device and method of using a standardized carrier in semiconductor packaging Download PDF

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TWI658543B
TWI658543B TW103136991A TW103136991A TWI658543B TW I658543 B TWI658543 B TW I658543B TW 103136991 A TW103136991 A TW 103136991A TW 103136991 A TW103136991 A TW 103136991A TW I658543 B TWI658543 B TW I658543B
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semiconductor
semiconductor die
carrier
die
wafer
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TW103136991A
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TW201523802A (en
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托瑪斯Ｊ 施特羅特曼
達米安Ｍ 普里科洛
沈一權
耀劍 林
海茲 彼得 華茲
尹勝煜
潘迪Ｃ 瑪莉姆蘇
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新加坡商史達晶片有限公司
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Abstract

一種半導體裝置具有一有固定大小的載體。複數個第一半導體晶粒從一第一半導體晶圓處被單體化裁切出來。該些第一半導體晶粒被設置在該載體上方。在該載體上的第一半導體晶粒的數量不相依於從該第一半導體晶圓處單體化裁切出來的第一半導體晶粒的大小與數量。一囊封體被沉積在該些第一半導體晶粒與該載體上方及周圍，用以形成一重組式鑲板。一互連結構被形成在該重組式鑲板上方，同時保留該囊封體沒有該互連結構。該重組式鑲板被單體化裁切貫穿該囊封體。該些第一半導體晶粒從該載體處被移除。一具有不同於該些第一半導體晶粒之大小的大小的第二半導體晶粒被設置在該載體上方。該載體的固定大小不相依於該第二半導體晶粒的大小。 A semiconductor device has a carrier having a fixed size. The plurality of first semiconductor dies are singulated from a first semiconductor wafer. The first semiconductor dies are disposed above the carrier. The number of first semiconductor crystal grains on the carrier does not depend on the size and number of the first semiconductor crystal grains cut from the first semiconductor wafer by singulation. An encapsulation body is deposited above and around the first semiconductor dies and the carrier to form a recombination panel. An interconnecting structure is formed over the recombination panel, while leaving the encapsulation body free of the interconnecting structure. The recombination panel is singulated and cut through the encapsulation body. The first semiconductor dies are removed from the carrier. A second semiconductor die having a size different from the size of the first semiconductor die is disposed above the carrier. The fixed size of the carrier does not depend on the size of the second semiconductor die.

Description

在半導體封裝中使用標準化載體的半導體裝置及方法 Semiconductor device and method using standardized carrier in semiconductor package

本發明大體上和半導體裝置有關，且更明確地說，本發明係關於使用標準化載體來形成晶圓級晶片尺寸封裝(Wafer Level Chip Scale Package，WLCSP)的半導體裝置及方法。 The present invention relates generally to semiconductor devices, and more specifically, the present invention relates to a semiconductor device and method for forming a wafer level chip scale package (WLCSP) using a standardized carrier.

優先權之主張 Claim of priority

本申請案為2013年3月15日所提申之美國專利申請案第13/832,809號的部份接續案，該案主張2012年10月2日所提申之美國臨時申請案第61/744,699號的權利，本文以引用的方式將此些申請案併入。 This application is a partial continuation of U.S. Patent Application No. 13 / 832,809 filed on March 15, 2013, which claims that the United States Provisional Application No. 61 / 744,699 filed on October 2, 2012 No., which is incorporated herein by reference.

在現代的電子產品中經常發現半導體裝置。半導體裝置會有不同數量與密度的電氣組件。離散式半導體裝置通常含有某一種類型的電氣組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。積體式半導體裝置通常含有數百個至數百萬個電氣組件。積體式半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池、 以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。 Semiconductor devices are often found in modern electronics. Semiconductor devices have different numbers and densities of electrical components. Discrete semiconductor devices usually contain certain types of electrical components, such as light emitting diodes (LEDs), small signal transistors, resistors, capacitors, inductors, and power metal oxide semiconductor field effects Transistor (Metal Oxide Semiconductor Field Effect Transistor, MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge-coupled devices (CCDs), solar cells, And Digital Micro-mirror Device (DMD).

半導體裝置會實施各式各樣的功能，例如，訊號處理、高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。 Semiconductor devices perform a variety of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electrical energy, and generating visual projections of television displays. Semiconductor devices are found in the fields of entertainment, communications, power conversion, networking, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

半導體裝置會利用半導體材料的電氣特性。半導體材料的結構使得可藉由施加電場或基極電流或是經由摻雜處理來操縱其導電性。摻雜會將雜質引入至半導體材料之中，以便操縱及控制半導體裝置的傳導性。 Semiconductor devices take advantage of the electrical properties of semiconductor materials. The structure of a semiconductor material makes it possible to manipulate its electrical conductivity by applying an electric or base current, or through a doping process. Doping introduces impurities into the semiconductor material in order to manipulate and control the conductivity of the semiconductor device.

半導體裝置含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)會控制電流的流動。藉由改變摻雜程度以及施加電場或基極電流，電晶體便會提高或限制電流的流動。被動式結構(其包含電阻器、電容器、以及電感器)會創造用以實施各式各樣電氣功能所需要的電壓和電流之間的關係。該些被動式結構與主動式結構會被電氣連接以形成讓半導體裝置實施高速計算及其它實用功能的電路。 The semiconductor device includes an active electrical structure and a passive electrical structure. Active structures (which include bipolar transistors and field effect transistors) control the flow of current. By changing the degree of doping and applying an electric or base current, the transistor will increase or limit the flow of current. Passive structures (which include resistors, capacitors, and inductors) create the relationship between voltage and current needed to perform a variety of electrical functions. The passive structures and the active structures are electrically connected to form a circuit that allows the semiconductor device to perform high-speed computing and other practical functions.

半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個半導體晶粒通常相同並且含有藉由電氣連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的半導體晶粒並且封裝該晶粒，用以提供結構性支撐以及環境隔離。本文中所使用的「半導體晶粒(semiconductor die)」 一詞兼具單數和複數形式，且據此會表示單一半導體裝置以及多個半導體裝置兩者。 Semiconductor devices are typically manufactured using two complex processes, that is, front-end manufacturing and back-end manufacturing, each of which may involve hundreds of steps. Front-end manufacturing involves forming a plurality of dies on the surface of a semiconductor wafer. Each semiconductor die is usually the same and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor dies from the finished wafer and packaging the dies to provide structural support and environmental isolation. "Semiconductor die" as used in this article The term has both singular and plural forms, and accordingly it means both a single semiconductor device and multiple semiconductor devices.

半導體製造的其中一個目標便係生產較小型的半導體裝置。較小型裝置通常會消耗較少的電力，具有較高的效能，並且能夠被更有效地生產。此外，較小型的半導體裝置還具有較小的覆蓋區，這係較小型末端產品所需要的。藉由改良前端製程能夠達成較小的半導體晶粒尺寸，從而導致具有較小尺寸以及較高密度之主動式組件和被動式組件的半導體晶粒。後端製程可以藉由改良電氣互連及封裝材料而導致具有較小覆蓋區的半導體裝置封裝。 One of the goals of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher efficiency, and can be produced more efficiently. In addition, smaller semiconductor devices also have smaller footprints, which are needed for smaller end products. By improving the front-end process, smaller semiconductor die sizes can be achieved, resulting in semiconductor die with smaller sizes and higher density for active and passive devices. Back-end processes can lead to semiconductor device packages with smaller footprints by improving electrical interconnects and packaging materials.

習知的半導體晶圓通常含有藉由一切割道而被分開的複數個半導體晶粒。主動式電路和被動式電路係被形成在每一個半導體晶粒的表面中。一互連結構會被形成在該半導體晶粒的表面上。該半導體晶圓會被單體化裁切成個別的半導體晶粒，以便使用在各式各樣的電子產品中。半導體製造的一項重要觀點係高產量以及對應的低成本。 Conventional semiconductor wafers usually contain a plurality of semiconductor dies that are separated by a scribe line. Active circuits and passive circuits are formed in the surface of each semiconductor die. An interconnect structure is formed on the surface of the semiconductor die. The semiconductor wafer is singulated and cut into individual semiconductor dies for use in a variety of electronic products. An important point in semiconductor manufacturing is high throughput and correspondingly low cost.

半導體晶圓會被製作成具有相依於被用來生產該些半導體晶圓和半導體晶粒之設備的各種直徑及半導體晶粒大小。半導體處理設備通常係根據每一種特殊半導體晶粒大小及進料半導體晶圓大小來開發。舉例來說，200毫米(mm)的晶圓係利用200mm設備來處理，而300mm的晶圓係利用300mm設備來處理。從一晶圓處被單體化裁切出來的半導體晶粒係在一載體上被處理。該載體的大小係根據要被處理器的半導體晶粒的大小來選擇。舉例來說，10mm乘10mm的半導體晶粒係利用和5mm乘5mm的半導體晶粒不同的設備來處理。所以，用於封裝半導體裝置的設備在處理 該設備被設計使用的特定半導體晶粒大小或半導體晶圓大小的能力方面會受到限制。當進料半導體晶粒大小及半導體晶圓大小改變時，則必須額外投資製造設備。投資用於特定大小的半導體晶粒或半導體晶圓的設備會產生半導體裝置製造商的資本投資風險。當進料半導體晶圓大小改變時，特定晶圓設備便會成為廢品。同樣地，被設計用於特定大小半導體晶粒的載體與設備也會成為廢品，因為該些載體在處理不同大小半導體晶粒的能力會受到限制。不斷地開發與施行不同的設備會增加最終半導體裝置的成本。 Semiconductor wafers are fabricated with various diameters and semiconductor die sizes depending on the equipment used to produce the semiconductor wafers and semiconductor dies. Semiconductor processing equipment is usually developed based on the size of each particular semiconductor die and the size of the incoming semiconductor wafer. For example, a 200 millimeter (mm) wafer series is processed using a 200mm device, and a 300mm wafer series is processed using a 300mm device. The semiconductor dies that are singulated from a wafer are processed on a carrier. The size of the carrier is selected based on the size of the semiconductor die to be processed. For example, a semiconductor die of 10 mm by 10 mm is processed using a device different from a semiconductor die of 5 mm by 5 mm. Therefore, equipment for packaging semiconductor devices is processing The device is designed to be limited in its ability to use a specific semiconductor die size or semiconductor wafer size. When the incoming semiconductor die size and semiconductor wafer size change, additional investment in manufacturing equipment is required. Investing in equipment for semiconductor wafers or semiconductor wafers of a particular size poses a capital investment risk for semiconductor device manufacturers. When the size of the incoming semiconductor wafer changes, certain wafer equipment becomes scrap. Similarly, carriers and equipment designed for semiconductor wafers of a certain size will also be scrapped, as the ability of these carriers to handle semiconductor wafers of different sizes will be limited. Continuous development and implementation of different equipment will increase the cost of the final semiconductor device.

半導體晶圓包含各種直徑並且通常以被設計用於每一種特定大小半導體晶粒的製造設備來處理。半導體晶粒通常被密封在半導體封裝裡面以達該晶粒之電氣互連、結構性支撐、以及環境保護的目的。倘若半導體晶粒的一部分曝露在外部元素中的話，尤其是當表面裝設該晶粒時，半導體便會遭到破壞或毀損。舉例來說，半導體晶粒在處理及曝光期間會被破壞或毀損。 Semiconductor wafers contain a variety of diameters and are typically processed in manufacturing equipment designed for each specific size semiconductor die. The semiconductor die is usually sealed inside the semiconductor package for the purposes of electrical interconnection, structural support, and environmental protection of the die. If a part of the semiconductor die is exposed to external elements, especially when the die is mounted on the surface, the semiconductor will be damaged or destroyed. For example, semiconductor dies can be damaged or destroyed during processing and exposure.

本技術領域需要使用能夠應付多種大小之半導體晶粒和進料晶圓的載體及設備來有效製造半導體裝置。據此，於一實施例中，本發明係一種製造半導體裝置的方法，該方法包括下面步驟：提供一固定大小的載體；以及設置複數個第一半導體晶粒於該載體上方。該載體的固定大小不相依於該第一半導體晶粒的大小。 The technical field requires carriers and equipment capable of coping with semiconductor dies of various sizes and feed wafers to efficiently manufacture semiconductor devices. Accordingly, in one embodiment, the present invention is a method for manufacturing a semiconductor device. The method includes the steps of: providing a carrier of a fixed size; and placing a plurality of first semiconductor dies on the carrier. The fixed size of the carrier does not depend on the size of the first semiconductor die.

於另一實施例中，本發明係一種製造半導體裝置的方法，該方法包括下面步驟：提供一載體；以及設置一第一半導體晶粒於該載體上方。該載體的大小不相依於該第一半導體晶粒的大小。 In another embodiment, the present invention is a method for manufacturing a semiconductor device. The method includes the following steps: providing a carrier; and disposing a first semiconductor die on the carrier. The size of the carrier does not depend on the size of the first semiconductor die.

於另一實施例中，本發明係一種製造半導體裝置的方法，該方法包括下面步驟：提供一半導體晶粒；沉積一囊封體於該半導體晶粒上方與周圍，用以形成一重組式鑲板；於該重組式鑲板上方形成一互連結構，同時保留該囊封體沒有該互連結構；以及單體化裁切該重組式鑲板貫穿該囊封體。 In another embodiment, the present invention is a method for manufacturing a semiconductor device. The method includes the following steps: providing a semiconductor die; and depositing an encapsulation body over and around the semiconductor die to form a recombined insert. Forming an interconnection structure above the recombined panel while retaining the encapsulation body without the interconnect structure; and singulating the recombination panel through the encapsulation body.

於另一實施例中，本發明係一種半導體裝置，其包括一半導體晶粒。一囊封體被沉積在該半導體晶粒上方以及相鄰於該半導體晶粒的周邊區域之中。一互連結構被形成在該半導體晶粒上方。該周邊區域不會有該互連結構。 In another embodiment, the present invention is a semiconductor device including a semiconductor die. An encapsulation is deposited over the semiconductor die and in a peripheral region adjacent to the semiconductor die. An interconnect structure is formed over the semiconductor die. The peripheral area will not have the interconnect structure.

50‧‧‧電子裝置 50‧‧‧ electronic device

52‧‧‧印刷電路板(PCB) 52‧‧‧Printed Circuit Board (PCB)

54‧‧‧訊號線路 54‧‧‧Signal line

56‧‧‧焊線封裝 56‧‧‧ wire package

58‧‧‧覆晶 58‧‧‧ flip chip

60‧‧‧球柵陣列(BGA) 60‧‧‧Ball Grid Array (BGA)

62‧‧‧凸塊晶片載體(BCC) 62‧‧‧ Bump Wafer Carrier (BCC)

64‧‧‧雙直列封裝(DIP) 64‧‧‧DIP

66‧‧‧平台格柵陣列(LGA) 66‧‧‧platform grid array (LGA)

68‧‧‧多晶片模組(MCM) 68‧‧‧Multi-Chip Module (MCM)

70‧‧‧方形扁平無導線封裝(QFN) 70‧‧‧ Square Flat Wireless Package (QFN)

72‧‧‧方形扁平封裝 72‧‧‧ Square Flat Package

74‧‧‧半導體晶粒 74‧‧‧semiconductor die

76‧‧‧接觸墊 76‧‧‧ contact pad

78‧‧‧中間載體 78‧‧‧ intermediate carrier

80‧‧‧導體導線 80‧‧‧ Conductor wire

82‧‧‧焊線 82‧‧‧ welding wire

84‧‧‧囊封體 84‧‧‧ Capsule

88‧‧‧半導體晶粒 88‧‧‧semiconductor die

90‧‧‧載體 90‧‧‧ carrier

92‧‧‧底層填充材料或環氧樹脂膠黏材料 92‧‧‧ Underfill material or epoxy adhesive material

94‧‧‧焊線 94‧‧‧ welding wire

96‧‧‧接觸墊 96‧‧‧ contact pad

98‧‧‧接觸墊 98‧‧‧contact pad

100‧‧‧模製化合物或囊封體 100‧‧‧ molded compound or encapsulation

102‧‧‧接觸墊 102‧‧‧contact pad

104‧‧‧凸塊 104‧‧‧ bump

106‧‧‧中間載體 106‧‧‧ Intermediate carrier

108‧‧‧主動區 108‧‧‧active zone

110‧‧‧凸塊 110‧‧‧ bump

112‧‧‧凸塊 112‧‧‧ bump

114‧‧‧訊號線 114‧‧‧ signal line

116‧‧‧模製化合物或囊封體 116‧‧‧ Moulded compound or capsule

120‧‧‧半導體晶圓 120‧‧‧Semiconductor wafer

122‧‧‧基礎基板材料 122‧‧‧Basic Substrate Materials

124‧‧‧半導體晶粒或組件 124‧‧‧Semiconductor die or component

126‧‧‧切割道 126‧‧‧cut road

128‧‧‧背表面或非主動表面 128‧‧‧back surface or inactive surface

130‧‧‧主動表面 130‧‧‧active surface

132‧‧‧導電層 132‧‧‧ conductive layer

134‧‧‧絕緣層或鈍化層 134‧‧‧Insulation layer or passivation layer

136‧‧‧導電層或重新分佈層(RDL) 136‧‧‧ conductive layer or redistribution layer (RDL)

138‧‧‧雷射 138‧‧‧laser

140‧‧‧主動表面的一部分 140‧‧‧ part of the active surface

142‧‧‧導電層 142‧‧‧ conductive layer

144‧‧‧鋸片或雷射削切工具 144‧‧‧Saw blade or laser cutting tool

150‧‧‧載體或暫時性基板 150‧‧‧ carrier or temporary substrate

152‧‧‧介面層或雙面膠帶 152‧‧‧Interface layer or double-sided tape

153‧‧‧重組式晶圓或重新配置晶圓 153‧‧‧Reassembled wafers or reconfigured wafers

154‧‧‧囊封體或模製化合物 154‧‧‧ Encapsulated body or molded compound

156‧‧‧雷射 156‧‧‧Laser

160‧‧‧球體或凸塊 160‧‧‧ sphere or bump

162‧‧‧鋸片或雷射削切工具 162‧‧‧Saw blade or laser cutting tool

164‧‧‧WLCSP 164‧‧‧WLCSP

170‧‧‧半導體晶圓 170‧‧‧Semiconductor wafer

172‧‧‧基礎基板材料 172‧‧‧Basic substrate material

174‧‧‧半導體晶粒或組件 174‧‧‧Semiconductor die or component

176‧‧‧切割道 176‧‧‧cut road

178‧‧‧背表面或非主動表面 178‧‧‧back surface or inactive surface

180‧‧‧主動表面 180‧‧‧ Active Surface

182‧‧‧導電層 182‧‧‧ conductive layer

184‧‧‧導電層 184‧‧‧ conductive layer

186‧‧‧絕緣層或鈍化層 186‧‧‧Insulation layer or passivation layer

188‧‧‧導電層或重新分佈層(RDL) 188‧‧‧ conductive layer or redistribution layer (RDL)

190‧‧‧雷射 190‧‧‧laser

192‧‧‧主動表面的一部分 192‧‧‧ part of the active surface

194‧‧‧鋸片或雷射削切工具 194‧‧‧Saw blade or laser cutting tool

200‧‧‧載體或暫時性基板 200‧‧‧ carrier or temporary substrate

202‧‧‧介面層或雙面膠帶 202‧‧‧Interface layer or double-sided tape

203‧‧‧重組式晶圓或重新配置晶圓 203‧‧‧Reassembled wafers or reconfigured wafers

204‧‧‧囊封體或模製化合物 204‧‧‧ Encapsulation or molding compound

206‧‧‧雷射 206‧‧‧laser

210‧‧‧球體或凸塊 210‧‧‧ sphere or bump

212‧‧‧鋸片或雷射削切工具 212‧‧‧Saw blade or laser cutting tool

214‧‧‧WLCSP 214‧‧‧WLCSP

220‧‧‧半導體晶粒 220‧‧‧Semiconductor die

222‧‧‧背表面或非主動表面 222‧‧‧back surface or inactive surface

224‧‧‧主動表面 224‧‧‧active surface

226‧‧‧導電層 226‧‧‧ conductive layer

228‧‧‧導電層 228‧‧‧ conductive layer

230‧‧‧球體或凸塊 230‧‧‧ sphere or bump

232‧‧‧基板 232‧‧‧ substrate

234‧‧‧導體線路 234‧‧‧Conductor line

236‧‧‧重組式晶圓或重新配置晶圓 236‧‧‧Reassembled wafer or reconfigured wafer

238‧‧‧主動表面的一部分 238‧‧‧ part of the active surface

239‧‧‧鋸片或雷射削切工具 239‧‧‧Saw blade or laser cutting tool

240‧‧‧模製底層填充(MUF)材料 240‧‧‧ Moulded Underfill (MUF) Material

242‧‧‧載體或暫時性基板 242‧‧‧ Carrier or temporary substrate

243‧‧‧介面層或雙面膠帶 243‧‧‧Interface layer or double-sided tape

244‧‧‧囊封體或模製化合物 244‧‧‧ Encapsulated body or molded compound

245‧‧‧雷射 245‧‧‧laser

246‧‧‧球體或凸塊 246‧‧‧ sphere or bump

248‧‧‧鋸片或雷射削切工具 248‧‧‧Saw blade or laser cutting tool

250‧‧‧晶圓級晶片尺寸封裝(WLCSP) 250‧‧‧ Wafer Level Wafer Size Package (WLCSP)

260‧‧‧半導體晶粒 260‧‧‧Semiconductor die

262‧‧‧背表面或非主動表面 262‧‧‧back surface or inactive surface

264‧‧‧主動表面 264‧‧‧active surface

266‧‧‧導電層 266‧‧‧ conductive layer

268‧‧‧基板 268‧‧‧ substrate

270‧‧‧晶粒附著黏著劑 270‧‧‧ Grain Adhesive

272‧‧‧導體線路 272‧‧‧conductor line

274‧‧‧焊線 274‧‧‧welding wire

276‧‧‧囊封體或模製化合物 276‧‧‧ Encapsulated body or molded compound

278‧‧‧囊封體或模製化合物 278‧‧‧ Encapsulation or molding compound

280‧‧‧球體或凸塊 280‧‧‧ sphere or bump

282‧‧‧半導體封裝 282‧‧‧Semiconductor Package

290‧‧‧半導體晶圓 290‧‧‧semiconductor wafer

292‧‧‧基礎基板材料 292‧‧‧Basic substrate material

294‧‧‧半導體晶粒或組件 294‧‧‧Semiconductor die or component

296‧‧‧切割道 296‧‧‧cut road

300‧‧‧半導體晶圓 300‧‧‧Semiconductor wafer

302‧‧‧基礎基板材料 302‧‧‧Basic substrate material

304‧‧‧半導體晶粒或組件 304‧‧‧Semiconductor die or component

306‧‧‧切割道 306‧‧‧cut road

310‧‧‧背表面或非主動表面 310‧‧‧back surface or inactive surface

312‧‧‧主動表面 312‧‧‧active surface

314‧‧‧導電層 314‧‧‧ conductive layer

316‧‧‧絕緣層或鈍化層 316‧‧‧ Insulating layer or passivation layer

318‧‧‧雷射 318‧‧‧laser

320‧‧‧絕緣層的表面 320‧‧‧ Surface of insulation layer

322‧‧‧鋸片或雷射削切工具 322‧‧‧Saw blade or laser cutting tool

324‧‧‧邊緣、側壁、或是側表面 324‧‧‧Edge, side wall, or side surface

330‧‧‧載體或暫時性基板 330‧‧‧ Carrier or temporary substrate

332‧‧‧介面層或雙面膠帶 332‧‧‧Interface layer or double-sided tape

334‧‧‧介面層的表面 334‧‧‧ Surface of interface layer

336‧‧‧重組式晶圓或重新配置晶圓 336‧‧‧Reassembled wafer or reconfigured wafer

338‧‧‧重組式晶圓或重組式鑲板 338‧‧‧Reassembled wafer or reassembled panel

340‧‧‧處理設備 340‧‧‧treatment equipment

342‧‧‧控制系統 342‧‧‧Control System

344‧‧‧囊封體或模製化合物 344‧‧‧ Encapsulated body or molded compound

345‧‧‧研磨機 345‧‧‧Grinding machine

346‧‧‧背側表面 346‧‧‧ dorsal surface

347‧‧‧平坦的背側表面 347‧‧‧ flat backside surface

348‧‧‧表面 348‧‧‧ surface

349‧‧‧絕緣層或鈍化層 349‧‧‧Insulation layer or passivation layer

350‧‧‧絕緣層或鈍化層 350‧‧‧ Insulating layer or passivation layer

352‧‧‧開口 352‧‧‧ opening

354‧‧‧導電層 354‧‧‧ conductive layer

356‧‧‧絕緣層或鈍化層 356‧‧‧Insulation layer or passivation layer

358‧‧‧開口 358‧‧‧ opening

360‧‧‧導電層 360‧‧‧ conductive layer

362‧‧‧球體或凸塊 362‧‧‧ sphere or bump

366‧‧‧增進互連結構 366‧‧‧Enhance interconnection structure

370‧‧‧鋸片或雷射削切工具 370‧‧‧Saw blade or laser cutting tool

372‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 372‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

380‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 380‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

384‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 384‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

386‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 386‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

388‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 388‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

410‧‧‧絕緣層 410‧‧‧Insulation

412‧‧‧開口 412‧‧‧ opening

414‧‧‧導電層 414‧‧‧ conductive layer

416‧‧‧絕緣層或鈍化層 416‧‧‧Insulation layer or passivation layer

418‧‧‧開口 418‧‧‧ opening

420‧‧‧鋸片或雷射削切工具 420‧‧‧Saw blade or laser cutting tool

422‧‧‧側壁或側表面 422‧‧‧Side or side surface

430‧‧‧載體 430‧‧‧ carrier

432‧‧‧介面層 432‧‧‧Interface layer

436‧‧‧重組式晶圓或鑲板 436‧‧‧ Reassembled wafer or panel

438‧‧‧囊封體或模製化合物 438‧‧‧ Encapsulation or molding compound

440‧‧‧背側表面 440‧‧‧ dorsal surface

442‧‧‧研磨機 442‧‧‧Grinding machine

444‧‧‧平坦的背側表面 444‧‧‧ flat backside surface

448‧‧‧表面 448‧‧‧ surface

460‧‧‧導電層 460‧‧‧ conductive layer

462‧‧‧球體或凸塊 462‧‧‧ sphere or bump

466‧‧‧增進互連結構 466‧‧‧Enhance interconnection structure

470‧‧‧鋸片或雷射削切工具 470‧‧‧Saw blade or laser cutting tool

472‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 472‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

480‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 480‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

482‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 482‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

484‧‧‧背側絕緣層 484‧‧‧Back side insulation

486‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 486‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

488‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 488‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

490‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 490‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

500‧‧‧半導體晶圓 500‧‧‧semiconductor wafer

502‧‧‧基礎基板材料 502‧‧‧Basic substrate material

504‧‧‧半導體晶粒或組件 504‧‧‧Semiconductor die or component

506‧‧‧切割道 506‧‧‧cut road

508‧‧‧背表面或非主動表面 508‧‧‧back surface or inactive surface

510‧‧‧主動表面 510‧‧‧active surface

512‧‧‧導電層 512‧‧‧ conductive layer

514‧‧‧絕緣層或鈍化層 514‧‧‧Insulation layer or passivation layer

516‧‧‧邊緣或側壁 516‧‧‧Edge or side wall

518‧‧‧雷射 518‧‧‧laser

520‧‧‧鋸片或雷射削切工具 520‧‧‧Saw blade or laser cutting tool

522‧‧‧側表面 522‧‧‧side surface

530‧‧‧載體或暫時性基板 530‧‧‧ carrier or temporary substrate

532‧‧‧介面層或雙面膠帶 532‧‧‧Interface layer or double-sided tape

534‧‧‧表面 534‧‧‧ surface

536‧‧‧重組式晶圓或重組式鑲板 536‧‧‧ Reassembled wafer or reassembled panel

550‧‧‧囊封體或模製化合物 550‧‧‧ Encapsulation or molding compound

552‧‧‧背側表面 552‧‧‧ dorsal surface

554‧‧‧表面 554‧‧‧ surface

560‧‧‧導電層 560‧‧‧ conductive layer

562‧‧‧絕緣層或鈍化層 562‧‧‧Insulation layer or passivation layer

564‧‧‧球體或凸塊 564‧‧‧ sphere or bump

566‧‧‧增進互連結構 566‧‧‧Enhance interconnection structure

570‧‧‧鋸片或雷射削切工具 570‧‧‧Saw blade or laser cutting tool

572‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 572‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

580‧‧‧側表面 580‧‧‧side surface

590‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 590‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

592‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 592‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

594‧‧‧導電層 594‧‧‧ conductive layer

596‧‧‧背側絕緣層 596‧‧‧Back side insulation

600‧‧‧半導體晶圓 600‧‧‧ semiconductor wafer

602‧‧‧基礎基板材料 602‧‧‧Basic substrate material

604‧‧‧半導體晶粒或組件 604‧‧‧Semiconductor die or component

606‧‧‧切割道 606‧‧‧cut road

608‧‧‧邊緣或側壁 608‧‧‧Edge or side wall

610‧‧‧背表面或非主動表面 610‧‧‧back surface or inactive surface

612‧‧‧主動表面 612‧‧‧active surface

614‧‧‧導電層 614‧‧‧ conductive layer

616‧‧‧絕緣層或鈍化層 616‧‧‧Insulation layer or passivation layer

618‧‧‧雷射 618‧‧‧laser

620‧‧‧鋸片或雷射削切工具 620‧‧‧Saw blade or laser cutting tool

622‧‧‧側表面 622‧‧‧ side surface

630‧‧‧載體或暫時性基板 630‧‧‧ carrier or temporary substrate

632‧‧‧介面層或雙面膠帶 632‧‧‧Interface layer or double-sided tape

634‧‧‧表面 634‧‧‧ surface

640‧‧‧重組式晶圓或重新配置晶圓 640‧‧‧Reassembled wafer or reconfigured wafer

644‧‧‧囊封體或模製化合物 644‧‧‧ Encapsulated body or molded compound

646‧‧‧背表面 646‧‧‧Back surface

648‧‧‧表面 648‧‧‧ surface

650‧‧‧導電層 650‧‧‧ conductive layer

660‧‧‧絕緣層或鈍化層 660‧‧‧ Insulating layer or passivation layer

662‧‧‧球體或凸塊 662‧‧‧ sphere or bump

664‧‧‧增進互連結構 664‧‧‧Enhance interconnection structure

670‧‧‧鋸片或雷射削切工具 670‧‧‧Saw blade or laser cutting tool

672‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 672‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

674‧‧‧嵌入式晶圓級晶片尺寸封裝(eWLCSP) 674‧‧‧Embedded Wafer Level Chip Scale Package (eWLCSP)

676‧‧‧背側絕緣層 676‧‧‧Backside insulation

圖1所示的係一印刷電路板(PCB)，在其表面裝設著不同類型的封裝；圖2a至2c所示的係被裝設至該PCB的代表性半導體封裝的進一步細節；圖3a至3d所示的係具有藉由切割道分離之複數個半導體晶粒的半導體晶圓；圖4a至4e所示的係沉積一囊封體在一WLCSP中的一半導體晶粒的主動表面的側邊與裸露部分上方的製程；圖5所示的係該半導體晶粒的主動表面的側邊與裸露部分被該囊封體覆蓋的WLCSP；圖6a至6c所示的係具有藉由切割道分離之複數個半導體晶粒的半導體晶圓； 圖7a至7e所示的係沉積一囊封體在一WLCSP中的一半導體晶粒的主動表面的側邊與裸露部分上方的另一製程；圖8所示的係該半導體晶粒的主動表面的側邊與裸露部分被該囊封體覆蓋的WLCSP；圖9a至9h所示的係在一WLCSP中沉積一具有一半導體晶粒的主動表面的側邊與一部分的模製底層填充(Mold UnderFill，MUF)材料的製程；圖10所示的係該半導體晶粒的主動表面的側邊與該部分被該MUF材料覆蓋的WLCSP；圖11所示的係被設置在該半導體晶粒與基板之間的MUF材料；圖12所示的係該半導體晶粒的主動表面的側邊與該部分被該MUF材料覆蓋的半導體封裝；圖13a至13p所示的係形成一重組式或嵌入式晶圓級晶片尺寸封裝(embedded Wafer Level Chip Scale Package，eWLCSP)的製程；圖14所示的係一eWLCSP，其具有一位在該半導體晶粒之側壁上方的囊封體以及一背側保護層；圖15所示的係一eWLCSP，其具有一背側保護層；圖16所示的係一eWLCSP，其具有一位在該半導體晶粒之側壁與背側上方的囊封體；圖17所示的係一eWLCSP，其具有位在該半導體晶粒之背側上方的囊封體；圖18所示的係一eWLCSP，其具有有裸露側壁與背側的半導體晶粒；圖19a至19k所示的係形成一eWLCSP的替代製程； 圖20所示的係一eWLCSP，其具有一位在該半導體晶粒之側壁與背側上方的囊封體；圖21所示的係一eWLCSP，其具有位在該半導體晶粒之背側上方的囊封體；圖22所示的係一eWLCSP，其具有位在該側壁上方的囊封體以及一背側保護層；圖23所示的係另一eWLCSP，其具有位在該側壁上方的囊封體以及一背側保護層；圖24所示的係一eWLCSP，其具有一背側保護層；圖25所示的係一eWLCSP，其具有有裸露側壁與背側的半導體晶粒；圖26a至26k所示的係形成一eWLCSP的製程，其具有位在一半導體晶粒之背側上方的囊封體；圖27所示的係一eWLCSP，其具有有裸露側壁與背側的半導體晶粒；圖28所示的係一eWLCSP，其具有一背側保護層；圖29a至29i所示的係形成一eWLCSP的另一製程，其具有薄側壁囊封；以及圖30所示的係一eWLCSP，其具有一背側保護層以及薄側壁囊封。 Figure 1 shows a printed circuit board (PCB) with different types of packages mounted on its surface; Figures 2a to 2c show further details of a representative semiconductor package mounted on the PCB; Figure 3a The system shown to 3d is a semiconductor wafer having a plurality of semiconductor dies separated by dicing lines; the system shown in FIGS. 4a to 4e deposits a side of the active surface of a semiconductor die in a WLCSP. The process above the edge and the exposed part; Figure 5 shows the side of the active surface of the semiconductor die and the WLCSP where the exposed part is covered by the encapsulation body; the system shown in Figures 6a to 6c has a separation by a cutting line. A semiconductor wafer of a plurality of semiconductor dies; 7a to 7e show another process for depositing an encapsulation body on the side of the active surface of a semiconductor die in a WLCSP and over the exposed part; FIG. 8 shows the active surface of the semiconductor die. The sides and the exposed part of the WLCSP covered by the encapsulant; Figures 9a to 9h show the sides of an active surface with a semiconductor die deposited in a WLCSP and a portion of the mold underfill (Mold UnderFill) , MUF) material; the side of the active surface of the semiconductor die shown in FIG. 10 and the WLCSP covered by the MUF material; the system shown in FIG. 11 is placed between the semiconductor die and the substrate The MUF material shown in FIG. 12 is the side of the active surface of the semiconductor die and the semiconductor package in which the portion is covered by the MUF material. The system shown in FIGS. 13a to 13p forms a reassembled or embedded wafer. Process of embedded Wafer Level Chip Scale Package (eWLCSP); FIG. 14 is an eWLCSP, which has an encapsulation body above the sidewall of the semiconductor die and a backside protective layer; 15 is an eWLCSP, which has A backside protective layer; an eWLCSP shown in FIG. 16 having an encapsulation body above the side wall and the backside of the semiconductor die; an eWLCSP shown in FIG. 17 having an encapsulation located at the semiconductor The encapsulation body above the dorsal side of the die; the system shown in FIG. 18 is an eWLCSP, which has a semiconductor die with exposed sidewalls and the back side; the system shown in FIGS. 19a to 19k forms an alternative process of an eWLCSP; An eWLCSP shown in FIG. 20 has an encapsulation body above the side wall and the back side of the semiconductor die; an eWLCSP shown in FIG. 21 has an encapsulation located above the back side of the semiconductor die Encapsulation body shown in FIG. 22 is an eWLCSP with an encapsulation body located on the side wall and a back side protective layer; FIG. 23 is another eWLCSP with an eWLCSP located above the side wall. Encapsulation body and a backside protective layer; an eWLCSP shown in FIG. 24 having a backside protective layer; an eWLCSP shown in FIG. 25 having a semiconductor die with exposed sidewalls and a backside; The process shown in 26a to 26k forms an eWLCSP process, which has an encapsulation body located above the back side of a semiconductor die; the system shown in FIG. 27 has an eWLCSP, which has a semiconductor wafer with exposed sidewalls and back sides. The system shown in FIG. 28 has an eWLCSP with a backside protective layer; the system shown in FIGS. 29a to 29i forms another eWLCSP with a thin sidewall encapsulation; and the system shown in FIG. 30 eWLCSP, which has a backside protective layer and a thin sidewall encapsulation.

在下面的說明中參考圖式於一或更多個實施例中說明本發明，於該些圖式中，相同的符號代表相同或雷同的元件。雖然本文以達成本發明之目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及 它們的等效範圍所定義的本發明的精神與範疇內可以併入的替代例、修正例、以及等效例。 The invention is explained in one or more embodiments in the following description with reference to the drawings, in which the same symbols represent the same or similar elements. Although the present invention is described in the best mode for achieving the purpose of the present invention, those skilled in the art will understand that the present invention is intended to cover the scope of the accompanying patents, which are supported by the following disclosure and drawings. Alternatives, amendments, and equivalents that can be incorporated within the spirit and scope of the invention as defined by their equivalent ranges.

半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電氣組件和被動式電氣組件，它們會被電氣連接而形成功能性電路。主動式電氣組件(例如電晶體與二極體)能夠控制電流的流動。被動式電氣組件(例如電容器、電感器、以及電阻器)會創造用以實施電路功能所需要的電壓和電流之間的關係。 Semiconductor devices are typically manufactured using two complex processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active electrical components and passive electrical components, which are electrically connected to form a functional circuit. Active electrical components (such as transistors and diodes) can control the flow of current. Passive electrical components (such as capacitors, inductors, and resistors) create the relationship between voltage and current required to perform circuit functions.

被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該些製程步驟包含：摻雜、沉積、光微影術、蝕刻、以及平坦化。摻雜會藉由下面的技術將雜質引入至半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會藉由響應於電場或基極電流來動態改變半導體材料傳導性而修正主動式裝置中半導體材料的導電性。電晶體含有不同類型及不同摻雜程度的多個區域，它們會在必要時被排列成用以在施加電場或基極電流下讓該電晶體提高或限制電流的流動。 Passive components and active components are formed over the surface of the semiconductor wafer through a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into semiconductor materials using techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of semiconductor materials in active devices by dynamically changing the conductivity of semiconductor materials in response to an electric or base current. The transistor contains multiple regions of different types and different doping levels, which are arranged when necessary to allow the transistor to increase or limit the flow of current when an electric or base current is applied.

主動式組件和被動式組件係由具有不同電氣特性的多層材料構成。該些層能夠藉由各式各樣的沉積技術來形成，其部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程、以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件、被動式組件、或是組件之間的電氣連接線的一部分。 Active and passive components are composed of multiple layers of materials with different electrical characteristics. These layers can be formed by a variety of deposition techniques, depending in part on the type of material to be deposited. For example, the thin film deposition may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an electrolyte plating process, and an electrodeless plating process. Each layer is usually patterned to form an active component, a passive component, or part of the electrical connection between the components.

後端製造係指將已完成的晶圓切割或單體化裁切成個別的 晶粒，並且接著封裝該半導體晶粒，以達結構性支撐以及環境隔離的效果。為單體化裁切半導體晶粒，該晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。晶圓會利用雷射切割工具或鋸片來進行單體化裁切。經過單體化裁切之後，個別半導體晶粒便會被裝設至包含接針或接觸墊的封裝基板，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸墊接著會被連接至該封裝裡面的接觸墊。該些電氣連接線可利用焊料凸塊、短柱凸塊、導電膏、或是焊線來製成。一囊封體或是其它模製材料會被沉積在該封裝的上方，用以提供物理性支撐和電氣隔離。接著，已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。 Back-end manufacturing refers to the cutting or singulation of completed wafers into individual Die, and then the semiconductor die is packaged to achieve the effects of structural support and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along a non-functional area called a saw street or scribe in the wafer. The wafer is singulated using laser cutting tools or saw blades. After singulation, individual semiconductor dies are mounted on a package substrate that includes pins or contact pads for interconnection with other system components. The contact pads formed over the semiconductor die are then connected to the contact pads inside the package. The electrical connecting wires can be made of solder bumps, stud bumps, conductive paste, or solder wires. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system and allows other system components to access the functions of the semiconductor device.

圖1圖解電子裝置50，其具有一晶片載體基板或是印刷電路板(Printed Circuit Board，PCB)52，在其表面上裝設著複數個半導體封裝。電子裝置50會具有某一種類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋的目的，圖1中顯示不同類型的半導體封裝。 FIG. 1 illustrates an electronic device 50 having a wafer carrier substrate or a printed circuit board (PCB) 52, and a plurality of semiconductor packages are mounted on its surface. The electronic device 50 may have a certain type of semiconductor package or multiple types of semiconductor packages, depending on the application. For the purpose of explanation, different types of semiconductor packages are shown in FIG. 1.

電子裝置50能夠係單獨型系統，其使用該些半導體封裝來實施一或更多項電氣功能。或者，電子裝置50亦能夠係一較大型系統中的子組件。舉例來說，電子裝置50能夠係蜂巢式電話、個人數位助理(Personal Digital Assistant，PDA)、數位錄像機(Digital Video Camera，DVC)、或是其它電子通信裝置的一部分。或者，電子裝置50能夠係圖形卡、網路介面卡、或是能夠被插入在電腦之中的其它訊號處理卡。該半導體封裝能夠包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、RF電路、離散式裝置、或是其它半導體晶粒 或電氣組件。該些產品要被市場接受，微型化以及減輕重量相當重要。半導體裝置之間的距離必須縮小，以達更高密度的目的。 The electronic device 50 can be a stand-alone system that uses these semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 50 can be a sub-component in a larger system. For example, the electronic device 50 can be a part of a cellular phone, a personal digital assistant (PDA), a digital video camera (DVC), or other electronic communication devices. Alternatively, the electronic device 50 can be a graphics card, a network interface card, or another signal processing card that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, an Application Specific Integrated Circuits (ASIC), a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die. Or electrical components. For these products to be accepted by the market, miniaturization and weight reduction are very important. The distance between semiconductor devices must be reduced to achieve a higher density.

在圖1中，PCB 52提供一通用基板，用以達到結構性支撐以及電氣互連被裝設在該PCB上的半導體封裝的目的。多條導體訊號線路54會利用下面製程被形成在PCB 52的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程。訊號線路54會在該些半導體封裝、被裝設的組件、以及其它外部系統組件中的每一者之間提供電氣通訊。線路54還提供連接至每一個該些半導體封裝的電力連接線及接地連接線。 In FIG. 1, the PCB 52 provides a universal substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. The plurality of conductor signal lines 54 are formed on one surface or multiple layers of the PCB 52 using the following process: an evaporation process, an electrolyte plating process, an electrodeless plating process, a screen printing process, or other suitable metal deposition processes. The signal line 54 provides electrical communication between each of the semiconductor packages, mounted components, and other external system components. The line 54 also provides a power connection line and a ground connection line to each of these semiconductor packages.

於某些實施例中，一半導體裝置有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間載體的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載體附接至該PCB。於其它實施例中，一半導體裝置可以僅有該第一層封裝，其中，該晶粒係以機械方式及電氣方式直接被裝設至該PCB。 In some embodiments, a semiconductor device has two packaging layers. The first layer package is a technology for mechanically and electrically attaching the semiconductor die to an intermediate carrier. The second layer of packaging involves mechanically and electrically attaching the intermediate carrier to the PCB. In other embodiments, a semiconductor device may have only the first layer package, wherein the die is directly and mechanically and electrically mounted on the PCB.

為達解釋的目的，圖中在PCB 52上顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，圖中還顯示被裝設在PCB 52上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載體(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無導線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，被配置成具有第一層封裝樣式和第二層封裝樣式之任何組合的半導體封裝和其它電 子組件所組成的任何組合皆能夠被連接至PCB 52。於某些實施例中，電子裝置50包含單一附接半導體封裝；不過，其它實施例則會需要多個互連封裝。藉由在單一基板上方組合一或更多個半導體封裝，製造商便能夠將事先製造的組件併入電子裝置和系統之中。因為該些半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而降低消費者的成本。 For the purpose of explanation, several types of first-layer packages are shown on the PCB 52 in the figure, including a wire bond package 56 and a flip chip 58. In addition, the figure also shows several types of second-layer packages mounted on the PCB 52, including: Ball Grid Array (BGA) 60; Bump Chip Carrier (BCC) ) 62; Dual In-line Package (DIP) 64; Land Grid Array (LGA) 66; Multi-Chip Module (MCM) 68; Square Flat No-Wire Package ( Quad Flat Non-leaded package (QFN) 70; and square flat package 72. Depending on the system requirements, semiconductor packages and other electrical components that are configured to have any combination of first-level package style and second-level package style Any combination of subassemblies can be connected to PCB 52. In some embodiments, the electronic device 50 includes a single attached semiconductor package; however, other embodiments may require multiple interconnect packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-manufactured components into electronic devices and systems. Because these semiconductor packages contain sophisticated functions, electronic devices can be manufactured using less expensive components and efficient processes. The resulting device is less likely to fail and is cheaper to manufacture, thereby reducing consumer costs.

圖2a至圖2c所示的係示範性半導體封裝。圖2a所示的係被裝設在PCB 52上的DIP 64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該些類比電路或數位電路會被施行為形成在該晶粒裡面的主動式裝置、被動式裝置、導體層、以及介電層，並且會根據該晶粒的電氣設計進行電氣互連。舉例來說，該電路能夠包含被形成在半導體晶粒74之主動區裡面的一或更多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76係由導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或是銀(Ag))所製成的一或更多層，並且被電氣連接至形成在半導體晶粒74裡面的電路元件。在DIP 64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂或是環氧樹脂)被裝設至中間載體78。封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體導線80以及焊線82會在半導體晶粒74與PCB 52之間提供電氣互連。囊封體84會被沉積在該封裝的上方，用以藉由防止濕氣和粒子進入封裝並且防止污染晶粒74或焊線82而達到環境保護的目的。 2a to 2c are exemplary semiconductor packages. Further details of the DIP 64 shown in FIG. 2a are mounted on the PCB 52. The semiconductor die 74 includes an active region including an analog circuit or a digital circuit, and the analog circuit or the digital circuit is applied to an active device, a passive device, a conductor layer, and a dielectric layer formed in the die, and Electrical interconnections are performed according to the electrical design of the die. For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements formed within the active region of the semiconductor die 74. The contact pad 76 is one or more layers made of a conductive material such as aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), or silver (Ag). And is electrically connected to a circuit element formed inside the semiconductor die 74. During the assembly of the DIP 64, the semiconductor die 74 is mounted to the intermediate carrier 78 using a gold-silicon eutectic alloy layer or an adhesive material (such as a thermal epoxy or epoxy). The package body includes an insulating packaging material, such as a polymer or a ceramic. The conductor wires 80 and the bonding wires 82 provide electrical interconnection between the semiconductor die 74 and the PCB 52. The encapsulation body 84 is deposited on the package to protect the environment by preventing moisture and particles from entering the package and preventing contamination of the die 74 or the bonding wire 82.

圖2b所示的係被裝設在PCB 52之上的BCC 62的進一步細節。半導體晶粒88係利用底層填充材料或環氧樹脂膠黏材料92被裝設在載 體90的上方。焊線94會在接觸墊96與98之間提供第一層封裝互連。模製化合物或囊封體100係被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電氣隔離效果。多個接觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在PCB 52的表面上方，用以防止氧化。接觸墊102會被電氣連接至PCB 52中的一或更多條導體訊號線路54。多個凸塊104會被形成在BCC 62的接觸墊98和PCB 52的接觸墊102之間。 Further details of the BCC 62 shown on Fig. 2b are mounted on the PCB 52. The semiconductor die 88 is mounted on the substrate using an underfill material or an epoxy adhesive material 92 Above the body 90. The bonding wire 94 provides a first-level package interconnection between the contact pads 96 and 98. The molding compound or encapsulation body 100 is deposited over the semiconductor die 88 and the bonding wire 94 to provide physical support and electrical isolation for the device. The plurality of contact pads 102 are formed over the surface of the PCB 52 using a suitable metal deposition process (such as electrolytic plating or electrodeless plating) to prevent oxidation. The contact pads 102 are electrically connected to one or more conductor signal lines 54 in the PCB 52. A plurality of bumps 104 are formed between the contact pads 98 of the BCC 62 and the contact pads 102 of the PCB 52.

在圖2c中，半導體晶粒58會利用覆晶樣式的第一層封裝以面朝下的方式被裝設至中間載體106。半導體晶粒58的主動區108含有類比電路或數位電路，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路能夠包含在主動區108裡面的一或更多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載體106。 In FIG. 2 c, the semiconductor die 58 is mounted on the intermediate carrier 106 in a face-down manner using a flip-chip-type first-layer package. The active region 108 of the semiconductor die 58 contains analog circuits or digital circuits that are applied to active devices, passive devices, conductor layers, and dielectric layers formed according to the electrical design of the die. . For example, the circuit can include one or more transistors, diodes, inductors, capacitors, resistors, and other circuit elements within the active region 108. The semiconductor die 58 is electrically and mechanically connected to the carrier 106 via the plurality of bumps 110.

BGA 60會以利用多個凸塊112的BGA樣式第二層封裝，以電氣方式及機械方式被連接至PCB 52。半導體晶粒58會經由凸塊110、訊號線114、以及凸塊112被電氣連接至PCB 52中的導體訊號線路54。一模製化合物或囊封體116會被沉積在半導體晶粒58和載體106的上方，用以為該裝置提供物理性支撐以及電氣隔離效果。該覆晶半導體裝置會從半導體晶粒58上的主動式裝置至PCB 52上的傳導軌提供一條短電傳導路徑，以便縮短訊號傳播距離、降低電容、並且改良整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方 式直接被連接至PCB 52，而沒有中間載體106。 The BGA 60 will be electrically and mechanically connected to the PCB 52 in a BGA-style second-layer package utilizing a plurality of bumps 112. The semiconductor die 58 is electrically connected to the conductor signal line 54 in the PCB 52 via the bump 110, the signal line 114, and the bump 112. A molding compound or encapsulant 116 is deposited over the semiconductor die 58 and the carrier 106 to provide physical support and electrical isolation for the device. The flip-chip semiconductor device will provide a short electrical conduction path from the active device on the semiconductor die 58 to the conductive track on the PCB 52 in order to shorten the signal propagation distance, reduce capacitance, and improve overall circuit performance. In another embodiment, the semiconductor die 58 is mechanically and electrically using a flip-chip-type first-layer package. Is directly connected to the PCB 52 without the intermediate carrier 106.

圖3a所示的係半導體晶圓120，其具有基礎基板材料122(例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽)用以達到結構性支撐的目的。複數個半導體晶粒或組件124會被形成在晶圓120上，藉由如上面所述之非主動的晶粒間晶圓區域或切割道126來分離。切割道126提供削切區，以便將半導體晶圓120單體化裁切成個別的半導體晶粒124。於其中一實施例中，半導體晶圓120的直徑為200至300毫米(mm)。於另一實施例中，半導體晶圓120的直徑為100至450mm。在將半導體晶圓單體化裁切成個別的半導體晶粒124之前，半導體晶圓120可以有任何直徑。 The semiconductor wafer 120 shown in FIG. 3a has a base substrate material 122 (for example, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide) for structural support. A plurality of semiconductor dies or components 124 are formed on the wafer 120 and separated by inactive inter-die wafer regions or scribe lines 126 as described above. The dicing track 126 provides a cutting area for singulating the semiconductor wafer 120 into individual semiconductor dies 124. In one embodiment, the diameter of the semiconductor wafer 120 is 200 to 300 millimeters (mm). In another embodiment, the diameter of the semiconductor wafer 120 is 100 to 450 mm. Prior to singulating the semiconductor wafer into individual semiconductor dies 124, the semiconductor wafer 120 may have any diameter.

圖3b所示的係半導體晶圓120的一部分的剖視圖。每一個半導體晶粒124皆有一背表面或非主動表面128以及含有類比電路或數位電路的主動表面130，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面130裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒124可以還含有用於RF訊號處理的積體被動式裝置(Integrated Passive Device，IPD)，例如，電感器、電容器、以及電阻器。 A cross-sectional view of a portion of the semiconductor wafer 120 shown in FIG. 3b. Each semiconductor die 124 has a back surface or an inactive surface 128 and an active surface 130 containing analog circuits or digital circuits. These analog circuits or digital circuits are formed according to the electrical design and function of the die. Active devices, passive devices, conductor layers, and dielectric layers within and within the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in the active surface 130 to implement an analog circuit or a digital circuit, such as a digital signal processor (Digital Signal Processor) Signal Processor (DSP), ASIC, memory, or other signal processing circuits. The semiconductor die 124 may further include an integrated passive device (IPD) for RF signal processing, such as an inductor, a capacitor, and a resistor.

一導電層132會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面130的上方。導體層132能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或 是其它合宜的導電材料。導體層132的操作如同被電氣連接至主動表面130上之電路的接觸墊。導體層132會被形成為多個接觸墊，它們以並排的方式被設置在和半導體晶粒124的邊緣相隔第一距離處，如圖3b之中所示。或者，導體層132會被形成為偏移在多列之中的多個接觸墊，俾使得第一列接觸墊會被設置在和該晶粒的邊緣相隔第一距離處，而與該第一列交錯的第二列接觸墊則被設置在和該晶粒的邊緣相隔第二距離處。 A conductive layer 132 is formed over the active surface 130 using a PVD, CVD, electrolyte plating, electrodeless plating process, or other suitable metal deposition process. The conductor layer 132 can be made of one or more layers made of: Al, Cu, Sn, Ni, Au, Ag, or Is other suitable conductive materials. The conductor layer 132 operates like a contact pad that is electrically connected to a circuit on the active surface 130. The conductive layer 132 is formed as a plurality of contact pads, which are arranged side by side at a first distance from the edge of the semiconductor die 124, as shown in FIG. 3b. Alternatively, the conductive layer 132 may be formed as a plurality of contact pads offset in a plurality of rows, so that the first row of contact pads are disposed at a first distance from the edge of the die, and from the first The staggered second row of contact pads are disposed at a second distance from the edge of the die.

一第一絕緣層或鈍化層134係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在半導體晶粒124和導體層132的上方。絕緣層134含有由下面所製成的一或更多層：二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、三氧化二鋁(Al2O3)、二氧化鉿(HfO2)、環苯丁烯(BCB)、聚亞醯胺(PI)、聚苯并噁唑纖維(PBO)、聚合物、或是具有雷同結構特性及絕緣特性的其它介電材料。 A first insulating layer or passivation layer 134 is formed over the semiconductor die 124 and the conductor layer 132 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 134 contains one or more layers made of: silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), and aluminum trioxide ( Al2O3), hafnium dioxide (HfO2), cyclic styrene butadiene (BCB), polyimide (PI), polybenzoxazole fiber (PBO), polymer, or other materials with similar structural and insulation Dielectric material.

一導電層或重新分佈層(ReDistribution Layer，RDL)136會使用諸如濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程被形成在該第一絕緣層134的上方。導體層136能夠為由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。一部分的導體層136會被電氣連接至半導體晶粒124的導體層132。其它部分的導體層136則能夠相依於半導體晶粒124的設計與功能而為共電或是被電氣隔離。 A conductive layer or a redistribution layer (RDL) 136 is formed over the first insulating layer 134 using a patterning and metal deposition process such as sputtering, electrolyte plating, and electrodeless plating. The conductive layer 136 can be one or more layers made of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. A portion of the conductor layer 136 is electrically connected to the conductor layer 132 of the semiconductor die 124. The other conductive layers 136 can be electrically common or electrically isolated depending on the design and function of the semiconductor die 124.

一第二絕緣層或鈍化層134會被形成在導體層136以及第一絕緣層134的上方。多個絕緣層134與導體層136會被形成在半導體晶粒124的主動表面130的上方。表面檢查會被實施，用以偵測鈍化或RDL缺陷。 A second insulating layer or passivation layer 134 is formed on the conductive layer 136 and the first insulating layer 134. A plurality of insulating layers 134 and conductor layers 136 are formed above the active surface 130 of the semiconductor die 124. Surface inspections are performed to detect passivation or RDL defects.

一部分的絕緣層134會利用雷射138藉由雷射直接燒蝕(Laser Direction Ablation，LDA)被移除，用以露出導體層132以及沿著半導體晶粒124的表面邊緣的主動表面130的一部分140。也就是，沿著半導體晶粒124的表面邊緣的主動表面130的一部分140沒有絕緣層134。或者，一部分的絕緣層134會藉由蝕刻製程貫穿一已圖樣化光阻層而被移除，用以露出導體層132以及沿著半導體晶粒124的表面邊緣的主動表面130的一部分140。 A portion of the insulating layer 134 is removed by laser direct ablation (Laser Direction Ablation (LDA)) using laser 138 to expose the conductive layer 132 and a portion of the active surface 130 along the surface edge of the semiconductor die 124. 140. That is, a portion 140 of the active surface 130 along the surface edge of the semiconductor die 124 has no insulating layer 134. Alternatively, a portion of the insulating layer 134 is removed through an patterned photoresist layer by an etching process to expose the conductive layer 132 and a portion 140 of the active surface 130 along the surface edge of the semiconductor die 124.

在圖3c中，一導電層142會在最終重新鈍化之後利用PVD、CVD、蒸發、電解質電鍍、無電極電鍍、或是其它合宜的金屬沉積製程被形成在導體層132與絕緣層134的裸露部分的上方。導體層142能夠為Al、Cu、Sn、Ni、Au、Ag、鎢(W)、或是其它合宜的導電材料。導體層142係一凸塊下層金屬(Under Bump Metallization，UBM)，其被電氣連接至導體層132。UBM 142能夠係一具有黏著層、屏障層、以及晶種層或潤濕層的多金屬堆疊。黏著層係被形成在導體層132的上方並且能夠為鈦(Ti)、氮化鈦(TiN)、鎢化鈦(TiW)、Al、或是鉻(Cr)。屏障層係被形成在黏著層的上方並且能夠為Ni、NiV、鉑(Pt)、鈀(Pd)、TiW、Ti、或是銅化鉻(CrCu)。該屏障層會阻止Cu擴散至該晶粒的主動區之中。晶種層係被形成在屏障層的上方並且能夠為Cu、Ni、NiV、Au、或是Al。UBM 142為導體層132提供一低阻值互連線，並且提供一屏障阻止焊料擴散，以及提供用於焊料潤濕的晶種層。 In FIG. 3c, a conductive layer 142 is formed on the exposed portions of the conductive layer 132 and the insulating layer 134 by PVD, CVD, evaporation, electrolyte plating, electrodeless plating, or other suitable metal deposition processes after final re-passivation. Above. The conductive layer 142 can be Al, Cu, Sn, Ni, Au, Ag, tungsten (W), or other suitable conductive materials. The conductor layer 142 is an under bump metallization (UBM), which is electrically connected to the conductor layer 132. UBM 142 can be a multi-metal stack with an adhesion layer, a barrier layer, and a seed layer or a wetting layer. The adhesive layer system is formed above the conductor layer 132 and can be titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer is formed over the adhesive layer and can be Ni, NiV, platinum (Pt), palladium (Pd), TiW, Ti, or chromium copper (CrCu). The barrier layer prevents Cu from diffusing into the active area of the grain. The seed layer system is formed over the barrier layer and can be Cu, Ni, NiV, Au, or Al. The UBM 142 provides a low-resistance interconnection for the conductor layer 132, and provides a barrier to prevent solder diffusion, and a seed layer for solder wetting.

半導體晶圓120會進行電氣測試與檢查，作為品質控制過程的一部分。手動視覺檢查及自動光學系統會被用來在半導體晶圓120上實 施檢查。軟體會被使用在半導體晶圓120的自動光學分析中。視覺檢查方法可以運用諸如掃描電子顯微鏡、高強度光或紫外光、或是冶金顯微鏡的設備。半導體晶圓120的結構性特徵會被檢查，其包含：翹曲、厚度變異、表面微粒、不規則性、裂痕、脫層、以及變色。 The semiconductor wafer 120 is electrically tested and inspected as part of the quality control process. Manual visual inspection and automatic optical system will be used to implement the semiconductor wafer 120 Implement inspection. The software is used in the automatic optical analysis of the semiconductor wafer 120. The visual inspection method may use equipment such as a scanning electron microscope, high-intensity light or ultraviolet light, or a metallurgical microscope. Structural features of the semiconductor wafer 120 are inspected, including: warpage, thickness variation, surface particles, irregularities, cracks, delamination, and discoloration.

半導體晶粒124裡面的主動式組件和被動式組件會在晶圓級進行電氣效能與電路功能的測試。每一個半導體晶粒124係利用一探針或是其它測試裝置來測試功能與電氣參數。探針係被用來電氣接觸每一個半導體晶粒124上的節點或接觸墊132並且提供電氣刺激給該些接觸墊。半導體晶粒124會回應該些電氣刺激，該回應會被測量並且和預期的回應作比較，以便測試該半導體晶粒的功能。該些電氣測試可以包含電路功能、導線完整性、電阻係數、連續性、可靠度、接面深度、靜電放電(Electro-Static Disharge，ESD)、射頻(Radio Frequency，RF)效能、驅動電流、臨界電流、漏電流、以及該組件類型特有的操作參數。半導體晶圓120的檢查與電氣測試可讓通過測試而被指定為已知良品晶粒(Known Good Die，KGD)的半導體晶粒124使用於半導體封裝中。 Active components and passive components in the semiconductor die 124 are tested for electrical performance and circuit functions at the wafer level. Each semiconductor die 124 uses a probe or other testing device to test the functional and electrical parameters. The probe system is used to electrically contact a node or contact pad 132 on each semiconductor die 124 and provide electrical stimulus to the contact pads. The semiconductor die 124 will respond to some electrical stimulus, and the response will be measured and compared with the expected response to test the function of the semiconductor die. These electrical tests can include circuit function, lead integrity, resistivity, continuity, reliability, junction depth, Electro-Static Disharge (ESD), radio frequency (RF) performance, drive current, criticality Current, leakage current, and operating parameters specific to this component type. The inspection and electrical test of the semiconductor wafer 120 may allow the semiconductor die 124 designated as a Known Good Die (KGD) to pass through the test to be used in a semiconductor package.

在圖3d中，半導體晶圓120會利用鋸片或雷射削切工具144被單體化裁切貫穿切割道126成為個別的半導體晶粒124。個別的半導體晶粒124皆會被檢查與電氣測試，以便找出單體化裁切後的KGD。 In FIG. 3d, the semiconductor wafer 120 is singulated and cut through the scribe line 126 into individual semiconductor dies 124 using a saw blade or a laser cutting tool 144. Individual semiconductor dies 124 are inspected and electrically tested to find the KGD after singulation cutting.

圖4a至4e配合圖1以及2a至2c圖解沉積一囊封體在一WLCSP中的一半導體晶粒的主動表面的側邊與裸露部分上方的製程。圖4a所示的係一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板 150的一部分的剖視圖。一介面層或雙面膠帶152會被形成在載體150的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。 FIGS. 4 a to 4 e in conjunction with FIGS. 1 and 2 a to 2 c illustrate a process of depositing an encapsulation body on a side of an active surface of a semiconductor die in a WLCSP and over a bare portion. Figure 4a shows a carrier or temporary substrate containing a sacrificial base material (e.g., silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support purposes). A sectional view of a portion of 150. An interface layer or a double-sided tape 152 is formed on the carrier 150 as a temporary adhesive solder film, an etch stop layer, or a thermal release layer.

載體150能夠為一可容納多個半導體晶粒124的圓形或矩形鑲板。載體150的表面積可以大於半導體晶圓120的表面積。較大的載體會降低半導體封裝的製造成本，因為有較多的半導體晶粒能夠在該較大載體上被處理，從而降低每個單元的成本。半導體封裝與處理設備會針對正在被處理的晶圓或載體的大小來設計與配置。 The carrier 150 can be a circular or rectangular panel that can accommodate a plurality of semiconductor dies 124. The surface area of the carrier 150 may be larger than the surface area of the semiconductor wafer 120. A larger carrier reduces the manufacturing cost of a semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or carrier being processed.

為進一步降低製造成本，載體150的大小不相依於半導體晶粒124的大小或是半導體晶圓120的大小來選擇。也就是，載體150具有固定或是標準化大小，其能夠容納從一或更多個半導體晶圓120處單體化裁切出來的各種大小半導體晶粒124。於其中一實施例中，載體150為直徑330mm的圓形。於另一實施例中，載體150為寬度560mm以及長度600mm的矩形。半導體晶粒124可以有10mm乘10mm的面積，它們係被放置在標準化載體150上。或者，半導體晶粒124可以有20mm乘20mm的面積，它們被放置在相同的標準化載體150上。據此，標準化載體150能夠應付任何大小的半導體晶粒124，其允許後續的半導體處理設備針對共同的載體被標準化，也就是，不相依於晶粒大小或是進料晶圓大小。半導體封裝設備能夠針對一標準晶圓來設計與配置，該半導體封裝設備能夠被用於處理來自任何進料晶圓大小的任何半導體晶粒大小。具有固定大小與形狀的載體150允許利用一組共同的處理工具、設備、以及材料來處理來自不同大小半導體晶圓120的不同大小半導體晶粒124。舉例來說，來自200mm半導體晶圓的10mm乘10mm半導體晶粒124或是來自450mm半導體晶圓的20mm 乘20mm半導體晶粒124能夠利用相同的設備與材料清單在載體150上被處理。該共同或標準化載體150藉由減少或消弭以晶粒大小或進料晶圓大小為基礎的特殊化半導體處理線的需求而降低製造成本。該標準化載體大小降低資本風險，因為即使半導體晶圓大小改變，處理設備仍然維持不變。藉由選擇預設的載體大小用在來自所有半導體晶圓的任何大小半導體晶粒便能夠施行靈活的製造線。 In order to further reduce the manufacturing cost, the size of the carrier 150 is selected independently of the size of the semiconductor die 124 or the size of the semiconductor wafer 120. That is, the carrier 150 has a fixed or standardized size, which is capable of accommodating semiconductor chips 124 of various sizes cut out from one or more semiconductor wafers 120 singulated. In one embodiment, the carrier 150 has a circular shape with a diameter of 330 mm. In another embodiment, the carrier 150 is a rectangle with a width of 560 mm and a length of 600 mm. The semiconductor die 124 may have an area of 10 mm by 10 mm, and they are placed on a standardized carrier 150. Alternatively, the semiconductor die 124 may have an area of 20 mm by 20 mm, and they are placed on the same standardized carrier 150. Accordingly, the standardized carrier 150 can cope with semiconductor dies 124 of any size, which allows subsequent semiconductor processing equipment to be standardized for a common carrier, that is, independent of the die size or the size of the incoming wafer. Semiconductor packaging equipment can be designed and configured for a standard wafer. The semiconductor packaging equipment can be used to process any semiconductor die size from any incoming wafer size. The carrier 150 having a fixed size and shape allows different sets of semiconductor dies 124 from different sized semiconductor wafers 120 to be processed using a common set of processing tools, equipment, and materials. For example, a 10mm by 10mm semiconductor die 124 from a 200mm semiconductor wafer or a 20mm from a 450mm semiconductor wafer The 20mm semiconductor die 124 can be processed on the carrier 150 using the same equipment and bill of materials. The common or standardized carrier 150 reduces manufacturing costs by reducing or eliminating the need for specialized semiconductor processing lines based on die size or feed wafer size. This standardized carrier size reduces capital risk because the processing equipment remains the same even if the semiconductor wafer size changes. Flexible manufacturing lines can be implemented by selecting a preset carrier size for use with any size semiconductor die from all semiconductor wafers.

圖3d中的半導體晶粒124被裝設至載體150與介面層152，舉例來說，利用拾放操作，絕緣層134則被定位朝向該載體。圖4b顯示多個半導體晶粒124被裝設至載體150的介面層152，成為重組式晶圓或重新配置晶圓153。半導體晶粒124的主動表面130藉由接觸該介面層的絕緣層134及/或導體層142的特性而被固持離開或偏離介面層152，也就是，在主動表面130的一部分140與介面層152之間有一間隙。 The semiconductor die 124 in FIG. 3d is mounted on the carrier 150 and the interface layer 152. For example, using a pick-and-place operation, the insulating layer 134 is positioned toward the carrier. FIG. 4 b shows that a plurality of semiconductor dies 124 are mounted on the interface layer 152 of the carrier 150 and become reassembled wafers or reconfigured wafers 153. The active surface 130 of the semiconductor die 124 is held away from or deviates from the interface layer 152 by contacting the characteristics of the insulating layer 134 and / or the conductor layer 142 of the interface layer, that is, a portion 140 of the active surface 130 and the interface layer 152 There is a gap between them.

重組式晶圓或重組式鑲板153能夠被處理成許多類型的半導體封裝，其包含扇入晶圓級晶片尺寸封裝(WLCSP)、重組式或嵌入式晶圓級晶片尺寸封裝(embedded Wafer Level Chip Scale Package，eWLCSP)、扇出WLCSP、覆晶封裝、三維(Three Dimensional，3D)封裝(例如，封裝上封裝(Package-on-Package，PoP))、或是其它半導體封裝。重組式鑲板153會根據所生成的半導體封裝的規格來配置。於其中一實施例中，多個半導體晶粒124以高密度排列方式被放置在載體150上，也就是，分隔300微米(μm)或更小，以便處理扇入裝置。於另一實施例中，半導體晶粒124在載體150上分開50μm的距離。載體150上的半導體晶粒124之間的距離會被最佳化，以便以最低的單元成本來製造半導體封裝。較大的載體150表面積會 容納較多的半導體晶粒124並且降低製造成本，因為每個重組式鑲板153中可處理較多的半導體晶粒124。被裝設至載體150的半導體晶粒124的數量能夠大於、小於、或是等於從半導體晶圓120處單體化裁切出來的半導體晶粒124的數量。載體150與重組式鑲板153提供利用來自不同大小半導體晶圓120的不同大小半導體晶粒124來製造許多不同類型半導體封裝的靈活性。 Reassembled wafers or reassembled panels 153 can be processed into many types of semiconductor packages, including fan-in wafer-level wafer-scale package (WLCSP), reassembled or embedded wafer-level wafer-scale package Scale Package (eWLCSP), fan-out WLCSP, flip-chip package, Three Dimensional (3D) package (for example, Package-on-Package (PoP)), or other semiconductor packages. The recombination panel 153 is configured according to the specifications of the generated semiconductor package. In one embodiment, the plurality of semiconductor dies 124 are placed on the carrier 150 in a high-density arrangement, that is, separated by 300 micrometers (μm) or less to process the fan-in device. In another embodiment, the semiconductor dies 124 are separated by a distance of 50 μm on the carrier 150. The distance between the semiconductor dies 124 on the carrier 150 is optimized to manufacture a semiconductor package with the lowest unit cost. Larger 150 surface area of the carrier will More semiconductor dies 124 are accommodated and manufacturing costs are reduced because more semiconductor dies 124 can be processed in each reassembled panel 153. The number of semiconductor dies 124 mounted on the carrier 150 can be greater than, less than, or equal to the number of semiconductor dies 124 cut from the semiconductor wafer 120 by singulation. The carrier 150 and the recombination panel 153 provide the flexibility to fabricate many different types of semiconductor packages using different sized semiconductor dies 124 from different sized semiconductor wafers 120.

在圖4c中，一囊封體或模製化合物154會利用焊膏印刷(paste printing)塗敷機、壓縮模製(compressive molding)塗敷機、轉印模製(transfer molding)塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124以及載體150的上方。囊封體154能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體154係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。明確地說，囊封體154被設置在半導體晶粒124的側邊中以及主動表面130與介面層152之間的間隙中，並且因而覆蓋半導體晶粒124的側邊以及沿著該半導體晶粒的表面邊緣的主動表面130的裸露部分140上至絕緣層134。據此，囊封體154會覆蓋或接觸半導體晶粒124的至少五個表面，也就是，該半導體晶粒的四個側表面以及主動表面130的一部分140。 In FIG. 4c, an encapsulation body or a molding compound 154 uses a paste printing coater, a compression molding coater, a transfer molding coater, A liquid encapsulated body mold coater, vacuum stack coater, spin coater, or other suitable coater is deposited over the semiconductor die 124 and the carrier 150. The encapsulation body 154 can be a polymer synthetic material, for example, an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulation body 154 is non-conducting and provides environmental protection for the semiconductor device, and is protected from external elements and pollutants. Specifically, the encapsulation body 154 is disposed in the sides of the semiconductor die 124 and in the gap between the active surface 130 and the interface layer 152, and thus covers the sides of the semiconductor die 124 and along the semiconductor die 124. The exposed portion 140 of the active surface 130 on the surface edge is up to the insulating layer 134. Accordingly, the encapsulation body 154 covers or contacts at least five surfaces of the semiconductor die 124, that is, four side surfaces of the semiconductor die and a portion 140 of the active surface 130.

在圖4d中，載體150和介面層152會藉由化學蝕刻、機械性剝除、化學機械性平坦化(Chemical Mechanical Planarization，CMP)、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，以便露出絕緣層134以及導體層142。一部分的囊封體154會利用雷射156藉由LDA被移 除。或者，一部分的囊封體154會藉由蝕刻製程貫穿一已圖樣化光阻層而被移除。沿著半導體晶粒124的表面邊緣的主動表面130的一部分140以及該半導體晶粒的側邊仍被囊封體154覆蓋成為一保護性鑲板用以提高產量，尤其是當表面裝設該半導體晶粒時。囊封體154還保護半導體晶粒124，避免因曝露於光中而受損。半導體晶粒124會以下面一或更多道步驟來清洗絕緣層134與導體層142而準備進行電氣測試：電漿清洗、濕式溶劑清洗、銅氧化物清洗、或是乾式清洗。 In FIG. 4d, the carrier 150 and the interface layer 152 are subjected to chemical etching, mechanical peeling, chemical mechanical planarization (CMP), mechanical polishing, thermal baking, UV light, laser scanning, Alternatively, the wet removal is removed to expose the insulating layer 134 and the conductive layer 142. A part of the encapsulation body 154 will be moved by LDA using laser 156 except. Alternatively, a part of the encapsulation body 154 may be removed through an patterned photoresist layer by an etching process. A portion 140 of the active surface 130 along the surface edge of the semiconductor die 124 and the sides of the semiconductor die are still covered by the encapsulant 154 to form a protective panel to increase yield, especially when the semiconductor is mounted on the surface Grains. The encapsulation body 154 also protects the semiconductor die 124 from being damaged by exposure to light. The semiconductor die 124 is cleaned by one or more of the following steps to prepare for the electrical test: plasma cleaning, wet solvent cleaning, copper oxide cleaning, or dry cleaning.

在圖4e中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層142的上方。於其中一實施例中，該凸塊材料係利用一丸滴模板來沉積，也就是，不需要用到任何遮罩。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、鉛(Pb)、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層142。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊160。於某些應用中，凸塊160會被二次回焊，以便改良和導體層142的電氣接觸效果。凸塊160亦能夠被壓縮焊接或熱壓縮焊接至導體層142。凸塊160代表能夠被形成在導體層142上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。雷射標記能夠在凸塊成形之前或之後或是在移除載體150之後被實施。 In FIG. 4e, a conductive bump material is deposited on the conductive layer 142 by using an evaporation process, an electrolytic plating process, an electrodeless plating process, a shot process, or a screen printing process. In one embodiment, the bump material is deposited using a drop template, that is, no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), Bi, Cu, solder, and combinations thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high-lead solder, or a lead-free solder. The bump material is soldered to the conductor layer 142 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 160. In some applications, the bump 160 is re-soldered in order to improve the electrical contact with the conductive layer 142. The bump 160 can also be compression welded or thermally compressed to the conductor layer 142. The bump 160 represents one of the types of interconnect structures that can be formed over the conductor layer 142. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines. Laser marking can be implemented before or after bump formation or after removal of the carrier 150.

半導體晶粒124會利用鋸片或雷射削切工具162被單體化裁切貫穿囊封體154成為個別的嵌入式WLCSP 164。圖5所示的係在單體化 裁切之後的WLCSP 164。於其中一實施例中，WLCSP 164的維度為3.0毫米(mm)x2.6mmx0.7mm，節距為0.4mm。半導體晶粒124被電氣連接至凸塊160，以便達到外部互連的目的。囊封體154覆蓋半導體晶粒124的側邊以及主動表面130的一部分140，用以保護該半導體晶粒的該些側邊與表面邊緣並且提高製造產量，尤其是當表面裝設該半導體晶粒時。囊封體154還保護半導體晶粒124，避免因曝露於光中而受損。WLCSP 164會在單體化裁切之前或之後進行電氣測試。 The semiconductor die 124 is singulated and cut through the encapsulation body 154 into individual embedded WLCSP 164 using a saw blade or a laser cutting tool 162. The system shown in Figure 5 is singularized WLCSP 164 after cropping. In one embodiment, the dimensions of the WLCSP 164 are 3.0 millimeters (mm) x 2.6 mm x 0.7 mm, and the pitch is 0.4 mm. The semiconductor die 124 is electrically connected to the bump 160 in order to achieve the purpose of external interconnection. The encapsulation body 154 covers the sides of the semiconductor die 124 and a portion 140 of the active surface 130 to protect the sides and surface edges of the semiconductor die and improve manufacturing yield, especially when the semiconductor die is mounted on the surface Time. The encapsulation body 154 also protects the semiconductor die 124 from being damaged by exposure to light. WLCSP 164 undergoes electrical testing before or after singulation cutting.

圖6a至6c所示的係半導體晶圓170的另一實施例，其具有基礎基板材料172(例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽)用以達到結構性支撐的目的，雷同於圖3a。複數個半導體晶粒或組件174會被形成在晶圓170上，藉由如上面所述之非主動的晶粒間晶圓區域或切割道176來分離。切割道176提供削切區，以便將半導體晶圓170單體化裁切成個別的半導體晶粒174。於其中一實施例中，半導體晶圓170的直徑為200至300mm。於另一實施例中，半導體晶圓170的直徑為100至450mm。在將半導體晶圓單體化裁切成個別的半導體晶粒174之前，半導體晶圓170可以有任何直徑。 Another embodiment of the semiconductor wafer 170 shown in FIGS. 6a to 6c has a base substrate material 172 (for example, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide) for structural support. The purpose is the same as in Figure 3a. A plurality of semiconductor dies or components 174 are formed on the wafer 170 and separated by inactive inter-die wafer regions or scribe lines 176 as described above. The dicing track 176 provides a cutting area for singulating the semiconductor wafer 170 into individual semiconductor dies 174. In one embodiment, the diameter of the semiconductor wafer 170 is 200 to 300 mm. In another embodiment, the diameter of the semiconductor wafer 170 is 100 to 450 mm. Prior to singulating the semiconductor wafer into individual semiconductor dies 174, the semiconductor wafer 170 may have any diameter.

圖6a所示的係半導體晶圓170的一部分的剖視圖。每一個半導體晶粒174皆有一背表面或非主動表面178以及含有類比電路或數位電路的主動表面180，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面180裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電 路或數位電路，例如，DSP、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒174可以還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。 A cross-sectional view of a portion of a series semiconductor wafer 170 shown in FIG. 6a. Each semiconductor die 174 has a back surface or an inactive surface 178 and an active surface 180 containing an analog circuit or a digital circuit. These analog circuits or digital circuits are formed according to the electrical design and function of the die. Active devices, passive devices, conductor layers, and dielectric layers within and within the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in the active surface 180 for performing analog power. Circuit or digital circuit, such as DSP, ASIC, memory, or other signal processing circuits. The semiconductor die 174 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

一導電層182會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面180的上方。導體層182能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層182的操作如同被電氣連接至主動表面180上之電路的接觸墊。導體層182會被形成為多個接觸墊，它們以並排的方式被設置在和半導體晶粒174的邊緣相隔第一距離處，如圖6a之中所示。或者，導體層182會被形成為偏移在多列之中的多個接觸墊，俾使得第一列接觸墊會被設置在和該晶粒的邊緣相隔第一距離處，而與該第一列交錯的第二列接觸墊則被設置在和該晶粒的邊緣相隔第二距離處。 A conductive layer 182 is formed over the active surface 180 using a PVD, CVD, electrolyte plating, electrodeless plating process, or other suitable metal deposition process. The conductive layer 182 can be made of one or more layers made of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductor layer 182 operates like a contact pad that is electrically connected to a circuit on the active surface 180. The conductive layer 182 is formed as a plurality of contact pads, which are disposed side by side at a first distance from the edge of the semiconductor die 174, as shown in FIG. 6a. Alternatively, the conductive layer 182 may be formed as a plurality of contact pads offset in a plurality of rows, so that the first row of contact pads may be disposed at a first distance from the edge of the die, and from the first The staggered second row of contact pads are disposed at a second distance from the edge of the die.

一導電層184會利用PVD、CVD、蒸發、電解質電鍍、無電極電鍍、或是其它合宜的金屬沉積製程被形成在導體層182的上方。導體層184能夠為Al、Cu、Sn、Ni、Au、Ag、W、或是其它合宜的導電材料。導體層184係一UBM，其被電氣連接至導體層182。UBM 184能夠係一具有黏著層、屏障層、以及晶種層或潤濕層的多金屬堆疊。黏著層係被形成在導體層182的上方並且能夠為Ti、TiN、TiW、Al、或是Cr。屏障層係被形成在黏著層的上方並且能夠為Ni、NiV、Pt、Pd、TiW、Ti、或是CrCu。該屏障層會阻止Cu擴散至該晶粒的主動區之中。晶種層係被形成在屏障層的上方並且能夠為Cu、Ni、NiV、Au、或是Al。UBM 184為導體層182提供一低阻值互連線，並且提供一屏障阻止焊料擴散，以及提供用於焊料潤 濕的晶種層。 A conductive layer 184 is formed on the conductive layer 182 by PVD, CVD, evaporation, electrolyte plating, electrodeless plating, or other suitable metal deposition processes. The conductive layer 184 can be Al, Cu, Sn, Ni, Au, Ag, W, or other suitable conductive materials. The conductor layer 184 is a UBM, which is electrically connected to the conductor layer 182. UBM 184 can be a multi-metal stack with an adhesion layer, a barrier layer, and a seed or wetting layer. The adhesive layer system is formed above the conductor layer 182 and can be Ti, TiN, TiW, Al, or Cr. The barrier layer is formed above the adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti, or CrCu. The barrier layer prevents Cu from diffusing into the active area of the grain. The seed layer system is formed over the barrier layer and can be Cu, Ni, NiV, Au, or Al. UBM 184 provides a low-resistance interconnect for conductor layer 182, and provides a barrier to prevent solder diffusion, and Wet seed layer.

在圖6b中，一第一絕緣層或鈍化層186係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在半導體晶粒174和導體層184的上方。絕緣層186含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物、或是具有雷同結構特性及絕緣特性的其它介電材料。 In FIG. 6b, a first insulating layer or passivation layer 186 is formed over the semiconductor die 174 and the conductor layer 184 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 186 contains one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer, or other dielectrics with similar structural and insulating properties material.

一導電層或RDL 188會使用諸如濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程被形成在該第一絕緣層186的上方。導體層188能夠為由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。一部分的導體層188會被電氣連接至半導體晶粒174的導體層182。其它部分的導體層188則能夠相依於半導體晶粒174的設計與功能而為共電或是被電氣隔離。 A conductive layer or RDL 188 is formed over the first insulating layer 186 using patterning and metal deposition processes such as sputtering, electrolyte plating, and electrodeless plating. The conductive layer 188 can be one or more layers made of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. A portion of the conductor layer 188 is electrically connected to the conductor layer 182 of the semiconductor die 174. The other part of the conductor layer 188 can be common or electrically isolated depending on the design and function of the semiconductor die 174.

一第二絕緣層或鈍化層186會被形成在導體層188以及第一絕緣層186的上方。多個絕緣層186與導體層188會被形成在半導體晶粒174的主動表面180的上方。表面檢查會被實施，用以偵測鈍化或RDL缺陷。 A second insulating layer or passivation layer 186 is formed over the conductive layer 188 and the first insulating layer 186. A plurality of insulating layers 186 and conductive layers 188 are formed above the active surface 180 of the semiconductor die 174. Surface inspections are performed to detect passivation or RDL defects.

一部分的絕緣層186會利用雷射190藉由LDA被移除，用以露出導體層184以及沿著半導體晶粒174的表面邊緣的主動表面180的一部分192。也就是，沿著半導體晶粒174的表面邊緣的主動表面180的一部分192沒有絕緣層186。或者，一部分的絕緣層186會藉由蝕刻製程貫穿一已圖樣化光阻層而被移除，用以露出導體層182以及沿著半導體晶粒174的表面邊緣的主動表面180的一部分192。 A portion of the insulating layer 186 is removed by LDA using a laser 190 to expose the conductive layer 184 and a portion 192 of the active surface 180 along the surface edge of the semiconductor die 174. That is, a portion 192 of the active surface 180 along the surface edge of the semiconductor die 174 is free of the insulating layer 186. Alternatively, a portion of the insulating layer 186 is removed through an patterned photoresist layer by an etching process to expose the conductive layer 182 and a portion 192 of the active surface 180 along the surface edge of the semiconductor die 174.

在圖6c中，半導體晶圓170會利用鋸片或雷射削切工具194被單體化裁切貫穿切割道176成為個別的半導體晶粒174。個別的半導體晶粒174皆會被檢查與電氣測試，以便找出單體化裁切後的KGD。 In FIG. 6c, the semiconductor wafer 170 is singulated using a saw blade or a laser cutting tool 194 and cut through the scribe lines 176 to form individual semiconductor dies 174. Individual semiconductor dies 174 are inspected and electrically tested to find the KGD after singulation cutting.

圖7a至7e配合圖1以及2a至2c圖解沉積一囊封體在一WLCSP中的一半導體晶粒的主動表面的側邊與裸露部分上方的另一製程。圖7a所示的係一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板200的一部分的剖視圖。一介面層或雙面膠帶202會被形成在載體200的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。 7a to 7e and FIG. 1 and 2a to 2c illustrate another process of depositing an encapsulation body on the side of the active surface of a semiconductor die in a WLCSP and over the exposed portion. FIG. 7a shows a carrier or temporary substrate 200 containing a sacrificial base material (e.g., silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support purposes). Partial sectional view. An interface layer or a double-sided tape 202 is formed on the carrier 200 as a temporary adhesive solder film, an etch stop layer, or a thermal release layer.

載體200能夠為一可容納多個半導體晶粒174的龐大圓形或矩形鑲板(大於300mm)。載體200的表面積可以大於半導體晶圓170的表面積。較大的載體會降低半導體封裝的製造成本，因為有較多的半導體晶粒能夠在該較大載體上被處理，從而降低每個單元的成本。半導體封裝與處理設備會針對正在被處理的晶圓或載體的大小來設計與配置。 The carrier 200 can be a large circular or rectangular panel (greater than 300 mm) that can accommodate a plurality of semiconductor dies 174. The surface area of the carrier 200 may be larger than the surface area of the semiconductor wafer 170. A larger carrier reduces the manufacturing cost of a semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or carrier being processed.

為進一步降低製造成本，載體200的大小會不相依於半導體晶粒174的大小或是半導體晶圓170的大小來選擇。也就是，載體200具有固定或是標準化大小，其能夠容納從一或更多個半導體晶圓170處單體化裁切出來的各種大小半導體晶粒174。於其中一實施例中，載體200為直徑330mm的圓形。於另一實施例中，載體200為寬度560mm以及長度600mm的矩形。半導體晶粒174可以有10mm乘10mm的面積，它們係被放置在標準化載體200上。或者，半導體晶粒174可以有20mm乘20mm的面積，它們被放置在相同的標準化載體200上。據此，標準化載體200能夠應付任何 大小的半導體晶粒174，其允許後續的半導體處理設備針對共同的載體被標準化，也就是，不相依於晶粒大小或是進料晶圓大小。半導體封裝設備能夠針對一標準晶圓來設計與配置，利用一組共同的處理工具、設備、以及材料清單來處理來自任何進料晶圓大小的任何半導體晶粒大小。該共同或標準化載體200藉由減少或消弭以晶粒大小或進料晶圓大小為基礎的特殊化半導體處理線的需求而降低製造成本與資本風險。藉由選擇預設的載體大小用在來自所有半導體晶圓的任何大小半導體晶粒便能夠施行靈活的製造線。 In order to further reduce manufacturing costs, the size of the carrier 200 may be selected independently of the size of the semiconductor die 174 or the size of the semiconductor wafer 170. That is, the carrier 200 has a fixed or standardized size, which can accommodate various sizes of semiconductor dies 174 cut out from one or more semiconductor wafers 170 singulated. In one embodiment, the carrier 200 has a circular shape with a diameter of 330 mm. In another embodiment, the carrier 200 is rectangular with a width of 560 mm and a length of 600 mm. The semiconductor die 174 may have an area of 10 mm by 10 mm, and they are placed on a standardized carrier 200. Alternatively, the semiconductor die 174 may have an area of 20 mm by 20 mm, and they are placed on the same standardized carrier 200. Accordingly, the standardized carrier 200 can cope with any Size semiconductor die 174, which allows subsequent semiconductor processing equipment to be standardized for a common carrier, that is, independent of die size or feed wafer size. Semiconductor packaging equipment can be designed and configured for a standard wafer, utilizing a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 200 reduces manufacturing costs and capital risks by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size. Flexible manufacturing lines can be implemented by selecting a preset carrier size for use with any size semiconductor die from all semiconductor wafers.

圖6c中的半導體晶粒174被裝設至載體200與介面層202，舉例來說，利用拾放操作，絕緣層186則被定位朝向該載體。圖7b顯示多個半導體晶粒174被裝設至載體200的介面層202，成為重組式晶圓或重新配置晶圓203。半導體晶粒174的主動表面180藉由接觸該介面層的絕緣層186的特性而被固持離開或偏離介面層202，也就是，在主動表面180的一部分192與介面層202之間有一間隙。 The semiconductor die 174 in FIG. 6c is mounted on the carrier 200 and the interface layer 202. For example, using a pick-and-place operation, the insulating layer 186 is positioned toward the carrier. FIG. 7 b shows that a plurality of semiconductor dies 174 are mounted on the interface layer 202 of the carrier 200 and become a reassembled wafer or a reconfigured wafer 203. The active surface 180 of the semiconductor die 174 is held away from or deviates from the interface layer 202 by contacting the characteristics of the insulating layer 186 of the interface layer, that is, there is a gap between a portion 192 of the active surface 180 and the interface layer 202.

重組式晶圓或重組式鑲板203能夠被處理成許多類型的半導體封裝，其包含扇入WLCSP、重組式或嵌入式WLCSP或是eWLCSP、扇出WLCSP、3D封裝(例如，PoP)、或是其它半導體封裝。重組式鑲板203會根據所生成的半導體封裝的規格來配置。於其中一實施例中，多個半導體晶粒174以高密度排列方式被放置在載體200上，也就是，分隔300μm或更小，以便處理扇入裝置。於另一實施例中，半導體晶粒174在載體200上分開50μm的距離。載體200上的半導體晶粒174之間的距離會被最佳化，以便以最低的單元成本來製造半導體封裝。較大的載體200表面積會 容納較多的半導體晶粒174並且降低製造成本，因為每個重組式鑲板203中可處理較多的半導體晶粒174。被裝設至載體200的半導體晶粒174的數量能夠大於、小於、或是等於從半導體晶圓170處單體化裁切出來的半導體晶粒174的數量。載體200與重組式鑲板203提供利用來自不同大小半導體晶圓170的不同大小半導體晶粒174來製造許多不同類型半導體封裝的靈活性。 The restructured wafer or restructured panel 203 can be processed into many types of semiconductor packages, including fan-in WLCSP, recombined or embedded WLCSP or eWLCSP, fan-out WLCSP, 3D package (for example, PoP), or Other semiconductor packages. The reorganized panel 203 is configured according to the specifications of the generated semiconductor package. In one embodiment, a plurality of semiconductor dies 174 are placed on the carrier 200 in a high-density arrangement, that is, separated by 300 μm or less in order to process a fan-in device. In another embodiment, the semiconductor dies 174 are separated by a distance of 50 μm on the carrier 200. The distance between the semiconductor dies 174 on the carrier 200 is optimized to manufacture a semiconductor package with the lowest unit cost. Larger surface area of 200 Accommodates more semiconductor dies 174 and reduces manufacturing costs because more semiconductor dies 174 can be processed in each reassembled panel 203. The number of the semiconductor dies 174 mounted on the carrier 200 can be greater than, less than, or equal to the number of the semiconductor dies 174 singulated from the semiconductor wafer 170. The carrier 200 and the recombination panel 203 provide the flexibility to manufacture many different types of semiconductor packages using different sized semiconductor dies 174 from different sized semiconductor wafers 170.

在圖7c中，一囊封體或模製化合物204會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒174以及載體200的上方。囊封體204能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體204係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。明確地說，囊封體204被設置在半導體晶粒174的側邊中以及主動表面180與介面層202之間的間隙中，並且因而覆蓋半導體晶粒174的側邊以及沿著該半導體晶粒的表面邊緣的主動表面180的裸露部分192上至絕緣層186。據此，囊封體204會覆蓋或接觸半導體晶粒174的至少五個表面，也就是，該半導體晶粒的四個側表面以及主動表面180的一部分192。 In FIG. 7c, an encapsulation body or molding compound 204 will use a solder paste printing coater, compression molding coater, transfer molding coater, liquid encapsulation body molding coater, and vacuum lamination. A coater, spin coater, or other suitable coater is deposited over the semiconductor die 174 and the carrier 200. The encapsulation body 204 can be a polymer synthetic material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulation body 204 is non-conductive and provides environmental protection for the semiconductor device, and is protected from external elements and pollutants. Specifically, the encapsulation body 204 is disposed in the sides of the semiconductor die 174 and in the gap between the active surface 180 and the interface layer 202, and thus covers the sides of the semiconductor die 174 and along the semiconductor die The exposed portion 192 of the active surface 180 of the surface edge is up to the insulating layer 186. Accordingly, the encapsulation body 204 may cover or contact at least five surfaces of the semiconductor die 174, that is, four side surfaces of the semiconductor die and a portion 192 of the active surface 180.

在圖7d中，載體200和介面層202會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，以便露出絕緣層186以及導體層184。一部分的囊封體204會利用雷射206藉由LDA被移除。或者，一部分的囊封體204會藉由蝕刻製程貫穿 一已圖樣化光阻層而被移除。沿著半導體晶粒174的表面邊緣的主動表面180的一部分192以及該半導體晶粒的側邊仍被囊封體204覆蓋成為一保護性鑲板用以提高產量，尤其是當表面裝設該半導體晶粒時。囊封體204還保護半導體晶粒174，避免因曝露於光中而受損。半導體晶粒174會以下面一或更多道步驟來清洗絕緣層186與導體層184而準備進行電氣測試：電漿清洗、濕式溶劑清洗、銅氧化物清洗、或是乾式清洗。 In FIG. 7d, the carrier 200 and the interface layer 202 are removed by chemical etching, mechanical stripping, CMP, mechanical polishing, thermal baking, UV light, laser scanning, or wet removal, so that The insulating layer 186 and the conductor layer 184 are exposed. A part of the encapsulation body 204 is removed by the LDA using the laser 206. Alternatively, a part of the encapsulation body 204 may be penetrated by an etching process. A patterned photoresist layer is removed. A portion 192 of the active surface 180 along the surface edge of the semiconductor die 174 and the sides of the semiconductor die are still covered by the encapsulation body 204 to form a protective panel to improve yield, especially when the semiconductor is mounted on the surface Grains. The encapsulation body 204 also protects the semiconductor die 174 from being damaged by exposure to light. The semiconductor die 174 is prepared for electrical testing by cleaning the insulating layer 186 and the conductor layer 184 in one or more of the following steps: plasma cleaning, wet solvent cleaning, copper oxide cleaning, or dry cleaning.

在圖7e中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層184的上方。於其中一實施例中，該凸塊材料係利用一丸滴模板來沉積，也就是，不需要用到任何遮罩。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層184。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊210。於某些應用中，凸塊210會被二次回焊，以便改良和導體層184的電氣接觸效果。凸塊210亦能夠被壓縮焊接或熱壓縮焊接至導體層184。凸塊210代表能夠被形成在導體層184上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。雷射標記能夠在凸塊成形之前或之後或是在移除載體200之後被實施。 In FIG. 7e, a conductive bump material is deposited on the conductive layer 184 by using an evaporation process, an electrolytic plating process, an electrodeless plating process, a shot dropping process, or a screen printing process. In one embodiment, the bump material is deposited using a drop template, that is, no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and a combination thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high-lead solder, or a lead-free solder. The bump material is soldered to the conductor layer 184 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 210. In some applications, the bump 210 is re-soldered in order to improve the electrical contact with the conductive layer 184. The bump 210 can also be compression welded or thermally compression welded to the conductor layer 184. The bump 210 represents one of the types of interconnect structures that can be formed over the conductor layer 184. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines. The laser marking can be implemented before or after the bump is formed or after the carrier 200 is removed.

半導體晶粒174會利用鋸片或雷射削切工具212被單體化裁切貫穿囊封體204成為個別的WLCSP 214。圖8所示的係在單體化裁切之後的WLCSP 214。於其中一實施例中，WLCSP 214的維度為3.0毫米 (mm)x2.6mmx0.7mm，節距為0.4mm。半導體晶粒174被電氣連接至凸塊210，以便達到外部互連的目的。囊封體204覆蓋半導體晶粒174的側邊以及主動表面180的一部分192，用以保護半導體晶粒174的該些側邊與表面邊緣並且提高製造產量，尤其是當表面裝設該半導體晶粒時。囊封體204還保護半導體晶粒174，避免因曝露於光中而受損。WLCSP 214會在單體化裁切之前或之後進行電氣測試。 The semiconductor die 174 is singulated and cut through the encapsulation body 204 into individual WLCSP 214 using a saw blade or a laser cutting tool 212. The system shown in Figure 8 is WLCSP 214 after singulation cutting. In one embodiment, the dimension of WLCSP 214 is 3.0 mm. (mm) x2.6mmx0.7mm, the pitch is 0.4mm. The semiconductor die 174 is electrically connected to the bump 210 so as to achieve the purpose of external interconnection. The encapsulation body 204 covers the sides of the semiconductor die 174 and a portion 192 of the active surface 180 to protect the sides and surface edges of the semiconductor die 174 and improve manufacturing yield, especially when the semiconductor die is mounted on the surface Time. The encapsulation body 204 also protects the semiconductor die 174 from being damaged by exposure to light. WLCSP 214 undergoes electrical testing before or after singulation cutting.

圖9a至9h配合圖1以及2a至2c圖解沉積MUF材料在一WLCSP中的一半導體晶粒的主動表面的側邊與裸露部分上方的製程。圖9a所示的係一來自雷同於圖3a之半導體晶圓的半導體晶粒220，其具有一背表面或非主動表面222以及含有類比電路或數位電路的主動表面224，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面224裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，DSP、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒220可以還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。於其中一實施例中，半導體晶粒220係一覆晶類型半導體晶粒。 FIGS. 9a to 9h, together with FIGS. 1 and 2a to 2c, illustrate the process of depositing MUF material on the side of the active surface of a semiconductor die in a WLCSP and over the exposed portion. FIG. 9a shows a semiconductor die 220 from the semiconductor wafer similar to FIG. 3a, which has a back surface or an inactive surface 222 and an active surface 224 containing an analog circuit or a digital circuit. The circuit is applied to active devices, passive devices, conductor layers, and dielectric layers that are formed in the die and are electrically interconnected according to the electrical design and functions of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in the active surface 224 to implement analog or digital circuits, such as DSP, ASIC, memory , Or other signal processing circuits. The semiconductor die 220 may further include an IPD for RF signal processing, such as an inductor, a capacitor, and a resistor. In one embodiment, the semiconductor die 220 is a flip-chip semiconductor die.

一導電層226會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面224的上方。導體層226能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層226的操作如同被電氣連接至主動表面224上之電路的接觸墊。 A conductive layer 226 is formed over the active surface 224 using a PVD, CVD, electrolyte plating, electrodeless plating process, or other suitable metal deposition process. The conductive layer 226 can be made of one or more layers made of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductor layer 226 operates like a contact pad that is electrically connected to a circuit on the active surface 224.

一導電層228會利用諸如濺鍍、電解質電鍍、以及無電極電鍍的圖樣化和金屬沉積製程被形成在導體層226的上方。導體層228能夠為Al、Cu、Sn、Ni、Au、Ag、W、或是其它合宜的導電材料。導體層228係一UBM，其被電氣連接至導體層226。UBM 228能夠係一具有黏著層、屏障層、以及晶種層或潤濕層的多金屬堆疊。黏著層係被形成在導體層226的上方並且能夠為Ti、TiN、TiW、Al、或是Cr。屏障層係被形成在黏著層的上方並且能夠為Ni、NiV、Pt、Pd、TiW、Ti、或是CrCu。該屏障層會阻止Cu擴散至該晶粒的主動區之中。晶種層係被形成在屏障層的上方並且能夠為Cu、Ni、NiV、Au、或是Al。UBM 228為導體層226提供一低阻值互連線，並且提供一屏障阻止焊料擴散，以及提供用於焊料潤濕的晶種層。 A conductive layer 228 is formed over the conductive layer 226 using a patterning and metal deposition process such as sputtering, electrolyte plating, and electrodeless plating. The conductive layer 228 can be Al, Cu, Sn, Ni, Au, Ag, W, or other suitable conductive materials. The conductor layer 228 is a UBM, which is electrically connected to the conductor layer 226. UBM 228 can be a multi-metal stack with an adhesion layer, a barrier layer, and a seed layer or a wetting layer. The adhesive layer system is formed above the conductor layer 226 and can be Ti, TiN, TiW, Al, or Cr. The barrier layer is formed above the adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti, or CrCu. The barrier layer prevents Cu from diffusing into the active area of the grain. The seed layer system is formed over the barrier layer and can be Cu, Ni, NiV, Au, or Al. The UBM 228 provides a low-resistance interconnect for the conductor layer 226, and provides a barrier to prevent solder diffusion, and a seed layer for solder wetting.

一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層228的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層228。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊230。於某些應用中，凸塊230會被二次回焊，以便改良和導體層228的電氣接觸效果。凸塊230亦能夠被壓縮焊接或熱壓縮焊接至導體層228。凸塊230代表能夠被形成在導體層228上方的其中一種類型互連結構。該互連結構亦能夠使用短柱凸塊、微凸塊、或是其它電氣互連線。 A conductive bump material is deposited on the conductive layer 228 by using an evaporation process, an electrolytic plating process, an electrodeless plating process, a pill process, or a screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and a combination thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high-lead solder, or a lead-free solder. The bump material is soldered to the conductor layer 228 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 230. In some applications, the bump 230 is re-soldered in order to improve the electrical contact with the conductive layer 228. The bump 230 can also be compression welded or thermally compressed to the conductor layer 228. The bump 230 represents one of the types of interconnect structures that can be formed over the conductor layer 228. The interconnect structure can also use stub bumps, micro-bumps, or other electrical interconnection lines.

半導體晶粒220被裝設至基板232，舉例來說，利用拾放操 作，凸塊230則被定位朝向該基板。基板232包含導體線路234，用以貫穿該基板進行垂直與橫向互連。圖9b顯示被裝設至基板232的半導體晶粒220，成為重組式晶圓或重新配置晶圓236，凸塊230會以冶金方式及電氣方式被焊接至導體線路234。半導體晶粒220的主動表面224藉由凸塊230的特性而被固持離開或偏離基板232，也就是，在主動表面224的一部分238與基板232之間有一間隙。基板232能夠為一可容納多個半導體晶粒220的龐大圓形或矩形鑲板(大於300mm)。 The semiconductor die 220 is mounted to a substrate 232, for example, using a pick and place operation Operation, the bump 230 is positioned toward the substrate. The substrate 232 includes conductor lines 234 for vertical and lateral interconnections through the substrate. FIG. 9b shows that the semiconductor die 220 mounted on the substrate 232 becomes a reconstituted wafer or a reconfigured wafer 236, and the bump 230 is soldered to the conductor line 234 by metallurgy and electricity. The active surface 224 of the semiconductor die 220 is held away from or deviated from the substrate 232 by the characteristics of the bump 230, that is, there is a gap between a portion 238 of the active surface 224 and the substrate 232. The substrate 232 can be a large circular or rectangular panel (greater than 300 mm) capable of accommodating a plurality of semiconductor dies 220.

在圖9c中，一模製底層填充(MUF)材料240會利用焊膏印刷塗敷製程、壓縮模製塗敷製程、轉印模製塗敷製程、液體囊封體模製塗敷製程、真空層疊塗敷製程、旋塗塗敷製程、模製底層填充塗敷製程、或是其它合宜的塗敷製程被沉積在半導體晶粒220以及基板232的上方。MUF材料240能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。MUF材料240係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。明確地說，MUF材料240被設置在半導體晶粒220的側邊中以及主動表面224與基板232之間的間隙中，並且因而覆蓋半導體晶粒220的側邊以及沿著該半導體晶粒的表面邊緣的主動表面224的裸露部分238。 In FIG. 9c, a mold underfill (MUF) material 240 uses a solder paste printing coating process, a compression molding coating process, a transfer molding coating process, a liquid encapsulated body molding coating process, and a vacuum. A stacked coating process, a spin coating process, a mold underfill coating process, or other suitable coating processes are deposited over the semiconductor die 220 and the substrate 232. The MUF material 240 can be a polymer synthetic material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. MUF material 240 is non-conducting and will protect the semiconductor device from environmental elements and contaminants. Specifically, the MUF material 240 is disposed in the sides of the semiconductor die 220 and in the gap between the active surface 224 and the substrate 232, and thus covers the sides of the semiconductor die 220 and the surface along the semiconductor die. The exposed portion 238 of the edge of the active surface 224.

在圖9d中，半導體晶粒220會利用鋸片或雷射削切工具239被單體化裁切貫穿MUF材料240與基板232，以便分離該半導體晶粒與該些基板單元。個別的半導體晶粒220皆會被檢查與電氣測試，以便找出單體化裁切後的KGD。 In FIG. 9 d, the semiconductor die 220 is cut and cut through the MUF material 240 and the substrate 232 by using a saw blade or a laser cutting tool 239 to separate the semiconductor die and the substrate units. Individual semiconductor dies 220 are inspected and electrically tested to find the KGD after singulation cutting.

圖9e所示的係一含有犧牲基礎材料(例如，矽、聚合物、氧 化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板242的一部分的剖視圖。一介面層或雙面膠帶243會被形成在載體242的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。 The system shown in Figure 9e contains sacrificial base materials (e.g., silicon, polymer, oxygen A cross-sectional view of a portion of the carrier or temporary substrate 242 of beryllium, glass, or other suitable low cost rigid materials for structural support purposes). An interface layer or a double-sided adhesive tape 243 is formed on the carrier 242 as a temporary adhesive solder film, an etch stop layer, or a thermal release layer.

載體242能夠為一可容納多個半導體晶粒220與基板232單元的龐大圓形或矩形鑲板(大於300mm)。較大的載體會降低半導體封裝的製造成本，因為有較多的半導體晶粒能夠在該較大載體上被處理，從而降低每個單元的成本。半導體封裝與處理設備會針對正在被處理的晶圓或載體的大小來設計與配置。 The carrier 242 can be a large circular or rectangular panel (greater than 300 mm) capable of accommodating a plurality of semiconductor dies 220 and a substrate 232 unit. A larger carrier reduces the manufacturing cost of a semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or carrier being processed.

為進一步降低製造成本，載體242的大小會不相依於半導體晶粒220的大小來選擇。也就是，載體242具有固定或是標準化大小，其能夠容納從一或更多個半導體晶圓處單體化裁切出來的各種大小半導體晶粒220。於其中一實施例中，載體242為直徑330mm的圓形。於另一實施例中，載體242為寬度560mm以及長度600mm的矩形。半導體晶粒220可以有10mm乘10mm的面積，它們係被放置在標準化載體242上。或者，半導體晶粒220可以有20mm乘20mm的面積，它們被放置在相同的標準化載體242上。據此，標準化載體242能夠應付任何大小的半導體晶粒220，其允許後續的半導體處理設備針對共同的載體被標準化，也就是，不相依於晶粒大小或是進料晶圓大小。半導體封裝設備能夠針對一標準晶圓來設計與配置，利用一組共同的處理工具、設備、以及材料清單來處理來自任何進料晶圓大小的任何半導體晶粒大小。該共同或標準化載體242藉由減少或消弭以晶粒大小或進料晶圓大小為基礎的特殊化半導體處理線的需求而降 低製造成本與資本風險。藉由選擇預設的載體大小用在來自所有半導體晶圓的任何大小半導體晶粒便能夠施行靈活的製造線。 In order to further reduce the manufacturing cost, the size of the carrier 242 is selected independently of the size of the semiconductor die 220. That is, the carrier 242 has a fixed or standardized size, and it can accommodate semiconductor wafers 220 of various sizes that are singulated from one or more semiconductor wafers. In one embodiment, the carrier 242 has a circular shape with a diameter of 330 mm. In another embodiment, the carrier 242 is a rectangle with a width of 560 mm and a length of 600 mm. The semiconductor die 220 may have an area of 10 mm by 10 mm, and they are placed on a standardized carrier 242. Alternatively, the semiconductor die 220 may have an area of 20 mm by 20 mm, and they are placed on the same standardized carrier 242. Accordingly, the standardized carrier 242 can cope with semiconductor dies 220 of any size, which allows subsequent semiconductor processing equipment to be standardized for a common carrier, that is, independent of the die size or the size of the incoming wafer. Semiconductor packaging equipment can be designed and configured for a standard wafer, utilizing a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 242 is reduced by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size Low manufacturing costs and capital risks. Flexible manufacturing lines can be implemented by selecting a preset carrier size for use with any size semiconductor die from all semiconductor wafers.

半導體晶粒220以及基板232單元被裝設至載體242與介面層243，舉例來說，利用拾放操作，該基板則被定位朝向該載體。圖9f顯示被裝設至載體242之介面層243的半導體晶粒220以及基板232單元。 The semiconductor die 220 and the substrate 232 unit are mounted on the carrier 242 and the interface layer 243. For example, the substrate is positioned toward the carrier using a pick and place operation. FIG. 9f shows the semiconductor die 220 and the substrate 232 unit mounted on the interface layer 243 of the carrier 242.

一囊封體或模製化合物244會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在MUF材料240、基板232、以及載體242的上方。囊封體244能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體244係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。 A capsule or molding compound 244 uses a solder paste printing coater, a compression molding coater, a transfer molding coater, a liquid capsule molding coater, a vacuum stack coater, A coater, or other suitable coater, is deposited over the MUF material 240, the substrate 232, and the carrier 242. The encapsulant 244 can be a polymer synthetic material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulation body 244 is non-conducting and provides environmental protection for the semiconductor device, and is protected from external elements and pollutants.

在圖9g中，載體242和介面層243會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，以便露出基板232以及囊封體244。一部分的囊封體244會利用雷射245藉由LDA被移除。或者，一部分的囊封體244會藉由蝕刻製程貫穿一已圖樣化光阻層而被移除。 In FIG. 9g, the carrier 242 and the interface layer 243 are removed by chemical etching, mechanical stripping, CMP, mechanical polishing, thermal baking, UV light, laser scanning, or wet removal, so that The substrate 232 and the encapsulation body 244 are exposed. A portion of the encapsulation body 244 is removed by LDA using laser 245. Alternatively, a part of the encapsulation body 244 may be removed through an patterned photoresist layer by an etching process.

在圖9h中，一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在反向於半導體晶粒220的基板232的導體層234的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊 料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層234。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊246。於某些應用中，凸塊246會被二次回焊，以便改良和導體層234的電氣接觸效果。凸塊246亦能夠被壓縮焊接或熱壓縮焊接至導體層234。凸塊246代表能夠被形成在導體層234上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。 In FIG. 9h, a conductive bump material is deposited on the conductor layer 234 of the substrate 232 opposite to the semiconductor die 220 using an evaporation process, an electrolytic plating process, an electrodeless plating process, a pill process, or a screen printing process. Above. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and a combination thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high lead solder, or a lead-free solder. material. The bump material is soldered to the conductor layer 234 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 246. In some applications, the bumps 246 are re-soldered to improve the electrical contact with the conductive layer 234. The bumps 246 can also be compression welded or thermally compression welded to the conductor layer 234. The bump 246 represents one of the types of interconnect structures that can be formed over the conductor layer 234. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines.

雷射標記能夠在凸塊成形之前或之後或是在移除載體242之後被實施。 Laser marking can be implemented before or after bump formation or after removal of the carrier 242.

半導體晶粒220會利用鋸片或雷射削切工具248被單體化裁切貫穿囊封體244成為個別的WLCSP 250。圖10所示的係在單體化裁切之後的WLCSP 250。於其中一實施例中，WLCSP 250的維度為3.0毫米(mm)x2.6mmx0.7mm，節距為0.4mm。半導體晶粒220被電氣連接至基板232以及凸塊246，以便達到外部互連的目的。MUF材料240覆蓋半導體晶粒220的側邊以及主動表面224的一部分238，用以保護該半導體晶粒的該些側邊與表面邊緣並且提高製造產量，尤其是當表面裝設該半導體晶粒時。MUF材料240還保護半導體晶粒220，避免因曝露於光中而受損。囊封體244覆蓋WLCSP 250，用以保護該裝置。WLCSP 250會在單體化裁切之前或之後進行電氣測試。 The semiconductor die 220 is singulated and cut through the encapsulation body 244 into individual WLCSP 250 using a saw blade or a laser cutting tool 248. Figure 10 shows the WLCSP 250 after singulation cutting. In one embodiment, the dimensions of the WLCSP 250 are 3.0 millimeters (mm) x 2.6 mm x 0.7 mm, and the pitch is 0.4 mm. The semiconductor die 220 is electrically connected to the substrate 232 and the bump 246 so as to achieve the purpose of external interconnection. The MUF material 240 covers the sides of the semiconductor die 220 and a portion 238 of the active surface 224 to protect the sides and surface edges of the semiconductor die and improve manufacturing yield, especially when the semiconductor die is mounted on the surface . The MUF material 240 also protects the semiconductor die 220 from damage caused by exposure to light. The encapsulation body 244 covers the WLCSP 250 to protect the device. The WLCSP 250 undergoes electrical testing before or after singulation cutting.

圖11所示的係WLCSP的一實施例，雷同於圖10，MUF材料240被設置在半導體晶粒220與囊封體244的下方，用以覆蓋該半導體晶粒的側表面。 An embodiment of the WLCSP shown in FIG. 11 is similar to FIG. 10. The MUF material 240 is disposed below the semiconductor die 220 and the encapsulation body 244 to cover the side surfaces of the semiconductor die.

圖12所示的係一半導體封裝的另一實施例，其包含來自雷同於圖3a之半導體晶圓的半導體晶粒220，其具有一背表面或非主動表面262以及含有類比電路或數位電路的主動表面264，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面264裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，DSP、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒260可以還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。於其中一實施例中，半導體晶粒260係一焊線類型半導體晶粒。 Another embodiment of a semiconductor package shown in FIG. 12 includes a semiconductor die 220 from the semiconductor wafer similar to that of FIG. 3a, which has a back surface or an inactive surface 262 and an analog or digital circuit. Active surface 264. The analog or digital circuits are applied to active devices, passive devices, conductor layers, and dielectric layers that are formed in the die and electrically interconnected according to the electrical design and functions of the die. . For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in the active surface 264 to implement analog or digital circuits, such as DSP, ASIC, memory , Or other signal processing circuits. The semiconductor die 260 may further include an IPD for RF signal processing, such as an inductor, a capacitor, and a resistor. In one embodiment, the semiconductor die 260 is a wire-type semiconductor die.

一導電層266會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面264的上方。導體層266能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層266的操作如同被電氣連接至主動表面264上之電路的接觸墊。 A conductive layer 266 is formed over the active surface 264 using PVD, CVD, electrolyte plating, electrodeless plating, or other suitable metal deposition processes. The conductive layer 266 can be made of one or more layers made of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductor layer 266 operates like a contact pad electrically connected to a circuit on the active surface 264.

半導體晶粒260利用晶粒附著黏著劑270(例如，環氧樹脂)被裝設至基板268，雷同於圖9a至9b。基板268包含導體線路272，用以貫穿該基板進行垂直與橫向互連。焊線274被形成在半導體晶粒260的導體層266以及基板268上的導體線路272之間。基板268能夠為一可容納多個半導體晶粒260的龐大圓形或矩形鑲板(大於300mm)。 The semiconductor die 260 is mounted on the substrate 268 using a die attach adhesive 270 (for example, epoxy resin), similarly to FIGS. 9a to 9b. The substrate 268 includes conductor lines 272 for vertical and lateral interconnections through the substrate. The bonding wire 274 is formed between the conductive layer 266 of the semiconductor die 260 and the conductive line 272 on the substrate 268. The substrate 268 can be a large circular or rectangular panel (greater than 300 mm) that can accommodate a plurality of semiconductor dies 260.

一囊封體或模製化合物204會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、 旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒260以及基板268的上方，雷同於圖9c。囊封體276能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體276係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。 An encapsulation body or molding compound 204 uses a solder paste printing coater, a compression molding coater, a transfer molding coater, a liquid encapsulation body molding coater, a vacuum lamination coater, A spin coater or other suitable coater is deposited over the semiconductor die 260 and the substrate 268, similar to FIG. 9c. The encapsulant 276 can be a polymer synthetic material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulation body 276 is non-conducting and will provide environmental protection for the semiconductor device, and be protected from external elements and pollutants.

半導體晶粒260會被單體化裁切貫穿囊封體276與基板268，雷同於圖9d。經單體化裁切的半導體晶粒260與基板268會被裝設至一載體，雷同於圖9e。一囊封體或模製化合物278會利用焊膏印刷塗敷機、壓縮模製塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在囊封體276以及基板268的上方，雷同於圖9f。囊封體278能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體278係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。該載體會被移除。 The semiconductor die 260 is cut through the encapsulation body 276 and the substrate 268 by singulation, similar to FIG. 9d. The singulated semiconductor die 260 and the substrate 268 are mounted on a carrier, which is similar to FIG. 9e. An encapsulation body or molding compound 278 uses a solder paste printing coater, a compression molding coater, a transfer molding coater, a liquid encapsulation body molding coater, a vacuum stack coater, A coating applicator, or other suitable applicator, is deposited over the encapsulation body 276 and the substrate 268, similarly to FIG. 9f. The encapsulation body 278 can be a polymer synthetic material, for example, an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulation body 278 is non-conducting and will provide environmental protection for the semiconductor device, and be protected from external elements and pollutants. The carrier will be removed.

一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在反向於半導體晶粒260的基板268的導體層272的上方。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層272。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊280。於某些應用中，凸塊280會被二次回焊，以便改良和導體層272的 電氣接觸效果。凸塊280亦能夠被壓縮焊接或熱壓縮焊接至導體層272。凸塊280代表能夠被形成在導體層272上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。 A conductive bump material is deposited on the conductive layer 272 of the substrate 268 opposite to the semiconductor die 260 by an evaporation process, an electrolytic plating process, an electrodeless plating process, a pill process, or a screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and a combination thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high-lead solder, or a lead-free solder. The bump material is soldered to the conductor layer 272 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 280. In some applications, the bump 280 is re-soldered in order to improve the performance of the conductive layer 272. Electrical contact effect. The bumps 280 can also be compression welded or thermally compression welded to the conductor layer 272. The bump 280 represents one of the types of interconnect structures that can be formed over the conductor layer 272. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines.

雷射標記能夠在凸塊成形之前或之後或是在移除該載體之後被實施。該裝配件會進行電漿清洗或是助焊劑印刷。 Laser marking can be implemented before or after bump formation or after removing the carrier. The assembly will be plasma cleaned or flux printed.

半導體晶粒260會被單體化裁切貫穿囊封體244成為個別的半導體封裝282，它們的維度為3.0毫米(mm)x2.6mmx0.7mm，節距為0.4mm。半導體晶粒260被電氣連接至基板268以及凸塊280，以便達到外部互連的目的。囊封體276覆蓋半導體晶粒260的側表面，用以保護該半導體晶粒的該些表面邊緣並且提高製造產量，尤其是當表面裝設該半導體晶粒時。 The semiconductor die 260 is cut through the encapsulation body 244 into individual semiconductor packages 282 by singulation, and their dimensions are 3.0 millimeters (mm) x 2.6 mm x 0.7 mm, and the pitch is 0.4 mm. The semiconductor die 260 is electrically connected to the substrate 268 and the bump 280 so as to achieve the purpose of external interconnection. The encapsulation body 276 covers the side surface of the semiconductor die 260 to protect the surface edges of the semiconductor die and improve manufacturing yield, especially when the semiconductor die is mounted on the surface.

圖13a至13p配合圖1以及2a至2c圖解形成一重組式或嵌入式扇入WLCSP的製程。圖13a所示的係一半導體晶圓290，其具有基礎基板材料292(例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽)用以達到結構性支撐的目的。複數個半導體晶粒或組件294會被形成在晶圓290上，藉由如上面所述之非主動的晶粒間晶圓區域或切割道296來分離。切割道296提供削切區，以便將半導體晶圓290單體化裁切成個別的半導體晶粒294。在將半導體晶圓單體化裁切成個別的半導體晶粒294之前，半導體晶圓290可以有任何直徑。於其中一實施例中，半導體晶圓290的直徑為200至300mm。於另一實施例中，半導體晶圓290的直徑為100至450mm。半導體晶粒294可以有任何大小，並且於其中一實施例中，半導體晶粒220具有10mm乘10mm的面積。 Figures 13a to 13p cooperate with Figures 1 and 2a to 2c to form a recombined or embedded fan-in WLCSP process. A semiconductor wafer 290 shown in FIG. 13a has a base substrate material 292 (for example, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide) for structural support. A plurality of semiconductor dies or components 294 are formed on the wafer 290 and separated by inactive inter-die wafer regions or scribe lines 296 as described above. The dicing track 296 provides a cutting area for singulating the semiconductor wafer 290 into individual semiconductor dies 294. Prior to singulating the semiconductor wafer into individual semiconductor dies 294, the semiconductor wafer 290 may have any diameter. In one embodiment, the diameter of the semiconductor wafer 290 is 200 to 300 mm. In another embodiment, the diameter of the semiconductor wafer 290 is 100 to 450 mm. The semiconductor die 294 may have any size, and in one embodiment, the semiconductor die 220 has an area of 10 mm by 10 mm.

圖13a同樣顯示半導體晶圓300，其雷同於半導體晶圓290。 半導體晶圓300包含一基礎基板材料302(例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽)用以達到結構性支撐的目的。複數個半導體晶粒或組件304會被形成在晶圓300上，藉由如上面所述之非主動的晶粒間晶圓區域或切割道306來分離。切割道306提供削切區，以便將半導體晶圓300單體化裁切成個別的半導體晶粒304。半導體晶圓300可以有和半導體晶圓290相同的直徑或是不同的直徑。在將半導體晶圓單體化裁切成個別的半導體晶粒304之前，半導體晶圓300可以有任何直徑。於其中一實施例中，半導體晶圓300的直徑為200至300mm。於另一實施例中，半導體晶圓300的直徑為100至450mm。半導體晶粒304可以有任何大小，並且於其中一實施例中，半導體晶粒304具有5mm乘5mm的面積。 FIG. 13 a also shows the semiconductor wafer 300, which is similar to the semiconductor wafer 290. The semiconductor wafer 300 includes a base substrate material 302 (for example, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide) for structural support purposes. A plurality of semiconductor dies or components 304 are formed on the wafer 300 and separated by inactive inter-die wafer regions or scribe lines 306 as described above. The dicing track 306 provides a cutting area for singulating the semiconductor wafer 300 into individual semiconductor dies 304. The semiconductor wafer 300 may have the same diameter as the semiconductor wafer 290 or a different diameter. Prior to singulating the semiconductor wafer into individual semiconductor dies 304, the semiconductor wafer 300 may have any diameter. In one embodiment, the diameter of the semiconductor wafer 300 is 200 to 300 mm. In another embodiment, the diameter of the semiconductor wafer 300 is 100 to 450 mm. The semiconductor die 304 may have any size, and in one embodiment, the semiconductor die 304 has an area of 5 mm by 5 mm.

圖13b所示的係半導體晶圓290的一部分的剖視圖。每一個半導體晶粒294皆有一背表面或非主動表面310以及含有類比電路或數位電路的主動表面312，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面312裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，DSP、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒294可以還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。 A cross-sectional view of a portion of the semiconductor wafer 290 shown in FIG. 13b. Each semiconductor die 294 has a back surface or an inactive surface 310 and an active surface 312 containing analog circuits or digital circuits. The analog circuits or digital circuits are formed according to the electrical design and function of the die. Active devices, passive devices, conductor layers, and dielectric layers within and within the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in the active surface 312 to implement analog or digital circuits, such as DSP, ASIC, memory , Or other signal processing circuits. The semiconductor die 294 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

一導電層314會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面312的上方。導體層314能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或 是其它合宜的導電材料。導體層314的操作如同被電氣連接至主動表面312上之電路的接觸墊。導體層314會被形成為多個接觸墊，它們以並排的方式被設置在和半導體晶粒294的邊緣相隔第一距離處，如圖13b之中所示。或者，導體層314會被形成為偏移在多列之中的多個接觸墊，俾使得第一列接觸墊會被設置在和晶粒294的邊緣相隔第一距離處，而與該第一列交錯的第二列接觸墊則被設置在和晶粒294的邊緣相隔第二距離處。 A conductive layer 314 is formed over the active surface 312 using PVD, CVD, electrolyte plating, electrodeless plating, or other suitable metal deposition processes. The conductor layer 314 can be made of one or more layers made of: Al, Cu, Sn, Ni, Au, Ag, or Is other suitable conductive materials. The conductor layer 314 operates like a contact pad electrically connected to a circuit on the active surface 312. The conductive layer 314 is formed as a plurality of contact pads, which are disposed side by side at a first distance from the edge of the semiconductor die 294, as shown in FIG. 13b. Alternatively, the conductive layer 314 may be formed as a plurality of contact pads offset in a plurality of rows, so that the first row of contact pads may be disposed at a first distance from the edge of the die 294, and from the first The staggered second row of contact pads are disposed at a second distance from the edge of the die 294.

一第一絕緣層或鈍化層316係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在半導體晶粒294和導體層314的上方。絕緣層316含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物、或是具有雷同結構特性及絕緣特性的其它介電材料。於其中一實施例中，絕緣層316係一低溫固化光敏介電聚合物，具有或不具有在小於200℃處被固化的絕緣填充劑。絕緣層316覆蓋主動表面312並且為主動表面312提供保護。一部分的絕緣層316會利用雷射318藉由LDA被移除，或者，藉由蝕刻製程貫穿一已圖樣化光阻層而被移除，以便經由絕緣層316的表面320露出導體層314並且用於進行後續的電氣互連。 A first insulating layer or passivation layer 316 is formed over the semiconductor die 294 and the conductor layer 314 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 316 contains one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer, or other dielectrics having similar structural and insulating properties material. In one embodiment, the insulating layer 316 is a low-temperature-curable photosensitive dielectric polymer, with or without an insulating filler cured at less than 200 ° C. The insulating layer 316 covers and protects the active surface 312. A part of the insulating layer 316 is removed by LDA using laser 318, or is removed through an patterned photoresist layer by an etching process, so that the conductive layer 314 is exposed through the surface 320 of the insulating layer 316 and used For subsequent electrical interconnections.

半導體晶圓290會進行電氣測試與檢查，作為品質控制過程的一部分。手動視覺檢查及自動光學系統會被用來在半導體晶圓290上實施檢查。軟體會被使用在半導體晶圓290的自動光學分析中。視覺檢查方法可以運用諸如掃描電子顯微鏡、高強度光或紫外光、或是冶金顯微鏡的設備。半導體晶圓290的結構性特徵會被檢查，其包含：翹曲、厚度變異、表面微粒、不規則性、裂痕、脫層、以及變色。 The semiconductor wafer 290 is electrically tested and inspected as part of the quality control process. Manual visual inspection and automatic optical systems are used to perform inspections on the semiconductor wafer 290. The software is used in the automated optical analysis of the semiconductor wafer 290. The visual inspection method may use equipment such as a scanning electron microscope, high-intensity light or ultraviolet light, or a metallurgical microscope. Structural features of the semiconductor wafer 290 are inspected, including: warpage, thickness variation, surface particles, irregularities, cracks, delamination, and discoloration.

半導體晶粒294裡面的主動式組件和被動式組件會在晶圓級進行電氣效能與電路功能的測試。每一個半導體晶粒294係利用一探針或是其它測試裝置來測試功能與電氣參數。探針係被用來電氣接觸每一個半導體晶粒294上的節點或接觸墊314並且提供電氣刺激給該些接觸墊。半導體晶粒294會回應該些電氣刺激，該回應會被測量並且和預期的回應作比較，以便測試該半導體晶粒的功能。該些電氣測試可以包含電路功能、導線完整性、電阻係數、連續性、可靠度、接面深度、ESD、RF效能、驅動電流、臨界電流、漏電流、以及該組件類型特有的操作參數。半導體晶圓290的檢查與電氣測試可讓通過測試而被指定為KGD的半導體晶粒294使用於半導體封裝中。 The active components and passive components in the semiconductor die 294 are tested for electrical performance and circuit functions at the wafer level. Each semiconductor die 294 uses a probe or other testing device to test the functional and electrical parameters. The probe system is used to electrically contact the nodes or contact pads 314 on each semiconductor die 294 and provide electrical stimulation to the contact pads. The semiconductor die 294 responds to some electrical stimulus, and the response is measured and compared with the expected response to test the function of the semiconductor die. These electrical tests may include circuit function, wire integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, critical current, leakage current, and operating parameters specific to the type of component. The inspection and electrical testing of the semiconductor wafer 290 allows the semiconductor die 294 designated as KGD by the test to be used in a semiconductor package.

在圖13c中，半導體晶圓290會利用鋸片或雷射削切工具322被單體化裁切貫穿切割道296成為個別的半導體晶粒294，該些半導體晶粒294具有邊緣、側壁、或是側表面324。同樣地，圖13a中的半導體晶圓300會利用鋸片或雷射削切工具322被單體化裁切貫穿切割道306成為個別的半導體晶粒304。個別的半導體晶粒294與304皆會被檢查與電氣測試，以便找出單體化裁切後的KGD。 In FIG. 13c, the semiconductor wafer 290 is singulated using a saw blade or a laser cutting tool 322 and cut through the scribe line 296 to form individual semiconductor dies 294, which have edges, sidewalls, or Is the side surface 324. Similarly, the semiconductor wafer 300 in FIG. 13 a is singulated using a saw blade or a laser cutting tool 322 to cut through the scribe lines 306 to form individual semiconductor dies 304. Individual semiconductor dies 294 and 304 are inspected and electrically tested to find the KGD after singulation cutting.

圖13d所示的係一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板330的一部分的剖視圖。一介面層或雙面膠帶332會被形成在載體330的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。 13d is a carrier or temporary substrate 330 containing a sacrificial base material (for example, silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid materials for structural support purposes). Partial sectional view. An interface layer or double-sided tape 332 may be formed on the carrier 330 as a temporary adhesive solder film, an etch stop layer, or a thermal release layer.

載體330係一可容納多個半導體晶粒的標準化載體並且能 夠容納從具有任何直徑的半導體晶圓處單體化裁切出來的多種尺寸半導體晶粒。舉例來說，載體330能夠為具有305mm或更大直徑的圓形鑲板，或者，能夠為具有300mm或更大長度以及300mm或更大寬度的矩形鑲板。載體300的表面積可以大於半導體晶圓290或300的表面積。於其中一實施例中，半導體晶圓290具有300mm的直徑並且含有長度10mm且寬度10mm的半導體晶粒294。於其中一實施例中，半導體晶圓300具有200mm的直徑並且含有長度5mm且寬度5mm的半導體晶粒304。載體330能夠容納10mm乘10mm的半導體晶粒294以及5mm乘5mm的半導體晶粒304。載體330攜載5mm乘5mm的半導體晶粒304的數量大於10mm乘10mm的半導體晶粒294的數量。於另一實施例中，半導體晶粒294與304具有相同的維度。載體330具有標準化的尺寸與形狀，以便容納任何尺寸的半導體晶粒。較大的載體會降低半導體封裝的製造成本，因為有較多的半導體晶粒能夠在該較大載體上被處理，從而降低每個單元的成本。 The carrier 330 is a standardized carrier capable of accommodating a plurality of semiconductor dies and capable of Enough to accommodate semiconductor die of various sizes cut out from semiconductor wafers of any diameter. For example, the carrier 330 can be a circular panel having a diameter of 305 mm or more, or can be a rectangular panel having a length of 300 mm or more and a width of 300 mm or more. The surface area of the carrier 300 may be larger than the surface area of the semiconductor wafer 290 or 300. In one embodiment, the semiconductor wafer 290 has a diameter of 300 mm and contains a semiconductor die 294 with a length of 10 mm and a width of 10 mm. In one embodiment, the semiconductor wafer 300 has a diameter of 200 mm and contains a semiconductor die 304 having a length of 5 mm and a width of 5 mm. The carrier 330 can accommodate a semiconductor die 294 of 10 mm by 10 mm and a semiconductor die 304 of 5 mm by 5 mm. The carrier 330 carries a number of semiconductor die 304 of 5 mm by 5 mm greater than a number of semiconductor die 294 of 10 mm by 10 mm. In another embodiment, the semiconductor dies 294 and 304 have the same dimensions. The carrier 330 has a standardized size and shape so as to accommodate semiconductor dies of any size. A larger carrier reduces the manufacturing cost of a semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit.

半導體封裝與處理設備會針對正在被處理的半導體晶粒與載體的大小來設計與配置。為進一步降低製造成本，載體330的大小會不相依於半導體晶粒294或304的大小並且不相依於半導體晶圓290與300的大小來選擇。也就是，載體330具有固定或是標準化大小，其能夠容納從一或更多個半導體晶圓290或300處單體化裁切出來的各種大小半導體晶粒294與304。於其中一實施例中，載體330為直徑330mm的圓形。於另一實施例中，載體330為寬度560mm以及長度600mm的矩形。 Semiconductor packaging and processing equipment is designed and configured for the size of the semiconductor die and carrier being processed. In order to further reduce manufacturing costs, the size of the carrier 330 may be selected independently of the sizes of the semiconductor dies 294 or 304 and independent of the sizes of the semiconductor wafers 290 and 300. That is, the carrier 330 has a fixed or standardized size, which can accommodate semiconductor wafers 294 and 304 of various sizes cut out from one or more semiconductor wafers 290 or 300 by singulation. In one embodiment, the carrier 330 has a circular shape with a diameter of 330 mm. In another embodiment, the carrier 330 is a rectangle with a width of 560 mm and a length of 600 mm.

該標準化載體(載體330)的大小與維度會在該處理設備的設計期間被選擇，以便開發一針對半導體裝置的所有後端半導體製造為一致 的製造線。不論要被製造的半導體封裝的大小與類型為何，載體330皆維持不變的大小。舉例來說，半導體晶粒294可以有10mm乘10mm的面積並且被放置在標準化載體330上。或者，半導體晶粒294可以有20mm乘20mm的面積並且被放置在相同的標準化載體330上。據此，標準化載體330能夠應付任何大小的半導體晶粒294與304，其允許後續的半導體處理設備針對共同的載體被標準化，也就是，不相依於晶粒大小或是進料晶圓大小。半導體封裝設備能夠針對一標準晶圓來設計與配置，利用一組共同的處理工具、設備、以及材料清單來處理來自任何進料晶圓大小的任何半導體晶粒大小。該共同或標準化載體330藉由減少或消弭以晶粒大小或進料晶圓大小為基礎的特殊化半導體處理線的需求而降低製造成本與資本風險。藉由選擇預設的載體大小用在來自所有半導體晶圓的任何大小半導體晶粒便能夠施行靈活的製造線。 The size and dimensions of the standardized carrier (carrier 330) will be selected during the design of the processing equipment in order to develop a consistent back-end semiconductor manufacturing for all semiconductor devices. Manufacturing line. Regardless of the size and type of the semiconductor package to be manufactured, the carrier 330 remains the same size. For example, the semiconductor die 294 may have an area of 10 mm by 10 mm and is placed on a standardized carrier 330. Alternatively, the semiconductor die 294 may have an area of 20 mm by 20 mm and be placed on the same standardized carrier 330. Accordingly, the standardized carrier 330 can cope with semiconductor dies 294 and 304 of any size, which allows subsequent semiconductor processing equipment to be standardized for a common carrier, that is, independent of the die size or the size of the incoming wafer. Semiconductor packaging equipment can be designed and configured for a standard wafer, utilizing a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 330 reduces manufacturing costs and capital risks by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size. Flexible manufacturing lines can be implemented by selecting a preset carrier size for use with any size semiconductor die from all semiconductor wafers.

在圖13e中，圖13c中的半導體晶粒294被裝設至載體330與介面層332，舉例來說，利用拾放操作，絕緣層316則被定位朝向載體330。多個半導體晶粒294被裝設至載體330的介面層332，成為重組式晶圓或重新配置晶圓336。於其中一實施例中，絕緣層316被嵌入在介面層332裡面。舉例來說，半導體晶粒294的主動表面312可以共面於介面層332的表面334。於另一實施例中，絕緣層316被裝設在介面層332的上方，俾使得半導體晶粒294的主動表面312偏離介面層332。 In FIG. 13e, the semiconductor die 294 in FIG. 13c is mounted on the carrier 330 and the interface layer 332. For example, using a pick and place operation, the insulating layer 316 is positioned toward the carrier 330. The plurality of semiconductor dies 294 are mounted on the interface layer 332 of the carrier 330 and become a reassembled wafer or a reconfigured wafer 336. In one embodiment, the insulating layer 316 is embedded in the interface layer 332. For example, the active surface 312 of the semiconductor die 294 may be coplanar with the surface 334 of the interface layer 332. In another embodiment, the insulating layer 316 is disposed above the interface layer 332 such that the active surface 312 of the semiconductor die 294 is offset from the interface layer 332.

重組式晶圓或重組式鑲板336能夠被處理成許多類型的半導體封裝，其包含扇入WLCSP、重組式WLCSP或是eWLCSP、扇出WLCSP、覆晶封裝、3D封裝(例如，PoP)、或是其它半導體封裝。重組式鑲板336會 根據所生成的半導體封裝的規格來配置。於其中一實施例中，多個半導體晶粒294以高密度排列方式被放置在載體330上，也就是，分隔300μm或更小，以便處理扇入裝置。多個半導體晶粒294被放置在載體330，半導體晶粒294之間分離一間隙或距離D。半導體晶粒294之間的距離D係以要被處理的半導體封裝的設計與規格來選擇。於其中一實施例中，半導體晶粒294之間的距離D為50μm或更小。於另一實施例中，半導體晶粒294之間的距離D為100μm或更小。載體330上的半導體晶粒294之間的距離D會被最佳化，以便以最低的單元成本來製造半導體封裝。 The reassembled wafer or reassembled panel 336 can be processed into many types of semiconductor packages including fan-in WLCSP, recombined WLCSP or eWLCSP, fan-out WLCSP, flip-chip package, 3D package (for example, PoP), or Other semiconductor packages. Recombination panel 336 It is configured according to the specifications of the generated semiconductor package. In one embodiment, a plurality of semiconductor dies 294 are placed on the carrier 330 in a high-density arrangement, that is, separated by 300 μm or less to process a fan-in device. A plurality of semiconductor dies 294 are placed on the carrier 330, and the semiconductor dies 294 are separated by a gap or distance D. The distance D between the semiconductor dies 294 is selected based on the design and specifications of the semiconductor package to be processed. In one embodiment, the distance D between the semiconductor dies 294 is 50 μm or less. In another embodiment, the distance D between the semiconductor dies 294 is 100 μm or less. The distance D between the semiconductor dies 294 on the carrier 330 is optimized in order to manufacture a semiconductor package with the lowest unit cost.

圖13f所示的係重組式鑲板336的平面圖，其具有被裝設至或被設置在載體330上方的半導體晶粒294。載體330係一標準化的形狀與大小，且所以，會構成一標準化載體。載體330可容納從各種大小的半導體晶圓處單體化裁切出來的各種大小與數量的半導體晶粒。於其中一實施例中，載體330為矩形形狀並且具有560mm的寬度W1以及600mm的長度L1。於另一實施例中，載體330為矩形形狀並且具有330mm的寬度W1以及330mm的長度L1。於另一實施例中，載體330為圓形形狀並且具有330mm的直徑。 FIG. 13f is a plan view of the reorganized panel 336, which has a semiconductor die 294 mounted on or above the carrier 330. The carrier 330 has a standardized shape and size, and therefore, it will constitute a standardized carrier. The carrier 330 can accommodate semiconductor wafers of various sizes and numbers singulated from semiconductor wafers of various sizes. In one embodiment, the carrier 330 is rectangular and has a width W1 of 560 mm and a length L1 of 600 mm. In another embodiment, the carrier 330 is rectangular and has a width W1 of 330 mm and a length L1 of 330 mm. In another embodiment, the carrier 330 is circular in shape and has a diameter of 330 mm.

被設置在載體330上方的半導體晶粒294的數量相依於半導體晶粒294的大小以及重組式鑲板336的結構裡面的半導體晶粒294之間的距離D。被裝設至載體330的半導體晶粒294的數量能夠大於、小於、或是等於從半導體晶圓290處單體化裁切出來的半導體晶粒294的數量。載體330的較大表面積會容納較多的半導體晶粒294並且降低製造成本，因為每一個重組式鑲板336中會處理較多的半導體晶粒294。於其中一範例中，半 導體晶圓290的直徑為300mm，在半導體晶圓290中會形成數量約600個獨特的10mm乘10mm半導體晶粒294。半導體晶粒294係從一或更多個半導體晶圓290處單體化裁切出來。舉例來說，載體330被製備為具有560mm的標準寬度W1以及600mm的標準長度L1。具有560mm之寬度W1的載體330的大小被設計成用以在載體330的寬度W1中容納數量約54個半導體晶粒294，它們的面積為10mm乘10mm並且分隔200μm的距離D。具有600mm之長度L1的載體330的大小被設計成用以在載體330的長度L1中容納數量約58個半導體晶粒294，它們的面積為10mm乘10mm並且分隔200μm的距離D。據此，載體330的表面積為寬度W1乘以長度L1，容納數量約3,000個面積為10mm乘10mm的半導體晶粒294並且半導體晶粒294之間的間隙或距離D為200μm。多個半導體晶粒294能夠被放置在載體330上，半導體晶粒294之間的間隙或距離D小於200μm，以便提高載體330上的半導體晶粒294的密度並且進一步降低處理半導體晶粒294的成本。 The number of semiconductor dies 294 disposed above the carrier 330 depends on the size of the semiconductor dies 294 and the distance D between the semiconductor dies 294 in the structure of the reorganized panel 336. The number of the semiconductor dies 294 mounted on the carrier 330 can be greater than, less than, or equal to the number of the semiconductor dies 294 singulated from the semiconductor wafer 290. The larger surface area of the carrier 330 will accommodate more semiconductor dies 294 and reduce manufacturing costs, as more semiconductor dies 294 will be processed in each reassembled panel 336. In one example, half The conductor wafer 290 has a diameter of 300 mm, and about 600 unique 10 mm by 10 mm semiconductor dies 294 are formed in the semiconductor wafer 290. The semiconductor die 294 is singulated from one or more semiconductor wafers 290. For example, the carrier 330 is prepared to have a standard width W1 of 560 mm and a standard length L1 of 600 mm. The size of the carrier 330 having a width W1 of 560 mm is designed to accommodate about 54 semiconductor dies 294 in the width W1 of the carrier 330, and their area is 10 mm by 10 mm and separated by a distance D of 200 μm. The size of the carrier 330 having a length L1 of 600 mm is designed to accommodate about 58 semiconductor dies 294 in the length L1 of the carrier 330, and their area is 10 mm by 10 mm and separated by a distance D of 200 μm. According to this, the surface area of the carrier 330 is the width W1 times the length L1, and the number of semiconductor wafers 294 having an area of 10 mm by 10 mm is accommodated in about 3,000, and the gap or distance D between the semiconductor wafers 294 is 200 μm. Multiple semiconductor dies 294 can be placed on the carrier 330, and the gap or distance D between the semiconductor dies 294 is less than 200 μm in order to increase the density of the semiconductor dies 294 on the carrier 330 and further reduce the cost of processing the semiconductor dies 294. .

自動拾放設備會被用來以半導體晶粒294的數量及大小為基礎並且以載體330的面積為基礎來製備重組式鑲板336。舉例來說，半導體晶粒294被選擇為具有10mm乘10mm的面積。載體330具有標準的面積，舉例來說，560mm的寬度W1以及600mm的長度L1。自動設備會配合半導體晶粒294的面積以及載體330的面積被程式化，以便處理重組式鑲板336。在單體化裁切半導體晶圓290之後，一第一半導體晶粒294會被該自動拾放設備選擇。一第一半導體晶粒294會被裝設至載體330，定位在由該可程式化自動拾放設備所決定的載體330上的某個位置中。一第二半導體晶粒294會被該自動拾放設備選擇，並且被放置在載體330上以及被定位在載體330 上的第一列之中。相鄰半導體晶粒294之間的距離D會被程式化至該自動拾放設備之中並且以要被處理的半導體封裝的設計與規格為基礎被選擇。於其中一實施例中，相鄰半導體晶粒294之間的間隙或距離D為200μm。一第三半導體晶粒294會被該自動拾放設備選擇，並且被放置在載體330上以及被定位在載體330上的第一列之中，其會與一相鄰半導體晶粒294分隔200μm的距離D。該拾放操作會重複進行，直到第一列約54個半導體晶粒294被設置在載體330的寬度W1之中為止。 Automatic pick-and-place equipment is used to prepare the recombination panel 336 based on the number and size of the semiconductor dies 294 and the area of the carrier 330. For example, the semiconductor die 294 is selected to have an area of 10 mm by 10 mm. The carrier 330 has a standard area, for example, a width W1 of 560 mm and a length L1 of 600 mm. Automatic equipment is programmed to match the area of the semiconductor die 294 and the area of the carrier 330 in order to process the reassembled panel 336. After the semiconductor wafer 290 is singulated, a first semiconductor die 294 is selected by the automatic pick and place device. A first semiconductor die 294 is mounted on the carrier 330 and positioned in a position on the carrier 330 determined by the programmable automatic pick and place device. A second semiconductor die 294 is selected by the automatic pick and place device, and is placed on the carrier 330 and positioned on the carrier 330. On the first column. The distance D between adjacent semiconductor dies 294 is programmed into the automatic pick and place device and is selected based on the design and specifications of the semiconductor package to be processed. In one embodiment, the gap or distance D between adjacent semiconductor dies 294 is 200 μm. A third semiconductor die 294 is selected by the automatic pick-and-place device, and is placed on the carrier 330 and positioned in the first row on the carrier 330, which is separated from an adjacent semiconductor die 294 by 200 μm. Distance D. This pick-and-place operation is repeated until about 54 semiconductor dies 294 in the first row are set within the width W1 of the carrier 330.

另一半導體晶粒294會被該自動拾放設備選擇，並且被放置在載體330上以及被定位在載體330上相鄰於該第一列的第二列之中。相鄰列的半導體晶粒294之間的距離D會被事先選擇並且被程式化至該自動拾放設備之中。於其中一實施例中，第一列半導體晶粒294與第二列半導體晶粒294之間的距離D為200μm。該拾放操作會重複進行，直到約58列的半導體晶粒294被設置在載體330的長度L1之中為止。該標準化載體(具有560mm的寬度W1以及600mm的長度L1的載體330)容納約54行以及58列的10mm乘10mm半導體晶粒294，總數量約3,000個半導體晶粒294被設置在載體330上。該拾放操作會重複進行，直到載體330部分或完全被半導體晶粒294佔據為止。該自動拾放設備能夠配合一標準化載體(例如，載體330)裝設任何大小的半導體晶粒294於載體330上，用以形成重組式鑲板336。重組式鑲板336接著便能夠利用已針對標準化載體330進行標準化的後端處理設備來處理。 Another semiconductor die 294 is selected by the automatic pick and place device, and is placed on the carrier 330 and positioned on the carrier 330 in a second column adjacent to the first column. The distance D between the adjacent rows of semiconductor dies 294 is selected in advance and programmed into the automatic pick and place device. In one embodiment, the distance D between the first row of semiconductor dies 294 and the second row of semiconductor dies 294 is 200 μm. This pick-and-place operation is repeated until about 58 rows of semiconductor dies 294 are set within the length L1 of the carrier 330. The standardized carrier (carrier 330 having a width W1 of 560 mm and a length L1 of 600 mm) accommodates approximately 54 rows and 58 columns of 10 mm by 10 mm semiconductor dies 294, and a total number of approximately 3,000 semiconductor dies 294 are disposed on the carrier 330. This pick and place operation is repeated until the carrier 330 is partially or completely occupied by the semiconductor die 294. The automatic pick-and-place device can be used with a standardized carrier (for example, the carrier 330) to mount semiconductor chips 294 of any size on the carrier 330 to form a reorganized panel 336. The recombination panel 336 can then be processed using back-end processing equipment that has been standardized for the standardized carrier 330.

圖13g所示的係重組式晶圓或重組式鑲板338的平面圖，多個半導體晶粒304被裝設至載體330或被設置在載體330上。相同的標準化 載體330或是具有和載體330相同大小的標準化載體會如同被用來處理重組式鑲板336般地被用來處理重組式鑲板338。半導體晶粒或是重組式晶圓或鑲板的任何配置皆能夠被載體330支撐。被設置在載體330上的半導體晶粒304的數量相依於半導體晶粒304的大小以及重組式鑲板338之結構裡面的半導體晶粒304之間的距離D1。被裝設至載體330的半導體晶粒304的數量能夠大於、小於、或是等於從半導體晶圓300處單體化裁切出來的半導體晶粒304的數量。載體330的較大表面積會容納較多的半導體晶粒304並且降低製造成本，因為每一個重組式鑲板338中會處理較多的半導體晶粒304。 A plan view of a reorganized wafer or a reorganized panel 338 shown in FIG. 13g, a plurality of semiconductor dies 304 are mounted on or on the carrier 330. Same standardization The carrier 330 or a standardized carrier having the same size as the carrier 330 will be used to process the recombination panel 338 as it is used to process the recombination panel 336. Any configuration of a semiconductor die or a reconstituted wafer or panel can be supported by the carrier 330. The number of semiconductor dies 304 disposed on the carrier 330 depends on the size of the semiconductor dies 304 and the distance D1 between the semiconductor dies 304 in the structure of the reorganized panel 338. The number of semiconductor dies 304 mounted on the carrier 330 can be greater than, less than, or equal to the number of semiconductor dies 304 cut from the semiconductor wafer 300 by singulation. The larger surface area of the carrier 330 will accommodate more semiconductor dies 304 and reduce manufacturing costs, as more semiconductor dies 304 will be processed in each reassembled panel 338.

於其中一範例中，半導體晶圓300的直徑為200mm，在半導體晶圓300中會形成數量約1,000個獨特的5mm乘5mm半導體晶粒304。半導體晶粒304係從一或更多個半導體晶圓300處單體化裁切出來。舉例來說，載體330被製備為具有560mm的標準寬度W1以及600mm的標準長度L1。具有560mm之寬度W1的載體330的大小被設計成用以在載體330的寬度W1中容納數量約107個半導體晶粒304，它們的面積為5mm乘5mm並且分隔200μm的距離D1。具有600mm之長度L1的載體330的大小被設計成用以在載體330的長度L1中容納數量約115個半導體晶粒304，它們的面積為5mm乘5mm並且分隔200μm的距離D1。據此，載體330的表面積為寬度W1乘以長度L1，容納約12,000個半導體晶粒304，它們的面積為5mm乘5mm並且分隔200μm的距離D1。多個半導體晶粒304能夠被放置在載體330上，半導體晶粒304之間的間隙或距離D1小於200μm，以便提高載體330上的半導體晶粒304的密度並且進一步降低處理半導體晶粒 304的成本。 In one example, the semiconductor wafer 300 has a diameter of 200 mm, and approximately 1,000 unique 5 mm by 5 mm semiconductor dies 304 are formed in the semiconductor wafer 300. The semiconductor die 304 is singulated from one or more semiconductor wafers 300. For example, the carrier 330 is prepared to have a standard width W1 of 560 mm and a standard length L1 of 600 mm. The size of the carrier 330 having a width W1 of 560 mm is designed to accommodate a number of about 107 semiconductor dies 304 in the width W1 of the carrier 330, and their area is 5 mm by 5 mm and separated by a distance D1 of 200 μm. The size of the carrier 330 having a length L1 of 600 mm is designed to accommodate about 115 semiconductor dies 304 in the length L1 of the carrier 330, and their areas are 5 mm by 5 mm and separated by a distance D1 of 200 μm. According to this, the surface area of the carrier 330 is the width W1 times the length L1, which accommodates about 12,000 semiconductor dies 304, whose area is 5 mm by 5 mm and separated by a distance D1 of 200 μm. Multiple semiconductor dies 304 can be placed on the carrier 330, and the gap or distance D1 between the semiconductor dies 304 is less than 200 μm in order to increase the density of the semiconductor dies 304 on the carrier 330 and further reduce the processing of the semiconductor dies. The cost of 304.

自動拾放設備會被用來以半導體晶粒304的數量及大小為基礎並且以載體330的面積為基礎來製備重組式鑲板338。舉例來說，半導體晶粒304被選擇為具有5mm乘5mm的面積。載體330具有標準的面積，舉例來說，560mm的寬度W1以及600mm的長度L1。自動設備會配合半導體晶粒304的面積以及載體330的面積被程式化，以便處理重組式鑲板338。在單體化裁切半導體晶圓300之後，一第一半導體晶粒304會被該自動拾放設備選擇。一第一半導體晶粒304會被裝設至載體330，定位在由該可程式化自動拾放設備所決定的載體330上的某個位置中。一第二半導體晶粒304會被該自動拾放設備選擇，並且被放置在載體330上以及被定位在載體330上的第一列之中與該第一半導體晶粒304相隔距離D1。相鄰半導體晶粒304之間的距離D1會被程式化至該自動拾放設備之中並且以要被處理的半導體封裝的設計與規格為基礎被選擇。於其中一實施例中，相鄰半導體晶粒304之間的間隙或距離D1為200μm。一第三半導體晶粒304會被該自動拾放設備選擇，並且被放置在載體330上以及被定位在載體330上的第一列之中。該拾放操作會重複進行，直到一列約107個半導體晶粒304被設置在載體330的寬度W1之中為止。 Automatic pick-and-place equipment is used to prepare the recombination panel 338 based on the number and size of the semiconductor dies 304 and the area of the carrier 330. For example, the semiconductor die 304 is selected to have an area of 5 mm by 5 mm. The carrier 330 has a standard area, for example, a width W1 of 560 mm and a length L1 of 600 mm. Automatic equipment is programmed to match the area of the semiconductor die 304 and the area of the carrier 330 in order to process the recombination panel 338. After the semiconductor wafer 300 is singulated, a first semiconductor die 304 is selected by the automatic pick-and-place device. A first semiconductor die 304 is mounted on the carrier 330 and positioned in a position on the carrier 330 determined by the programmable automatic pick and place device. A second semiconductor die 304 is selected by the automatic pick and place device, and is placed on the carrier 330 and positioned in a first row on the carrier 330 with a distance D1 from the first semiconductor die 304. The distance D1 between adjacent semiconductor dies 304 is programmed into the automatic pick and place device and is selected based on the design and specifications of the semiconductor package to be processed. In one embodiment, the gap or distance D1 between adjacent semiconductor dies 304 is 200 μm. A third semiconductor die 304 is selected by the automatic pick and place device, and is placed on the carrier 330 and positioned in a first column on the carrier 330. This pick-and-place operation is repeated until a row of about 107 semiconductor dies 304 is set within the width W1 of the carrier 330.

另一半導體晶粒304會被該自動拾放設備選擇，並且被放置在載體330上以及被定位在載體330上相鄰於該第一列的第二列之中。相鄰列的半導體晶粒304之間的距離D1會被事先選擇並且被程式化至該自動拾放設備之中。於其中一實施例中，第一列半導體晶粒304與第二列半導體晶粒304之間的距離D1為200μm。該拾放操作會重複進行，直到約115 列的半導體晶粒304被設置在載體330的長度L1之中為止。該標準化載體(具有560mm的寬度W1以及600mm的長度L1的載體330)容納約107行以及115列的5mm乘5mm半導體晶粒304，總數量約12,000個半導體晶粒304被設置在載體330上。該拾放操作會重複進行，直到載體330部分或完全被半導體晶粒304佔據為止。該自動拾放設備能夠配合一標準化載體(例如，載體330)裝設任何大小的半導體晶粒於載體330上，用以形成重組式鑲板338。重組式鑲板338接著便能夠利用如同被用來處理重組式鑲板336般地利用相同的載體330及相同的後端處理設備來處理。 Another semiconductor die 304 is selected by the automatic pick and place device, and is placed on the carrier 330 and positioned in the second column adjacent to the first column on the carrier 330. The distance D1 between adjacent rows of semiconductor dies 304 is selected in advance and programmed into the automatic pick and place device. In one embodiment, the distance D1 between the first row of semiconductor dies 304 and the second row of semiconductor dies 304 is 200 μm. This pick and place operation is repeated until about 115 The rows of semiconductor dies 304 are provided up to the length L1 of the carrier 330. The standardized carrier (carrier 330 having a width W1 of 560 mm and a length L1 of 600 mm) accommodates approximately 107 rows and 115 columns of 5 mm by 5 mm semiconductor dies 304, and a total number of approximately 12,000 semiconductor dies 304 are disposed on the carrier 330. This pick and place operation is repeated until the carrier 330 is partially or completely occupied by the semiconductor die 304. The automatic pick-and-place device can be used with a standardized carrier (for example, the carrier 330) to mount semiconductor chips of any size on the carrier 330 to form a reorganized panel 338. The recombination panel 338 can then be processed using the same carrier 330 and the same back-end processing equipment as it is used to process the recombination panel 336.

圖13f中的重組式鑲板336及圖13g中的重組式鑲板338針對重組式鑲板336與重組式鑲板338兩者使用相同的載體330或是使用一具有相同標準化大小的載體。被設計成用於該些重組式晶圓或鑲板之後端處理的處理設備會針對載體330被標準化並且能夠處理被形成在載體330上的重組式晶圓或鑲板的任何配置以及被放置在載體330上的任何大小半導體晶粒。因為重組式鑲板336與338兩者使用相同的標準化載體330，所以，該些重組式鑲板能夠在相同的製造線上被處理。據此，標準化載體330的一用途便係簡化用以製造半導體封裝所需要的設備。 The recombination panel 336 in FIG. 13f and the recombination panel 338 in FIG. 13g use the same carrier 330 for both the recombination panel 336 and the recombination panel 338 or use a carrier having the same standardized size. Processing equipment designed for the rear end processing of these reconstituted wafers or panels will be standardized for the carrier 330 and capable of processing any configuration of the reconstituted wafers or panels formed on the carrier 330 and placed on Any size semiconductor die on the carrier 330. Because the restructured panels 336 and 338 both use the same standardized carrier 330, the restructured panels can be processed on the same manufacturing line. Accordingly, one use of the standardized carrier 330 is to simplify the equipment required for manufacturing a semiconductor package.

於另一範例中，重組式鑲板338包含半導體晶粒294與304，其中，每一個半導體晶粒294與304皆有相同的維度，並且該些半導體晶粒源自具有不同直徑的半導體晶圓290與300。半導體晶圓290具有450mm的直徑，在半導體晶圓290上會形成數量約2,200個獨特的8mm乘8mm半導體晶粒294。具有8mm乘8mm之面積的半導體晶粒294係從一或更多個半導體晶圓290處單體化裁切出來。除此之外，半導體晶圓300具有300mm 的直徑，在半導體晶圓300上會形成數量約900個獨特的8mm乘8mm半導體晶粒304。具有8mm乘8mm之面積的半導體晶粒304係從一或更多個半導體晶圓300處單體化裁切出來。舉例來說，載體330被製備為具有560mm的標準寬度W1以及600mm的標準長度L1。具有560mm之寬度W1的載體330的大小被設計成用以在載體330的寬度W1中容納數量約69個半導體晶粒294或304，它們的面積為8mm乘8mm並且分隔100μm的距離D或D1。具有600mm之長度L1的載體330的大小被設計成用以在載體330的長度L1中容納數量約74個半導體晶粒294或304，它們的面積為8mm乘8mm並且分隔100μm的距離D或D1。載體330的表面積為寬度W1乘以長度L1，容納約5,000個半導體晶粒294或304，它們的面積為8mm乘8mm並且分隔100μm的距離D或D1。多個半導體晶粒294與304能夠被放置在載體330上，半導體晶粒294或304之間的間隙或距離D或D1小於100μm，以便提高載體330上的半導體晶粒294與304的密度並且進一步降低處理半導體晶粒294與304的成本。 In another example, the recombination panel 338 includes semiconductor dies 294 and 304, wherein each of the semiconductor dies 294 and 304 has the same dimensions, and the semiconductor dies are derived from semiconductor wafers having different diameters 290 and 300. The semiconductor wafer 290 has a diameter of 450 mm, and about 2,200 unique 8 mm by 8 mm semiconductor dies 294 are formed on the semiconductor wafer 290. The semiconductor die 294 having an area of 8 mm by 8 mm is cut out from one or more semiconductor wafers 290 by singulation. In addition, the semiconductor wafer 300 has a thickness of 300 mm. Diameter, about 900 unique 8mm by 8mm semiconductor dies 304 will be formed on the semiconductor wafer 300. The semiconductor die 304 having an area of 8 mm by 8 mm is cut out from one or more semiconductor wafers 300 by singulation. For example, the carrier 330 is prepared to have a standard width W1 of 560 mm and a standard length L1 of 600 mm. The size of the carrier 330 having a width W1 of 560 mm is designed to accommodate about 69 semiconductor dies 294 or 304 in the width W1 of the carrier 330, and their area is 8 mm by 8 mm and separated by a distance D or D1 of 100 μm. The size of the carrier 330 having a length L1 of 600 mm is designed to accommodate about 74 semiconductor dies 294 or 304 in the length L1 of the carrier 330, and their area is 8 mm by 8 mm and separated by a distance D or D1 of 100 μm. The surface area of the carrier 330 is the width W1 times the length L1, and contains about 5,000 semiconductor dies 294 or 304, which have an area of 8 mm by 8 mm and are separated by a distance D or D1 of 100 μm. A plurality of semiconductor dies 294 and 304 can be placed on the carrier 330, and the gap or distance D or D1 between the semiconductor dies 294 or 304 is less than 100 μm in order to increase the density of the semiconductor dies 294 and 304 on the carrier 330 and further Reduce the cost of processing the semiconductor dies 294 and 304.

自動拾放設備會被用來以半導體晶粒294與304的數量及大小為基礎並且以載體330的面積為基礎來製備重組式鑲板338。在單體化裁切半導體晶圓300之後，一第一半導體晶粒294或304會被該自動拾放設備選擇。8mm乘8mm的半導體晶粒294或304能夠源自具有450mm直徑的半導體晶圓290或是源自具有300mm直徑的半導體晶圓300。或者，該些8mm乘8mm的半導體晶粒源自具有不同直徑的另一半導體晶圓。一第一半導體晶粒294或304會被裝設至載體330，定位在由該已程式化自動拾放設備所決定的載體330上的某個位置中。一第二半導體晶粒294或304會被該自動 拾放設備選擇，並且被放置在載體330上，被定位在載體330上的第一列之中。相鄰半導體晶粒294或304之間的距離D或D1會被程式化至該自動拾放設備之中並且以要被處理的半導體封裝的設計與規格為基礎被選擇。於其中一實施例中，相鄰半導體晶粒294或304之間的間隙或距離D或D1為100μm。該拾放操作會重複進行，直到一列約69個半導體晶粒294或304被設置在載體330的寬度W1之中為止。 Automatic pick-and-place equipment is used to prepare the recombination panel 338 based on the number and size of the semiconductor dies 294 and 304 and based on the area of the carrier 330. After the semiconductor wafer 300 is singulated, a first semiconductor die 294 or 304 is selected by the automatic pick and place device. The 8 mm by 8 mm semiconductor die 294 or 304 can be derived from a semiconductor wafer 290 having a diameter of 450 mm or from a semiconductor wafer 300 having a diameter of 300 mm. Alternatively, the 8 mm by 8 mm semiconductor dies are derived from another semiconductor wafer having a different diameter. A first semiconductor die 294 or 304 is mounted on the carrier 330 and positioned in a position on the carrier 330 determined by the programmed automatic pick and place device. A second semiconductor die 294 or 304 will be automatically Pick-and-place equipment is selected and placed on the carrier 330, positioned in the first column on the carrier 330. The distance D or D1 between adjacent semiconductor dies 294 or 304 is programmed into the automatic pick and place device and selected based on the design and specifications of the semiconductor package to be processed. In one embodiment, the gap or distance D or D1 between adjacent semiconductor dies 294 or 304 is 100 μm. This pick-and-place operation is repeated until a row of about 69 semiconductor dies 294 or 304 is set within the width W1 of the carrier 330.

另一半導體晶粒294或304會被該自動拾放設備選擇，並且被放置在載體330上以及被定位在載體330上相鄰於該第一列的第二列之中。於其中一實施例中，第一列半導體晶粒294或304與第二列半導體晶粒294或304之間的距離D或D1為100μm。該拾放操作會重複進行，直到約74列的半導體晶粒294或304被設置在載體330的長度L1之中為止。該標準化載體(具有560mm的寬度W1以及600mm的長度L1的載體330)容納約69行以及74列的8mm乘8mm半導體晶粒294與304，總數量約5,000個半導體晶粒294或304被設置在載體330上。該拾放操作會重複進行，直到載體330部分或完全被半導體晶粒294或304佔據為止。所以，重組式鑲板338可以包含從任何大小半導體晶圓處單體化裁切出來的半導體晶粒294與304。載體330的大小不相依於半導體晶粒294與304的大小並且不相依於半導體晶圓290與300的大小。重組式鑲板338能夠如同被用來處理重組式鑲板336般地利用相同的載體330及相同的後端處理設備來處理。針對具有從不同大小進料晶圓處單體化裁切出來之相同大小半導體晶粒的重組式晶圓或鑲板來說，標準化載體330允許相同的材料被用於每一個重組式晶圓或鑲板。所以，用於載體330上的一重組式鑲板336或338的材料清單會維 持不變。一致性且可預測的材料清單提供改善的半導體封裝成本分析與規劃。 Another semiconductor die 294 or 304 is selected by the automatic pick-and-place device, and is placed on the carrier 330 and positioned in the second column adjacent to the first column on the carrier 330. In one embodiment, the distance D or D1 between the first row of semiconductor dies 294 or 304 and the second row of semiconductor dies 294 or 304 is 100 μm. This pick-and-place operation is repeated until about 74 rows of semiconductor dies 294 or 304 are set within the length L1 of the carrier 330. This standardized carrier (carrier 330 with a width W1 of 560mm and a length L1 of 600mm) accommodates approximately 69 rows and 74 columns of 8mm by 8mm semiconductor dies 294 and 304, and a total number of approximately 5,000 semiconductor dies 294 or 304 are provided Carrier 330. This pick and place operation is repeated until the carrier 330 is partially or completely occupied by the semiconductor die 294 or 304. Therefore, the recombination panel 338 may include semiconductor dies 294 and 304 that are singulated and cut from semiconductor wafers of any size. The size of the carrier 330 does not depend on the sizes of the semiconductor dies 294 and 304 and does not depend on the sizes of the semiconductor wafers 290 and 300. The recombination panel 338 can be processed using the same carrier 330 and the same back-end processing equipment as it is used to process the recombination panel 336. For reconstituted wafers or panels with semiconductor wafers of the same size singulated from feed wafers of different sizes, the standardized carrier 330 allows the same material to be used for each reconstituted wafer or panel. Therefore, the bill of materials for a reassembled panel 336 or 338 on the carrier 330 maintains Remain unchanged. A consistent and predictable bill of materials provides improved semiconductor package cost analysis and planning.

於另一實施例中，一重組式鑲板338含有被設置在載體330上的各式各樣半導體晶粒大小。舉例來說，10mm乘10mm的半導體晶粒294被裝設至載體330並且5mm乘5mm的半導體晶粒304被裝設至載體330，以便形成重組式鑲板338。該重組式鑲板在相同的重組式鑲板上含有多種大小的半導體晶粒。換言之，一部分的重組式鑲板338含有其中一種大小的半導體晶粒，而該重組式鑲板的另一部分則含有另一種大小的半導體晶粒。在載體330上同時含有不同大小之半導體晶粒294與304的重組式鑲板338會如同被用來處理具有被設置在載體330上方之均勻大小半導體晶粒的另一重組式鑲板336般地利用相同的後端處理設備來處理。 In another embodiment, a recombination panel 338 contains various semiconductor die sizes disposed on the carrier 330. For example, a semiconductor die 294 of 10 mm by 10 mm is mounted to the carrier 330 and a semiconductor die 304 of 5 mm by 5 mm is mounted to the carrier 330 to form a recombination panel 338. The recombination panel contains semiconductor grains of various sizes on the same recombination panel. In other words, a part of the recombination panel 338 contains semiconductor grains of one size, and another part of the recombination panel contains semiconductor grains of another size. The recombination panel 338 containing semiconductor dies 294 and 304 of different sizes at the same time on the carrier 330 will be treated as another recombination panel 336 having uniformly sized semiconductor dies disposed above the carrier 330. Use the same back-end processing equipment for processing.

總結來說，載體330可容納從各種大小半導體晶圓處單體化裁切出來的各種大小與數量的半導體晶粒。載體330的大小不會隨著正在被處理的半導體晶粒的大小改變。該標準化載體(載體330)的大小固定並且能夠容納多種大小的半導體晶粒。標準化載體330的大小不相依於半導體晶粒或半導體晶圓的維度。相較於較大的半導體晶粒，有更多小型半導體晶粒能夠適配在載體330上。適配在載體330上的半導體晶粒294或304的數量會隨著半導體晶粒294或304的大小以及半導體晶粒294或304之間的間隔或距離D而改變。舉例來說，具有長度L1與寬度W1的載體330在載體330的表面積上方容納5mm乘5mm的半導體晶粒304的數量大於在載體330的表面積上方容納10mm乘10mm的半導體晶粒294的數量。舉例來說，載體330擁有約3,000個10mm乘10mm的半導體晶粒或是約12,000個5mm 乘5mm的半導體晶粒。載體330的大小與形狀保持固定並且不相依於半導體晶粒294或304的大小或是用以單體化裁切出半導體晶粒294或304的半導體晶圓290或300的大小。載體330提供利用一組共同處理設備將重組式鑲板336或338製造成許多不同類型半導體封裝的靈活性，該些不同類型的半導體封裝具有來自不同大小半導體晶圓290與300的不同大小半導體晶粒294與304。 In summary, the carrier 330 can accommodate semiconductor wafers of various sizes and numbers singulated from semiconductor wafers of various sizes. The size of the carrier 330 does not change with the size of the semiconductor die being processed. The standardized carrier (carrier 330) has a fixed size and is capable of accommodating semiconductor dies of various sizes. The size of the standardized carrier 330 does not depend on the dimensions of the semiconductor die or semiconductor wafer. Compared with larger semiconductor dies, there are more small semiconductor dies that can fit on the carrier 330. The number of semiconductor dies 294 or 304 fitted on the carrier 330 will vary with the size of the semiconductor dies 294 or 304 and the interval or distance D between the semiconductor dies 294 or 304. For example, the number of semiconductor dies 304 containing 5 mm by 5 mm above the surface area of the carrier 330 is greater than the number of semiconductor dies 294 containing 10 mm by 10 mm above the surface area of the carrier 330. For example, the carrier 330 has about 3,000 10mm by 10mm semiconductor dies or about 12,000 5mm Multiply the semiconductor die by 5mm. The size and shape of the carrier 330 remains fixed and does not depend on the size of the semiconductor die 294 or 304 or the size of the semiconductor wafer 290 or 300 used to individually cut the semiconductor die 294 or 304. Carrier 330 provides the flexibility to manufacture reassembled panels 336 or 338 into a number of different types of semiconductor packages using a common set of processing equipment, the different types of semiconductor packages having different size semiconductor wafers from different size semiconductor wafers 290 and 300 Grains 294 and 304.

圖13h所示的係利用載體330來製造半導體封裝的製程。處理設備340係被用來在半導體晶粒上實施後端製程，例如，囊封體與絕緣層的沉積、導體層的沉積、凸塊製程(bumping)、回焊製程、標記製程、單體化裁切製程、以及其它後端製程。處理設備340係針對一標準化載體(例如，載體330)的大小與形狀所設計。處理設備340相容於載體330，因為處理設備340的機械性組件與電氣組件係針對載體330的標準化大小與形狀所設計。 The process shown in FIG. 13h uses a carrier 330 to manufacture a semiconductor package. The processing equipment 340 is used to implement back-end processes on the semiconductor die, such as deposition of encapsulation body and insulation layer, deposition of conductor layer, bumping process, reflow process, marking process, singulation Cutting process, and other back-end processes. The processing device 340 is designed for the size and shape of a standardized carrier (eg, the carrier 330). The processing device 340 is compatible with the carrier 330 because the mechanical and electrical components of the processing device 340 are designed for the standardized size and shape of the carrier 330.

處理設備340係由控制系統342所控制。控制系統342能夠為一軟體程式或演算法，其被用來根據載體330上的半導體晶粒的大小與形狀來配置處理設備340。控制系統342會被程式化與客製化，以便讓處理設備340應付被形成在標準化載體330上的每一個不同的重組式晶圓或鑲板，例如，重組式鑲板336與338。 The processing device 340 is controlled by a control system 342. The control system 342 can be a software program or algorithm that is used to configure the processing device 340 according to the size and shape of the semiconductor die on the carrier 330. The control system 342 is programmed and customized to allow the processing equipment 340 to cope with each different reconstituted wafer or panel formed on the standardized carrier 330, such as the reconstituted panels 336 and 338.

藉由標準化載體330的維度，處理設備340能夠維持不變，因為載體330的維度不會隨著半導體晶粒大小與半導體晶圓大小的變動而改變。控制系統342針對載體330上的每一個重組式鑲板使用各種演算法。舉例來說，控制系統342能夠被用來最佳化半導體晶粒294在載體330上之 初始拾放操作期間的間隔。重組式鑲板336的規格會被輸入至控制系統342之中。控制系統342被程式化用以控制處理設備340，以便拾取多個獨特的半導體晶粒294並且將半導體晶粒294放置在載體330上分隔距離D，用以形成重組式鑲板336。舉例來說，重組式鑲板336包含10mm乘10mm的半導體晶粒294以及載體330的標準面積，寬度W1與長度L1。處理設備340被控制系統342配置成用以在重組式鑲板336上實施後端製程，該重組式鑲板336係在載體330上。控制系統342指導處理設備340根據半導體晶粒294的10mm乘10mm大小以及標準大小的載體330來實施沉積以及其它製造步驟。 By standardizing the dimensions of the carrier 330, the processing equipment 340 can remain unchanged because the dimensions of the carrier 330 will not change as the semiconductor die size and semiconductor wafer size change. The control system 342 uses various algorithms for each recombined panel on the carrier 330. For example, the control system 342 can be used to optimize the semiconductor die 294 on the carrier 330. Interval during the initial pick and place operation. The specifications of the reassembled panel 336 are input into the control system 342. The control system 342 is programmed to control the processing equipment 340 to pick up a plurality of unique semiconductor dies 294 and place the semiconductor dies 294 on the carrier 330 separated by a distance D to form a recombination panel 336. For example, the recombination panel 336 includes a semiconductor die 294 of 10 mm by 10 mm and a standard area of the carrier 330, a width W1 and a length L1. The processing device 340 is configured by the control system 342 to perform a back-end process on a reassembled panel 336 that is attached to a carrier 330. The control system 342 instructs the processing device 340 to perform the deposition and other manufacturing steps based on the 10 mm by 10 mm size of the semiconductor die 294 and a standard size carrier 330.

控制系統342允許處理設備340針對標準化載體330上的每一個重組式晶圓或鑲板被客製化。處理設備340不需要針對不同大小的半導體晶粒而被重建。在處理重組式鑲板336之後，處理設備340便準備處理載體330上的另一個重組式鑲板，其具有相同或不同的半導體晶粒大小與間隔。重組式鑲板338的規格會被輸入至控制系統342之中。控制系統342被程式化用以控制處理設備340，以便拾取多個獨特的半導體晶粒304並且將半導體晶粒304放置在載體330上分隔距離D，用以形成重組式鑲板338。舉例來說，重組式鑲板338包含5mm乘5mm的半導體晶粒304以及載體330的標準面積，寬度W1與長度L1。處理設備340被控制系統342配置成用以在重組式鑲板338上實施後端製程，該重組式鑲板338係在載體330上。控制系統342指導處理設備340根據半導體晶粒304的5mm乘5mm大小以及標準大小的載體330來實施沉積以及其它製造步驟。 The control system 342 allows the processing equipment 340 to be customized for each reconstituted wafer or panel on the standardized carrier 330. The processing device 340 does not need to be reconstructed for semiconductor dies of different sizes. After processing the recombination panel 336, the processing device 340 is ready to process another recombination panel on the carrier 330, which has the same or different semiconductor die size and spacing. The specifications of the reassembled panel 338 are input into the control system 342. The control system 342 is programmed to control the processing equipment 340 to pick up a plurality of unique semiconductor dies 304 and place the semiconductor dies 304 on the carrier 330 separated by a distance D to form a recombination panel 338. For example, the recombination panel 338 includes a semiconductor die 304 of 5 mm by 5 mm and a standard area of the carrier 330, a width W1 and a length L1. The processing device 340 is configured by the control system 342 to perform a back-end process on a recombined panel 338 that is attached to a carrier 330. The control system 342 instructs the processing equipment 340 to perform the deposition and other manufacturing steps based on the 5 mm by 5 mm size of the semiconductor die 304 and a standard size carrier 330.

不論處理設備340正在處理重組式鑲板336或338或是標準 化載體330上的其它重組式鑲板，處理設備340皆維持不變。處理設備340為可程式化並且處理設備340可輕易地適應於使用載體330的任何重組式晶圓或鑲板。所以，處理設備340的機械特徵與物理特徵會被設計成用以適應標準化載體330的物理特徵，同時，處理設備340亦可由控制系統342程式化而用以對載體330上的半導體晶粒的任何配置實施製造處理。 Whether processing equipment 340 is processing a reassembled panel 336 or 338 or standard The other reorganized panels on the carrier 330 and the processing equipment 340 remain unchanged. The processing device 340 is programmable and the processing device 340 can be easily adapted to any reconstituted wafer or panel using the carrier 330. Therefore, the mechanical and physical characteristics of the processing device 340 will be designed to adapt to the physical characteristics of the standardized carrier 330. At the same time, the processing device 340 can also be programmed by the control system 342 to apply any Configure the manufacturing process.

處理設備340被用於在載體330上製造來自一重組式晶圓或鑲板的各式各樣半導體封裝。舉例來說，處理設備340能夠被用來將重組式鑲板336或338處理成扇入WLCSP、重組式WLCSP或是eWLCSP、扇出WLCSP、覆晶封裝、3D封裝(例如，PoP)、或是其它半導體封裝。控制系統342被用來修正與控制處理設備340的操作，用以根據要被生產的半導體封裝來實施後端製造步驟。所以，處理設備340能夠被用來製造本文中所述的每一個半導體封裝。處理設備340能夠跨越共用相同大小載體330的多條產品製造線被使用。據此，和半導體晶粒的大小變化、半導體晶圓的大小變化、以及半導體封裝的類型變化相關聯的成本會下降。處理設備340的投資風險會下降，因為當載體330標準化之後，處理設備340的設計會簡化。 The processing equipment 340 is used to manufacture a variety of semiconductor packages on a carrier 330 from a reconstituted wafer or panel. For example, the processing device 340 can be used to process the recombination panel 336 or 338 into fan-in WLCSP, recombined WLCSP or eWLCSP, fan-out WLCSP, flip-chip package, 3D package (e.g., PoP), or Other semiconductor packages. The control system 342 is used to modify and control the operation of the processing device 340 to perform back-end manufacturing steps based on the semiconductor package to be produced. Therefore, the processing device 340 can be used to manufacture each of the semiconductor packages described herein. The processing device 340 can be used across multiple product manufacturing lines that share the same size carrier 330. Accordingly, the costs associated with changes in the size of the semiconductor die, changes in the size of the semiconductor wafer, and changes in the type of the semiconductor package will decrease. The investment risk of the processing device 340 will be reduced because when the carrier 330 is standardized, the design of the processing device 340 will be simplified.

在圖13i中，一囊封體或模製化合物344會利用焊膏印刷塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒294以及載體330的上方。囊封體344能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體344係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。於另一實施例中，囊封體344係一絕緣層或介電層，其含有由 下面所製成的一或更多層：光敏低固化溫度介電光阻、光敏合成光阻、層疊化合物膜、具有填充劑的絕緣膏、焊劑遮罩光阻膜、液體或粒狀模製化合物、聚亞醯胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、膠片、或是具有雷同絕緣特性及結構特性的其它介電材料，它們係利用印刷、旋塗、噴塗、有熱或無熱的真空層疊或壓力層疊、或是其它合宜製程所沉積。於其中一實施例中，囊封體344係一在低於200℃處固化之具有或不具有絕緣填充劑的低溫固化光敏介電聚合物。 In FIG. 13i, an encapsulation body or a molding compound 344 is applied by a solder paste printing coater, a transfer molding coater, a liquid encapsulation body molding coater, a vacuum lamination coater, and a spin coater. A coating machine, or other suitable coating machine, is deposited over the semiconductor die 294 and the carrier 330. The encapsulation body 344 can be a polymer synthetic material, for example, an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulation body 344 is non-conducting and provides environmental protection for the semiconductor device, and is protected from external elements and contaminants. In another embodiment, the encapsulation body 344 is an insulating layer or a dielectric layer. One or more layers made of: photosensitive low curing temperature dielectric photoresist, photosensitive synthetic photoresist, laminated compound film, insulating paste with filler, solder mask photoresist film, liquid or granular molding compound , Polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, film, or other dielectric materials with similar insulation and structural characteristics, they are printed, spin-coated, sprayed, thermally or Heatless vacuum stacking or pressure stacking, or other suitable processes. In one embodiment, the encapsulation body 344 is a low-temperature-curable photosensitive dielectric polymer cured with or without an insulating filler at a temperature below 200 ° C.

明確地說，囊封體344沿著半導體晶粒294的側表面324被設置並且因而覆蓋半導體晶粒294的每一個側表面324。據此，囊封體344覆蓋或接觸半導體晶粒294的至少四個表面，也就是，半導體晶粒294的四個側表面324。囊封體344還覆蓋半導體晶粒294的背表面310。囊封體344保護半導體晶粒294，避免因曝露在來自光或其它輻射的光子的關係而受損。於其中一實施例中，囊封體344為不透明並且為暗色或黑色。圖13i所示的係被囊封體344覆蓋的合成基板或重組式鑲板336。囊封體344能夠被用於雷射標記重組式鑲板336，以便進行對齊與單體化裁切。囊封體344被形成在半導體晶粒294的背表面310上方並且會在後續的背研磨步驟中被薄化。囊封體344亦能夠被沉積而使得該囊封體與背表面310共面並且不會覆蓋該背表面。 Specifically, the encapsulation body 344 is provided along the side surface 324 of the semiconductor die 294 and thus covers each side surface 324 of the semiconductor die 294. Accordingly, the encapsulation body 344 covers or contacts at least four surfaces of the semiconductor die 294, that is, the four side surfaces 324 of the semiconductor die 294. The encapsulation body 344 also covers the back surface 310 of the semiconductor die 294. The encapsulation body 344 protects the semiconductor die 294 from damage caused by exposure to photons from light or other radiation. In one embodiment, the encapsulation body 344 is opaque and dark or black. The synthetic substrate or recombination panel 336 covered by the encapsulation body 344 shown in FIG. 13i. The encapsulation body 344 can be used for laser marking recombination panels 336 for alignment and singulation cutting. The encapsulation body 344 is formed over the back surface 310 of the semiconductor die 294 and will be thinned in a subsequent back grinding step. The encapsulation body 344 can also be deposited such that the encapsulation body is coplanar with the back surface 310 and does not cover the back surface.

在圖13j中，囊封體344的背側表面346會以研磨機345進行研磨操作，用以平坦化且縮減囊封體344的厚度。化學蝕刻亦會被用來移除與平坦化囊封體344並且用以形成平坦的背側表面347。於其中一實施例中，囊封體344的厚度維持覆蓋在半導體晶粒294的背表面310上方。於 其中一實施例中，在沉積或背研磨之後殘留在半導體晶粒294的背表面310上方的囊封體344的厚度範圍從約170μm至230μm或更小。於另一實施例中，殘留在半導體晶粒294的背表面310上方的囊封體344的厚度範圍從約5μm 150μm。反向於背側表面346的囊封體344的表面348被設置在載體330與介面層332上方，俾使得囊封體344的表面348可以共面於半導體晶粒294的主動表面312。 In FIG. 13j, the back surface 346 of the encapsulation body 344 is ground by a grinder 345 to flatten and reduce the thickness of the encapsulation body 344. Chemical etching is also used to remove and planarize the encapsulation body 344 and to form a flat backside surface 347. In one embodiment, the thickness of the encapsulation body 344 is maintained to cover the back surface 310 of the semiconductor die 294. to In one embodiment, the thickness of the encapsulation body 344 remaining above the back surface 310 of the semiconductor die 294 after deposition or back grinding ranges from about 170 μm to 230 μm or less. In another embodiment, the thickness of the encapsulation body 344 remaining above the back surface 310 of the semiconductor die 294 ranges from about 5 μm to 150 μm. The surface 348 of the encapsulation body 344 opposite to the back surface 346 is disposed above the carrier 330 and the interface layer 332, so that the surface 348 of the encapsulation body 344 can be coplanar with the active surface 312 of the semiconductor die 294.

圖13k所示的係一替代的背研磨步驟，其中，囊封體344從半導體晶粒294的背表面310處被完全移除。在完成圖13k中的研磨操作之後，半導體晶粒294的背表面310會露出。半導體晶粒294的厚度同樣會因該研磨操作而縮減。於其中一實施例中，半導體晶粒294的厚度從225μm至305μm或更小。 An alternative back grinding step is shown in FIG. 13k, in which the encapsulant 344 is completely removed from the back surface 310 of the semiconductor die 294. After the grinding operation in FIG. 13k is completed, the back surface 310 of the semiconductor die 294 is exposed. The thickness of the semiconductor die 294 is also reduced due to the grinding operation. In one embodiment, the thickness of the semiconductor die 294 is from 225 μm to 305 μm or less.

在圖13l中，絕緣層或鈍化層349會在圖13k中的背研磨步驟完成之後被形成在囊封體344以及半導體晶粒294的背表面310上方。絕緣層349含有由下面所製成的一或更多層：光敏低固化溫度介電光阻、光敏合成光阻、層疊化合物膜、具有填充劑的絕緣膏、焊劑遮罩光阻膜、液體模製化合物、粒狀模製化合物、聚亞醯胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、膠片、或是具有雷同絕緣特性及結構特性的其它介電材料。絕緣層349係利用印刷、旋塗、噴塗、有熱或無熱的真空層疊或壓力層疊、或是其它合宜製程所沉積。於其中一實施例中，絕緣層349係一在低於200℃處固化之具有或不具有絕緣填充劑的低溫固化光敏介電聚合物。絕緣層349係一背側保護層並且為半導體晶粒294提供機械保護並且避免受光破壞。於其中一實施例中，絕緣層349的厚度範圍從約5至150μ m。 In FIG. 13l, an insulating layer or a passivation layer 349 is formed over the back surface 310 of the encapsulation body 344 and the semiconductor die 294 after the back grinding step in FIG. 13k is completed. Insulating layer 349 contains one or more of the following: photosensitive low curing temperature dielectric photoresist, photosensitive synthetic photoresist, laminated compound film, insulating paste with filler, solder mask photoresist film, liquid mold Compounds, granular molding compounds, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, film, or other dielectric materials with similar insulation and structural characteristics. The insulating layer 349 is deposited by printing, spin coating, spray coating, vacuum lamination with or without heat or pressure lamination, or other suitable processes. In one embodiment, the insulating layer 349 is a low-temperature-curable photosensitive dielectric polymer cured with or without an insulating filler at a temperature lower than 200 ° C. The insulating layer 349 is a backside protective layer and provides mechanical protection for the semiconductor die 294 and is protected from light damage. In one embodiment, the thickness of the insulating layer 349 ranges from about 5 to 150 μ. m.

載體330與介面層332會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，以便露出絕緣層316、導體層314、以及囊封體344的表面348。 The carrier 330 and the interface layer 332 are removed by chemical etching, mechanical peeling, CMP, mechanical polishing, thermal baking, UV light, laser scanning, or wet removal to expose the insulating layer 316, The conductive layer 314 and the surface 348 of the encapsulation body 344.

在圖13m中，一絕緣層或鈍化層350係利用PVD、CVD、印刷、旋塗、噴塗、網印、或是層疊被形成在絕緣層316和導體層314的上方。絕緣層350能夠係由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層350係一在低於200℃處被低溫固化之光敏介電聚合物。於其中一實施例中，絕緣層350被形成在半導體晶粒294的覆蓋區裡面並且不會延伸超過半導體晶粒294的覆蓋區而且被形成在囊封體344的表面348上方。換言之，相鄰於半導體晶粒294的半導體晶粒294的一周邊區域沒有絕緣層350。於另一實施例中，絕緣層350被形成在絕緣層316、半導體晶粒294、以及囊封體344的表面348的上方，並且在囊封體344的表面348上方的一部分絕緣層350會利用一已圖樣化光阻層藉由蝕刻製程或是藉由LDA被移除。一部分的絕緣層350會利用一已圖樣化光阻層被一蝕刻製程移除或是藉由LDA來移除，用以形成多個開口352，以便露出導體層314。 In FIG. 13m, an insulating layer or passivation layer 350 is formed over the insulating layer 316 and the conductor layer 314 by PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 350 can be made of one or more layers made of the following: SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating properties and structural properties. In one embodiment, the insulating layer 350 is a photosensitive dielectric polymer that is cured at a temperature lower than 200 ° C. In one embodiment, the insulating layer 350 is formed inside the coverage area of the semiconductor die 294 and does not extend beyond the coverage area of the semiconductor die 294 and is formed over the surface 348 of the encapsulation body 344. In other words, a peripheral region of the semiconductor die 294 adjacent to the semiconductor die 294 has no insulating layer 350. In another embodiment, the insulating layer 350 is formed over the insulating layer 316, the semiconductor die 294, and the surface 348 of the encapsulation body 344, and a part of the insulating layer 350 above the surface 348 of the encapsulation body 344 is used. A patterned photoresist layer is removed by an etching process or by LDA. A part of the insulating layer 350 is removed by an etching process using a patterned photoresist layer or by LDA to form a plurality of openings 352 to expose the conductive layer 314.

在圖13n中，一導電層354會利用諸如印刷、PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化與金屬沉積製程被形成在絕緣層350與導體層314的上方。導體層354能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ti、Ni、Au、Ag、W、或是其它合宜的導電材料。一部分的導體層354沿著絕緣層350並且平行於半導體晶粒294的主動表面312 水平延伸，以便橫向重新分佈該電氣互連線至導體層314。導體層354的操作如同用於半導體晶粒294之電氣信號的RDL。導體層354被形成在半導體晶粒294的一覆蓋區上方並且不會延伸超過半導體晶粒294的該覆蓋區或是延伸在囊封體344的表面348上方。換言之，相鄰於半導體晶粒294的半導體晶粒294的一周邊區域沒有導體層354，俾使得囊封體344的表面348仍保持從導體層354處露出。一部分的導體層354被電氣連接至導體層314。導體層354的其它部分則相依於半導體晶粒294的連接而共電或是被電氣隔離。 In FIG. 13n, a conductive layer 354 is formed over the insulating layer 350 and the conductor layer 314 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolyte plating, and electrodeless plating. The conductive layer 354 can be made of one or more layers made of Al, Cu, Sn, Ti, Ni, Au, Ag, W, or other suitable conductive materials. A portion of the conductor layer 354 runs along the insulating layer 350 and is parallel to the active surface 312 of the semiconductor die 294 Extend horizontally to redistribute the electrical interconnection lines laterally to the conductor layer 314. The conductor layer 354 operates like an RDL for electrical signals of the semiconductor die 294. The conductive layer 354 is formed over a coverage area of the semiconductor die 294 and does not extend beyond the coverage area of the semiconductor die 294 or over the surface 348 of the encapsulation body 344. In other words, there is no conductive layer 354 in a peripheral region of the semiconductor die 294 adjacent to the semiconductor die 294, so that the surface 348 of the encapsulation body 344 remains exposed from the conductive layer 354. A part of the conductor layer 354 is electrically connected to the conductor layer 314. The other parts of the conductor layer 354 are electrically connected or electrically isolated depending on the connection of the semiconductor die 294.

一絕緣層或鈍化層356會利用下面方法被形成在絕緣層350和導體層354的上方：PVD、CVD、印刷、旋塗、噴塗、網印、或是層疊。絕緣層356能夠係由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層356係一在低於200℃處被低溫固化的光敏介電質聚合物。於其中一實施例中，絕緣層356被形成在半導體晶粒294的覆蓋區裡面並且不會延伸超過囊封體344上方的半導體晶粒294的覆蓋區。換言之，相鄰於半導體晶粒294的半導體晶粒294的一周邊區域不會有絕緣層356，俾使得囊封體344的表面348仍保持從絕緣層356處露出。於另一實施例中，絕緣層356被形成在絕緣層316、半導體晶粒294、以及囊封體344的上方，並且在囊封體344上方的一部分絕緣層350會利用一已圖樣化光阻層被一蝕刻製程移除或是藉由LDA來移除。一部分絕緣層350會利用一已圖樣化光阻層被一蝕刻製程移除或是藉由LDA來移除，用以形成多個開口358，以便露出導體層354。 An insulating layer or passivation layer 356 is formed on the insulating layer 350 and the conductive layer 354 by the following methods: PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 356 can be made of one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating properties and structural properties. In one embodiment, the insulating layer 356 is a photosensitive dielectric polymer that is cured at a temperature lower than 200 ° C. In one embodiment, the insulating layer 356 is formed inside the coverage area of the semiconductor die 294 and does not extend beyond the coverage area of the semiconductor die 294 above the encapsulation body 344. In other words, there is no insulating layer 356 in a peripheral region of the semiconductor die 294 adjacent to the semiconductor die 294, so that the surface 348 of the encapsulation body 344 remains exposed from the insulating layer 356. In another embodiment, the insulating layer 356 is formed over the insulating layer 316, the semiconductor die 294, and the encapsulation body 344, and a portion of the insulation layer 350 above the encapsulation body 344 uses a patterned photoresist The layer is removed by an etching process or by LDA. A part of the insulating layer 350 is removed by an etching process using a patterned photoresist layer or by LDA to form a plurality of openings 358 to expose the conductive layer 354.

在圖13o中，一導電層360會在最終重新鈍化之後利用PVD、CVD、蒸發、電解質電鍍、無電極電鍍、或是其它合宜的金屬沉積製程被形成在導體層354的裸露部分上方以及絕緣層356的上方。導體層360能夠為Al、Cu、Sn、Ti、Ni、Au、Ag、W、或是其它合宜的導電材料。導體層360係一UBM，其被電氣連接至導體層354與314。UBM 360能夠係一具有黏著層、屏障層、以及晶種層或潤濕層的多金屬堆疊。黏著層係被形成在導體層354的上方並且能夠為Ti、TiN、TiW、Al、或是Cr。屏障層係被形成在黏著層的上方並且能夠為Ni、NiV、Pt、Pd、TiW、Ti、或是CrCu。該屏障層會阻止Cu擴散至半導體晶粒294的主動表面312之中。晶種層係被形成在屏障層的上方並且能夠為Cu、Ni、NiV、Au、或是Al。UBM 360為導體層354提供一低阻值互連線，並且提供一屏障阻止焊料擴散，以及提供用於焊料潤濕的晶種層。 In FIG. 13o, a conductive layer 360 is formed over the exposed portion of the conductive layer 354 and the insulating layer using PVD, CVD, evaporation, electrolyte plating, electrodeless plating, or other suitable metal deposition processes after final repassivation. Above 356. The conductive layer 360 can be Al, Cu, Sn, Ti, Ni, Au, Ag, W, or other suitable conductive materials. The conductor layer 360 is a UBM, which is electrically connected to the conductor layers 354 and 314. UBM 360 can be a multi-metal stack with an adhesion layer, a barrier layer, and a seed layer or a wetting layer. The adhesive layer system is formed above the conductor layer 354 and can be Ti, TiN, TiW, Al, or Cr. The barrier layer is formed above the adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti, or CrCu. The barrier layer prevents Cu from diffusing into the active surface 312 of the semiconductor die 294. The seed layer system is formed over the barrier layer and can be Cu, Ni, NiV, Au, or Al. UBM 360 provides a low-resistance interconnect for conductor layer 354, and a barrier to prevent solder diffusion, and a seed layer for solder wetting.

一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層360的上方。於其中一實施例中，該凸塊材料係利用一丸滴模板來沉積，也就是，不需要用到任何遮罩。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層360。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊362。於某些應用中，凸塊362會被二次回焊，以便改良和導體層360的電氣接觸效果。凸塊362亦能夠被壓縮焊接或熱壓縮焊接至導體層360。凸塊362代表能夠 被形成在導體層360上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。雷射標記能夠在凸塊成形之前或之後或是在移除載體330之後被實施。 A conductive bump material is deposited on the conductive layer 360 by an evaporation process, an electrolytic plating process, an electrodeless plating process, a pill process, or a screen printing process. In one embodiment, the bump material is deposited using a drop template, that is, no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and a combination thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high-lead solder, or a lead-free solder. The bump material is soldered to the conductor layer 360 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 362. In some applications, the bump 362 is re-soldered in order to improve the electrical contact with the conductive layer 360. The bump 362 can also be compression welded or thermally compressed to the conductor layer 360. Bump 362 represents capable One of the types of interconnect structures formed over the conductor layer 360. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines. The laser marking can be implemented before or after the bump is formed or after the carrier 330 is removed.

絕緣層350與356、導體層354與360、以及凸塊362一起構成被形成在半導體晶粒294上方及半導體晶粒294的一覆蓋區裡面的增進互連結構366。相鄰於半導體晶粒294的半導體晶粒294的一周邊區域不會有互連結構366，俾使得囊封體344的表面348仍保持從互連結構366處露出。增進互連結構366可以僅包含一RDL或導體層(例如，導體層354)以及一絕緣層(例如，絕緣層350)。額外的絕緣層和RDL會在形成凸塊362之前被形成在絕緣層356的上方，以便根據半導體晶粒294的設計和功能在該封裝中提供額外的垂直與水平電氣連接。 The insulating layers 350 and 356, the conductor layers 354 and 360, and the bumps 362 together form an enhanced interconnect structure 366 formed over the semiconductor die 294 and in a footprint of the semiconductor die 294. A peripheral region of the semiconductor die 294 adjacent to the semiconductor die 294 does not have the interconnect structure 366, so that the surface 348 of the encapsulation body 344 remains exposed from the interconnect structure 366. The enhanced interconnect structure 366 may include only an RDL or conductor layer (eg, the conductor layer 354) and an insulation layer (eg, the insulation layer 350). An additional insulating layer and RDL are formed over the insulating layer 356 before forming the bumps 362 to provide additional vertical and horizontal electrical connections in the package based on the design and function of the semiconductor die 294.

在圖13p中，半導體晶粒294會利用鋸片或雷射削切工具370被單體化裁切貫穿囊封體344成為個別的eWLCSP 372。eWLCSP 372會在單體化裁切之前或之後進行電氣測試。重組式鑲板336會被單體化裁切成多個eWLCSP 372，用以在半導體晶粒294的側表面324上方留下一薄層的囊封體344。或者，重組式鑲板336會被單體化裁切而從側表面324處完全移除囊封體344。 In FIG. 13p, the semiconductor die 294 is singulated and cut through the encapsulation body 344 into individual eWLCSP 372 using a saw blade or a laser cutting tool 370. The eWLCSP 372 undergoes electrical testing before or after singulation cutting. The recombination panel 336 is singulated and cut into a plurality of eWLCSP 372 to leave a thin layer of encapsulation body 344 above the side surface 324 of the semiconductor die 294. Alternatively, the recombination panel 336 may be singulated to completely remove the encapsulation body 344 from the side surface 324.

圖14所示的係在單體化裁切之後的eWLCSP 372，其具有一位在該半導體晶粒294之側壁324上方的囊封體以及一位在背表面310上方的絕緣層349。半導體晶粒294經由導體層314、354、以及360被電氣連接至凸塊362，以便經由互連結構366達到外部互連的目的。互連結構366不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。背側 絕緣層349被形成在半導體晶粒294的背表面310上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。 The eWLCSP 372 shown in FIG. 14 after singulation cutting has an encapsulation body above the sidewall 324 of the semiconductor die 294 and an insulation layer 349 above the back surface 310. The semiconductor die 294 is electrically connected to the bump 362 via the conductor layers 314, 354, and 360 so as to achieve the purpose of external interconnection via the interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. Dorsal An insulating layer 349 is formed over the back surface 310 of the semiconductor die 294 to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation.

囊封體344覆蓋半導體晶粒294的側表面324，用以保護半導體晶粒294，避免因曝露在來自光或其它輻射的光子的關係而受損。在eWLCSP 372中，位在側表面324上方的囊封體344的厚度小於150μm。於其中一實施例中，eWLCSP 372的體積為長度4.595mm x寬度4.025mm x高度0.470mm，凸塊362的節距為0.4mm，其中，半導體晶粒294的面積為長度4.445mm以及寬度3.875mm。於另一實施例中，位在半導體晶粒294的側表面324上方的囊封體344的厚度為75μm或更小。eWLCSP 372的體積為長度6.075mm x寬度6.075mm x高度0.8mm，凸塊362的節距為0.5mm，其中，半導體晶粒294的體積為長度6.0mm x寬度6.0mm x高度0.470mm。於又一實施例中，eWLCSP 372的體積為長度5.92mm x寬度5.92mm x高度0.765mm，凸塊362的節距為0.5mm，其中，半導體晶粒294的體積為長度5.75mm x寬度5.75mm x高度0.535mm。於另一實施例中，位在半導體晶粒294的側表面324上方的囊封體344的厚度為25μm或更小。於又一實施例中，位在半導體晶粒294的側表面324上方的囊封體344的厚度為約50μm或更小。eWLCSP 372係利用針對單一標準化載體大小所設計的設備藉由在標準化載體330上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 372的設備成本與材料成本。eWLCSP 372係利用標準化載體330以較高的數量來製造，從而簡化製造過程並且降低單元成本。 The encapsulation body 344 covers the side surface 324 of the semiconductor die 294 to protect the semiconductor die 294 from damage caused by exposure to photons from light or other radiation. In eWLCSP 372, the thickness of the encapsulation body 344 located above the side surface 324 is less than 150 μm. In one embodiment, the volume of the eWLCSP 372 is 4.595 mm in length x 4.025 mm in width x 0.470 mm in height, and the pitch of the bumps 362 is 0.4 mm. The area of the semiconductor die 294 is 4.445 mm in length and 3.875 mm in width. . In another embodiment, the thickness of the encapsulation body 344 located above the side surface 324 of the semiconductor die 294 is 75 μm or less. The volume of the eWLCSP 372 is 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and the pitch of the bumps 362 is 0.5 mm. The volume of the semiconductor die 294 is 6.0 mm in length x 6.0 mm in width x 0.470 mm in height. In yet another embodiment, the volume of the eWLCSP 372 is 5.92 mm in length x 5.92 mm in width x 0.765 mm in height, and the pitch of the bumps 362 is 0.5 mm, wherein the volume of the semiconductor die 294 is 5.75 mm in length x 5.75 mm in width x height 0.535mm. In another embodiment, the thickness of the encapsulation body 344 located above the side surface 324 of the semiconductor die 294 is 25 μm or less. In yet another embodiment, the thickness of the encapsulation body 344 located above the side surface 324 of the semiconductor die 294 is about 50 μm or less. The eWLCSP 372 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 330, which will reduce the equipment cost and material cost of the eWLCSP 372. The eWLCSP 372 is manufactured in a higher quantity using a standardized carrier 330, thereby simplifying the manufacturing process and reducing unit costs.

圖15所示的係一替代的eWLCSP 380，其具有位在半導體晶粒294的背表面310上方的絕緣層349以及半導體晶粒294的裸露側壁324。 半導體晶粒294經由導體層314、354、以及360被電氣連接至凸塊362，以便經由互連結構366達到外部互連的目的。互連結構366不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。背側絕緣層349被形成在半導體晶粒294的背表面310上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。囊封體344在單體化裁切期間從半導體晶粒294的側表面324處被完全移除，以便露出側表面324。eWLCSP 380的長度與寬度和半導體晶粒294的長度與寬度相同。於其中一實施例中，eWLCSP 380的面積為約長度4.4mm x寬度3.9mm，凸塊362的節距為0.35至0.50mm。eWLCSP 380係利用針對單一標準化載體大小所設計的設備藉由在標準化載體330上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 380的設備成本與材料成本。eWLCSP 380係利用標準化載體330以較高的數量來製造，從而簡化製造過程並且降低單元成本。 An alternative eWLCSP 380 shown in FIG. 15 has an insulating layer 349 located above the back surface 310 of the semiconductor die 294 and an exposed sidewall 324 of the semiconductor die 294. The semiconductor die 294 is electrically connected to the bump 362 via the conductor layers 314, 354, and 360 so as to achieve the purpose of external interconnection via the interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The back-side insulating layer 349 is formed over the back surface 310 of the semiconductor die 294 to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation. The encapsulation body 344 is completely removed from the side surface 324 of the semiconductor die 294 during singulation cutting so as to expose the side surface 324. The length and width of the eWLCSP 380 and the length and width of the semiconductor die 294 are the same. In one embodiment, the area of the eWLCSP 380 is about 4.4 mm in length x 3.9 mm in width, and the pitch of the bumps 362 is 0.35 to 0.50 mm. The eWLCSP 380 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 330, which will reduce the equipment cost and material cost of the eWLCSP 380. The eWLCSP 380 series is manufactured in high quantities using standardized carriers 330, thereby simplifying the manufacturing process and reducing unit costs.

圖16所示的係另一eWLCSP 384，其具有被形成在半導體晶粒294的背表面310與側壁324上方的囊封體344。半導體晶粒294經由導體層314、354、以及360被電氣連接至凸塊362，以便經由互連結構366達到外部互連的目的。互連結構366不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體344在圖13j中所示的研磨操作之後仍殘留在半導體晶粒294的背表面310上方。在單體化裁切之後，囊封體344殘留在半導體晶粒294的側表面324上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。所以，囊封體344被形成在半導體晶粒294的五個側邊上方，也就是，在四個側表面324上方以及在背表面310上方。在半導體晶粒294的背表面310上方的囊封體 344省略背側保護層或背側疊板的需求，因而降低eWLCSP 384的成本。 Another eWLCSP 384 shown in FIG. 16 has an encapsulation body 344 formed on the back surface 310 and the side wall 324 of the semiconductor die 294. The semiconductor die 294 is electrically connected to the bump 362 via the conductor layers 314, 354, and 360 so as to achieve the purpose of external interconnection via the interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 344 remains over the back surface 310 of the semiconductor die 294 after the grinding operation shown in FIG. 13j. After the singulation cutting, the encapsulation body 344 remains on the side surface 324 of the semiconductor die 294 to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation. Therefore, the encapsulation body 344 is formed above the five sides of the semiconductor die 294, that is, above the four side surfaces 324 and above the back surface 310. Encapsulation body over back surface 310 of semiconductor die 294 The 344 eliminates the need for a backside protective layer or a backside stack, thereby reducing the cost of the eWLCSP 384.

在eWLCSP 384中，側表面324上方的囊封體344的厚度小於150μm。於其中一實施例中，eWLCSP 384的體積為長度4.595mm x寬度4.025mm x高度0.470mm，凸塊362的節距為0.4mm，其中，半導體晶粒294的面積為長度4.445mm x寬度3.875mm。於另一實施例中，半導體晶粒294的側表面324上方的囊封體344的厚度為75μm或更小。eWLCSP 384的體積為長度6.075mm x寬度6.075mm x高度0.8mm，凸塊362的節距為0.5mm，其中，半導體晶粒294的體積為長度6.0mm x寬度6.05mm x高度0.470mm。於又一實施例中，eWLCSP 384的體積為長度5.92mm x寬度5.92mm x高度0.765mm，凸塊362的節距為0.5mm，其中，半導體晶粒294的體積為長度5.75mm x寬度5.75mm x高度0.535mm。於另一實施例中，半導體晶粒294的側表面324上方的囊封體344的厚度為25μm或更小。於又一實施例中，半導體晶粒294的側表面324上方的囊封體344的厚度為約50μm或更小。eWLCSP 384係利用針對單一標準化載體大小所設計的設備藉由在標準化載體330上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 384的設備成本與材料成本。eWLCSP 384係利用標準化載體330以較高的數量來製造，從而簡化製造過程並且降低單元成本。 In eWLCSP 384, the thickness of the encapsulation body 344 above the side surface 324 is less than 150 μm. In one embodiment, the volume of the eWLCSP 384 is 4.595mm in length x 4.025mm in width x 0.470mm in height, and the pitch of the bumps 362 is 0.4mm, wherein the area of the semiconductor die 294 is 4.445mm in length x 3.875mm in width . In another embodiment, the thickness of the encapsulation body 344 above the side surface 324 of the semiconductor die 294 is 75 μm or less. The volume of the eWLCSP 384 is 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and the pitch of the bumps 362 is 0.5 mm. The volume of the semiconductor die 294 is 6.0 mm in length x 6.05 mm in width x 0.470 mm in height. In yet another embodiment, the volume of the eWLCSP 384 is 5.92mm in length x 5.92mm in width x 0.765mm in height, and the pitch of the bumps 362 is 0.5mm, wherein the volume of the semiconductor die 294 is 5.75mm in length x 5.75mm in width x height 0.535mm. In another embodiment, the thickness of the encapsulation body 344 above the side surface 324 of the semiconductor die 294 is 25 μm or less. In yet another embodiment, the thickness of the encapsulation body 344 above the side surface 324 of the semiconductor die 294 is about 50 μm or less. The eWLCSP 384 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 330, which will reduce the equipment cost and material cost of the eWLCSP 384. The eWLCSP 384 is manufactured in a higher quantity using a standardized carrier 330, thereby simplifying the manufacturing process and reducing unit costs.

圖17所示的係另一eWLCSP 386，其具有背側囊封體以及裸露的側壁。半導體晶粒294經由導體層314、354、以及360被電氣連接至凸塊362，以便經由互連結構366達到外部互連的目的。互連結構366不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體344在圖13j中所示的研磨操作之後仍殘留在半導體晶粒294的背表面310上 方。在半導體晶粒294的背表面310上方的囊封體344省略背側保護層或背側疊板的需求，因而降低eWLCSP 386的成本。囊封體344在單體化裁切期間從半導體晶粒294的側表面324處被完全移除，以便露出側表面324。eWLCSP 386的長度與寬度和半導體晶粒294的長度與寬度相同。於其中一實施例中，eWLCSP 386的面積為約長度4.445mm x寬度3.875mm，凸塊362的節距為0.35至0.50mm。eWLCSP 386係利用針對單一標準化載體大小所設計的設備藉由在標準化載體330上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 386的設備成本與材料成本。eWLCSP 386係利用標準化載體330以較高的數量來製造，從而簡化製造過程並且降低單元成本。 FIG. 17 shows another eWLCSP 386, which has a dorsal encapsulation body and an exposed sidewall. The semiconductor die 294 is electrically connected to the bump 362 via the conductor layers 314, 354, and 360 so as to achieve the purpose of external interconnection via the interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 344 remains on the back surface 310 of the semiconductor die 294 after the grinding operation shown in FIG. 13j square. The encapsulation body 344 above the back surface 310 of the semiconductor die 294 omits the need for a backside protection layer or a backside stack, thereby reducing the cost of the eWLCSP 386. The encapsulation body 344 is completely removed from the side surface 324 of the semiconductor die 294 during singulation cutting so as to expose the side surface 324. The length and width of the eWLCSP 386 and the length and width of the semiconductor die 294 are the same. In one embodiment, the area of the eWLCSP 386 is approximately 4.445 mm in length x 3.875 mm in width, and the pitch of the bumps 362 is 0.35 to 0.50 mm. The eWLCSP 386 is manufactured using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 330, which will reduce the equipment cost and material cost of the eWLCSP 386. The eWLCSP 386 series is manufactured in higher quantities using standardized carriers 330, thereby simplifying the manufacturing process and reducing unit costs.

圖18所示的係另一eWLCSP 388，其具有半導體晶粒294的裸露背表面310以及側壁324。半導體晶粒294經由導體層314、354、以及360被電氣連接至凸塊362，以便經由互連結構366達到外部互連的目的。互連結構366不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體344在圖13k中所示的研磨操作期間從半導體晶粒294的背表面310處被完全移除。囊封體344在單體化裁切期間從半導體晶粒294的側表面324處被完全移除，以便露出側表面324。在eWLCSP 388中沒有任何囊封體344殘留覆蓋半導體晶粒294的表面。eWLCSP 388的長度與寬度和半導體晶粒294的長度與寬度相同。於其中一實施例中，eWLCSP 388的面積為約長度4.4mm x寬度3.9mm，凸塊362的節距為0.35至0.50mm。eWLCSP 388係利用針對單一標準化載體大小所設計的設備藉由在標準化載體330上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 388的設備成本與材料成本。eWLCSP 388係利用標準化載體330以較高的數量來製造， 從而簡化製造過程並且降低單元成本。 Another eWLCSP 388 shown in FIG. 18 has an exposed back surface 310 and a sidewall 324 of the semiconductor die 294. The semiconductor die 294 is electrically connected to the bump 362 via the conductor layers 314, 354, and 360 so as to achieve the purpose of external interconnection via the interconnect structure 366. The interconnect structure 366 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 344 is completely removed from the back surface 310 of the semiconductor die 294 during the grinding operation shown in FIG. 13k. The encapsulation body 344 is completely removed from the side surface 324 of the semiconductor die 294 during singulation cutting so as to expose the side surface 324. In the eWLCSP 388, no encapsulation body 344 remains to cover the surface of the semiconductor die 294. The length and width of the eWLCSP 388 and the length and width of the semiconductor die 294 are the same. In one embodiment, the area of the eWLCSP 388 is about 4.4 mm in length x 3.9 mm in width, and the pitch of the bumps 362 is 0.35 to 0.50 mm. The eWLCSP 388 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 330, which will reduce the equipment cost and material cost of the eWLCSP 388. eWLCSP 388 is manufactured using standardized carrier 330 in higher quantities. This simplifies the manufacturing process and reduces unit costs.

圖19a至19k配合圖1以及2a至2c顯示一種形成重組式或嵌入式扇入WLCSP的製程。接續圖13b，圖19a所示的係一部分半導體晶圓290的剖視圖。導體層314被形成在半導體晶粒294的主動表面312的上方。絕緣層316被形成在主動表面312與導體層314的上方，有多個開口被形成貫穿絕緣層316，用以露出導體層314。 Figures 19a to 19k in conjunction with Figures 1 and 2a to 2c show a process for forming a recombined or embedded fan-in WLCSP. 13b and 19a are cross-sectional views of a portion of the semiconductor wafer 290. The conductor layer 314 is formed above the active surface 312 of the semiconductor die 294. The insulating layer 316 is formed above the active surface 312 and the conductor layer 314, and a plurality of openings are formed through the insulating layer 316 to expose the conductor layer 314.

在圖19a中，一絕緣層410被形成在絕緣層316和導體層314的上方。絕緣層410含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。絕緣層410係利用PVD、CVD、印刷、旋塗、噴塗、燒結、熱氧化、或是其它合宜製程所沉積。於其中一實施例中，絕緣層410係一在低於200℃處被低溫固化的光敏介電質聚合物。於其中一實施例中，絕緣層410被形成在絕緣層316、半導體晶粒294的上方以及基礎半導體材料292上方的半導體晶粒294的一覆蓋區外面。換言之，相鄰於半導體晶粒294的半導體晶粒294的一周邊區域包含絕緣層410。一部分絕緣層410會藉由曝光或顯影製程、LDA、蝕刻、或是其它合宜的製程來移除，用以形成多個開口412，以便露出導體墊314。 In FIG. 19a, an insulating layer 410 is formed over the insulating layer 316 and the conductor layer 314. The insulating layer 410 contains one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating properties and structural properties. The insulating layer 410 is deposited by PVD, CVD, printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable processes. In one embodiment, the insulating layer 410 is a photosensitive dielectric polymer that is cured at a low temperature below 200 ° C. In one embodiment, the insulating layer 410 is formed on the insulating layer 316, above the semiconductor die 294, and outside a coverage area of the semiconductor die 294 above the base semiconductor material 292. In other words, a peripheral region of the semiconductor die 294 adjacent to the semiconductor die 294 includes the insulating layer 410. A portion of the insulating layer 410 is removed by an exposure or development process, LDA, etching, or other suitable processes to form a plurality of openings 412 to expose the conductive pad 314.

在圖19b中，一導電層414會利用諸如印刷、PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化與金屬沉積製程被形成在絕緣層410與導體層314的上方。導體層414能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ti、Ni、Au、Ag、W、或是其它合宜的導電材料。一部分的導體層414沿著絕緣層410並且平行於半導體晶粒294的主動表面312水平延伸，以便橫向重新分佈該電氣互連線至導體層314。導體層414的操 作如同用於半導體晶粒294之電氣信號的RDL。導體層414被形成在半導體晶粒294的一覆蓋區上方並且不會延伸超過半導體晶粒294的該覆蓋區。換言之，相鄰於半導體晶粒294的半導體晶粒294的一周邊區域沒有導體層414。一部分的導體層414被電氣連接至導體層314。導體層414的其它部分則相依於半導體晶粒294的連接而共電或是被電氣隔離。 In FIG. 19b, a conductive layer 414 is formed over the insulating layer 410 and the conductor layer 314 using a patterning and metal deposition process such as printing, PVD, CVD, sputtering, electrolyte plating, and electrodeless plating. The conductive layer 414 can be made of one or more layers made of Al, Cu, Sn, Ti, Ni, Au, Ag, W, or other suitable conductive materials. A portion of the conductor layer 414 extends horizontally along the insulating layer 410 and parallel to the active surface 312 of the semiconductor die 294 so as to laterally redistribute the electrical interconnection line to the conductor layer 314. Operation of conductor layer 414 RDL acts as an electrical signal for semiconductor die 294. The conductor layer 414 is formed over a footprint of the semiconductor die 294 and does not extend beyond the footprint of the semiconductor die 294. In other words, a peripheral region of the semiconductor die 294 adjacent to the semiconductor die 294 has no conductor layer 414. A portion of the conductor layer 414 is electrically connected to the conductor layer 314. The other parts of the conductor layer 414 are electrically connected or electrically isolated depending on the connection of the semiconductor die 294.

一絕緣層或鈍化層416會利用下面方法被形成在絕緣層410和導體層414的上方：PVD、CVD、印刷、旋塗、噴塗、網印、或是層疊。絕緣層416能夠係由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層416係一在低於200℃處被低溫固化的光敏介電質聚合物。於其中一實施例中，絕緣層416被形成在半導體晶粒294的上方以及基礎半導體材料292上方的半導體晶粒294的一覆蓋區外面。於另一實施例中，絕緣層416被形成在半導體晶粒294的該覆蓋區裡面並且不會延伸超過半導體晶粒294的該覆蓋區。一部分絕緣層416會利用一已圖樣化光阻層被一蝕刻製程移除或是藉由LDA來移除，用以形成多個開口418，以便露出導體層414。 An insulating layer or passivation layer 416 is formed on the insulating layer 410 and the conductive layer 414 by the following methods: PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 416 can be made of one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating properties and structural properties. In one embodiment, the insulating layer 416 is a photosensitive dielectric polymer that is cured at a low temperature below 200 ° C. In one embodiment, the insulating layer 416 is formed above the semiconductor die 294 and a coverage area of the semiconductor die 294 above the base semiconductor material 292. In another embodiment, the insulating layer 416 is formed inside the footprint of the semiconductor die 294 and does not extend beyond the footprint of the semiconductor die 294. A portion of the insulating layer 416 is removed by an etching process using a patterned photoresist layer or by LDA to form a plurality of openings 418 to expose the conductive layer 414.

在圖19c中，半導體晶圓290會利用鋸片或雷射削切工具420被單體化裁切貫穿切割道296成為個別的半導體晶粒294。半導體晶圓290同樣會背單體化裁切貫穿絕緣層316、絕緣層410、以及絕緣層416，用以形成側壁或側表面422。側表面422包含半導體晶粒294的側邊以及絕緣層316、410、以及416的側邊。個別的半導體晶粒294皆會被檢查與電氣測試，以便找出單體化裁切後的KGD。 In FIG. 19c, the semiconductor wafer 290 is singulated using a saw blade or a laser cutting tool 420 to cut through the scribe lines 296 to form individual semiconductor dies 294. The semiconductor wafer 290 is also singulated and cut through the insulating layer 316, the insulating layer 410, and the insulating layer 416 to form a sidewall or a side surface 422. The side surface 422 includes the sides of the semiconductor die 294 and the sides of the insulating layers 316, 410, and 416. Individual semiconductor dies 294 are inspected and electrically tested to find the KGD after singulation.

在圖19d中，圖19c中的半導體晶粒294被裝設至載體430 與介面層432，舉例來說，利用拾放操作，主動表面312則被定位朝向載體430。多個半導體晶粒294被裝設至載體430的介面層432，用以形成為重組式或重新配置的晶圓或鑲板436。 In FIG. 19d, the semiconductor die 294 in FIG. 19c is mounted to the carrier 430 With the interface layer 432, for example, using a pick and place operation, the active surface 312 is positioned toward the carrier 430. A plurality of semiconductor dies 294 are mounted to the interface layer 432 of the carrier 430 to form a reassembled or reconfigured wafer or panel 436.

載體430能夠為一可容納多個半導體晶粒294的圓形或矩形鑲板(大於300mm)。載體430的表面積可以大於半導體晶圓290或300的表面積。較大的載體會降低半導體封裝的製造成本，因為有較多的半導體晶粒能夠在該較大載體上被處理，從而降低每個單元的成本。半導體封裝與處理設備會針對正在被處理的晶圓或載體的大小來設計與配置。 The carrier 430 can be a circular or rectangular panel (greater than 300 mm) that can accommodate a plurality of semiconductor dies 294. The surface area of the carrier 430 may be larger than the surface area of the semiconductor wafer 290 or 300. A larger carrier reduces the manufacturing cost of a semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or carrier being processed.

為進一步降低製造成本，載體430的大小會不相依於半導體晶粒294的大小或半導體晶圓290與300的大小來選擇。也就是，載體430具有固定或是標準化大小，其能夠容納從一或更多個半導體晶圓290與300處單體化裁切出來的各種大小半導體晶粒294。於其中一實施例中，載體430為直徑330mm的圓形。於另一實施例中，載體430為寬度560mm以及長度600mm的矩形。半導體晶粒294可以有10mm乘10mm的面積，它們係被放置在標準化載體430上。或者，半導體晶粒294可以有20mm乘20mm的面積，它們被放置在相同的標準化載體430上。據此，標準化載體430能夠應付任何大小的半導體晶粒294，其允許後續的半導體處理設備針對共同的載體被標準化，也就是，不相依於晶粒大小或是進料晶圓大小。半導體封裝設備能夠針對一標準晶圓來設計與配置，利用一組共同的處理工具、設備、以及材料清單來處理來自任何進料晶圓大小的任何半導體晶粒大小。該共同或標準化載體430藉由減少或消弭以晶粒大小或進料晶圓大小為基礎的特殊化半導體處理線的需求而降低製造成本與資本風險。藉由選擇預設的 載體大小用在來自所有半導體晶圓的任何大小半導體晶粒便能夠施行靈活的製造線。 In order to further reduce manufacturing costs, the size of the carrier 430 is selected independently of the size of the semiconductor die 294 or the sizes of the semiconductor wafers 290 and 300. That is, the carrier 430 has a fixed or standardized size, which can accommodate semiconductor dies 294 of various sizes cut out from one or more semiconductor wafers 290 and 300 by singulation. In one embodiment, the carrier 430 is a circle having a diameter of 330 mm. In another embodiment, the carrier 430 is a rectangle with a width of 560 mm and a length of 600 mm. The semiconductor die 294 may have an area of 10 mm by 10 mm, and they are placed on a standardized carrier 430. Alternatively, the semiconductor die 294 may have an area of 20 mm by 20 mm, and they are placed on the same standardized carrier 430. Accordingly, the standardized carrier 430 can cope with semiconductor dies 294 of any size, which allows subsequent semiconductor processing equipment to be standardized for a common carrier, that is, independent of die size or incoming wafer size. Semiconductor packaging equipment can be designed and configured for a standard wafer, utilizing a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 430 reduces manufacturing costs and capital risks by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size. By choosing the default The carrier size is used for any size semiconductor die from all semiconductor wafers to enable flexible manufacturing lines.

重組式晶圓或重組式鑲板436能夠被處理成許多類型的半導體封裝，其包含扇入WLCSP、重組式WLCSP或是eWLCSP、扇出WLCSP、3D封裝(例如，PoP)、或是其它半導體封裝。重組式鑲板436會根據所生成的半導體封裝的規格來配置。於其中一實施例中，多個半導體晶粒294以高密度排列方式被放置在載體430上，也就是，分隔300μm或更小，以便處理扇入裝置。多個半導體晶粒294被放置在載體430上，半導體晶粒294之間分開一間隙或距離D2。半導體晶粒294之間的距離D2係以要被處理的半導體封裝的設計與規格為基礎來選擇。於其中一實施例中，半導體晶粒294之間的距離D2為50μm或更小。於其中一實施例中，半導體晶粒294之間的距離D2為100μm或更小。載體430上的半導體晶粒294之間的距離D2會被最佳化，以便以最低的單元成本來製造半導體封裝。 Restructured wafers or restructured panels 436 can be processed into many types of semiconductor packages, including fan-in WLCSP, recombined WLCSP or eWLCSP, fan-out WLCSP, 3D package (for example, PoP), or other semiconductor packages . The recombination panel 436 is configured according to the specifications of the generated semiconductor package. In one embodiment, a plurality of semiconductor dies 294 are placed on the carrier 430 in a high-density arrangement, that is, separated by 300 μm or less to handle a fan-in device. A plurality of semiconductor dies 294 are placed on the carrier 430, and the semiconductor dies 294 are separated by a gap or distance D2. The distance D2 between the semiconductor dies 294 is selected based on the design and specifications of the semiconductor package to be processed. In one embodiment, the distance D2 between the semiconductor dies 294 is 50 μm or less. In one embodiment, the distance D2 between the semiconductor dies 294 is 100 μm or less. The distance D2 between the semiconductor dies 294 on the carrier 430 is optimized in order to manufacture a semiconductor package with the lowest unit cost.

圖19e所示的係重組式鑲板436的平面圖，多個半導體晶粒294被設置在載體430的上方。載體430具有標準化的形狀與大小，其可容納從各種大小的半導體晶圓處單體化裁切出來的各種大小與數量的半導體晶粒。於其中一實施例中，載體430為矩形形狀並且具有560mm的寬度W2以及600mm的長度L2。被裝設至載體430的半導體晶粒294的數量能夠大於、小於、或是等於從半導體晶圓290處單體化裁切出來的半導體晶粒294的數量。載體430的較大表面積會容納較多的半導體晶粒294並且降低製造成本，因為每一個重組式鑲板436中會處理較多的半導體晶粒294。 A plan view of the reorganized panel 436 shown in FIG. 19e, a plurality of semiconductor dies 294 are disposed above the carrier 430. The carrier 430 has a standardized shape and size, and can accommodate semiconductor chips of various sizes and numbers singulated from semiconductor wafers of various sizes. In one embodiment, the carrier 430 is rectangular and has a width W2 of 560 mm and a length L2 of 600 mm. The number of semiconductor dies 294 mounted on the carrier 430 can be greater than, less than, or equal to the number of semiconductor dies 294 singulated from the semiconductor wafer 290. The larger surface area of the carrier 430 will accommodate more semiconductor dies 294 and reduce manufacturing costs because more semiconductor dies 294 will be processed in each recombination panel 436.

該標準化載體(載體430)的大小固定並且能夠容納多種大小 的半導體晶粒。標準化載體430的大小不相依於半導體晶粒或半導體晶圓的維度。相較於較大的半導體晶粒，有更多小型半導體晶粒能夠適配在載體430上。舉例來說，載體430在載體430的表面積上方容納5mm乘5mm的晶粒的數量大於在載體430的表面積上方容納10mm乘10mm的晶粒的數量。 The standardized carrier (carrier 430) is fixed in size and can accommodate multiple sizes Semiconductor die. The size of the standardized carrier 430 does not depend on the dimensions of the semiconductor die or semiconductor wafer. Compared with larger semiconductor dies, there are more small semiconductor dies that can fit on the carrier 430. For example, the number of crystal grains of 5 mm by 5 mm above the surface area of the carrier 430 is greater than the number of crystal grains of 10 mm by 10 mm above the surface area of the carrier 430.

舉例來說，面積為10mm乘10mm的多個半導體晶粒294被放置在載體430上方，相鄰的半導體晶粒294之間的距離D2為200μm。從半導體晶圓290處單體化裁切出來的半導體晶粒294的數量為約600個半導體晶粒，其中，半導體晶圓290的直徑為300mm。能夠適配在載體430上的10mm乘10mm的半導體晶粒294的數量為約3,000個半導體晶粒。或者，面積為5mm乘5mm的多個半導體晶粒294被放置在載體430上方，相鄰的半導體晶粒294之間的距離D2為200μm。從半導體晶圓290處單體化裁切出來的半導體晶粒294的數量為約1,000個半導體晶粒，其中，半導體晶圓290的直徑為200mm。能夠適配在載體430上的5mm乘5mm的半導體晶粒294的數量為約12,000個半導體晶粒。 For example, a plurality of semiconductor dies 294 having an area of 10 mm by 10 mm are placed above the carrier 430, and a distance D2 between adjacent semiconductor dies 294 is 200 μm. The number of semiconductor dies 294 singulated from the semiconductor wafer 290 is about 600 semiconductor dies, and the diameter of the semiconductor wafer 290 is 300 mm. The number of 10 mm by 10 mm semiconductor dies 294 that can fit on the carrier 430 is about 3,000 semiconductor dies. Alternatively, a plurality of semiconductor dies 294 having an area of 5 mm by 5 mm are placed over the carrier 430, and a distance D2 between adjacent semiconductor dies 294 is 200 μm. The number of semiconductor dies 294 singulated from the semiconductor wafer 290 is about 1,000 semiconductor dies, and the diameter of the semiconductor wafer 290 is 200 mm. The number of 5 mm by 5 mm semiconductor dies 294 that can fit on the carrier 430 is about 12,000 semiconductor dies.

載體430的大小不會隨著正在被處理的半導體晶粒的大小改變。適配在載體430上的半導體晶粒294的數量隨著半導體晶粒294的大小以及半導體晶粒294之間的間隔或距離D2而改變。載體430的大小與形狀保持固定並且不相依於半導體晶粒294的大小或是用以單體化裁切出半導體晶粒294的半導體晶圓290的大小。載體430與重組式鑲板436提供利用一組共同處理設備(例如，圖13h中的處理設備340)來製造許多不同類型半導體封裝的靈活性，該些不同類型的半導體封裝具有來自不同大小半導 體晶圓290的不同大小半導體晶粒294。 The size of the carrier 430 does not change with the size of the semiconductor die being processed. The number of semiconductor dies 294 fitted on the carrier 430 varies with the size of the semiconductor dies 294 and the interval or distance D2 between the semiconductor dies 294. The size and shape of the carrier 430 remains fixed and does not depend on the size of the semiconductor die 294 or the size of the semiconductor wafer 290 used to singulate the semiconductor die 294. The carrier 430 and the recombination panel 436 provide the flexibility to use a common set of processing equipment (e.g., processing equipment 340 in FIG. 13h) to fabricate many different types of semiconductor packages having semiconductors from different sizes. Semiconductor wafers 294 of different sizes in the bulk wafer 290.

在圖19f中，一囊封體或模製化合物438會利用焊膏印刷塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒294以及載體430的上方。囊封體438能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體438係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。於另一實施例中，囊封體438係一絕緣層或介電層，其含有由下面所製成的一或更多層：光敏低固化溫度介電光阻、光敏合成光阻、層疊化合物膜、具有填充劑的絕緣膏、焊劑遮罩光阻膜、液體或粒狀模製化合物、聚亞醯胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、膠片、或是具有雷同絕緣特性及結構特性的其它介電材料，它們係利用印刷、旋塗、噴塗、有熱或無熱的真空層疊或壓力層疊、或是其它合宜製程所沉積。於其中一實施例中，囊封體438係一在低於200℃處固化之具有或不具有絕緣填充劑的低溫固化光敏介電聚合物。 In FIG. 19f, an encapsulation body or a molding compound 438 is applied by a solder paste printing coater, a transfer molding coater, a liquid encapsulation body molding coater, a vacuum lamination coater, and a spin coating. A coating machine, or other suitable coating machine, is deposited over the semiconductor die 294 and the carrier 430. The encapsulation body 438 can be a polymer synthetic material, for example, an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulation body 438 is non-conducting and will provide environmental protection for the semiconductor device and be protected from damage by external elements and pollutants. In another embodiment, the encapsulation body 438 is an insulating layer or a dielectric layer, which contains one or more layers made of: a photosensitive low curing temperature dielectric photoresist, a photosensitive synthetic photoresist, a laminated compound Film, insulating paste with filler, solder mask photoresist film, liquid or granular molding compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, film, or similar insulation Other dielectric materials with special properties and structural properties are deposited by printing, spin coating, spray coating, vacuum or pressure lamination with or without heat, or other suitable processes. In one embodiment, the encapsulation body 438 is a low-temperature-curable photosensitive dielectric polymer that is cured at less than 200 ° C with or without an insulating filler.

明確地說，囊封體438沿著半導體晶粒294的側表面422被設置並且因而覆蓋半導體晶粒294的每一個側表面422以及絕緣層316、410、以及416。據此，囊封體438覆蓋或接觸半導體晶粒294的至少四個表面，也就是，半導體晶粒294的四個側表面422。囊封體438還覆蓋半導體晶粒294的背表面310。囊封體438保護半導體晶粒294，避免因曝露在來自光或其它輻射的光子的關係而受損。於其中一實施例中，囊封體438為不透明並且為暗色或黑色。囊封體438能夠被用於雷射標記重組式鑲板 436，以便進行對齊與單體化裁切。於另一實施例中，囊封體438被沉積而使得囊封體438共面於半導體晶粒294的背表面310並且不會覆蓋背表面310。 Specifically, the encapsulation body 438 is provided along the side surface 422 of the semiconductor die 294 and thus covers each side surface 422 of the semiconductor die 294 and the insulating layers 316, 410, and 416. Accordingly, the encapsulation body 438 covers or contacts at least four surfaces of the semiconductor die 294, that is, the four side surfaces 422 of the semiconductor die 294. The encapsulation body 438 also covers the back surface 310 of the semiconductor die 294. The encapsulation body 438 protects the semiconductor die 294 from being damaged by the relationship of exposure to photons from light or other radiation. In one embodiment, the encapsulation body 438 is opaque and dark or black. Capsule 438 can be used for laser marking recombination panels 436 for alignment and singulation cutting. In another embodiment, the encapsulation body 438 is deposited such that the encapsulation body 438 is coplanar with the back surface 310 of the semiconductor die 294 and does not cover the back surface 310.

在圖19g中，囊封體344的背側表面440會以研磨機442進行研磨操作，用以平坦化且縮減囊封體344的厚度。化學蝕刻亦會被用來移除與平坦化囊封體438並且用以形成平坦的背側表面444。於其中一實施例中，囊封體438的厚度維持覆蓋在半導體晶粒294的背表面310上方。於其中一實施例中，半導體晶粒294的背表面310會在背研磨步驟期間露出。半導體晶粒294的厚度亦能夠因該研磨操作而縮減。於其中一實施例中，半導體晶粒294的厚度範圍為225μm至305μm或更小。 In FIG. 19 g, the back surface 440 of the encapsulation body 344 is ground by a grinder 442 to flatten and reduce the thickness of the encapsulation body 344. Chemical etching is also used to remove and planarize the encapsulation body 438 and to form a flat backside surface 444. In one embodiment, the thickness of the encapsulation body 438 is maintained to cover the back surface 310 of the semiconductor die 294. In one embodiment, the back surface 310 of the semiconductor die 294 is exposed during the back grinding step. The thickness of the semiconductor die 294 can also be reduced by the grinding operation. In one embodiment, the thickness of the semiconductor die 294 ranges from 225 μm to 305 μm or less.

圖19h所示的係被囊封體438覆蓋的重組式鑲板436。於其中一實施例中，在沉積或背研磨之後殘留在半導體晶粒294的背表面310上方的囊封體438的厚度範圍從約170μm至230μm或更小。於另一實施例中，殘留在半導體晶粒294的背表面310上方的囊封體438的厚度範圍從約5μm至150μm。反向於背側表面440的囊封體438的表面448被設置在載體430與介面層432上方。 The reassembled panel 436 shown in Fig. 19h is covered by an encapsulation body 438. In one embodiment, the thickness of the encapsulation body 438 remaining above the back surface 310 of the semiconductor die 294 after deposition or back grinding ranges from about 170 μm to 230 μm or less. In another embodiment, the thickness of the encapsulation body 438 remaining above the back surface 310 of the semiconductor die 294 ranges from about 5 μm to 150 μm. A surface 448 of the encapsulation body 438 opposite to the backside surface 440 is disposed above the carrier 430 and the interface layer 432.

在圖19i中，載體430與介面層432會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，以便露出絕緣層416、導體層414、以及囊封體438的表面448。 In FIG. 19i, the carrier 430 and the interface layer 432 are removed by chemical etching, mechanical stripping, CMP, mechanical polishing, thermal baking, UV light, laser scanning, or wet removal, so that A surface 448 of the insulating layer 416, the conductor layer 414, and the encapsulation body 438 is exposed.

在圖19j中，一導電層460會在最終重新鈍化之後利用PVD、CVD、蒸發、電解質電鍍、無電極電鍍、或是其它合宜的金屬沉積製程被形成在導體層414的裸露部分上方以及絕緣層416的上方。導體層460 能夠為Al、Cu、Sn、Ti、Ni、Au、Ag、W、或是其它合宜的導電材料。導體層460係一UBM，其被電氣連接至導體層414與314。UBM 460能夠係一具有黏著層、屏障層、以及晶種層或潤濕層的多金屬堆疊。黏著層係被形成在導體層414的上方並且能夠為Ti、TiN、TiW、Al、或是Cr。屏障層係被形成在黏著層的上方並且能夠為Ni、NiV、Pt、Pd、TiW、Ti、或是CrCu。該屏障層會阻止Cu擴散至半導體晶粒294的主動表面312之中。晶種層係被形成在屏障層的上方並且能夠為Cu、Ni、NiV、Au、或是Al。UBM 460為導體層414提供一低阻值互連線，並且提供一屏障阻止焊料擴散，以及提供用於焊料潤濕的晶種層。 In FIG. 19j, a conductive layer 460 is formed over the exposed portion of the conductor layer 414 and the insulating layer using PVD, CVD, evaporation, electrolyte plating, electrodeless plating, or other suitable metal deposition processes after final repassivation Above 416. Conductor layer 460 It can be Al, Cu, Sn, Ti, Ni, Au, Ag, W, or other suitable conductive materials. The conductor layer 460 is a UBM, which is electrically connected to the conductor layers 414 and 314. UBM 460 can be a multi-metal stack with an adhesion layer, a barrier layer, and a seed or wetting layer. The adhesive layer system is formed above the conductor layer 414 and can be Ti, TiN, TiW, Al, or Cr. The barrier layer is formed above the adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti, or CrCu. The barrier layer prevents Cu from diffusing into the active surface 312 of the semiconductor die 294. The seed layer system is formed over the barrier layer and can be Cu, Ni, NiV, Au, or Al. UBM 460 provides a low-resistance interconnect for conductor layer 414, and a barrier to prevent solder diffusion, and a seed layer for solder wetting.

一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層460的上方。於其中一實施例中，該凸塊材料係利用一丸滴模板來沉積，也就是，不需要用到任何遮罩。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層460。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊462。於某些應用中，凸塊462會被二次回焊，以便改良和導體層460的電氣接觸效果。凸塊462亦能夠被壓縮焊接或熱壓縮焊接至導體層460。凸塊462代表能夠被形成在導體層460上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。雷射標記能夠在凸塊成形之前或之後或是在移除載體430之後被實施。 A conductive bump material is deposited on the conductive layer 460 by using an evaporation process, an electrolytic plating process, an electrodeless plating process, a pill process, or a screen printing process. In one embodiment, the bump material is deposited using a drop template, that is, no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and a combination thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high-lead solder, or a lead-free solder. The bump material is soldered to the conductor layer 460 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 462. In some applications, the bump 462 is re-soldered in order to improve the electrical contact with the conductive layer 460. The bump 462 can also be compression welded or thermally compressed to the conductor layer 460. The bump 462 represents one of the types of interconnect structures that can be formed over the conductor layer 460. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines. Laser marking can be implemented before or after bump formation or after removal of the carrier 430.

絕緣層410與416、導體層414與416、以及凸塊462一起構成被形成在半導體晶粒294上方及半導體晶粒294的一覆蓋區裡面的增進互連結構466。相鄰於半導體晶粒294的半導體晶粒294的一周邊區域不會有互連結構466，並且囊封體438的表面448仍保持從互連結構466處露出。增進互連結構466可以僅包含一RDL或導體層(例如，導體層414)以及一絕緣層(例如，絕緣層410)。額外的絕緣層和RDL會在形成凸塊462之前被形成在絕緣層416的上方，以便根據半導體晶粒294的設計和功能在該封裝中提供額外的垂直與水平電氣連接。 The insulating layers 410 and 416, the conductor layers 414 and 416, and the bumps 462 together form an enhanced interconnect structure 466 formed over the semiconductor die 294 and in a footprint of the semiconductor die 294. A peripheral region of the semiconductor die 294 adjacent to the semiconductor die 294 does not have the interconnect structure 466, and the surface 448 of the encapsulation body 438 remains exposed from the interconnect structure 466. The enhanced interconnect structure 466 may include only an RDL or conductor layer (eg, the conductor layer 414) and an insulation layer (eg, the insulation layer 410). An additional insulating layer and RDL are formed over the insulating layer 416 before forming the bumps 462 to provide additional vertical and horizontal electrical connections in the package based on the design and function of the semiconductor die 294.

在圖19k中，半導體晶粒294會利用鋸片或雷射削切工具470被單體化裁切貫穿囊封體438成為個別的eWLCSP 472。重組式鑲板436被單體化裁切成為eWLCSP 472，用以在半導體晶粒294的側表面422以及絕緣層316、410、以及416的上方留下一薄層的囊封體438。或者，重組式鑲板436會被單體化裁切而從側表面422處完全移除囊封體438。eWLCSP 472會在單體化裁切之前或之後進行電氣測試。 In FIG. 19k, the semiconductor die 294 is singulated and cut through the encapsulation body 438 into individual eWLCSP 472 using a saw blade or laser cutting tool 470. The recombination panel 436 is singulated and cut into eWLCSP 472 to leave a thin layer of encapsulation body 438 on the side surface 422 of the semiconductor die 294 and the insulating layers 316, 410, and 416. Alternatively, the recombination panel 436 may be singulated to completely remove the encapsulation body 438 from the side surface 422. The eWLCSP 472 undergoes electrical testing before or after singulation cutting.

圖20所示的係eWLCSP 472，其具有被形成在半導體晶粒294之背表面310以及側壁422上方的囊封體。半導體晶粒294經由導體層314、414、以及460被電氣連接至凸塊462，以便經由互連結構466達到外部互連的目的。互連結構466不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體438在圖19g中所示的研磨操作之後仍殘留在半導體晶粒294的背表面310上方。囊封體438殘留在半導體晶粒294的側表面422以及絕緣層316、410、以及416的上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。所以，囊 封體438被形成在半導體晶粒294的五個側邊上方，也就是，在四個側表面422上方以及在背表面310上方。在半導體晶粒294的背表面310上方的囊封體438省略背側保護層或背側疊板的需求，因而降低eWLCSP 472的成本。 The system eWLCSP 472 shown in FIG. 20 has an encapsulation body formed on the back surface 310 and the sidewall 422 of the semiconductor die 294. The semiconductor die 294 is electrically connected to the bump 462 via the conductor layers 314, 414, and 460 so as to achieve the purpose of external interconnection via the interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 438 remains above the back surface 310 of the semiconductor die 294 after the grinding operation shown in FIG. 19g. The encapsulation body 438 remains on the side surface 422 of the semiconductor die 294 and the insulating layers 316, 410, and 416 to achieve the purpose of mechanical protection and to avoid being exposed to the relationship of photons from light or other radiation. damage. So, the capsule The package 438 is formed over the five sides of the semiconductor die 294, that is, over the four side surfaces 422 and over the back surface 310. The encapsulation body 438 above the back surface 310 of the semiconductor die 294 omits the need for a backside protective layer or a backside stack, thereby reducing the cost of the eWLCSP 472.

在eWLCSP 472中，側表面422上方的囊封體438的厚度小於150μm。於其中一實施例中，eWLCSP 472的體積為長度4.595mm x寬度4.025mm x高度0.470mm，凸塊462的節距為0.4mm，其中，半導體晶粒294的面積為長度4.445mm x寬度3.875mm。於另一實施例中，半導體晶粒294的側表面324上方的囊封體438的厚度為75μm或更小。eWLCSP 472的體積為長度6.075mm x寬度6.075mm x高度0.8mm，凸塊462的節距為0.5mm，其中，半導體晶粒294的體積為長度6.0mm x寬度6.0mm x高度0.470mm。於又一實施例中，eWLCSP 472的體積為長度5.92mm x寬度5.92mm x高度0.765mm，凸塊462的節距為0.5mm，其中，半導體晶粒294的體積為長度5.75mm x寬度5.75mm x高度0.535mm。於另一實施例中，側表面422上方的囊封體438的厚度為25μm或更小。於又一實施例中，側表面422上方的囊封體438的厚度為約50μm或更小。eWLCSP 472係利用針對單一標準化載體大小所設計的設備藉由在標準化載體430上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 472的設備成本與材料成本。eWLCSP 472係利用標準化載體430以較高的數量來製造，從而簡化製造過程並且降低單元成本。 In the eWLCSP 472, the thickness of the encapsulation body 438 above the side surface 422 is less than 150 μm. In one embodiment, the volume of the eWLCSP 472 is 4.595 mm in length x 4.025 mm in width x 0.470 mm in height, and the pitch of the bumps 462 is 0.4 mm, wherein the area of the semiconductor die 294 is 4.445 mm in length x 3.875 mm in width . In another embodiment, the thickness of the encapsulation body 438 above the side surface 324 of the semiconductor die 294 is 75 μm or less. The volume of the eWLCSP 472 is 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and the pitch of the bumps 462 is 0.5 mm. The volume of the semiconductor die 294 is 6.0 mm in length x 6.0 mm in width x 0.470 mm in height. In yet another embodiment, the volume of the eWLCSP 472 is 5.92 mm in length x 5.92 mm in width x 0.765 mm in height, and the pitch of the bumps 462 is 0.5 mm, wherein the volume of the semiconductor die 294 is 5.75 mm in length x 5.75 mm in width x height 0.535mm. In another embodiment, the thickness of the encapsulation body 438 above the side surface 422 is 25 μm or less. In yet another embodiment, the thickness of the encapsulation body 438 above the side surface 422 is about 50 μm or less. The eWLCSP 472 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 430, which will reduce the equipment cost and material cost of the eWLCSP 472. The eWLCSP 472 is manufactured in higher quantities using standardized carriers 430, thereby simplifying the manufacturing process and reducing unit costs.

圖21所示的係另一eWLCSP 480，其具有位在半導體晶粒294之背表面310上方的囊封體438並且具有半導體晶粒294的裸露側壁422。半導體晶粒294經由導體層314、414、以及460被電氣連接至凸塊462， 以便經由互連結構466達到外部互連的目的。互連結構466不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體438在圖19g中所示的研磨操作之後仍殘留在半導體晶粒294的背表面310上方。在半導體晶粒294的背表面310上方的囊封體438省略背側保護層或背側疊板的需求，因而降低eWLCSP 480的成本。囊封體438在單體化裁切期間從半導體晶粒294的側表面422以及絕緣層316、410、以及416處被完全移除，以便露出側表面422。eWLCSP 388的長度與寬度和半導體晶粒294的長度與寬度相同。於其中一實施例中，eWLCSP 480的面積為約長度4.445mm x寬度3.875mm，凸塊462的節距為0.35至0.50mm。eWLCSP 480係利用針對單一標準化載體大小所設計的設備藉由在標準化載體430上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 480的設備成本與材料成本。eWLCSP 480係利用標準化載體430以較高的數量來製造，從而簡化製造過程並且降低單元成本。 FIG. 21 shows another eWLCSP 480, which has an encapsulation body 438 positioned above the back surface 310 of the semiconductor die 294 and has an exposed sidewall 422 of the semiconductor die 294. The semiconductor die 294 is electrically connected to the bump 462 via the conductor layers 314, 414, and 460, In order to achieve the purpose of external interconnection via the interconnection structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 438 remains above the back surface 310 of the semiconductor die 294 after the grinding operation shown in FIG. 19g. The encapsulation body 438 above the back surface 310 of the semiconductor die 294 omits the need for a backside protective layer or a backside stack, thereby reducing the cost of the eWLCSP 480. The encapsulation body 438 is completely removed from the side surface 422 of the semiconductor die 294 and the insulating layers 316, 410, and 416 during the singulation cutting to expose the side surface 422. The length and width of the eWLCSP 388 and the length and width of the semiconductor die 294 are the same. In one embodiment, the area of the eWLCSP 480 is approximately 4.445 mm in length x 3.875 mm in width, and the pitch of the bumps 462 is 0.35 to 0.50 mm. The eWLCSP 480 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 430, which will reduce the equipment cost and material cost of the eWLCSP 480. The eWLCSP 480 is manufactured in a higher quantity using a standardized carrier 430, thereby simplifying the manufacturing process and reducing unit costs.

圖22所示的係在單體化裁切之後的eWLCSP 482，其具有位在半導體晶粒294之側壁422以及背側絕緣層484上方的囊封體438。半導體晶粒294經由導體層314、414、以及460被電氣連接至凸塊462，以便經由互連結構466達到外部互連的目的。互連結構466不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體438從半導體晶粒294的背表面310處被完全移除。背側絕緣層484被形成在半導體晶粒294的背表面310的上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。背側絕緣層484含有由下面所製成的一或更多層：光敏低固化溫度介電光阻、光敏合成光阻、層疊化合物膜、 具有填充劑的絕緣膏、焊劑遮罩光阻膜、液體或粒狀模製化合物、聚亞醯胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、膠片、或是具有雷同絕緣特性及結構特性的其它介電材料。背側絕緣層484係利用印刷、旋塗、噴塗、有熱或無熱的真空層疊或壓力層疊、或是其它合宜製程所沉積。於其中一實施例中，背側絕緣層484係一在低於200℃處固化之具有或不具有絕緣填充劑的低溫固化光敏介電聚合物。背側絕緣層484係一背側保護層並且為半導體晶粒294提供機械性保護以及避免受到光的影響。於其中一實施例中，背側絕緣層484的厚度範圍從約5μm至150μm。 The eWLCSP 482 shown in FIG. 22 after singulation cutting has an encapsulation body 438 located on the sidewall 422 of the semiconductor die 294 and above the back-side insulating layer 484. The semiconductor die 294 is electrically connected to the bump 462 via the conductor layers 314, 414, and 460 so as to achieve the purpose of external interconnection via the interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 438 is completely removed from the back surface 310 of the semiconductor die 294. The back-side insulating layer 484 is formed above the back surface 310 of the semiconductor die 294 to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation. The back-side insulating layer 484 contains one or more layers made of: a photosensitive low curing temperature dielectric photoresist, a photosensitive synthetic photoresist, a laminated compound film, Insulating paste with filler, solder mask photoresist film, liquid or granular molding compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, film, or similar insulation properties Structural properties of other dielectric materials. The back-side insulating layer 484 is deposited by printing, spin coating, spray coating, vacuum lamination with or without heat or pressure lamination, or other suitable processes. In one embodiment, the back-side insulating layer 484 is a low-temperature-curable photosensitive dielectric polymer cured with or without an insulating filler at a temperature below 200 ° C. The back-side insulating layer 484 is a back-side protection layer and provides mechanical protection for the semiconductor die 294 and is protected from light. In one embodiment, the thickness of the back-side insulating layer 484 ranges from about 5 μm to 150 μm.

囊封體438覆蓋半導體晶粒294的側表面422，用以保護半導體晶粒294，避免因曝露在來自光或其它輻射的光子的關係而受損。在eWLCSP 482中，側表面422上方的囊封體438的厚度小於150μm。於其中一實施例中，eWLCSP 482的體積為長度4.595mm x寬度4.025mm x高度0.470mm，凸塊462的節距為0.4mm，其中，半導體晶粒294的面積為長度4.445mm x寬度3.875mm。於另一實施例中，側表面422上方的囊封體438的厚度為75μm或更小。eWLCSP 482的體積為長度6.075mm x寬度6.075mm x高度0.8mm，凸塊462的節距為0.5mm，其中，半導體晶粒294的體積為長度6.0mm x寬度6.0mm x高度0.470mm。於又一實施例中，eWLCSP 482的體積為長度5.92mm x寬度5.92mm x高度0.765mm，凸塊462的節距為0.5mm，其中，半導體晶粒294的體積為長度5.75mm x寬度5.75mm x高度0.535mm。於另一實施例中，側表面422上方的囊封體438的厚度為25μm或更小。於又一實施例中，側表面422上方的囊封體438的厚度為約50μm或更小。eWLCSP 482係利用針對單一標準化載體大小所設計的設備藉由在 標準化載體430上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 482的設備成本與材料成本。eWLCSP 482係利用標準化載體430以較高的數量來製造，從而簡化製造過程並且降低單元成本。 The encapsulation body 438 covers the side surface 422 of the semiconductor die 294 to protect the semiconductor die 294 from damage caused by exposure to photons from light or other radiation. In eWLCSP 482, the thickness of the encapsulation body 438 above the side surface 422 is less than 150 μm. In one embodiment, the volume of the eWLCSP 482 is 4.595mm in length x 4.025mm in width x 0.470mm in height, and the pitch of the bumps 462 is 0.4mm, wherein the area of the semiconductor die 294 is 4.445mm in length x 3.875mm in width . In another embodiment, the thickness of the encapsulation body 438 above the side surface 422 is 75 μm or less. The volume of the eWLCSP 482 is 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and the pitch of the bumps 462 is 0.5 mm. The volume of the semiconductor die 294 is 6.0 mm in length x 6.0 mm in width x 0.470 mm in height. In yet another embodiment, the volume of the eWLCSP 482 is 5.92 mm in length x 5.92 mm in width x 0.765 mm in height, and the pitch of the bumps 462 is 0.5 mm. The volume of the semiconductor die 294 is 5.75 mm in length x 5.75 mm in width. x height 0.535mm. In another embodiment, the thickness of the encapsulation body 438 above the side surface 422 is 25 μm or less. In yet another embodiment, the thickness of the encapsulation body 438 above the side surface 422 is about 50 μm or less. eWLCSP 482 is a device designed for a single standardized carrier size. A standardized wafer or panel is formed on the standardized carrier 430 for manufacturing, which will reduce the equipment cost and material cost of the eWLCSP 482. The eWLCSP 482 is manufactured in higher quantities using standardized carriers 430, thereby simplifying the manufacturing process and reducing unit costs.

圖23所示的係一eWLCSP 486，雷同於eWLCSP 482，但是沒有導體層460。凸塊462直接被形成在導體層414上。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層414。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊462。於某些應用中，凸塊462會被二次回焊，以便改良和導體層414的電氣接觸效果。凸塊462亦能夠被壓縮焊接或熱壓縮焊接至導體層414。凸塊462代表能夠被形成在導體層414上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。 The eWLCSP 486 shown in FIG. 23 is similar to the eWLCSP 482, but has no conductive layer 460. The bump 462 is directly formed on the conductor layer 414. The bump material is soldered to the conductor layer 414 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 462. In some applications, the bump 462 is re-soldered to improve the electrical contact with the conductive layer 414. The bump 462 can also be compression welded or thermally compressed to the conductor layer 414. The bump 462 represents one of the types of interconnect structures that can be formed over the conductor layer 414. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines.

半導體晶粒294經由導體層314以及414被電氣連接至凸塊462，以便經由互連結構466達到外部互連的目的。互連結構466不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體438從半導體晶粒294的背表面310處被完全移除。背側絕緣層484被形成在半導體晶粒294的背表面310的上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。囊封體438覆蓋半導體晶粒294的側表面422，用以保護半導體晶粒294，避免因曝露在來自光或其它輻射的光子的關係而受損。在eWLCSP 486中，側表面422上方的囊封體438的厚度小於150μm。eWLCSP 486係利用針對單一標準化載體大小所設計的設備藉由在標準化載體430上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 486的設備成本與材料成本。eWLCSP 486係利用標準化載體 430以較高的數量來製造，從而簡化製造過程並且降低單元成本。 The semiconductor die 294 is electrically connected to the bump 462 via the conductor layers 314 and 414 so as to achieve the purpose of external interconnection via the interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 438 is completely removed from the back surface 310 of the semiconductor die 294. The back-side insulating layer 484 is formed above the back surface 310 of the semiconductor die 294 to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation. The encapsulation body 438 covers the side surface 422 of the semiconductor die 294 to protect the semiconductor die 294 from damage caused by exposure to photons from light or other radiation. In eWLCSP 486, the thickness of the encapsulation body 438 above the side surface 422 is less than 150 μm. The eWLCSP 486 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 430, which will reduce the equipment cost and material cost of the eWLCSP 486. eWLCSP 486 uses standardized vectors 430 is manufactured in higher quantities, thereby simplifying the manufacturing process and reducing unit costs.

圖24所示的係一替代eWLCSP 488，其具有背側絕緣層484以及裸露的側壁422。半導體晶粒294經由導體層314、414、以及460被電氣連接至凸塊462，以便經由互連結構466達到外部互連的目的。互連結構466不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體438從半導體晶粒294的背表面310處被完全移除。背側絕緣層484被形成在半導體晶粒294的背表面310的上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。囊封體438在單體化裁切期間從半導體晶粒294的側表面324處被完全移除，以便露出側表面422。eWLCSP 488的長度與寬度和半導體晶粒294的長度與寬度相同。於其中一實施例中，eWLCSP 488的面積為約長度4.4mm x寬度3.9mm，凸塊462的節距為0.35至0.50mm。eWLCSP 488係利用針對單一標準化載體大小所設計的設備藉由在標準化載體430上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 488的設備成本與材料成本。eWLCSP 488係利用標準化載體430以較高的數量來製造，從而簡化製造過程並且降低單元成本。 A replacement eWLCSP 488 shown in FIG. 24 has a back-side insulating layer 484 and an exposed sidewall 422. The semiconductor die 294 is electrically connected to the bump 462 via the conductor layers 314, 414, and 460 so as to achieve the purpose of external interconnection via the interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 438 is completely removed from the back surface 310 of the semiconductor die 294. The back-side insulating layer 484 is formed above the back surface 310 of the semiconductor die 294 to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation. The encapsulation body 438 is completely removed from the side surface 324 of the semiconductor die 294 during singulation cutting so as to expose the side surface 422. The length and width of the eWLCSP 488 and the length and width of the semiconductor die 294 are the same. In one embodiment, the area of the eWLCSP 488 is about 4.4 mm in length x 3.9 mm in width, and the pitch of the bumps 462 is 0.35 to 0.50 mm. The eWLCSP 488 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 430, which will reduce the equipment cost and material cost of the eWLCSP 488. The eWLCSP 488 is manufactured in a higher quantity using a standardized carrier 430, thereby simplifying the manufacturing process and reducing unit costs.

圖25所示的係另一eWLCSP 490，其具有半導體晶粒294的裸露背表面310以及側壁422。半導體晶粒294經由導體層314、414、以及460被電氣連接至凸塊462，以便經由互連結構466達到外部互連的目的。互連結構466不會延伸超過半導體晶粒294的一覆蓋區，並且因而形成一扇入封裝。囊封體438在圖19g中所示的研磨操作期間從半導體晶粒294的背表面310處被完全移除。囊封體438在單體化裁切期間從半導體晶粒294的側表面422處被完全移除，以便露出側表面422。eWLCSP 490的長度與寬 度和半導體晶粒294的長度與寬度相同。於其中一實施例中，eWLCSP 490的面積為約長度4.4mm x寬度3.9mm，凸塊462的節距為0.35至0.50mm。eWLCSP 490係利用針對單一標準化載體大小所設計的設備藉由在標準化載體430上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 490的設備成本與材料成本。eWLCSP 490係利用標準化載體430以較高的數量來製造，從而簡化製造過程並且降低單元成本。 FIG. 25 shows another eWLCSP 490, which has an exposed back surface 310 and a sidewall 422 of the semiconductor die 294. The semiconductor die 294 is electrically connected to the bump 462 via the conductor layers 314, 414, and 460 so as to achieve the purpose of external interconnection via the interconnect structure 466. The interconnect structure 466 does not extend beyond a footprint of the semiconductor die 294 and thus forms a fan-in package. The encapsulation body 438 is completely removed from the back surface 310 of the semiconductor die 294 during the grinding operation shown in FIG. 19g. The encapsulation body 438 is completely removed from the side surface 422 of the semiconductor die 294 during singulation cutting so as to expose the side surface 422. The length and width of eWLCSP 490 The length and width of the semiconductor die 294 are the same. In one embodiment, the area of the eWLCSP 490 is about 4.4 mm in length x 3.9 mm in width, and the pitch of the bumps 462 is 0.35 to 0.50 mm. The eWLCSP 490 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 430, which will reduce the equipment cost and material cost of the eWLCSP 490. The eWLCSP 490 is manufactured in a higher quantity using a standardized carrier 430, thereby simplifying the manufacturing process and reducing unit costs.

圖26a至26k配合圖1以及2a至2c顯示一種形成重組式或嵌入式扇入WLCSP的製程。圖26a所示的係一半導體晶圓500，其具有一基礎基板材料502(例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽)用以達到結構性支撐的目的。複數個半導體晶粒或組件504會被形成在晶圓500上，藉由如上面所述之非主動的晶粒間晶圓區域或切割道506來分離。切割道506提供削切區，以便將半導體晶圓500單體化裁切成個別的半導體晶粒504。於其中一實施例中，半導體晶圓500的直徑為200至300mm。於另一實施例中，半導體晶圓500的直徑為100至450mm。在將半導體晶圓單體化裁切成個別的半導體晶粒504之前，半導體晶圓500可以有任何直徑。 Figures 26a to 26k in conjunction with Figures 1 and 2a to 2c show a process for forming a recombined or embedded fan-in WLCSP. A semiconductor wafer 500 shown in FIG. 26a has a base substrate material 502 (for example, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide) for structural support. A plurality of semiconductor dies or components 504 are formed on the wafer 500 and separated by inactive inter-die wafer regions or scribe lines 506 as described above. The dicing track 506 provides a cutting area for singulating the semiconductor wafer 500 into individual semiconductor dies 504. In one embodiment, the diameter of the semiconductor wafer 500 is 200 to 300 mm. In another embodiment, the diameter of the semiconductor wafer 500 is 100 to 450 mm. Prior to singulating the semiconductor wafer into individual semiconductor dies 504, the semiconductor wafer 500 may have any diameter.

圖26a所示的係半導體晶圓500的一部分的剖視圖。每一個半導體晶粒504皆有一背表面或非主動表面508以及含有類比電路或數位電路的主動表面510，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面510裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，DSP、ASIC、記憶體、或是其它訊號處理電路。半 導體晶粒504可以還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。 A cross-sectional view of a portion of a series semiconductor wafer 500 shown in FIG. 26a. Each semiconductor die 504 has a back surface or an inactive surface 508 and an active surface 510 containing analog circuits or digital circuits. The analog circuits or digital circuits are formed according to the electrical design and function of the die. Active devices, passive devices, conductor layers, and dielectric layers within and within the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in the active surface 510 to implement analog or digital circuits, such as DSP, ASIC, memory , Or other signal processing circuits. half The conductor die 504 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

一導電層512會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面510的上方。導體層512能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層512的操作如同被電氣連接至主動表面510上之電路的接觸墊。導體層512會被形成為多個接觸墊，它們以並排的方式被設置在和半導體晶粒504的邊緣相隔第一距離處，如圖26a之中所示。或者，導體層512會被形成為偏移在多列之中的多個接觸墊，俾使得第一列接觸墊會被設置在和該晶粒的邊緣相隔第一距離處，而與該第一列交錯的第二列接觸墊則被設置在和該晶粒的邊緣相隔第二距離處。 A conductive layer 512 is formed over the active surface 510 using a PVD, CVD, electrolyte plating, electrodeless plating process, or other suitable metal deposition process. The conductive layer 512 can be made of one or more layers made of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductor layer 512 operates like a contact pad electrically connected to a circuit on the active surface 510. The conductive layer 512 is formed as a plurality of contact pads, which are arranged side by side at a first distance from the edge of the semiconductor die 504, as shown in FIG. 26a. Alternatively, the conductor layer 512 may be formed as a plurality of contact pads offset in a plurality of rows, so that the first row of contact pads may be disposed at a first distance from the edge of the die, and from the first The staggered second row of contact pads are disposed at a second distance from the edge of the die.

一第一絕緣層或鈍化層514係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在半導體晶粒504和導體層512的上方。絕緣層514含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物、或是具有雷同結構特性及絕緣特性的其它介電材料。於其中一實施例中，絕緣層514係一低溫固化光敏介電聚合物，具有或不具有在小於200℃處被固化的絕緣填充劑。絕緣層514覆蓋主動表面510並且為主動表面510提供保護。絕緣層514被保形塗敷在導體層512以及半導體晶粒504的主動表面510的上方並且不會延伸超過半導體晶粒504的邊緣或側壁516或是超過半導體晶粒504的一覆蓋區。換言之，相鄰於半導體晶粒504的半導體晶粒504的一周邊區域沒有絕緣層514。一部分的絕緣層514會利用雷射518藉由LDA被移除，或者，藉由蝕刻製 程貫穿一已圖樣化光阻層而被移除，以便經由絕緣層514露出導體層512並且用於進行後續的電氣互連。 A first insulating layer or passivation layer 514 is formed over the semiconductor die 504 and the conductor layer 512 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 514 contains one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer, or other dielectrics having similar structural and insulating properties material. In one embodiment, the insulating layer 514 is a low-temperature-curable photosensitive dielectric polymer, with or without an insulating filler cured at less than 200 ° C. The insulating layer 514 covers and protects the active surface 510. The insulating layer 514 is conformally applied over the conductive layer 512 and the active surface 510 of the semiconductor die 504 and does not extend beyond the edges or sidewalls 516 of the semiconductor die 504 or beyond a footprint of the semiconductor die 504. In other words, a peripheral region of the semiconductor die 504 adjacent to the semiconductor die 504 has no insulating layer 514. A part of the insulating layer 514 is removed by LDA using laser 518, or by etching The process is removed through a patterned photoresist layer so as to expose the conductor layer 512 through the insulating layer 514 and is used for subsequent electrical interconnection.

半導體晶圓500會進行電氣測試與檢查，作為品質控制過程的一部分。手動視覺檢查及自動光學系統會被用來在半導體晶圓500上實施檢查。軟體會被使用在半導體晶圓500的自動光學分析中。視覺檢查方法可以運用諸如掃描電子顯微鏡、高強度光或紫外光、或是冶金顯微鏡的設備。半導體晶圓500的結構性特徵會被檢查，其包含：翹曲、厚度變異、表面微粒、不規則性、裂痕、脫層、以及變色。 The semiconductor wafer 500 is electrically tested and inspected as part of the quality control process. Manual visual inspection and automatic optical systems are used to perform inspections on the semiconductor wafer 500. The software is used in the automatic optical analysis of the semiconductor wafer 500. The visual inspection method may use equipment such as a scanning electron microscope, high-intensity light or ultraviolet light, or a metallurgical microscope. Structural features of the semiconductor wafer 500 are inspected, including: warpage, thickness variation, surface particles, irregularities, cracks, delamination, and discoloration.

半導體晶粒504裡面的主動式組件和被動式組件會在晶圓級進行電氣效能與電路功能的測試。每一個半導體晶粒504係利用一探針或是其它測試裝置來測試功能與電氣參數。探針係被用來電氣接觸每一個半導體晶粒504上的節點或接觸墊512並且提供電氣刺激給該些接觸墊。半導體晶粒504會回應該些電氣刺激，該回應會被測量並且和預期的回應作比較，以便測試該半導體晶粒的功能。該些電氣測試可以包含電路功能、導線完整性、電阻係數、連續性、可靠度、接面深度、ESD、RF效能、驅動電流、臨界電流、漏電流、以及該組件類型特有的操作參數。半導體晶圓500的檢查與電氣測試可讓通過測試而被指定為KGD的半導體晶粒504使用於半導體封裝中。 The active components and passive components in the semiconductor die 504 are tested for electrical performance and circuit functions at the wafer level. Each semiconductor die 504 uses a probe or other testing device to test the functional and electrical parameters. The probe system is used to electrically contact a node or contact pad 512 on each semiconductor die 504 and provide electrical stimulation to the contact pads. The semiconductor die 504 responds to some electrical stimulus, and the response is measured and compared with the expected response to test the function of the semiconductor die. These electrical tests may include circuit function, wire integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, critical current, leakage current, and operating parameters specific to the type of component. The inspection and electrical testing of the semiconductor wafer 500 allows the semiconductor die 504 designated as KGD by the test to be used in a semiconductor package.

在圖26b中，半導體晶圓500會利用鋸片或雷射削切工具520被單體化裁切貫穿切割道506成為個別的半導體晶粒504。半導體晶圓500沿著切割道區域506裡面的一部分基礎基板材料502以沿著基礎基板側表面522的一薄削切區來單體化裁切，以便讓一部分基礎基板材料502仍保 持被設置在半導體晶粒504的側壁516上。該薄削切區的大小略大於半導體晶粒504介於半導體側壁516以及基礎基板側表面522之間的距離D3。在半導體晶粒504的側壁516上方的基礎基板材料502會在重組以及後面的單體化裁切過程期間因減少介電材料破裂而增強該裝置。於其中一實施例中，介於側壁516以及基礎基板側表面522之間的距離D3為至少10μm。於另一實施例中，介於側壁516以及基礎基板側表面522之間的距離D3的範圍為14μm至36μm。個別的半導體晶粒504皆會被檢查與電氣測試，以便找出單體化裁切後的KGD。 In FIG. 26b, the semiconductor wafer 500 is singulated using a saw blade or a laser cutting tool 520 and cut through the scribe line 506 to form individual semiconductor dies 504. The semiconductor wafer 500 is individually cut along a portion of the base substrate material 502 in the scribe line region 506 along a thin cutting area along the side surface 522 of the base substrate, so that a portion of the base substrate material 502 remains intact. The holder is disposed on the sidewall 516 of the semiconductor die 504. The size of the thin-cut region is slightly larger than the distance D3 between the semiconductor die 504 between the semiconductor sidewall 516 and the side surface 522 of the base substrate. The base substrate material 502 above the sidewalls 516 of the semiconductor die 504 will enhance the device during recombination and subsequent singularization cutting processes by reducing cracking of the dielectric material. In one embodiment, the distance D3 between the sidewall 516 and the side surface 522 of the base substrate is at least 10 μm. In another embodiment, the distance D3 between the side wall 516 and the side surface 522 of the base substrate ranges from 14 μm to 36 μm. Individual semiconductor dies 504 are inspected and electrically tested to find the KGD after singulation cutting.

圖26C所示的係一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板530的一部分的剖視圖。一介面層或雙面膠帶532會被形成在載體530的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。 The system shown in FIG. 26C is a carrier or temporary substrate 530 containing a sacrificial base material (for example, silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid materials for structural support purposes). Partial sectional view. An interface layer or a double-sided adhesive tape 532 is formed on the carrier 530 and serves as a temporary adhesive solder film, an etch stop layer, or a thermal release layer.

載體530能夠為一可容納多個半導體晶粒504的圓形或矩形鑲板(大於300mm)。載體530的表面積可以大於半導體晶圓500的表面積。較大的載體會降低半導體封裝的製造成本，因為有較多的半導體晶粒能夠在該較大載體上被處理，從而降低每個單元的成本。半導體封裝與處理設備會針對正在被處理的晶圓或載體的大小來設計與配置。 The carrier 530 can be a circular or rectangular panel (greater than 300 mm) that can accommodate a plurality of semiconductor dies 504. The surface area of the carrier 530 may be larger than the surface area of the semiconductor wafer 500. A larger carrier reduces the manufacturing cost of a semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or carrier being processed.

為進一步降低製造成本，載體530的大小會不相依於半導體晶粒504的大小或半導體晶圓500的大小來選擇。也就是，載體530具有固定或是標準化大小，其能夠容納從一或更多個半導體晶圓500處單體化裁切出來的各種大小半導體晶粒504。於其中一實施例中，載體530為直徑 330mm的圓形。於另一實施例中，載體530為寬度560mm以及長度600mm的矩形。半導體晶粒504可以有10mm乘10mm的面積，它們係被放置在標準化載體530上。或者，半導體晶粒504可以有20mm乘20mm的面積，它們被放置在相同的標準化載體530上。據此，標準化載體530能夠應付任何大小的半導體晶粒504，其允許後續的半導體處理設備針對共同的載體被標準化，也就是，不相依於晶粒大小或是進料晶圓大小。半導體封裝設備能夠針對一標準晶圓來設計與配置，利用一組共同的處理工具、設備、以及材料清單來處理來自任何進料晶圓大小的任何半導體晶粒大小。該共同或標準化載體530藉由減少或消弭以晶粒大小或進料晶圓大小為基礎的特殊化半導體處理線的需求而降低製造成本與資本風險。藉由選擇預設的載體大小用在來自所有半導體晶圓的任何大小半導體晶粒便能夠施行靈活的製造線。 In order to further reduce manufacturing costs, the size of the carrier 530 may be selected independently of the size of the semiconductor die 504 or the size of the semiconductor wafer 500. That is, the carrier 530 has a fixed or standardized size, which can accommodate semiconductor chips 504 of various sizes cut out from one or more semiconductor wafers 500 singulated. In one embodiment, the carrier 530 has a diameter 330mm round. In another embodiment, the carrier 530 is a rectangle with a width of 560 mm and a length of 600 mm. The semiconductor die 504 may have an area of 10 mm by 10 mm, and they are placed on a standardized carrier 530. Alternatively, the semiconductor die 504 may have an area of 20 mm by 20 mm, and they are placed on the same standardized carrier 530. According to this, the standardized carrier 530 can cope with semiconductor dies of any size 504, which allows subsequent semiconductor processing equipment to be standardized for a common carrier, that is, independent of the die size or the size of the incoming wafer. Semiconductor packaging equipment can be designed and configured for a standard wafer, utilizing a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 530 reduces manufacturing costs and capital risks by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size. Flexible manufacturing lines can be implemented by selecting a preset carrier size for use with any size semiconductor die from all semiconductor wafers.

在圖26d中，圖26b中的半導體晶粒504被裝設至載體530與介面層532，舉例來說，利用拾放操作，絕緣層514則被定位朝向載體530。 In FIG. 26d, the semiconductor die 504 in FIG. 26b is mounted on the carrier 530 and the interface layer 532. For example, using a pick and place operation, the insulating layer 514 is positioned toward the carrier 530.

圖26e所示的係半導體晶粒504被裝設至載體530的介面層532，用以形成重組式晶圓或重新配置晶圓336。於其中一實施例中，絕緣層514被嵌入在介面層532裡面。舉例來說，半導體晶粒504的主動表面510可以共面於介面層532的表面534。於另一實施例中，絕緣層514被裝設在介面層532的上方，俾使得半導體晶粒504的主動表面510偏離介面層532。 The semiconductor die 504 shown in FIG. 26e is mounted on the interface layer 532 of the carrier 530 to form a reassembled wafer or a reconfigured wafer 336. In one embodiment, the insulating layer 514 is embedded in the interface layer 532. For example, the active surface 510 of the semiconductor die 504 may be coplanar with the surface 534 of the interface layer 532. In another embodiment, the insulating layer 514 is disposed above the interface layer 532 such that the active surface 510 of the semiconductor die 504 is offset from the interface layer 532.

重組式晶圓或重組式鑲板536能夠被處理成許多類型的半導體封裝，其包含扇入WLCSP、重組式WLCSP或是eWLCSP、扇出WLCSP、 覆晶封裝、3D封裝(例如，PoP)、或是其它半導體封裝。重組式鑲板536會根據所生成的半導體封裝的規格來配置。於其中一實施例中，多個半導體晶粒504以高密度排列方式被放置在載體530上，也就是，分隔300μm或更小，以便處理扇入裝置。多個半導體晶粒504被放置在載體530，半導體晶粒504之間分離一間隙或距離D4。半導體晶粒504之間的距離D4係以要被處理的半導體封裝的設計與規格來選擇。於其中一實施例中，半導體晶粒504之間的距離D4為50μm或更小。於另一實施例中，半導體晶粒504之間的距離D4為100μm或更小。載體530上的半導體晶粒504之間的距離D4會被最佳化，以便以最低的單元成本來製造半導體封裝。 The reassembled wafer or reassembled panel 536 can be processed into many types of semiconductor packages, including fan-in WLCSP, recombined WLCSP or eWLCSP, fan-out WLCSP, Flip-chip packaging, 3D packaging (eg, PoP), or other semiconductor packaging. The recombination panel 536 is configured according to the specifications of the generated semiconductor package. In one embodiment, a plurality of semiconductor dies 504 are placed on the carrier 530 in a high-density arrangement, that is, separated by 300 μm or less in order to process a fan-in device. A plurality of semiconductor dies 504 are placed on the carrier 530, and the semiconductor dies 504 are separated by a gap or distance D4. The distance D4 between the semiconductor dies 504 is selected based on the design and specifications of the semiconductor package to be processed. In one embodiment, the distance D4 between the semiconductor dies 504 is 50 μm or less. In another embodiment, the distance D4 between the semiconductor dies 504 is 100 μm or less. The distance D4 between the semiconductor dies 504 on the carrier 530 is optimized to manufacture a semiconductor package with the lowest unit cost.

圖26f所示的係重組式鑲板536的平面圖，其具有被設置在載體530上方的半導體晶粒504。載體530係一標準化的形狀與大小，可容納從各種大小的半導體晶圓處單體化裁切出來的各種大小與數量的半導體晶粒。於其中一實施例中，載體530為矩形形狀並且具有560mm的寬度W3以及600mm的長度L3。被裝設至載體530的半導體晶粒504的數量能夠大於、小於、或是等於從半導體晶圓500處單體化裁切出來的半導體晶粒504的數量。載體530的較大表面積會容納較多的半導體晶粒504並且降低製造成本，因為每一個重組式鑲板536中會處理較多的半導體晶粒504。 A plan view of the reorganized panel 536 shown in FIG. 26f has a semiconductor die 504 disposed above a carrier 530. The carrier 530 has a standardized shape and size, and can accommodate semiconductor chips of various sizes and quantities cut out from semiconductor wafers of various sizes. In one embodiment, the carrier 530 is rectangular and has a width W3 of 560 mm and a length L3 of 600 mm. The number of the semiconductor dies 504 mounted on the carrier 530 can be greater than, less than, or equal to the number of the semiconductor dies 504 singulated from the semiconductor wafer 500. The larger surface area of the carrier 530 will accommodate more semiconductor dies 504 and reduce manufacturing costs, as more semiconductor dies 504 will be processed in each reassembled panel 536.

該標準化載體(載體530)的大小固定並且能夠容納多種大小的半導體晶粒。標準化載體530的大小不相依於半導體晶粒或半導體晶圓的維度。相較於較大的半導體晶粒，有更多小型半導體晶粒能夠適配在載體530上。舉例來說，載體530在載體530的表面積上方容納5mm乘5mm的晶粒的數量大於在載體530的表面積上方容納10mm乘10mm的晶粒的數 量。 The standardized carrier (carrier 530) has a fixed size and is capable of accommodating semiconductor dies of various sizes. The size of the standardized carrier 530 does not depend on the dimensions of the semiconductor die or semiconductor wafer. Compared with larger semiconductor dies, there are more small semiconductor dies that can fit on the carrier 530. For example, the number of crystal grains of 5 mm by 5 mm above the surface area of the carrier 530 is greater than the number of crystal grains of 10 mm by 10 mm above the surface area of the carrier 530 the amount.

舉例來說，面積為10mm乘10mm的多個半導體晶粒504被放置在載體530上方，相鄰的半導體晶粒504之間的距離D4為200μm。從半導體晶圓500處單體化裁切出來的半導體晶粒504的數量為約600個半導體晶粒，其中，半導體晶圓500的直徑為300mm。能夠適配在載體530上的10mm乘10mm的半導體晶粒504的數量超過3,000個半導體晶粒。或者，面積為5mm乘5mm的多個半導體晶粒504被放置在載體530上方，相鄰的半導體晶粒504之間的距離D4為200μm。從半導體晶圓500處單體化裁切出來的半導體晶粒504的數量為約1,000個半導體晶粒，其中，半導體晶圓500的直徑為200mm。能夠適配在載體530上的5mm乘5mm的半導體晶粒504的數量超過12,000個半導體晶粒。 For example, a plurality of semiconductor dies 504 having an area of 10 mm by 10 mm are placed above the carrier 530, and a distance D4 between adjacent semiconductor dies 504 is 200 μm. The number of semiconductor dies 504 singulated from the semiconductor wafer 500 is about 600 semiconductor dies, and the diameter of the semiconductor wafer 500 is 300 mm. The number of semiconductor die 504 that can fit 10 mm by 10 mm on the carrier 530 exceeds 3,000 semiconductor die. Alternatively, a plurality of semiconductor crystal grains 504 having an area of 5 mm by 5 mm are placed above the carrier 530, and a distance D4 between adjacent semiconductor crystal grains 504 is 200 μm. The number of semiconductor dies 504 singulated from the semiconductor wafer 500 is about 1,000 semiconductor dies, and the diameter of the semiconductor wafer 500 is 200 mm. The number of 5 mm by 5 mm semiconductor dies 504 that can fit on the carrier 530 exceeds 12,000 semiconductor dies.

載體530的大小不會隨著正在被處理的半導體晶粒的大小改變。適配在載體530上的半導體晶粒504的數量隨著半導體晶粒504的大小以及半導體晶粒504之間的間隔或距離D4而改變。載體530的大小與形狀保持固定並且不相依於半導體晶粒504的大小或是用以單體化裁切出半導體晶粒504的半導體晶圓500的大小。載體530與重組式鑲板536提供利用一組共同處理設備(例如，圖13h中的處理設備340)來製造許多不同類型半導體封裝的靈活性，該些不同類型的半導體封裝具有來自不同大小半導體晶圓500的不同大小半導體晶粒504。 The size of the carrier 530 does not change with the size of the semiconductor die being processed. The number of semiconductor dies 504 fitted on the carrier 530 varies with the size of the semiconductor dies 504 and the interval or distance D4 between the semiconductor dies 504. The size and shape of the carrier 530 remain fixed and do not depend on the size of the semiconductor die 504 or the size of the semiconductor wafer 500 used to singulate the semiconductor die 504. The carrier 530 and the recombination panel 536 provide the flexibility to use a common set of processing equipment (e.g., processing equipment 340 in FIG. 13h) to fabricate many different types of semiconductor packages having different sizes of semiconductor crystals. Circle 500 of different size semiconductor dies 504.

在圖26g中，一囊封體或模製化合物550會利用焊膏印刷塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒504以及載體530的上 方。囊封體550能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體550係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。於另一實施例中，囊封體550係一絕緣層或介電層，其含有由下面所製成的一或更多層：光敏低固化溫度介電光阻、光敏合成光阻、層疊化合物膜、具有填充劑的絕緣膏、焊劑遮罩光阻膜、液體或粒狀模製化合物、聚亞醯胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、膠片、或是具有雷同絕緣特性及結構特性的其它介電材料，它們係利用印刷、旋塗、噴塗、有熱或無熱的真空層疊或壓力層疊、或是其它合宜製程所沉積。於其中一實施例中，囊封體550係一在低於200℃處固化之具有或不具有絕緣填充劑的低溫固化光敏介電聚合物。 In FIG. 26g, an encapsulation body or a molding compound 550 is applied by a solder paste printing coater, a transfer molding coater, a liquid encapsulation body molding coater, a vacuum lamination coater, and a spin coater. Or other suitable coater is deposited on the semiconductor die 504 and the carrier 530 square. The encapsulant 550 can be a polymer synthetic material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulation body 550 is a non-conductor and provides environmental protection for the semiconductor device, and is protected from external elements and pollutants. In another embodiment, the encapsulant 550 is an insulating layer or a dielectric layer, which contains one or more layers made of: a photosensitive low curing temperature dielectric photoresist, a photosensitive synthetic photoresist, and a laminated compound Film, insulating paste with filler, solder mask photoresist film, liquid or granular molding compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, film, or similar insulation Other dielectric materials with special properties and structural properties are deposited by printing, spin coating, spray coating, vacuum or pressure lamination with or without heat, or other suitable processes. In one embodiment, the encapsulant 550 is a low-temperature-curable photosensitive dielectric polymer cured with or without an insulating filler at a temperature below 200 ° C.

明確地說，囊封體550沿著基礎基板側表面522被設置。囊封體550還覆蓋半導體晶粒504的背表面508。於其中一實施例中，囊封體550為不透明並且為暗色或黑色。囊封體550能夠被用於雷射標記重組式鑲板536，以便進行對齊與單體化裁切。囊封體550會在後續的背研磨步驟中被薄化。囊封體550亦能夠被沉積而使得囊封體550與半導體晶粒504的背表面508共面並且不會覆蓋該背表面508。反向於背側表面552的囊封體550的表面554被設置在載體530與介面層532的上方，俾使得囊封體550的表面554可以共面於半導體晶粒504的主動表面510。 Specifically, the encapsulation body 550 is provided along the base substrate side surface 522. The encapsulation body 550 also covers the back surface 508 of the semiconductor die 504. In one embodiment, the encapsulation body 550 is opaque and dark or black. The encapsulation body 550 can be used for laser marking recombination panels 536 for alignment and singularization cutting. The encapsulation body 550 is thinned in a subsequent back grinding step. The encapsulation body 550 can also be deposited such that the encapsulation body 550 is coplanar with the back surface 508 of the semiconductor die 504 and does not cover the back surface 508. A surface 554 of the encapsulation body 550 opposite to the back surface 552 is disposed above the carrier 530 and the interface layer 532, so that the surface 554 of the encapsulation body 550 can be coplanar with the active surface 510 of the semiconductor die 504.

在圖26h中，載體530與介面層532會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，以便露出絕緣層514、導體層512、以及囊封體550的表面554。 In FIG. 26h, the carrier 530 and the interface layer 532 are removed by chemical etching, mechanical stripping, CMP, mechanical polishing, thermal baking, UV light, laser scanning, or wet removal, so that The insulating layer 514, the conductive layer 512, and the surface 554 of the encapsulation body 550 are exposed.

一導電層560會利用印刷、PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化與金屬沉積製程被形成在絕緣層514與導體層512的上方。導體層560能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ti、Ni、Au、Ag、W、或是其它合宜的導電材料。一部分的導體層560沿著絕緣層514並且平行於半導體晶粒504的主動表面510水平延伸，以便橫向重新分佈該電氣互連線至導體層512。導體層560的操作如同用於半導體晶粒504之電氣信號的RDL。導體層560被形成在半導體晶粒504的一覆蓋區上方並且不會延伸超過半導體晶粒504的該覆蓋區以及不會延伸在囊封體550的上方。換言之，相鄰於半導體晶粒504的半導體晶粒504的一周邊區域沒有導體層560，俾使得囊封體550保持沒有導體層560。於其中一實施例中，導體層560被形成為和半導體晶粒504的側壁516相隔距離D5，並且距離D5至少為1μm。一部分的導體層560被電氣連接至導體層512。導體層560的其它部分則相依於半導體晶粒504的連接而共電或是被電氣隔離。 A conductive layer 560 is formed over the insulating layer 514 and the conductive layer 512 by a patterning and metal deposition process using printing, PVD, CVD, sputtering, electrolyte plating, and electrodeless plating. The conductive layer 560 can be made of one or more layers made of Al, Cu, Sn, Ti, Ni, Au, Ag, W, or other suitable conductive materials. A portion of the conductor layer 560 extends horizontally along the insulating layer 514 and parallel to the active surface 510 of the semiconductor die 504 so as to laterally redistribute the electrical interconnection line to the conductor layer 512. The conductor layer 560 operates like an RDL for electrical signals of the semiconductor die 504. The conductive layer 560 is formed over a coverage area of the semiconductor die 504 and does not extend beyond the coverage area of the semiconductor die 504 and does not extend above the encapsulation body 550. In other words, a peripheral region of the semiconductor die 504 adjacent to the semiconductor die 504 has no conductive layer 560, so that the encapsulation body 550 remains free of the conductive layer 560. In one embodiment, the conductive layer 560 is formed to be separated from the sidewall 516 of the semiconductor die 504 by a distance D5, and the distance D5 is at least 1 μm. A part of the conductor layer 560 is electrically connected to the conductor layer 512. The other parts of the conductor layer 560 are electrically connected or electrically isolated depending on the connection of the semiconductor die 504.

在圖26i中，一絕緣層或鈍化層562會利用下面方法被形成在絕緣層514和導體層560的上方：PVD、CVD、印刷、旋塗、噴塗、網印、或是層疊。絕緣層562能夠係由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層562係一在低於200℃處被低溫固化的光敏介電質聚合物。於其中一實施例中，絕緣層562被形成在半導體晶粒504的該覆蓋區裡面並且不會延伸超過囊封體550上方的半導體晶粒504的該覆蓋區。換言之，相鄰於半導體晶粒504的半導體晶粒504的一周邊區域沒有絕緣層562，俾使得囊封體550保持沒有絕緣層562。於另一實施例中，絕緣層562 被形成在絕緣層514、半導體晶粒504、以及囊封體550的上方。一部分絕緣層562會利用一已圖樣化光阻層被一蝕刻製程移除或是藉由LDA來移除，用以形成多個開口，以便露出導體層560。 In FIG. 26i, an insulating layer or passivation layer 562 is formed over the insulating layer 514 and the conductive layer 560 by the following methods: PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 562 can be made of one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating properties and structural properties. In one embodiment, the insulating layer 562 is a photosensitive dielectric polymer that is cured at a temperature lower than 200 ° C. In one embodiment, the insulating layer 562 is formed inside the cover area of the semiconductor die 504 and does not extend beyond the cover area of the semiconductor die 504 above the encapsulation body 550. In other words, a peripheral region of the semiconductor die 504 adjacent to the semiconductor die 504 has no insulating layer 562, so that the encapsulation body 550 remains free of the insulating layer 562. In another embodiment, the insulating layer 562 It is formed above the insulating layer 514, the semiconductor die 504, and the encapsulation body 550. A part of the insulating layer 562 is removed by an etching process using a patterned photoresist layer or by LDA to form a plurality of openings to expose the conductive layer 560.

一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層560的上方。於其中一實施例中，該凸塊材料係利用一丸滴模板來沉積，也就是，不需要用到任何遮罩。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層560。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊564。於某些應用中，凸塊564會被二次回焊，以便改良和導體層560的電氣接觸效果。凸塊564亦能夠被壓縮焊接或熱壓縮焊接至導體層560。凸塊564代表能夠被形成在導體層560上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。雷射標記能夠在凸塊成形之前或之後或是在移除載體530之後被實施。 A conductive bump material is deposited on the conductive layer 560 by using an evaporation process, an electrolytic plating process, an electrodeless plating process, a pill process, or a screen printing process. In one embodiment, the bump material is deposited using a drop template, that is, no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and a combination thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high-lead solder, or a lead-free solder. The bump material is soldered to the conductor layer 560 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 564. In some applications, the bumps 564 are re-soldered to improve the electrical contact with the conductive layer 560. The bump 564 can also be compression welded or thermally compressed to the conductor layer 560. The bump 564 represents one of the types of interconnect structures that can be formed over the conductor layer 560. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines. The laser marking can be implemented before or after the bump is formed or after the carrier 530 is removed.

絕緣層562、導體層560、以及凸塊564一起構成被形成在半導體晶粒504上方及半導體晶粒504的一覆蓋區裡面的囊封體550上方的增進互連結構566。相鄰於半導體晶粒504的半導體晶粒504的一周邊區域不會有互連結構566，俾使得囊封體550的表面554仍保持從互連結構566處露出。增進互連結構566可以僅包含一RDL或導體層(例如，導體層560)以及一絕緣層(例如，絕緣層562)。額外的絕緣層和RDL會在形成凸塊564 之前被形成在絕緣層562的上方，以便根據半導體晶粒504的設計和功能在該封裝中提供額外的垂直與水平電氣連接。 The insulating layer 562, the conductor layer 560, and the bumps 564 together form an enhanced interconnect structure 566 formed over the encapsulation body 550 formed over the semiconductor die 504 and in a footprint of the semiconductor die 504. A peripheral region of the semiconductor die 504 adjacent to the semiconductor die 504 does not have the interconnect structure 566, so that the surface 554 of the encapsulation body 550 remains exposed from the interconnect structure 566. The enhanced interconnect structure 566 may include only an RDL or conductor layer (eg, the conductor layer 560) and an insulation layer (eg, the insulation layer 562). Additional insulation and RDL will form bumps 564 It was previously formed over the insulating layer 562 to provide additional vertical and horizontal electrical connections in the package based on the design and function of the semiconductor die 504.

在圖26j中，半導體晶粒504會利用鋸片或雷射削切工具570被單體化裁切成為個別的eWLCSP 572。重組式鑲板536沿著側表面580被單體化裁切貫穿囊封體550以及基礎基板材料502，用以從半導體晶粒504的該些側邊處移除囊封體550以及從半導體晶粒504的該些側邊處移除一部分的基礎基板材料502。所以，基礎基板材料502會在eWLCSP 572的形成期間被切割或單體化裁切兩次，一次在晶圓級而一次在重組式鑲板級。因此，介電材料比較不會破裂並且eWLCSP 572的可靠度會獲得改善。 In FIG. 26j, the semiconductor die 504 is singulated into individual eWLCSP 572 using a saw blade or a laser cutting tool 570. The recombination panel 536 is singulated and cut through the encapsulation body 550 and the base substrate material 502 along the side surface 580, so as to remove the encapsulation body 550 from the sides of the semiconductor die 504 and the semiconductor wafer 504. A portion of the base substrate material 502 is removed at the sides of the particles 504. Therefore, the base substrate material 502 is cut or singulated during the formation of the eWLCSP 572 twice, once at the wafer level and once at the recombination panel level. As a result, the dielectric material is less likely to crack and the reliability of eWLCSP 572 is improved.

一部分的基礎基板材料502會在單體化裁切之後保持被設置在半導體晶粒504的側壁516中。在側壁516上方相鄰於半導體晶粒504的基礎基板材料502的厚度為至少1μm。換言之，介於側表面580和半導體晶粒504的側壁516之間的距離D6為至少1μm。eWLCSP 572會在單體化裁切之前或之後進行電氣測試。 A portion of the base substrate material 502 will remain in the sidewall 516 of the semiconductor die 504 after singulation cutting. The thickness of the base substrate material 502 above the sidewall 516 adjacent to the semiconductor die 504 is at least 1 μm. In other words, the distance D6 between the side surface 580 and the sidewall 516 of the semiconductor die 504 is at least 1 μm. The eWLCSP 572 undergoes electrical testing before or after singulation cutting.

圖26k所示的係單體化裁切之後的eWLCSP 572，其具有囊封體，用以覆蓋半導體晶粒504的背表面508。半導體晶粒504經由導體層512與560被電氣連接至凸塊564，以便經由互連結構566達到外部互連的目的。互連結構566不會延伸超過半導體晶粒504的一覆蓋區，並且因而形成一扇入封裝。囊封體550仍殘留在半導體晶粒504的背表面508上方。在半導體晶粒504的背表面508上方的囊封體550省略背側保護層或背側疊板的需求，因而降低eWLCSP 572的成本。囊封體550在單體化裁切期間從半導體晶粒504的側邊處被完全移除，以便露出基礎基板材料502的側表面 580。於其中一實施例中，eWLCSP 572的面積為約長度4.445mm x寬度3.875mm，凸塊564的節距為0.35至0.50mm。eWLCSP 572係利用針對單一標準化載體大小所設計的設備藉由在標準化載體530上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 572的設備成本與材料成本。eWLCSP 572係利用標準化載體530以較高的數量來製造，從而簡化製造過程並且降低單元成本。 The eWLCSP 572 shown in FIG. 26k is singulated and cut. The eWLCSP 572 has an encapsulation body for covering the back surface 508 of the semiconductor die 504. The semiconductor die 504 is electrically connected to the bump 564 via the conductor layers 512 and 560 so as to achieve the purpose of external interconnection via the interconnect structure 566. The interconnect structure 566 does not extend beyond a footprint of the semiconductor die 504 and thus forms a fan-in package. The encapsulation body 550 still remains above the back surface 508 of the semiconductor die 504. The encapsulation body 550 above the back surface 508 of the semiconductor die 504 omits the need for a backside protective layer or a backside stack, thereby reducing the cost of the eWLCSP 572. The encapsulation body 550 is completely removed from the side of the semiconductor die 504 during singulation cutting so as to expose the side surface of the base substrate material 502 580. In one embodiment, the area of the eWLCSP 572 is approximately 4.445 mm in length x 3.875 mm in width, and the pitch of the bumps 564 is 0.35 to 0.50 mm. The eWLCSP 572 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 530, which will reduce the equipment cost and material cost of the eWLCSP 572. The eWLCSP 572 is manufactured in higher quantities using standardized carriers 530, thereby simplifying the manufacturing process and reducing unit costs.

圖27所示的係一eWLCSP 590，其具有裸露的背側與側壁。半導體晶粒504經由導體層512與560被電氣連接至凸塊564，以便經由互連結構566達到外部互連的目的。互連結構566不會延伸超過半導體晶粒504的一覆蓋區，並且因而形成一扇入封裝。囊封體550在研磨操作期間從半導體晶粒504的背表面508處被完全移除。囊封體550在單體化裁切期間從半導體晶粒504的側邊處被完全移除，以便露出基礎基板材料502的側表面580。於其中一實施例中，eWLCSP 590的面積為約長度4.4mm x寬度3.9mm，凸塊564的節距為0.35至0.50mm。eWLCSP 590係利用針對單一標準化載體大小所設計的設備藉由在標準化載體530上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 590的設備成本與材料成本。eWLCSP 590係利用標準化載體530以較高的數量來製造，從而簡化製造過程並且降低單元成本。 The eWLCSP 590 shown in FIG. 27 has an exposed back side and a side wall. The semiconductor die 504 is electrically connected to the bump 564 via the conductor layers 512 and 560 so as to achieve the purpose of external interconnection via the interconnect structure 566. The interconnect structure 566 does not extend beyond a footprint of the semiconductor die 504 and thus forms a fan-in package. The encapsulation body 550 is completely removed from the back surface 508 of the semiconductor die 504 during the grinding operation. The encapsulation body 550 is completely removed from the side edges of the semiconductor die 504 during singulation cutting so as to expose the side surface 580 of the base substrate material 502. In one embodiment, the area of the eWLCSP 590 is approximately 4.4 mm in length x 3.9 mm in width, and the pitch of the bumps 564 is 0.35 to 0.50 mm. The eWLCSP 590 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 530, which will reduce the equipment cost and material cost of the eWLCSP 590. The eWLCSP 590 is manufactured in a higher quantity using a standardized carrier 530, thereby simplifying the manufacturing process and reducing unit costs.

圖28所示的係一替代eWLCSP 592，其具有UBM 594、背側絕緣層596、以及裸露的側表面580。一導電層594會在最終重新鈍化之後利用PVD、CVD、蒸發、電解質電鍍、無電極電鍍、或是其它合宜的金屬沉積製程被形成在導體層560的裸露部分上方以及絕緣層562上方。導體層 594能夠為Al、Cu、Sn、Ni、Au、Ag、W、或是其它合宜的導電材料。導體層594係一UBM，其被電氣連接至導體層560與512。UBM 594能夠係一具有黏著層、屏障層、以及晶種層或潤濕層的多金屬堆疊。黏著層係被形成在導體層182的上方並且能夠為Ti、TiN、TiW、Al、或是Cr。屏障層係被形成在黏著層的上方並且能夠為Ni、NiV、Pt、Pd、TiW、Ti、或是CrCu。該屏障層會阻止Cu擴散至半導體晶粒504的主動表面510之中。晶種層係被形成在屏障層的上方並且能夠為Cu、Ni、NiV、Au、或是Al。UBM 594為導體層512提供一低阻值互連線，並且提供一屏障阻止焊料擴散，以及提供用於焊料潤濕的晶種層。 A replacement eWLCSP 592 shown in FIG. 28 has a UBM 594, a back-side insulating layer 596, and an exposed side surface 580. A conductive layer 594 is formed over the exposed portion of the conductive layer 560 and the insulating layer 562 by PVD, CVD, evaporation, electrolytic plating, electrodeless plating, or other suitable metal deposition processes after final re-passivation. Conductor layer 594 can be Al, Cu, Sn, Ni, Au, Ag, W, or other suitable conductive materials. The conductor layer 594 is a UBM, which is electrically connected to the conductor layers 560 and 512. UBM 594 can be a multi-metal stack with an adhesion layer, a barrier layer, and a seed layer or a wetting layer. The adhesive layer system is formed above the conductor layer 182 and can be Ti, TiN, TiW, Al, or Cr. The barrier layer is formed above the adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti, or CrCu. The barrier layer prevents Cu from diffusing into the active surface 510 of the semiconductor die 504. The seed layer system is formed over the barrier layer and can be Cu, Ni, NiV, Au, or Al. UBM 594 provides a low-resistance interconnect for conductor layer 512, and provides a barrier to prevent solder diffusion, and a seed layer for solder wetting.

半導體晶粒504經由導體層512、560、以及594被電氣連接至凸塊564，以便經由互連結構566達到外部互連的目的。導體層560與594以及絕緣層514與562不會延伸超過半導體晶粒504的一覆蓋區，並且因而形成一扇入封裝。背側絕緣層596被形成在半導體晶粒504的背表面508的上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。背側絕緣層596含有由下面所製成的一或更多層：光敏低固化溫度介電光阻、光敏合成光阻、層疊化合物膜、具有填充劑的絕緣膏、焊劑遮罩光阻膜、液體或粒狀模製化合物、聚亞醯胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、膠片、或是具有雷同絕緣特性及結構特性的其它介電材料。背側絕緣層596係利用印刷、旋塗、噴塗、有熱或無熱的真空層疊或壓力層疊、或是其它合宜製程所沉積。於其中一實施例中，背側絕緣層596係一在低於200℃處固化之具有或不具有絕緣填充劑的低溫固化光敏介電聚合物。背側絕緣層596係一背側保護層並且為半導體 晶粒504提供機械性保護以及避免受到光的影響。於其中一實施例中，背側絕緣層596的厚度範圍從約5μm至150μm。 The semiconductor die 504 is electrically connected to the bump 564 via the conductor layers 512, 560, and 594 so as to achieve the purpose of external interconnection via the interconnect structure 566. The conductive layers 560 and 594 and the insulating layers 514 and 562 do not extend beyond a footprint of the semiconductor die 504 and thus form a fan-in package. The back-side insulating layer 596 is formed above the back surface 508 of the semiconductor die 504 to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation. The back-side insulating layer 596 contains one or more layers made of: a photosensitive low curing temperature dielectric photoresist, a photosensitive synthetic photoresist, a laminated compound film, an insulating paste with a filler, a solder mask photoresist film, Liquid or granular molding compounds, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, film, or other dielectric materials with similar insulation and structural properties. The back-side insulating layer 596 is deposited by printing, spin coating, spray coating, vacuum lamination with or without heat or pressure lamination, or other suitable processes. In one embodiment, the back-side insulating layer 596 is a low-temperature-curable photosensitive dielectric polymer cured with or without an insulating filler at a temperature lower than 200 ° C. The back-side insulating layer 596 is a back-side protective layer and is a semiconductor. The die 504 provides mechanical protection and protection from light. In one embodiment, the thickness of the back-side insulating layer 596 ranges from about 5 μm to 150 μm.

囊封體550在單體化裁切期間從半導體晶粒504的該些側邊處被完全移除，以便露出基礎基板材料502的側表面580。於其中一實施例中，eWLCSP 592的面積為約長度4.4mm x寬度3.9mm，凸塊564的節距為0.35至0.50mm。eWLCSP 592係利用針對單一標準化載體大小所設計的設備藉由在標準化載體530上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 592的設備成本與材料成本。eWLCSP 592係利用標準化載體430以較高的數量來製造，從而簡化製造過程並且降低單元成本。 The encapsulation body 550 is completely removed from the sides of the semiconductor die 504 during singulation cutting so as to expose the side surface 580 of the base substrate material 502. In one embodiment, the area of the eWLCSP 592 is approximately 4.4 mm in length x 3.9 mm in width, and the pitch of the bumps 564 is 0.35 to 0.50 mm. The eWLCSP 592 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 530, which will reduce the equipment cost and material cost of the eWLCSP 592. The eWLCSP 592 is manufactured in higher quantities using standardized carriers 430, thereby simplifying the manufacturing process and reducing unit costs.

圖29a至29i配合圖1以及2a至2c顯示一種形成重組式或嵌入式扇入WLCSP的製程。圖29a所示的係一部分半導體晶圓600的剖視圖。半導體晶圓600包含一基礎基板材料602(例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽)，用以達到結構性支撐的目的。複數個半導體晶粒或組件604會被形成在晶圓600上，藉由如上面所述之非主動的晶粒間晶圓區域或切割道606來分離。切割道606提供削切區，以便將半導體晶圓600單體化裁切成個別的半導體晶粒604。半導體晶粒604具有邊緣或側壁608。於其中一實施例中，半導體晶圓600的直徑為200至300mm。於另一實施例中，半導體晶圓600的直徑為100至450mm。在將半導體晶圓單體化裁切成個別的半導體晶粒604之前，半導體晶圓600可以有任何直徑。 Figures 29a to 29i in conjunction with Figures 1 and 2a to 2c show a process for forming a recombined or embedded fan-in WLCSP. A cross-sectional view of a portion of the semiconductor wafer 600 shown in FIG. 29a. The semiconductor wafer 600 includes a base substrate material 602 (for example, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide) for structural support purposes. A plurality of semiconductor dies or components 604 are formed on the wafer 600 and separated by inactive inter-die wafer regions or scribe lines 606 as described above. The dicing track 606 provides a cutting area for singulating the semiconductor wafer 600 into individual semiconductor dies 604. The semiconductor die 604 has edges or sidewalls 608. In one embodiment, the diameter of the semiconductor wafer 600 is 200 to 300 mm. In another embodiment, the diameter of the semiconductor wafer 600 is 100 to 450 mm. Prior to singulating the semiconductor wafer into individual semiconductor dies 604, the semiconductor wafer 600 may have any diameter.

每一個半導體晶粒604皆有一背表面或非主動表面610以及含有類比電路或數位電路的主動表面612，該些類比電路或數位電路會被施行為根據該晶粒的電氣設計與功能被形成在該晶粒裡面及電氣互連的主動 式裝置、被動式裝置、導體層、以及介電層。舉例來說，該電路可以包含被形成在主動表面612裡面的一或更多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，DSP、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒604可以還含有用於RF訊號處理的IPD，例如，電感器、電容器、以及電阻器。 Each semiconductor die 604 has a back surface or an inactive surface 610 and an active surface 612 containing analog circuits or digital circuits. The analog circuits or digital circuits are applied according to the electrical design and function of the die. Active within the die and electrical interconnection Devices, passive devices, conductor layers, and dielectric layers. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed in the active surface 612 to implement analog or digital circuits, such as DSP, ASIC, memory , Or other signal processing circuits. The semiconductor die 604 may further include an IPD for RF signal processing, such as an inductor, a capacitor, and a resistor.

一導電層512會使用PVD、CVD、電解質電鍍、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面612的上方。導體層614能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。導體層614的操作如同被電氣連接至主動表面612上之電路的接觸墊。導體層614會被形成為多個接觸墊，它們以並排的方式被設置在和半導體晶粒604的邊緣608相隔第一距離處，如圖29a之中所示。或者，導體層614會被形成為偏移在多列之中的多個接觸墊，俾使得第一列接觸墊會被設置在和半導體晶粒604的邊緣608相隔第一距離處，而與該第一列交錯的第二列接觸墊則被設置在和半導體晶粒604的邊緣608相隔第二距離處。 A conductive layer 512 is formed over the active surface 612 using a PVD, CVD, electrolyte plating, electrodeless plating process, or other suitable metal deposition process. The conductive layer 614 can be made of one or more layers made of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductor layer 614 operates like a contact pad that is electrically connected to a circuit on the active surface 612. The conductive layer 614 is formed as a plurality of contact pads, which are disposed side by side at a first distance from the edge 608 of the semiconductor die 604, as shown in FIG. 29a. Alternatively, the conductive layer 614 may be formed as a plurality of contact pads offset in a plurality of rows, so that the first row of contact pads are disposed at a first distance from the edge 608 of the semiconductor die 604 and are separated from The first row of staggered second row of contact pads are disposed at a second distance from the edge 608 of the semiconductor die 604.

一第一絕緣層或鈍化層616係利用PVD、CVD、印刷、旋塗、噴塗、燒結、或是熱氧化被形成在半導體晶粒604和導體層614的上方。絕緣層616含有由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物、或是具有雷同結構特性及絕緣特性的其它介電材料。於其中一實施例中，絕緣層616係一低溫固化光敏介電聚合物，具有或不具有在小於200℃處被固化的絕緣填充劑。絕緣層616覆蓋主動表面612並且為主動表面612提供保護。絕緣層616被保形塗敷在 導體層614以及半導體晶粒604的主動表面612的上方並且不會延伸在半導體晶粒604的側壁608上方或是超過半導體晶粒604的一覆蓋區。相鄰於半導體晶粒604的半導體晶粒604的一周邊區域沒有絕緣層616。一部分的絕緣層616會利用雷射618藉由LDA被移除，或者，藉由蝕刻製程貫穿一已圖樣化光阻層而被移除，以便經由絕緣層616露出導體層614並且用於進行後續的電氣互連。 A first insulating layer or passivation layer 616 is formed over the semiconductor die 604 and the conductor layer 614 by PVD, CVD, printing, spin coating, spray coating, sintering, or thermal oxidation. The insulating layer 616 contains one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer, or other dielectrics having similar structural and insulating properties material. In one embodiment, the insulating layer 616 is a low-temperature-curable photosensitive dielectric polymer, with or without an insulating filler that is cured at less than 200 ° C. The insulating layer 616 covers and protects the active surface 612. The insulating layer 616 is conformally applied to The conductive layer 614 and the active surface 612 of the semiconductor die 604 do not extend above the sidewall 608 of the semiconductor die 604 or exceed a coverage area of the semiconductor die 604. A peripheral region of the semiconductor die 604 adjacent to the semiconductor die 604 has no insulating layer 616. A part of the insulating layer 616 is removed by LDA using laser 618, or is removed through an patterned photoresist layer by an etching process, so that the conductive layer 614 is exposed through the insulating layer 616 and used for subsequent processes. Electrical interconnection.

半導體晶圓600會進行電氣測試與檢查，作為品質控制過程的一部分。手動視覺檢查及自動光學系統會被用來在半導體晶圓600上實施檢查。軟體會被使用在半導體晶圓600的自動光學分析中。視覺檢查方法可以運用諸如掃描電子顯微鏡、高強度光或紫外光、或是冶金顯微鏡的設備。半導體晶圓600的結構性特徵會被檢查，其包含：翹曲、厚度變異、表面微粒、不規則性、裂痕、脫層、以及變色。 The semiconductor wafer 600 is electrically tested and inspected as part of a quality control process. Manual visual inspection and automatic optical systems are used to perform inspections on the semiconductor wafer 600. The software is used in the automated optical analysis of the semiconductor wafer 600. The visual inspection method may use equipment such as a scanning electron microscope, high-intensity light or ultraviolet light, or a metallurgical microscope. Structural features of the semiconductor wafer 600 are inspected, including: warpage, thickness variation, surface particles, irregularities, cracks, delamination, and discoloration.

半導體晶粒604裡面的主動式組件和被動式組件會在晶圓級進行電氣效能與電路功能的測試。每一個半導體晶粒604係利用一探針或是其它測試裝置來測試功能與電氣參數。探針係被用來電氣接觸每一個半導體晶粒604上的節點或接觸墊614並且提供電氣刺激給該些接觸墊。半導體晶粒604會回應該些電氣刺激，該回應會被測量並且和預期的回應作比較，以便測試該半導體晶粒的功能。該些電氣測試可以包含電路功能、導線完整性、電阻係數、連續性、可靠度、接面深度、ESD、RF效能、驅動電流、臨界電流、漏電流、以及該組件類型特有的操作參數。半導體晶圓600的檢查與電氣測試可讓通過測試而被指定為KGD的半導體晶粒604使用於半導體封裝中。 The active components and passive components in the semiconductor die 604 are tested for electrical performance and circuit functions at the wafer level. Each semiconductor die 604 uses a probe or other testing device to test the functional and electrical parameters. The probe system is used to electrically contact a node or contact pad 614 on each semiconductor die 604 and provide electrical stimulation to the contact pads. The semiconductor die 604 responds to some electrical stimulus, and the response is measured and compared with the expected response to test the function of the semiconductor die. These electrical tests may include circuit function, wire integrity, resistivity, continuity, reliability, junction depth, ESD, RF performance, drive current, critical current, leakage current, and operating parameters specific to the type of component. The inspection and electrical testing of the semiconductor wafer 600 allows the semiconductor die 604 designated as KGD by the test to be used in a semiconductor package.

在圖29b中，半導體晶圓600會利用鋸片或雷射削切工具620被單體化裁切貫穿切割道606成為個別的半導體晶粒604。半導體晶圓600沿著切割道區域606裡面的一部分基礎基板材料602藉由沿著基礎基板側表面622進行削切來單體化裁切，以便讓一部分基礎基板材料602仍保持被設置在半導體晶粒604的側壁608上。介於半導體側壁608以及基礎基板側表面622之間的距離D7為至少1μm。個別的半導體晶粒604皆會被檢查與電氣測試，以便找出單體化裁切後的KGD。 In FIG. 29b, the semiconductor wafer 600 is singulated using a saw blade or a laser cutting tool 620 and cut through the scribe line 606 to become individual semiconductor dies 604. A part of the base substrate material 602 in the semiconductor wafer 600 along the scribe lane area 606 is cut individually by cutting along the side surface 622 of the base substrate so that a part of the base substrate material 602 is still set on the semiconductor crystal Particles 604 on the side walls 608. The distance D7 between the semiconductor sidewall 608 and the base substrate side surface 622 is at least 1 μm. Individual semiconductor dies 604 are inspected and electrically tested to find the KGD after singulation cutting.

圖29C所示的係一含有犧牲基礎材料(例如，矽、聚合物、氧化鈹、玻璃、或是用於達到結構性支撐之目的的其它合宜低成本剛性材料)的載體或暫時性基板630的一部分的剖視圖。一介面層或雙面膠帶632會被形成在載體630的上方，當作暫時性膠黏焊膜、蝕刻阻止層、或是熱脫模層。圖29b中的半導體晶粒604被裝設至載體630與介面層632，舉例來說，利用拾放操作，主動表面612則被定位朝向該載體。 The system shown in FIG. 29C is a carrier or temporary substrate 630 containing a sacrificial base material (for example, silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support purposes). Partial sectional view. An interface layer or a double-sided tape 632 is formed on the carrier 630, and is used as a temporary adhesive solder film, an etch stop layer, or a thermal release layer. The semiconductor die 604 in FIG. 29b is mounted to the carrier 630 and the interface layer 632. For example, using a pick-and-place operation, the active surface 612 is positioned toward the carrier.

載體630能夠為一可容納多個半導體晶粒604的圓形或矩形鑲板(大於300mm)。載體630的表面積可以大於半導體晶圓600的表面積。較大的載體會降低半導體封裝的製造成本，因為有較多的半導體晶粒能夠在該較大載體上被處理，從而降低每個單元的成本。半導體封裝與處理設備會針對正在被處理的晶圓或載體的大小來設計與配置。 The carrier 630 can be a circular or rectangular panel (greater than 300 mm) that can accommodate a plurality of semiconductor dies 604. The surface area of the carrier 630 may be larger than the surface area of the semiconductor wafer 600. A larger carrier reduces the manufacturing cost of a semiconductor package because more semiconductor dies can be processed on the larger carrier, thereby reducing the cost per unit. Semiconductor packaging and processing equipment is designed and configured for the size of the wafer or carrier being processed.

為進一步降低製造成本，載體630的大小會不相依於半導體晶粒604的大小或半導體晶圓600的大小來選擇。也就是，載體630具有固定或是標準化大小，其能夠容納從一或更多個半導體晶圓600處單體化裁切出來的各種大小半導體晶粒604。於其中一實施例中，載體630為直徑 330mm的圓形。於另一實施例中，載體630為寬度560mm以及長度600mm的矩形。半導體晶粒604可以有10mm乘10mm的面積，它們係被放置在標準化載體630上。或者，半導體晶粒604可以有20mm乘20mm的面積，它們被放置在相同的標準化載體630上。據此，標準化載體630能夠應付任何大小的半導體晶粒604，其允許後續的半導體處理設備針對共同的載體被標準化，也就是，不相依於晶粒大小或是進料晶圓大小。半導體封裝設備能夠針對一標準晶圓來設計與配置，利用一組共同的處理工具、設備、以及材料清單來處理來自任何進料晶圓大小的任何半導體晶粒大小。該共同或標準化載體630藉由減少或消弭以晶粒大小或進料晶圓大小為基礎的特殊化半導體處理線的需求而降低製造成本與資本風險。藉由選擇預設的載體大小用在來自所有半導體晶圓的任何大小半導體晶粒便能夠施行靈活的製造線。 In order to further reduce the manufacturing cost, the size of the carrier 630 may be selected independently of the size of the semiconductor die 604 or the size of the semiconductor wafer 600. That is, the carrier 630 has a fixed or standardized size, which can accommodate semiconductor dies of various sizes 604 that are individually cut out from one or more semiconductor wafers 600. In one embodiment, the carrier 630 has a diameter 330mm round. In another embodiment, the carrier 630 is a rectangle with a width of 560 mm and a length of 600 mm. The semiconductor die 604 may have an area of 10 mm by 10 mm, and they are placed on a standardized carrier 630. Alternatively, the semiconductor die 604 may have an area of 20 mm by 20 mm, and they are placed on the same standardized carrier 630. Accordingly, the standardized carrier 630 can cope with semiconductor dies of any size 604, which allows subsequent semiconductor processing equipment to be standardized for a common carrier, that is, independent of the die size or the size of the incoming wafer. Semiconductor packaging equipment can be designed and configured for a standard wafer, utilizing a common set of processing tools, equipment, and bill of materials to process any semiconductor die size from any incoming wafer size. The common or standardized carrier 630 reduces manufacturing costs and capital risks by reducing or eliminating the need for specialized semiconductor processing lines based on die size or incoming wafer size. Flexible manufacturing lines can be implemented by selecting a preset carrier size for use with any size semiconductor die from all semiconductor wafers.

圖29c所示的係半導體晶粒604被裝設至載體630的介面層632，用以形成重組式晶圓或重新配置晶圓640。於其中一實施例中，絕緣層616被嵌入在介面層632裡面。舉例來說，半導體晶粒604的主動表面612可以共面於介面層632的表面634。於另一實施例中，絕緣層616被裝設在介面層632的上方，俾使得半導體晶粒604的主動表面612偏離介面層632。 The semiconductor die 604 shown in FIG. 29c is mounted on the interface layer 632 of the carrier 630 to form a reassembled wafer or a reconfigured wafer 640. In one embodiment, the insulating layer 616 is embedded in the interface layer 632. For example, the active surface 612 of the semiconductor die 604 may be coplanar with the surface 634 of the interface layer 632. In another embodiment, the insulating layer 616 is disposed above the interface layer 632 such that the active surface 612 of the semiconductor die 604 is offset from the interface layer 632.

重組式晶圓或重組式鑲板640能夠被處理成許多類型的半導體封裝，其包含扇入WLCSP、重組式WLCSP或是eWLCSP、扇出WLCSP、覆晶封裝、3D封裝(例如，PoP)、或是其它半導體封裝。重組式鑲板640會根據所生成的半導體封裝的規格來配置。於其中一實施例中，多個半導體 晶粒604以高密度排列方式被放置在載體630上，也就是，分隔300μm或更小，以便處理扇入裝置。多個半導體晶粒604被放置在載體630，半導體晶粒604之間分離一間隙或距離D8。半導體晶粒604之間的距離D8係以要被處理的半導體封裝的設計與規格來選擇。於其中一實施例中，半導體晶粒604之間的距離D8為50μm或更小。於另一實施例中，半導體晶粒604之間的距離D8為100μm或更小。載體630上的半導體晶粒604之間的距離D8會被最佳化，以便以最低的單元成本來製造半導體封裝。 The reassembled wafer or reassembled panel 640 can be processed into many types of semiconductor packages including fan-in WLCSP, recombined WLCSP or eWLCSP, fan-out WLCSP, flip-chip package, 3D package (for example, PoP), or Other semiconductor packages. The recombination panel 640 is configured according to the specifications of the generated semiconductor package. In one embodiment, a plurality of semiconductors The dies 604 are placed on the carrier 630 in a high-density arrangement, that is, separated by 300 μm or less in order to process the fan-in device. A plurality of semiconductor dies 604 are placed on the carrier 630, and the semiconductor dies 604 are separated by a gap or distance D8. The distance D8 between the semiconductor dies 604 is selected based on the design and specifications of the semiconductor package to be processed. In one embodiment, the distance D8 between the semiconductor dies 604 is 50 μm or less. In another embodiment, the distance D8 between the semiconductor dies 604 is 100 μm or less. The distance D8 between the semiconductor dies 604 on the carrier 630 is optimized to manufacture a semiconductor package with the lowest unit cost.

圖29d所示的係重組式鑲板640的平面圖，其具有被設置在載體630上方的半導體晶粒604。載體630係一標準化的形狀與大小，可容納從各種大小的半導體晶圓處單體化裁切出來的各種大小與數量的半導體晶粒。於其中一實施例中，載體630為矩形形狀並且具有560mm的寬度W4以及600mm的長度L4。被裝設至載體630的半導體晶粒604的數量能夠大於、小於、或是等於從半導體晶圓600處單體化裁切出來的半導體晶粒604的數量。載體630的較大表面積會容納較多的半導體晶粒604並且降低製造成本，因為每一個重組式鑲板640中會處理較多的半導體晶粒604。 A plan view of the reorganized panel 640 shown in FIG. 29d, which has a semiconductor die 604 disposed above a carrier 630. The carrier 630 has a standardized shape and size, and can accommodate semiconductor chips of various sizes and numbers cut from individual sizes of semiconductor wafers. In one embodiment, the carrier 630 is rectangular and has a width W4 of 560 mm and a length L4 of 600 mm. The number of the semiconductor dies 604 mounted on the carrier 630 can be greater than, less than, or equal to the number of the semiconductor dies 604 singulated from the semiconductor wafer 600. The larger surface area of the carrier 630 will accommodate more semiconductor dies 604 and reduce manufacturing costs, as more semiconductor dies 604 will be processed in each reassembled panel 640.

該標準化載體(載體630)的大小固定並且能夠容納多種大小的半導體晶粒。標準化載體630的大小不相依於半導體晶粒或半導體晶圓的維度。相較於較大的半導體晶粒，有更多小型半導體晶粒能夠適配在載體630上。舉例來說，載體630在載體630的表面積上方容納5mm乘5mm的晶粒的數量大於在載體630的表面積上方容納10mm乘10mm的晶粒的數量。 The standardized carrier (carrier 630) has a fixed size and is capable of accommodating semiconductor dies of various sizes. The size of the standardized carrier 630 does not depend on the dimensions of the semiconductor die or semiconductor wafer. Compared with larger semiconductor dies, there are more small semiconductor dies that can fit on the carrier 630. For example, the number of crystal grains of 5 mm by 5 mm above the surface area of the carrier 630 is greater than the number of crystal grains of 10 mm by 10 mm above the surface area of the carrier 630.

舉例來說，面積為10mm乘10mm的多個半導體晶粒604被 放置在載體630上方，相鄰的半導體晶粒604之間的距離D8為200μm。從半導體晶圓600處單體化裁切出來的半導體晶粒604的數量為約600個半導體晶粒，其中，半導體晶圓600的直徑為300mm。能夠適配在載體630上的10mm乘10mm的半導體晶粒604的數量超過3,000個半導體晶粒。 For example, a plurality of semiconductor dies 604 having an area of 10 mm by 10 mm are Placed on the carrier 630, the distance D8 between the adjacent semiconductor dies 604 is 200 μm. The number of semiconductor dies 604 singulated from the semiconductor wafer 600 is about 600 semiconductor dies, and the diameter of the semiconductor wafer 600 is 300 mm. The number of semiconductor dies 10 by 10 mm that can fit on the carrier 630 exceeds 3,000 semiconductor dies.

或者，面積為5mm乘5mm的多個半導體晶粒604被放置在載體630上方，相鄰的半導體晶粒604之間的距離D8為200μm。從半導體晶圓600處單體化裁切出來的半導體晶粒604的數量為約1,000個半導體晶粒，其中，半導體晶圓600的直徑為200mm。能夠適配在載體630上的5mm乘5mm的半導體晶粒604的數量超過12,000個半導體晶粒。 Alternatively, a plurality of semiconductor dies 604 having an area of 5 mm by 5 mm are placed over the carrier 630, and a distance D8 between adjacent semiconductor dies 604 is 200 μm. The number of semiconductor dies 604 singulated from the semiconductor wafer 600 is about 1,000 semiconductor dies, and the diameter of the semiconductor wafer 600 is 200 mm. The number of 5mm by 5mm semiconductor dies 604 that can fit on the carrier 630 exceeds 12,000 semiconductor dies.

載體630的大小不會隨著正在被處理的半導體晶粒的大小改變。適配在載體630上的半導體晶粒604的數量隨著半導體晶粒604的大小以及半導體晶粒604之間的間隔或距離D8而改變。載體630的大小與形狀保持固定並且不相依於半導體晶粒604的大小或是用以單體化裁切出半導體晶粒604的半導體晶圓600的大小。載體630與重組式鑲板640提供利用一組共同處理設備(例如，圖13h中的處理設備340)來製造許多不同類型半導體封裝的靈活性，該些不同類型的半導體封裝具有來自不同大小半導體晶圓600的不同大小半導體晶粒604。 The size of the carrier 630 does not change with the size of the semiconductor die being processed. The number of semiconductor dies 604 fitted on the carrier 630 varies with the size of the semiconductor dies 604 and the interval or distance D8 between the semiconductor dies 604. The size and shape of the carrier 630 remains fixed and does not depend on the size of the semiconductor die 604 or the size of the semiconductor wafer 600 used to singulate the semiconductor die 604. The carrier 630 and the recombination panel 640 provide the flexibility to use a common set of processing equipment (e.g., processing equipment 340 in FIG. 13h) to fabricate many different types of semiconductor packages having different sizes from semiconductor wafers of different sizes. Circle 600 of different sized semiconductor dies 604.

在圖29e中，一囊封體或模製化合物644會利用焊膏印刷塗敷機、轉印模製塗敷機、液體囊封體模製塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒604以及載體630的上方。囊封體644能夠為聚合物合成材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封體644 係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物的破壞。於另一實施例中，囊封體644係一絕緣層或介電層，其含有由下面所製成的一或更多層：光敏低固化溫度介電光阻、光敏合成光阻、層疊化合物膜、具有填充劑的絕緣膏、焊劑遮罩光阻膜、液體或粒狀模製化合物、聚亞醯胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、膠片、或是具有雷同絕緣特性及結構特性的其它介電材料，它們係利用印刷、旋塗、噴塗、有熱或無熱的真空層疊或壓力層疊、或是其它合宜製程所沉積。於其中一實施例中，囊封體644係一在低於200℃處固化之具有或不具有絕緣填充劑的低溫固化光敏介電聚合物。 In FIG. 29e, an encapsulation body or molding compound 644 is applied by a solder paste printing coater, a transfer molding coater, a liquid encapsulation body molding coater, a vacuum lamination coater, and a spin coater A coating machine, or other suitable coating machine, is deposited over the semiconductor die 604 and the carrier 630. The encapsulant 644 can be a polymer synthetic material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. Capsule 644 It is non-conductive and protects the semiconductor device from external elements and contaminants. In another embodiment, the encapsulation body 644 is an insulating layer or a dielectric layer, which contains one or more layers made of: a photosensitive low curing temperature dielectric photoresist, a photosensitive synthetic photoresist, and a laminated compound. Film, insulating paste with filler, solder mask photoresist film, liquid or granular molding compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, film, or similar insulation Other dielectric materials with special properties and structural properties are deposited by printing, spin coating, spray coating, vacuum or pressure lamination with or without heat, or other suitable processes. In one embodiment, the encapsulant 644 is a low-temperature-curable photosensitive dielectric polymer cured with or without an insulating filler at a temperature lower than 200 ° C.

明確地說，囊封體644沿著基礎基板側表面622被設置。囊封體644還覆蓋半導體晶粒604的背表面610。於其中一實施例中，囊封體644為不透明並且為暗色或黑色。囊封體644能夠被用於雷射標記重組式鑲板640，以便進行對齊與單體化裁切。囊封體644會在後續的背研磨步驟中被薄化。囊封體644亦能夠被沉積而使得囊封體的背表面646與半導體晶粒604的背表面610共面並且不會覆蓋該背表面610。反向於背側表面646的囊封體644的表面648被設置在載體630與介面層632的上方，俾使得囊封體644的表面648可以共面於半導體晶粒604的主動表面612。 Specifically, the encapsulation body 644 is provided along the base substrate side surface 622. The encapsulation body 644 also covers the back surface 610 of the semiconductor die 604. In one embodiment, the encapsulation body 644 is opaque and dark or black. The encapsulation body 644 can be used for laser marking recombination panel 640 for alignment and singularization cutting. The encapsulation body 644 will be thinned in a subsequent back grinding step. The encapsulation body 644 can also be deposited such that the back surface 646 of the encapsulation body is coplanar with the back surface 610 of the semiconductor die 604 and does not cover the back surface 610. The surface 648 of the encapsulation body 644 opposite to the back surface 646 is disposed above the carrier 630 and the interface layer 632, so that the surface 648 of the encapsulation body 644 can be coplanar with the active surface 612 of the semiconductor die 604.

在圖29f中，載體630與介面層632會藉由化學蝕刻、機械性剝除、CMP、機械性研磨、熱烘烤、UV光、雷射掃描、或是濕式脫除被移除，以便露出絕緣層616、導體層614、以及囊封體644的表面648。 In FIG. 29f, the carrier 630 and the interface layer 632 are removed by chemical etching, mechanical stripping, CMP, mechanical polishing, thermal baking, UV light, laser scanning, or wet removal, so that A surface 648 of the insulating layer 616, the conductor layer 614, and the encapsulation body 644 is exposed.

一導電層650會利用印刷、PVD、CVD、濺鍍、電解質電鍍、以及無電極電鍍的圖樣化與金屬沉積製程被形成在絕緣層616與導體層614 的上方。導體層650能夠係由下面所製成的一或更多層：Al、Cu、Sn、Ti、Ni、Au、Ag、W、或是其它合宜的導電材料。一部分的導體層650沿著絕緣層616並且平行於半導體晶粒604的主動表面612水平延伸，以便橫向重新分佈該電氣互連線至導體層614。導體層650的操作如同用於半導體晶粒604之電氣信號的RDL。導體層650被形成在半導體晶粒604的一覆蓋區上方並且不會延伸超過半導體晶粒604的該覆蓋區或是延伸在囊封體644的上方。換言之，相鄰於半導體晶粒604的半導體晶粒604的一周邊區域沒有導體層650。於其中一實施例中，導體層650被形成在半導體晶粒604的一覆蓋區裡面並且和半導體晶粒604的側壁608相隔至少為1μm的距離D9。一部分的導體層650被電氣連接至導體層614。導體層650的其它部分則相依於半導體晶粒604的連接而共電或是被電氣隔離。 A conductive layer 650 is formed on the insulating layer 616 and the conductor layer 614 by a patterning and metal deposition process using printing, PVD, CVD, sputtering, electrolyte plating, and electrodeless plating. Above. The conductive layer 650 can be made of one or more layers made of Al, Cu, Sn, Ti, Ni, Au, Ag, W, or other suitable conductive materials. A portion of the conductor layer 650 extends horizontally along the insulating layer 616 and parallel to the active surface 612 of the semiconductor die 604 so as to laterally redistribute the electrical interconnection line to the conductor layer 614. The conductor layer 650 operates like an RDL for electrical signals of the semiconductor die 604. The conductive layer 650 is formed over a coverage area of the semiconductor die 604 and does not extend beyond the coverage area of the semiconductor die 604 or over the encapsulation body 644. In other words, a peripheral region of the semiconductor die 604 adjacent to the semiconductor die 604 has no conductive layer 650. In one embodiment, the conductive layer 650 is formed in a coverage area of the semiconductor die 604 and separated from the sidewall 608 of the semiconductor die 604 by a distance D9 of at least 1 μm. A portion of the conductor layer 650 is electrically connected to the conductor layer 614. The other parts of the conductive layer 650 are electrically connected or electrically isolated depending on the connection of the semiconductor die 604.

在圖29g中，一絕緣層或鈍化層660會利用下面方法被形成在絕緣層616和導體層650的上方：PVD、CVD、印刷、旋塗、噴塗、網印、或是層疊。絕緣層660能夠係由下面所製成的一或更多層：SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有雷同絕緣特性及結構特性的其它材料。於其中一實施例中，絕緣層660係一在低於200℃處被低溫固化的光敏介電質聚合物。於其中一實施例中，絕緣層660被形成在絕緣層616、半導體晶粒604的上方並且延伸超過半導體晶粒604的該覆蓋區1μm或更大的距離D10並且延伸在囊封體644的表面648上方。絕緣層660覆蓋半導體晶粒604與囊封體644之間的介面，以便在處理期間保護該介面並且改善該裝置的可靠度。一部分絕緣層660會利用一已圖樣化光阻層被一蝕刻製程移除或是藉由LDA來移除，用以形成多個開口，以便露出導體層650。 In FIG. 29g, an insulating layer or passivation layer 660 is formed over the insulating layer 616 and the conductive layer 650 by the following methods: PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 660 can be made of one or more layers made of: SiO2, Si3N4, SiON, Ta2O5, Al2O3, or other materials having similar insulating characteristics and structural characteristics. In one embodiment, the insulating layer 660 is a photosensitive dielectric polymer that is cured at a temperature lower than 200 ° C. In one embodiment, the insulating layer 660 is formed above the insulating layer 616 and the semiconductor die 604 and extends beyond the coverage area of the semiconductor die 604 by a distance D10 or more and extends on the surface of the encapsulation body 644. Above 648. The insulating layer 660 covers the interface between the semiconductor die 604 and the encapsulation body 644 in order to protect the interface and improve the reliability of the device during processing. A part of the insulating layer 660 is removed by an etching process using a patterned photoresist layer or by LDA to form a plurality of openings to expose the conductive layer 650.

一導電凸塊材料會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程、或是網印製程被沉積在導體層650的上方。於其中一實施例中，該凸塊材料係利用一丸滴模板來沉積，也就是，不需要用到任何遮罩。該凸塊材料能夠係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶液。舉例來說，該凸塊材料能夠是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。該凸塊材料會利用合宜的附著或焊接製程被焊接至導體層650。於其中一實施例中，該凸塊材料會藉由將該材料加熱至其熔點以上而被回焊，用以形成球體或凸塊662。於某些應用中，凸塊662會被二次回焊，以便改良和導體層650的電氣接觸效果。凸塊662亦能夠被壓縮焊接或熱壓縮焊接至導體層650。凸塊662代表能夠被形成在導體層650上方的其中一種類型互連結構。該互連結構亦能夠使用焊線、導體膏、短柱凸塊、微凸塊、或是其它電氣互連線。雷射標記能夠在凸塊成形之前或之後或是在移除載體630之後被實施。 A conductive bump material is deposited on the conductive layer 650 by using an evaporation process, an electrolytic plating process, an electrodeless plating process, a pill process, or a screen printing process. In one embodiment, the bump material is deposited using a drop template, that is, no mask is required. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and a combination thereof, which may have an unnecessary flux solution. For example, the bump material can be a Sn / Pb eutectic alloy, a high-lead solder, or a lead-free solder. The bump material is soldered to the conductor layer 650 using a suitable attachment or soldering process. In one embodiment, the bump material is re-soldered by heating the material above its melting point to form a sphere or bump 662. In some applications, the bump 662 is re-soldered to improve the electrical contact with the conductive layer 650. The bump 662 can also be compression welded or thermally compressed to the conductor layer 650. The bump 662 represents one of the types of interconnect structures that can be formed over the conductor layer 650. The interconnection structure can also use bonding wires, conductor paste, stub bumps, micro-bumps, or other electrical interconnection lines. The laser marking can be implemented before or after the bump is formed or after the carrier 630 is removed.

絕緣層660、導體層650、以及凸塊662一起構成被形成在半導體晶粒604與囊封體644上方的增進互連結構664。或者，增進互連結構664完全被形成在半導體晶粒604的一覆蓋區裡面。增進互連結構664可以僅包含一RDL或導體層(例如，導體層650)以及一絕緣層(例如，絕緣層660)。額外的絕緣層和RDL會在形成凸塊662之前被形成在絕緣層660的上方，以便根據半導體晶粒604的設計和功能在該封裝中提供額外的垂直與水平電氣連接。 The insulation layer 660, the conductor layer 650, and the bumps 662 together form an enhanced interconnection structure 664 formed over the semiconductor die 604 and the encapsulation body 644. Alternatively, the enhanced interconnect structure 664 is formed entirely within a footprint of the semiconductor die 604. The enhanced interconnect structure 664 may include only an RDL or conductor layer (eg, the conductor layer 650) and an insulation layer (eg, the insulation layer 660). An additional insulating layer and RDL are formed over the insulating layer 660 before forming the bumps 662 to provide additional vertical and horizontal electrical connections in the package according to the design and function of the semiconductor die 604.

在圖29h中，半導體晶粒604會利用鋸片或雷射削切工具670被單體化裁切成為個別的eWLCSP 672。重組式鑲板640被單體化裁切 貫穿囊封體644。一部分的囊封體644在單體化裁切之後仍保持被設置在半導體晶粒604的該些側邊中。eWLCSP 672會在單體化裁切之前或之後進行電氣測試。 In FIG. 29h, the semiconductor die 604 is singulated into individual eWLCSP 672 using a saw blade or laser cutting tool 670. Recombination panel 640 is singulated and cut Through the capsule body 644. A part of the encapsulation body 644 remains disposed in the sides of the semiconductor die 604 after singulation cutting. The eWLCSP 672 undergoes electrical testing before or after singulation cutting.

在圖29i中所示的係eWLCSP 672，其具有被形成在半導體晶粒604的背表面610與側壁608上方的囊封體644。半導體晶粒604經由導體層614以及650被電氣連接至凸塊662，以便經由互連結構664達到外部互連的目的。互連結構664的導體層不會延伸超過半導體晶粒604的一覆蓋區，並且因而形成一扇入封裝。於其中一實施例中，導體層650被形成在半導體晶粒604的一覆蓋區裡面並且與半導體晶粒604的側壁608相隔至少1μm的距離D9。絕緣層660覆蓋半導體晶粒604與囊封體644之間的介面，以便在處理期間保護該介面並且改善該裝置的可靠度。於其中一實施例中，絕緣層660延伸超過半導體晶粒604的該覆蓋區1μm或更大的距離D10並且延伸在囊封體644的表面648上方。 The system eWLCSP 672 shown in FIG. 29i has an encapsulation body 644 formed over the back surface 610 and the side wall 608 of the semiconductor die 604. The semiconductor die 604 is electrically connected to the bump 662 via the conductor layers 614 and 650 so as to achieve the purpose of external interconnection via the interconnect structure 664. The conductor layer of the interconnect structure 664 does not extend beyond a footprint of the semiconductor die 604 and thus forms a fan-in package. In one embodiment, the conductive layer 650 is formed in a coverage area of the semiconductor die 604 and separated from the sidewall 608 of the semiconductor die 604 by a distance D9 of at least 1 μm. The insulating layer 660 covers the interface between the semiconductor die 604 and the encapsulation body 644 in order to protect the interface and improve the reliability of the device during processing. In one embodiment, the insulating layer 660 extends beyond the coverage area D10 of the semiconductor die 604 by a distance D10 or more and extends above the surface 648 of the encapsulation body 644.

囊封體644在非必要的研磨操作之後仍殘留在基礎基板側表面622的上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。所以，囊封體644被形成在半導體晶粒604的五個側邊上方，也就是，在四個基礎基板側表面622上方以及在背表面610上方。在半導體晶粒604的背表面610上方的囊封體644省略背側保護層或背側疊板的需求，因而降低eWLCSP 672的成本。 The encapsulation body 644 still remains above the side surface 622 of the base substrate after unnecessary grinding operations to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation. Therefore, the encapsulation body 644 is formed above the five sides of the semiconductor die 604, that is, above the four base substrate side surfaces 622 and above the back surface 610. The encapsulation body 644 above the back surface 610 of the semiconductor die 604 omits the need for a backside protective layer or a backside stack, thereby reducing the cost of the eWLCSP 672.

在eWLCSP 672中，基礎基板側表面622上方的囊封體644的厚度小於150μm。於其中一實施例中，eWLCSP 672的體積為長度4.595mm x寬度4.025mm x高度0.470mm，凸塊662的節距為0.4mm，其中，半導體 晶粒604的面積為長度4.445mm x寬度3.875mm。於另一實施例中，基礎基板側表面622上方的囊封體644的厚度為75μm或更小。eWLCSP 672的體積為長度6.075mm x寬度6.075mm x高度0.8mm，凸塊662的節距為0.5mm，其中，半導體晶粒604的體積為長度6.0mm x寬度6.0mm x高度0.470mm。於又一實施例中，eWLCSP 672的體積為長度5.92mm x寬度5.92mm x高度0.765mm，凸塊662的節距為0.5mm，其中，半導體晶粒604的體積為長度5.75mm x寬度5.75mm x高度0.535mm。於另一實施例中，基礎基板側表面622上方的囊封體644的厚度為25μm或更小。於又一實施例中，基礎基板側表面622上方的囊封體644的厚度為約50μm或更小。eWLCSP 672係利用針對單一標準化載體大小所設計的設備藉由在標準化載體630上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 672的設備成本與材料成本。eWLCSP 672係利用標準化載體630以較高的數量來製造，從而簡化製造過程並且降低單元成本。 In eWLCSP 672, the thickness of the encapsulation body 644 above the base substrate side surface 622 is less than 150 μm. In one embodiment, the volume of the eWLCSP 672 is 4.595 mm in length x 4.025 mm in width x 0.470 mm in height, and the pitch of the bumps 662 is 0.4 mm. The area of the die 604 is 4.445 mm in length x 3.875 mm in width. In another embodiment, the thickness of the encapsulation body 644 above the side surface 622 of the base substrate is 75 μm or less. The volume of the eWLCSP 672 is 6.075 mm in length x 6.075 mm in width x 0.8 mm in height and the pitch of the bumps 662 is 0.5 mm. The volume of the semiconductor die 604 is 6.0 mm in length x 6.0 mm in width x 0.470 mm in height. In yet another embodiment, the volume of the eWLCSP 672 is 5.92 mm in length x 5.92 mm in width x 0.765 mm in height, and the pitch of the bumps 662 is 0.5 mm. The volume of the semiconductor die 604 is 5.75 mm in length x 5.75 mm in width x height 0.535mm. In another embodiment, the thickness of the encapsulation body 644 above the side surface 622 of the base substrate is 25 μm or less. In yet another embodiment, the thickness of the encapsulation body 644 above the side surface 622 of the base substrate is about 50 μm or less. The eWLCSP 672 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 630, which will reduce the equipment cost and material cost of the eWLCSP 672. The eWLCSP 672 is manufactured in a higher quantity using a standardized carrier 630, thereby simplifying the manufacturing process and reducing unit costs.

圖30所示的係在單體化裁切之後的eWLCSP 674，其具有位在側壁608上方的囊封體644並且具有背側絕緣層676。半導體晶粒604經由導體層614以及650被電氣連接至凸塊662，以便經由互連結構664達到外部互連的目的。互連結構664不會延伸超過半導體晶粒604的一覆蓋區，並且因而形成一扇入封裝。絕緣層660覆蓋半導體晶粒604與囊封體644之間的介面，以便在處理期間保護該介面並且改善該裝置的可靠度。 The eWLCSP 674 shown in FIG. 30 after singulation cutting has an encapsulation body 644 located above the side wall 608 and a back-side insulating layer 676. The semiconductor die 604 is electrically connected to the bump 662 via the conductor layers 614 and 650 so as to achieve the purpose of external interconnection via the interconnect structure 664. The interconnect structure 664 does not extend beyond a footprint of the semiconductor die 604 and thus forms a fan-in package. The insulating layer 660 covers the interface between the semiconductor die 604 and the encapsulation body 644 in order to protect the interface and improve the reliability of the device during processing.

背側絕緣層676被形成在半導體晶粒604的背表面610的上方，用以達到機械性保護的目的並且避免因曝露在來自光或其它輻射的光子的關係而受損。背側絕緣層676含有由下面所製成的一或更多層：光敏 低固化溫度介電光阻、光敏合成光阻、層疊化合物膜、具有填充劑的絕緣膏、焊劑遮罩光阻膜、液體或粒狀模製化合物、聚亞醯胺、BCB、PBO、SiO2、Si3N4、SiON、Ta2O5、Al2O3、膠片、或是具有雷同絕緣特性及結構特性的其它介電材料。背側絕緣層676係利用印刷、旋塗、噴塗、有熱或無熱的真空層疊或壓力層疊、或是其它合宜製程所沉積。於其中一實施例中，背側絕緣層676係一在低於200℃處固化之具有或不具有絕緣填充劑的低溫固化光敏介電聚合物。背側絕緣層676係一背側保護層並且為半導體晶粒604提供機械性保護以及避免受到光的影響。於其中一實施例中，背側絕緣層676的厚度範圍從約5μm至150μm。 A back-side insulating layer 676 is formed above the back surface 610 of the semiconductor die 604 to achieve the purpose of mechanical protection and avoid damage due to the relationship of exposure to photons from light or other radiation. The back-side insulating layer 676 contains one or more layers made of: Low curing temperature dielectric photoresist, photosensitive synthetic photoresist, laminated compound film, insulating paste with filler, solder mask photoresist film, liquid or granular molding compound, polyimide, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, film, or other dielectric materials with similar insulation and structural characteristics. The back-side insulating layer 676 is deposited by printing, spin coating, spray coating, vacuum lamination or pressure lamination with or without heat, or other suitable processes. In one embodiment, the back-side insulating layer 676 is a low-temperature-curable photosensitive dielectric polymer that is cured at a temperature below 200 ° C. with or without an insulating filler. The back-side insulating layer 676 is a back-side protective layer and provides mechanical protection for the semiconductor die 604 and is protected from light. In one embodiment, the thickness of the back-side insulating layer 676 ranges from about 5 μm to 150 μm.

囊封體644覆蓋基礎基板側表面622，用以保護半導體晶粒604，避免因曝露在來自光或其它輻射的光子的關係而受損。在eWLCSP 674中，基礎基板側表面622上方的囊封體644的厚度小於150μm。於其中一實施例中，eWLCSP 674的體積為長度4.595mm x寬度4.025mm x高度0.470mm，凸塊662的節距為0.4mm，其中，半導體晶粒604的面積為長度4.445mm x寬度3.875mm。於另一實施例中，基礎基板側表面622上方的囊封體644的厚度為75μm或更小。eWLCSP 674的體積為長度6.075mm x寬度6.075mm x高度0.8mm，凸塊662的節距為0.5mm，其中，半導體晶粒604的體積為長度6.0mm x寬度6.0mm x高度0.470mm。於又一實施例中，eWLCSP 674的體積為長度5.92mm x寬度5.92mm x高度0.765mm，凸塊662的節距為0.5mm，其中，半導體晶粒604的體積為長度5.75mm x寬度5.75mm x高度0.535mm。於另一實施例中，基礎基板側表面622上方的囊封體644的厚度為25μm或更小。於又一實施例中，基礎基板側表面622上方的囊 封體644的厚度為約50μm或更小。eWLCSP 674係利用針對單一標準化載體大小所設計的設備藉由在標準化載體630上形成一重組式晶圓或鑲板來製造，其會降低eWLCSP 674的設備成本與材料成本。eWLCSP 674係利用標準化載體630以較高的數量來製造，從而簡化製造過程並且降低單元成本。 The encapsulation body 644 covers the side surface 622 of the base substrate to protect the semiconductor die 604 from being damaged due to the relationship of exposure to photons from light or other radiation. In eWLCSP 674, the thickness of the encapsulation body 644 above the base substrate side surface 622 is less than 150 μm. In one embodiment, the volume of the eWLCSP 674 is 4.595mm in length x 4.025mm in width x 0.470mm in height, and the pitch of the bumps 662 is 0.4mm, wherein the area of the semiconductor die 604 is 4.445mm in length x 3.875mm in width . In another embodiment, the thickness of the encapsulation body 644 above the side surface 622 of the base substrate is 75 μm or less. The volume of the eWLCSP 674 is 6.075 mm in length x 6.075 mm in width x 0.8 mm in height, and the pitch of the bumps 662 is 0.5 mm. The volume of the semiconductor die 604 is 6.0 mm in length x 6.0 mm in width x 0.470 mm in height. In yet another embodiment, the volume of the eWLCSP 674 is 5.92 mm in length x 5.92 mm in width x 0.765 mm in height, and the pitch of the bumps 662 is 0.5 mm. The volume of the semiconductor die 604 is 5.75 mm in length x 5.75 mm in width x height 0.535mm. In another embodiment, the thickness of the encapsulation body 644 above the side surface 622 of the base substrate is 25 μm or less. In yet another embodiment, the capsule above the side surface 622 of the base substrate The thickness of the sealing body 644 is about 50 μm or less. The eWLCSP 674 is manufactured by using a device designed for a single standardized carrier size by forming a reconstituted wafer or panel on the standardized carrier 630, which will reduce the equipment cost and material cost of the eWLCSP 674. The eWLCSP 674 is manufactured in a higher quantity using a standardized carrier 630, thereby simplifying the manufacturing process and reducing unit costs.

本文雖然已經詳細解釋本發明的一或更多個實施例；但是，熟習本技術的人士便會明白，可以對此些實施例進行修正與更動，其並不會脫離如後面的申請專利範圍之中所提出之本發明的範疇。 Although one or more embodiments of the present invention have been explained in detail herein, those skilled in the art will understand that these embodiments can be modified and changed without departing from the scope of the patent application as described later. The scope of the invention proposed in.

Claims (15)

一種製造半導體裝置的方法，其包括：提供一第一半導體晶圓，其包含基礎基板材料和形成在所述基礎基板材料中的複數個第一半導體晶粒；單體化裁切該第一半導體晶圓，用以將該些第一半導體晶粒的每一個分開，其中該些第一半導體晶粒中的每一個包括附接到個別的第一半導體晶粒之所述基礎基板材料的一區域，所述基礎基板材料的該區域在所述個別的第一半導體晶粒的覆蓋區之外部；提供一第一載體，其中，該第一載體的大小不相依於從該第一半導體晶圓處單體化裁切出來的該些第一半導體晶粒的大小和數量；以及在單體化裁切該第一半導體晶圓之後，將該些第一半導體晶粒以高密度排列方式設置在該第一載體的上方，其中在所述個別的第一半導體晶粒之間的距離是50μm或更小；沉積一囊封體在該些第一半導體晶粒和該第一載體上方，以形成一重組式鑲板；形成一第一絕緣層於所述第一半導體晶粒上，其中該基礎基板材料的該區域仍缺乏該第一絕緣層；形成第二絕緣層於所述第一半導體晶粒及該第一絕緣層上，其中該第二絕緣層接觸該囊封體與該基礎基板材料的該區域；以及單體化裁切該重組式鑲板，其中單體化裁切該重組式鑲板的動作將附接到每個第一半導體晶粒的所述基礎基板材料的該區域的第一部分移除同時仍保留附接到該第一半導體晶粒的所述基礎基板材料的該區域的第二部分。A method for manufacturing a semiconductor device includes: providing a first semiconductor wafer including a base substrate material and a plurality of first semiconductor crystal grains formed in the base substrate material; and singulating the first semiconductor A wafer to separate each of the first semiconductor dies, wherein each of the first semiconductor dies includes a region of the base substrate material attached to an individual first semiconductor die The region of the base substrate material is outside the coverage area of the individual first semiconductor die; a first carrier is provided, wherein the size of the first carrier does not depend on the position from the first semiconductor wafer; The size and number of the first semiconductor dies cut out by singulation; and after the first semiconductor wafer is cut singulated by singulation, the first semiconductor dies are arranged in the high-density arrangement on the first semiconductor wafer. Above the first carrier, wherein a distance between the individual first semiconductor crystal grains is 50 μm or less; and an encapsulation body is deposited over the first semiconductor crystal grains and the first carrier in a shape of A reorganized panel; forming a first insulating layer on the first semiconductor die, wherein the region of the base substrate material still lacks the first insulating layer; forming a second insulating layer on the first semiconductor die And the first insulating layer, wherein the second insulating layer is in contact with the area of the encapsulation body and the base substrate material; and singularizing and cutting the recombination panel, wherein singularizing and cutting the recombination panel The action of the panel removes a first portion of the region of the base substrate material attached to each first semiconductor die while still retaining the region of the base substrate material attached to the first semiconductor die The second part. 根據申請專利範圍第1項的方法，其進一步包含：提供一第二半導體晶圓，其包含該複數個第二半導體晶粒，其中，該第二半導體晶圓的寬度不同於該第一半導體晶圓的寬度，並且該第二半體晶粒的寬度不同於該第一半導體晶粒的寬度；單體化裁切該第二半導體晶圓，用以分開該些第二半導體晶粒；以及將該些第二半導體晶粒設置在一第二載體的上方，該第二載體的寬度與該第一載體的寬度大約相等，其中，被設置在該第二載體上方的第二半導體晶粒的數量不相依於從該第二半導體晶圓處單體化裁切出來的第二半導體晶粒的數量。The method according to item 1 of the patent application scope, further comprising: providing a second semiconductor wafer including the plurality of second semiconductor wafers, wherein a width of the second semiconductor wafer is different from the first semiconductor wafer The width of the circle, and the width of the second half die is different from the width of the first semiconductor die; singulating the second semiconductor wafer to separate the second semiconductor die; and The second semiconductor dies are disposed above a second carrier, and the width of the second carrier is approximately equal to the width of the first carrier, wherein the number of the second semiconductor dies disposed above the second carrier is It does not depend on the number of the second semiconductor die cut from the singulation at the second semiconductor wafer. 根據申請專利範圍第1項的方法，其進一步包含設置複數個第二半導體晶粒在一第二載體上方，而該第二半導體晶粒的大小不同於該第一半導體晶粒的大小，並且該第二載體的大小與該第一載體的大小大約相等。The method according to item 1 of the patent application scope, further comprising setting a plurality of second semiconductor grains on a second carrier, and the size of the second semiconductor grains is different from the size of the first semiconductor grains, and the The size of the second carrier is approximately equal to the size of the first carrier. 根據申請專利範圍第1項的方法，其進一步包含設置複數個第二半導體晶粒在該第一載體上方，該第二半導體晶粒包含不同於該第一半導體晶粒之大小的大小。The method according to item 1 of the patent application scope, further comprising placing a plurality of second semiconductor crystal grains on the first carrier, the second semiconductor crystal grains having a size different from the size of the first semiconductor crystal grains. 根據申請專利範圍第1項的方法，其中該第一載體所容納的第一半導體晶粒的數量是大於從該第一半導體晶圓處單體化裁切出來的該些第一半導體晶粒的數量。The method according to item 1 of the scope of patent application, wherein the number of the first semiconductor dies contained in the first carrier is greater than Quantity. 一種製造半導體裝置的方法，其包括：提供一半導體晶粒；設置一第二半導體晶粒相鄰於該第一半導體晶粒；沉積一囊封體於該第一半導體晶粒和該第二半導體晶粒上方與周圍，用以形成一重組式鑲板；於該些半導體晶粒上方形成一互連結構，而不形成該互連結構於該囊封體上方；在一單一製程步驟中移除該囊封體的一部分、該第一半導體晶粒的一部分以及該第二半導體晶粒的一部分；以及形成絕緣層，其包括在該第一半導體晶粒上方的該絕緣層的一第一部分和在該第二半導體晶粒上方的該絕緣層的一第二部分，其中該囊封體在該絕緣層的該第一部分和該絕緣層的該第二部分之間露出。A method for manufacturing a semiconductor device includes: providing a semiconductor die; setting a second semiconductor die adjacent to the first semiconductor die; and depositing an encapsulation body on the first semiconductor die and the second semiconductor Above and around the die are used to form a recombination panel; an interconnect structure is formed over the semiconductor die without forming the interconnect structure above the encapsulation body; removed in a single process step A portion of the encapsulation body, a portion of the first semiconductor die, and a portion of the second semiconductor die; and forming an insulating layer including a first portion of the insulating layer above the first semiconductor die and a portion A second portion of the insulating layer above the second semiconductor die, wherein the encapsulant is exposed between the first portion of the insulating layer and the second portion of the insulating layer. 根據申請專利範圍第6項的方法，其進一步包含：提供一半導體晶圓，其包含複數個半導體晶粒；單體化裁切該半導體晶圓，用以從該半導體晶圓中分開該第一半導體晶粒和該第二半導體晶粒；以及將該第一半導體晶粒和該第二半導體晶粒設置在一載體的上方，其中，被設置在該載體上方的半導體晶粒的數量不相依於從該半導體晶圓處單體化裁切出來的半導體晶粒的數量。The method according to claim 6 of the patent application scope, further comprising: providing a semiconductor wafer including a plurality of semiconductor dies; singulating the semiconductor wafer to separate the first wafer from the semiconductor wafer; A semiconductor crystal grain and the second semiconductor crystal grain; and placing the first semiconductor crystal grain and the second semiconductor crystal grain on a carrier, wherein the number of semiconductor crystal grains disposed on the carrier does not depend on The number of semiconductor die cut out from the semiconductor wafer is singulated. 根據申請專利範圍第6項的方法，其進一步包含單體化裁切該重組式鑲板貫穿該囊封體而保留囊封體的一第一部分覆蓋該第一半導體晶粒的一側邊。The method according to item 6 of the patent application scope, further comprising singulating the reorganized panel through the encapsulation body while retaining a first portion of the encapsulation body to cover one side of the first semiconductor die. 根據申請專利範圍第6項的方法，其進一步包含單體化裁切該重組式鑲板貫穿該囊封體以從該第一半導體晶粒和該第二半導體晶粒之間完全地移除該囊封體。The method according to claim 6 of the application, further comprising singulating the reorganized panel through the encapsulation body to completely remove the between the first semiconductor die and the second semiconductor die. Encapsulation body. 根據申請專利範圍第6項的方法，其中該單一製程步驟包含單體化裁切在該第一半導體晶粒和該第二半導體晶粒之間的該重組式鑲板。The method of claim 6, wherein the single process step includes singulating the reorganized panel between the first semiconductor die and the second semiconductor die. 根據申請專利範圍第6項的方法，其中該單一製程步驟包含背研磨操作，其減少該第一半導體晶粒和該第二半導體晶粒的厚度。The method of claim 6, wherein the single process step includes a back grinding operation that reduces the thickness of the first semiconductor die and the second semiconductor die. 一種製造半導體裝置的方法，其包括：提供一第一半導體晶圓，其包含第一數量的第一半導體晶粒；提供一第二半導體晶圓，其包含第二數量的第二半導體晶粒；提供一載體；設置該第一半導體晶粒和該第二半導體晶粒於該載體上方，其中該載體的大小不相依於該第一半導體晶粒的大小和該第二半導體晶粒的大小，並且該載體容納來自該第一半導體晶圓的該第一數量的第一半導體晶粒的每一個以及來自該第二半導體晶圓的該第二半導體晶粒的一部份；沉積一囊封體於該載體、該第一半導體晶粒和該第二半導體晶粒上方，以形成一重組式鑲板；從該載體移除該第一半導體晶粒和該第二半導體晶粒；在沉積該囊封體之後，形成絕緣層於該第一半導體晶粒和該第二半導體晶粒上方，其中該絕緣層接觸該囊封體且該囊封體從在該第一半導體晶粒和該第二半導體晶粒之間的該絕緣層露出；以及單體化裁切該重組式鑲板，其中該囊封體被完全地從該第一半導體晶粒的側表面移除。A method for manufacturing a semiconductor device includes: providing a first semiconductor wafer including a first number of first semiconductor dies; providing a second semiconductor wafer including a second number of second semiconductor dies; Providing a carrier; placing the first semiconductor die and the second semiconductor die above the carrier, wherein the size of the carrier does not depend on the size of the first semiconductor die and the size of the second semiconductor die, and The carrier accommodates each of the first number of first semiconductor dies from the first semiconductor wafer and a portion of the second semiconductor dies from the second semiconductor wafer; a capsule is deposited on Over the carrier, the first semiconductor die and the second semiconductor die to form a recombination panel; remove the first semiconductor die and the second semiconductor die from the carrier; and deposit the encapsulation After the body is formed, an insulating layer is formed over the first semiconductor die and the second semiconductor die, wherein the insulating layer contacts the encapsulation body and the encapsulation body starts from the first semiconductor die and the second half. The insulating layer is exposed between the grains; and the monomer of formula recombinant cut panel, wherein the encapsulation material is removed from the side surface of the first semiconductor die completely. 根據申請專利範圍第12項的方法，其進一步包含設置一第三半導體晶粒於該載體上方，其中該載體的該大小不相依於該第三半導體晶粒的大小。According to the method of claim 12, the method further includes disposing a third semiconductor die on the carrier, wherein the size of the carrier does not depend on the size of the third semiconductor die. 根據申請專利範圍第13項的方法，其進一步包含：在移除該第一半導體晶粒和該第二半導體晶粒之後，設置該第三半導體晶粒於該載體上方。The method according to item 13 of the patent application scope, further comprising: after removing the first semiconductor die and the second semiconductor die, placing the third semiconductor die above the carrier. 根據申請專利範圍第12項的方法，其中該第一數量的第一半導體晶粒代表形成在該第一半導體晶圓上的每個第一半導體晶粒。The method of claim 12, wherein the first number of first semiconductor dies represents each first semiconductor die formed on the first semiconductor wafer.
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