CN104701194A - Semiconductor device and method of using a standardized carrier in semiconductor packaging - Google Patents

Semiconductor device and method of using a standardized carrier in semiconductor packaging Download PDF

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Publication number
CN104701194A
CN104701194A CN201410741338.2A CN201410741338A CN104701194A CN 104701194 A CN104701194 A CN 104701194A CN 201410741338 A CN201410741338 A CN 201410741338A CN 104701194 A CN104701194 A CN 104701194A
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China
Prior art keywords
semiconductor element
carrier
semiconductor
sealant
size
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Pending
Application number
CN201410741338.2A
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Chinese (zh)
Inventor
T.J.斯特罗思曼
D.M.普里科洛
沈一权
林耀剑
H-P.维尔茨
尹胜煜
P.C.马里穆图
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Stats Chippac Pte Ltd
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Stats Chippac Pte Ltd
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Filing date
Publication date
Priority claimed from US14/097,534 external-priority patent/US9620413B2/en
Application filed by Stats Chippac Pte Ltd filed Critical Stats Chippac Pte Ltd
Priority to CN202111287658.1A priority Critical patent/CN113990766A/en
Publication of CN104701194A publication Critical patent/CN104701194A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

Description

Semiconductor device and use the method for standardized carrier in semiconductor packages
The part continuation application of U.S. Patent Application No. 13/832,809 that the application is the right of the U.S. Provisional Application numbers 61/744,699 requiring to submit on October 2nd, 2012, that submit on March 15th, 2013, these applications are incorporated in this by reference.
Technical field
The present invention relates generally to semiconductor device and particularly relates to semiconductor device and use standardized carrier to form the method for wafer level chip scale encapsulation (WLCSP).
Background technology
Usually semiconductor device is found in modern electronic product.Semiconductor device changes in the number and density of electric component.The electric component of discrete semiconductor device substantially containing a type, such as, light-emitting diode (LED), small-signal transistor, resistor, capacitor, inductor and power metal oxide semiconductor field-effect transistor (MOSFET).Integrated semiconductor device typically arrives millions of electric components containing hundreds of.The example of integrated semiconductor device comprises microcontroller, microprocessor, charge-coupled device (CCD), solar cell and Digital Micromirror Device (DMD).
Semiconductor device performs function miscellaneous, such as signal transacting, supercomputing, transmission and receiving electromagnetic signals, control electronic device, sunlight is transformed into the visual projection that electric power and establishment be used for TV display.Semiconductor device is found in the field of amusement, communication, power conversion, network, computer and consumer products.Also semiconductor device is found in Military Application, aviation, automobile, industrial control unit (ICU) and office equipment.
Semiconductor device utilizes the electrical properties of semi-conducting material.The structure of semi-conducting material allows by the applying of electric field or base current or the conductivity handling it through the technique of overdoping.Impurity is incorporated in semi-conducting material to handle and to control the conductivity of semiconductor device by doping.
Semiconductor device contains active and passive electrical structure.The active structure comprising bipolar transistor and field-effect transistor controls the flowing of electric current.By changing the applying of level and electric field or the base current adulterated, the flowing of transistor promotion or about beam electronic current.The passive structures comprising resistor, capacitor and inductor is created as and performs the necessary relation between voltage and electric current of various electric function.Passive structures and active structure electrical connection are formed circuit, and this circuit enables semiconductor device perform high speed operation and other useful function.
Two complicated manufacturing process (namely front end manufactures and rear end manufacture, each probably relate to a hundreds of step) are used to manufacture semiconductor device substantially.Front end manufactures to relate to and form multiple tube core on the surface of semiconductor crystal wafer.Each semiconductor element is same typically and containing by active parts is electrically connected formed circuit with passive component.Rear end manufactures and relates to segmentation other semiconductor element from the wafer completed and die package isolated to provide support structure and environment.Term as used herein " semiconductor element " not only refers to the singulative of word but also refers to the plural form of word, and therefore, it is possible to not only refers to single semiconductor device but also refer to multiple semiconductor device.
An object of semiconductor manufacturing produces less semiconductor device.Less device typically consumes less power, has higher performance and can more efficiently be produced.In addition, less semiconductor device has less area occupied (footprint), and this is desired for less final products.Less semi-conductor die size can be realized by the improvement of front-end process, thus produce the semiconductor element with less, more highdensity active parts and passive component.Backend process can produce the semiconductor packages with less area occupied by the improvement of electrical interconnection and encapsulating material.
Conventional semiconductor crystal wafer is typically containing the multiple semiconductor elements be separated by saw street.Source circuit and passive circuit is formed in the surface of each semiconductor element.Interconnection structure can be formed on the surface of semiconductor element.Semiconductor crystal wafer is divided into other semiconductor element for using in various electronic product.The importance of semiconductor manufacturing is high rate of finished products and corresponding low cost.
The equipment depended on for producing semiconductor crystal wafer and semiconductor element makes the semiconductor crystal wafer with various diameter and semi-conductor die size.(incoming) semiconductor die size according to each special semi-conductor die size and introducing typically develops semiconductor processing equipment.Such as, the wafer of 200 millimeters (mm) uses 200 mm equipment to process, and the wafer of 300 mm uses 300mm equipment to process.Carrier processes the semiconductor element split from wafer.The size of carrier is selected according to the size of the semiconductor element that will be processed.Such as, the semiconductor element of 10 mm × 10 mm uses the equipment different from the semiconductor element of 5 mm × 5 mm to process.Therefore, in disposal ability, be limited to for the equipment of encapsulated semiconductor device the specific semi-conductor die size or semiconductor die size that this equipment is designed to.Along with the size of the semiconductor element introduced and the size of semiconductor crystal wafer change, the additional investment of manufacturing equipment is necessary.Capital investment risk is caused for the semiconductor device producer that invests in the semiconductor element of specific dimensions or the equipment of semiconductor crystal wafer.Along with the size of the semiconductor crystal wafer introduced changes, the specific equipment of wafer just becomes out-of-date.Similarly, for semiconductor element specific dimensions designed by carrier and equipment can become out-of-date because this carrier dispose different size semiconductor element ability in be limited.The development of distinct device and enforcement add the cost of last semiconductor device.
Semiconductor crystal wafer comprises various diameter and the manufacturing equipment be typically utilized as designed by the semiconductor element of each specific dimensions processes.Typically semiconductor element is surrounded in the semiconductor packages for the electrical interconnection of tube core, support structure and environmental protection.If a part for semiconductor element is exposed to outside element, especially when surface mounted tubes core, semiconductor may wreck or degenerate.Such as, can semiconductor element be destroyed or semiconductor element is degenerated between disposal and exposure period.
Summary of the invention
Exist to use and can dispose the needs that the carrier of the semiconductor element of multiple size and the wafer of introducing and equipment manufacture semiconductor device efficiently.Therefore, in one embodiment, the present invention makes the method for semiconductor device, and the method comprises the following steps: providing package containing fixed dimension carrier and on this carrier face multiple first semiconductor element is set.The fixed dimension of this carrier is independent of the size of the first semiconductor element.
In another embodiment, the present invention is the method making semiconductor device, and the method comprises the following steps: provide carrier and on carrier, arrange the first semiconductor element.The size of this carrier is independent of the size of the first semiconductor element.
In another embodiment, the present invention makes the method for semiconductor device, and the method comprises the following steps: provide deposit sealant around semiconductor element, on a semiconductor die face and semiconductor element with is formed reconstruct panel, on the panel of reconstruct, form interconnection structure leave the sealant that lacks interconnection structure simultaneously and through sealant, the panel of reconstruct split.
In another embodiment, the present invention is the semiconductor device comprising semiconductor element.On a semiconductor die face and in the outer peripheral areas contiguous with semiconductor element deposit sealant.Face forms interconnection structure on a semiconductor die.This outer peripheral areas lacks interconnection structure.
Accompanying drawing explanation
Fig. 1 illustrates printed circuit board (PCB) (PCB), and this printed circuit board (PCB) has the dissimilar encapsulation on the surface being installed to it;
Fig. 2 a-2c diagram is installed to the further details of the representational semiconductor packages of PCB;
Fig. 3 a-3d diagram has the semiconductor crystal wafer of the multiple semiconductor elements be separated by saw street;
Fig. 4 a-4e is shown in the technique of deposit sealant on the part of the exposure of the active surface of semiconductor element and side in WLCSP;
Fig. 5 diagram utilizes sealant to cover the part of exposure and the WLCSP of side of the active surface of semiconductor element;
Fig. 6 a-6c diagram has the semiconductor crystal wafer of the multiple semiconductor elements be separated by saw street;
Fig. 7 a-7e is shown in another technique of deposit sealant on the part of the exposure of the active surface of semiconductor element and side in WLCSP;
Fig. 8 diagram utilizes sealant to cover the part of exposure and the WLCSP of side of the active surface of semiconductor element;
Fig. 9 a-9h is shown in WLCSP and is molded to the part of the active surface of semiconductor element and side deposit the technique that (MUF) material is filled at the end;
Figure 10 diagram utilizes MUF material to cover the part of active surface and the WLCSP of side of semiconductor element;
Figure 11 is shown in the MUF material arranged between semiconductor element and substrate;
Figure 12 diagram utilizes MUF material to cover the part of active surface and the semiconductor packages of side of semiconductor element;
Figure 13 a-13p illustrates the technique of wafer level chip scale encapsulation (eWLCSP) that is that form reconstruct or that embed;
Sealant above the sidewall that Figure 14 diagram has a semiconductor element and the eWLCSP of back side protection layer;
Figure 15 diagram has the eWLCSP of back side protection layer;
Figure 16 diagram has the eWLCSP of the sealant above the sidewall of semiconductor element and dorsal part;
Figure 17 diagram has the eWLCSP of the sealant on the dorsal part of semiconductor element;
Figure 18 diagram has the eWLCSP of semiconductor element, and this semiconductor element has sidewall and the dorsal part of exposure;
Figure 19 a-19k illustrates the technique substituted forming eWLCSP;
Figure 20 is shown in the eWLCSP above the sidewall of semiconductor element and dorsal part with sealant;
There is above the dorsal part that Figure 21 is shown in semiconductor element the eWLCSP of sealant;
Figure 22 illustrates the eWLCSP of sealant and the back side protection layer had above sidewall;
Figure 23 illustrates another eWLCSP of sealant and the back side protection layer had above sidewall;
Figure 24 diagram has the eWLCSP of back side protection layer;
Figure 25 diagram has the eWLCSP of semiconductor element, and this semiconductor element has sidewall and the dorsal part of exposure;
There is above the dorsal part that Figure 26 a-26k diagram is formed in semiconductor element the technique of the eWLCSP of sealant;
Figure 27 diagram has the eWLCSP of semiconductor element, and this semiconductor element has sidewall and the dorsal part of exposure;
Figure 28 diagram has the eWLCSP of back side protection layer;
Figure 29 a-29i illustrates another technique forming the eWLCSP with thin sidewall sealing; And
Figure 30 diagram has the eWLCSP of back side protection layer and the sealing of thin sidewall.
Embodiment
In the following description, the present invention is described, the same or similar element of wherein similar numeral with reference to accompanying drawing in one or more embodiments.Although according to the best mode for realizing target of the present invention to describe the present invention, but those skilled in the art will recognize, it be intended to cover in the spirit and scope of the present invention that can be contained in and limited by appended claims and their equivalent (supported by open and accompanying drawing below) alternative, revise and equivalent.
Following two complicated manufacturing process are used to manufacture semiconductor device substantially: front end manufactures and rear end manufacture.Front end manufactures the formation relating to multiple tube core on the surface of semiconductor crystal wafer.Each tube core on wafer contains active electrical component and electrical passive components, and described parts are electrically connected to form functional circuit.The active electric component of such as transistor and diode has the ability of the flowing controlling electric current.The such as electrical passive components of capacitor, inductor and resistor is created as the necessary relation between voltage and electric current of executive circuit function.
By comprising the series of process step of doping, deposit, photoetching, etching and complanation, on the surface of semiconductor crystal wafer, form passive component and active parts.Impurity is incorporated in semi-conducting material by the technology of such as ion implantation or thermal diffusion by doping.Doping process is modified in the conductivity of semi-conducting material in active device by dynamically changing the conductivity of semi-conducting material in response to electric field or base current.Transistor is containing the type of vicissitudinous doping and the region of degree, and described region is arranged to enable transistor to promote when the applying of electric field or base current or the flowing of about beam electronic current where necessary.
Active parts and passive component formed by the material layer with different electrical properties.Can by the type portions by the material be just deposited the various deposition technology determined form this layer.Such as, thin film deposition can relate to the technique of chemical vapor deposition (CVD), physical vapor deposition (PVD), metallide and chemical plating.Each layer is patterned the part of the electrical connection be formed with between source block, passive component or parts substantially.
Rear end manufactures and refers to the wafer completed cutting or be partitioned into other semiconductor element and then semiconductor die package be used for support structure and environment isolation.In order to dividing semiconductor tube core, wafer is scored along the non-functional region of the wafer being called saw street or line and is scratched.Laser cutting tool or saw blade is used to be split by wafer.Upon splitting, other semiconductor element individual is installed to package substrate, this package substrate comprises for the pin or contact pad with other system component interconnect.Then the contact pad that face is formed on a semiconductor die is connected to the contact pad in encapsulation.Solder projection, stud bumps, conductive paste or line can be utilized to engage and to make electrical connection.Sealant or other moulding material are deposited on above encapsulation to provide physical support and electrical isolation.Then the encapsulation completed to be inserted in electrical system and to make the functional system unit that can be used for other of semiconductor device.
Fig. 1 diagram has the electronic device 50 of chip carrier substrate or printed circuit board (PCB) (PCB) 52, and chip carrier substrate or printed circuit board (PCB) (PCB) 52 have multiple semiconductor packages of installing on its surface.Depend on application, electronic device 50 can have the semiconductor packages of a type or polytype semiconductor packages.In order to illustrated object, dissimilar semiconductor packages is illustrated in FIG.
Electronic device 50 can be independently system, this independently system use semiconductor packages to perform one or more electric function.Alternatively, electronic device 50 can be the subassembly of larger system.Such as, electronic device 50 can be the part of portable phone, PDA(Personal Digital Assistant), Digital Video (DVC) or other electronic communication device.Alternatively, electronic device 50 can be the graphics card that can be inserted in computer, network interface unit or other signal processing card.Semiconductor packages can comprise microprocessor, memory, application-specific integrated circuit (ASIC) (ASIC), logical circuit, analog circuit, RF circuit, discrete device or other semiconductor element or electric component.It is indispensable that miniaturized and weight reduces for the product that will be accepted by market.Distance between semiconductor device must be reduced to realize higher density.
In FIG, PCB 52 is provided for the support structure of the semiconductor packages be arranged on PCB and the general substrate of electric interconnection.Evaporation, metallide, chemical plating, silk screen printing or other suitable metal deposition process is used to form conductive signal trace 54 in the layer of PCB 52 or above the surface of PCB 52.The electrical communication of signal traces 54 between to provide in semiconductor packages, the parts of installation and the system unit of other outside each.Trace 54 also provides power supply to connect and grounding connection to each semiconductor packages.
In certain embodiments, semiconductor device has two package levels.First order encapsulation is for by semiconductor element mechanical attachment and the technology being electrically attached to intermediate carrier.Second level encapsulation relates to intermediate carrier mechanical attachment and is electrically attached to PCB.In other embodiments, semiconductor device can only have the first order encapsulation, wherein by tube core direct mechanical install and electrical install to PCB.
In order to illustrated object, PCB 52 illustrates the first order encapsulation of the several types comprising closing line encapsulation 56 and flip-chip 58.In addition, the second level encapsulation comprising the several types of ball grid array (BGA) 60, bump chip carrier (BCC) 62, dual in-line package (DIP) 64, planar lattice array (LGA) 66, multi-chip module (MCM) 68, quad flat non-leaded package (QFN) 70 and quad flat package 72 be arranged on PCB 52 is shown.Depend on the requirement of system, can be connected the semiconductor packages of any combination and any of other electronic unit that are configured with first order encapsulation style and the second level encapsulation style PCB 52.In certain embodiments, electronic device 50 comprises the semiconductor packages of single attachment, and other embodiment requires the encapsulation of multiple interconnection.One or more semiconductor packages combined by face on a single substrate, the parts made in advance can be incorporated in electronic device and system by producer.Because semiconductor packages comprises very complicated functional, so more cheap parts and streamlined manufacturing process can be used to manufacture electronic device.The device obtained unlikely is out of order and manufactures more cheaply, thus produces lower cost to consumer.
Fig. 2 a-2c illustrates that exemplary semiconductor encapsulates.Fig. 2 a diagram is arranged on the further details of the DIP 64 on PCB 52.Semiconductor element 74 includes source region, and this active region contains to be implemented as and formed in tube core and the analog or digital circuit of the active device be electrically, passive device, conductive layer and dielectric layer according to the electrical design of tube core.Such as, circuit can be included in the one or more transistors, diode, inductor, capacitor, resistor and other circuit element that are formed in the active region of semiconductor element 74.Contact pad 76 is one or more conductive material layers, such as aluminium (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au) or silver (Ag), and is electrically connected to the circuit element formed in semiconductor element 74.Between the erecting stage of DIP 64, use gold-silicon eutectic layer or cohesive material such as hot epoxy or epoxy resin that semiconductor element 74 is installed to intermediate carrier 78.Encapsulation matrix comprises the encapsulating material of insulation, such as polymer or pottery.Lead wire of conductor 80 and bonding wire 82 provide the electric interconnection between semiconductor element 74 and PCB 52.On encapsulate, deposit sealant 84 is for by stoping moisture and particle to enter encapsulation and polluting semiconductor element 74 or closing line 82 and carry out environmental protection.
Fig. 2 b is shown in the further details of the BCC 62 that PCB 52 installs.Use end filling or epoxy resin cohesive material 92, on carrier 90, semiconductor element 88 is installed.Closing line 94 provides the first order packaging interconnection between contact pad 96 and 98.Mold compound or sealant 100 are deposited on semiconductor element 88 and closing line 94 and provide physical support and electrical isolation above thus for device.Suitable metal deposition process such as metallide or chemical plating is used on the surface of PCB 52, to form contact pad 102 to stop oxidation.In PCB 52, contact pad 102 is connected electrically to one or more conductive signal trace 54.Projection 104 is formed between the contact pad 98 and the contact pad 102 of PCB 52 of BCC 62.
In figure 2 c, encapsulate semiconductor element 58 towards being installed to intermediate carrier 106 facing downward with the flip-chip pattern first order.The active region 108 of semiconductor element 58 is containing the analog or digital circuit being implemented as the active device, passive device, conductive layer and the dielectric layer that are formed according to the electrical design of tube core.Such as, circuit can comprise one or more transistor, diode, inductor, capacitor, resistor and other circuit element in active region 108.Semiconductor element 58 is typically electrically connected and is mechanically connected to carrier 106 through projection 110.
Use projection 112, with the encapsulation of the BGA pattern second level, BGA 60 is electrically connected and is mechanically connected to PCB 52.Semiconductor element 58 is electrically connected to the conductive signal trace 54 in PCB 52 through projection 110, holding wire 114 and projection 112.Mold compound or sealant 116 are deposited on semiconductor element 58 and carrier 106 and provide physical support and electrical isolation above thus for device.Flip-chip semiconductor device provides the short electrical conductivity path from the active device semiconductor element 58 to the conductive track on PCB 52 to reduce signal propagation distance, reduce electric capacity and improve overall circuit performance.In another embodiment, the flip-chip pattern first order can be used to encapsulate and do not have intermediate carrier 106 semiconductor element 58 direct mechanical connected and be connected electrically to PCB 52.
Fig. 3 a illustrates the semiconductor crystal wafer 120 of the base substrate material 122 had for the such as silicon of support structure, germanium, GaAs, indium phosphide or carborundum.As described above, by non-active, multiple semiconductor element that wafer area between tube core or saw street 126 are separated or parts 124 are formed on wafer 120.Saw street 126 provides the region of cutting semiconductor crystal wafer 120 to be partitioned into other semiconductor element 124.In one embodiment, the diameter of semiconductor crystal wafer 120 is 200-300 millimeter (mm).In another embodiment, the diameter of semiconductor crystal wafer 120 is 100-450 mm.Before semiconductor crystal wafer being partitioned into other semiconductor element 124, semiconductor crystal wafer 120 can have any diameter.
Fig. 3 b illustrates the viewgraph of cross-section of the part of semiconductor crystal wafer 120.Each semiconductor element 124 has surface 128 and the active surface 130 of the back side or non-active, this active surface 130 containing be implemented as formed in tube core according to the electrical design of tube core and function and the analog or digital circuit of the active device be electrically, passive device, conductive layer and dielectric layer.Such as, circuit can be included in interior one or more transistors, diode and other circuit element formed of active surface 130 to implement analog circuit or digital circuit, such as digital signal processor (DSP), ASIC, memory or other signal processing circuit.Semiconductor element 124 can also containing the integrated passive device (IPD) for RF signal transacting, such as inductor, capacitor and resistor.
PVD, CVD, metallide, chemical plating process or other suitable metal deposition process is used to form conductive layer 132 on active surface 130.Conductive layer 132 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.Conductive layer 132 is operating as the contact pad of the circuit be electrically connected on active surface 130.Conductive layer 132 can be formed the contact pad be arranged side by side from edge first distance of semiconductor element 124, shown by fig 3b.Alternatively, conductive layer 132 can be formed contact pad, this contact pad in multiple row by shift into make the first row of contact pad be set to from tube core edge first apart from and the second row of the contact pad replaced with the first row is set to from tube core edge second distance.
Use PVD, CVD, printing, rotary coating, spray application, sintering or thermal oxidation on semiconductor element 124 and conductive layer 132, form the first insulation or passivation layer 124.Insulating barrier 134 containing one or more layers silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminium oxide (Al2O3), hafnium oxide (HfO2), benzocyclobutene (BCB), polyimides (PI), polybenzoxazoles (PBO), polymer or there is other dielectric substance of similar structural property and insulating property (properties).
Use patterning and metal deposition process such as sputters, metallide and chemical plating form conductive layer or redistributing layer (RDL) 136 on the first insulating barrier 134.Conductive layer 136 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.A part for conductive layer 136 is electrically connected to the conductive layer 132 of semiconductor element 124.Depend on the Design and Features of semiconductor element 124, the other parts of conductive layer 136 can be electrically share or be electrically isolated.
The second insulation or passivation layer 134 is formed on conductive layer 136 and the first insulating barrier 134.Multiple insulating barrier 134 and conductive layer 136 can be formed on the active surface 130 of semiconductor element 124.Actuating surface inspection can detect passivation or RDL defect.
Use laser 138 directly to melt (LDA) by laser and remove the part of insulating barrier 134 to expose part 140 and the conductive layer 132 of active surface 130 along the marginal surface of semiconductor element 124.That is exactly lack insulating barrier 134 along the part 140 of the active surface 130 of the marginal surface of semiconductor element 124.Alternatively, the part of insulating barrier 134 is removed to expose part 140 and the conductive layer 132 of active surface 130 along the marginal surface of semiconductor element 124 by etching technics through the photoresist oxidant layer of patterning.
In figure 3 c, after last passivation again, use PVD, CVD, evaporation, metallide, chemical plating or other suitable metal deposition process to form conductive layer 142 on the part of the exposure of insulating barrier 134 and conductive layer 132.Conductive layer 142 can be Al, Cu, Sn, Ni, Au, Ag, tungsten (W) or other suitable electric conducting material.Conductive layer 142 is the under-bump metallizations (UBM) being electrically connected to conductive layer 132.UBM 142 can be have adhesive layer, barrier layer and Seed Layer or wettable layer how metal laminated.Adhesive layer is formed and can be titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), Al or chromium (Cr) on conductive layer 132.Barrier layer is formed and can be Ni, NiV, platinum (Pt), palladium (Pd), TiW, Ti or chromium-copper (CrCu) on adhesive layer.Barrier layer forbids that Cu is diffused in the active area of tube core.Seed Layer over the barrier layer face is formed and can be Cu, Ni, NiV, Au or Al.UBM 142 conductive layer 132 provides low resistance interconnect, and the stop of solder diffusion and Seed Layer for solder wettable.
Semiconductor crystal wafer 120 stands electric test and checks the part as quality control process.Artificial visual inspection and automation optical system is used to perform inspection to semiconductor crystal wafer 120.Software can be used in the automation optical analysis of semiconductor crystal wafer 120.The method of visual inspection can adopt the equipment of such as scanning electron microscopy, high-strength light or ultraviolet light or metallomicroscope.For comprise warpage, varied in thickness, surface particle, irregular, crack, layering and variable color architectural characteristic semiconductor crystal wafer 120 is checked.
Active parts in semiconductor element 124 and passive component stand the test in wafer scale for electric property and circuit function.Probe or other testing apparatus is used to test each semiconductor element 124 for functional and electric parameter.Probe is used to reach electrical contact with node or contact pad 132 on each semiconductor element 124, and provides electric stimulation to contact pad.Semiconductor element 124 is in response to electric stimulation, and this electrically stimulates measured and carry out the functional of measuring semiconductor tube core compared with the response of expection.Electric test can comprise circuit functionality, the integrality of lead-in wire, resistivity, continuity, reliability, the degree of depth of knot, Electrostatic Discharge, radio frequency (RF) performance, drive current, threshold current, leakage current and the operating parameter specific to unit type.The known good tube core (KGD) that the inspection of semiconductor crystal wafer 120 and electric test make qualified semiconductor element 124 be designated as to use in semiconductor packages.
In Fig. 3 d, use saw blade or laser cutting tool 144, through saw street 126, semiconductor crystal wafer 120 is partitioned into other semiconductor element 124.Can check other semiconductor element 124 individual and electric test for the identification of the KGD after splitting.
Fig. 4 a-4e illustrate relevant with Fig. 1 and 2 a-2c in WLCSP on the part of the exposure of the active surface of semiconductor element and side the technique of deposit sealant.Fig. 4 a illustrate containing sacrificial substrate material such as silicon, polymer, beryllium oxide, glass or other the suitable low cost for support structure, the viewgraph of cross-section of the firm temporary substrates 150 of material or the part of carrier.Boundary layer or two-sided tape 152 are formed on carrier 150 above as temporary adhesive bonding film, etching stop layer or Thermal release layer.
Carrier 150 can be the circle of the capacity with multiple semiconductor element 124 or the panel (being greater than 300 mm) of rectangle.Carrier 150 can have the surface area larger than the surface area of semiconductor crystal wafer 120.Larger carrier reduces the manufacturing cost of semiconductor packages, because can process more semiconductor element on larger carrier, thus reduces the cost of each unit.Size for just processed carrier or wafer designs and configuring semiconductor encapsulation and treatment facility.
In order to reduce manufacturing cost further, the size of carrier 150 is selected independent of the size of semiconductor crystal wafer 120 or the size of semiconductor element 124.That is exactly that carrier 150 has fixing or standardized size, and it can hold the semiconductor element 124 of the various sizes of segmentation from one or more semiconductor crystal wafer 120.In one embodiment, carrier 150 is circles of the diameter with 330 mm.In another embodiment, carrier 150 is the rectangles with the width of 560 mm and the length of 600 mm.Semiconductor element 124 can have the size of 10 mm × 10 mm, and it is placed on standard carriers 150.Alternatively, semiconductor element 124 can have the size of 20 mm × 20 mm, and it is placed on identical standard carriers 150.Therefore, standard carriers 150 can dispose the semiconductor element 124 of any size, and it allows the carrier for sharing to carry out standardization semiconductor processing equipment subsequently, namely independent of the size of tube core or the wafer size of introducing.Can for the carrier design of standard and configuring semiconductor sealed in unit, the carrier of this standard can be used for processing any semi-conductor die size from the wafer size of any introducing.The carrier 150 with fixed dimension and profile allows to use a set of handling implement, equipment and the material shared to process the semiconductor element 124 of the different size of the semiconductor crystal wafer 120 from different size.Such as, from the semiconductor element 124 of 10 × 10 mm of the semiconductor crystal wafer of 200 mm, or on carrier 150, identical equipment and the bill of materials is used to be processed from the semiconductor element 124 of 20 × 20 mm of the semiconductor crystal wafer of 450 mm.Share or standardized carrier 150 reduces manufacturing cost by the needs reduced or eliminated for the special semiconductor processes line of the wafer size based on die-size or introducing.Standard carriers size reduces the risk of fund, even if because treatment facility also remains unchanged along with the size of semiconductor element changes.By selecting the carrier dimensions of pre-determining for any scale semiconductor tube core from all semiconductor crystal wafers, can implement to manufacture line flexibly.
Such as use the operation of pickup and placement that the semiconductor element 124 from Fig. 3 d is installed to carrier 150 and boundary layer 152, wherein insulating barrier 134 is oriented to towards carrier.Fig. 4 b illustrate the semiconductor element 124 of the boundary layer 152 being installed to carrier 150 as reconstruct or the wafer 153 that configures again.Because the conductive layer 142 of contact interface layer and/or the attribute of insulating barrier 134 make the active surface 130 of semiconductor element 124 keep off with boundary layer 152 or offset, namely between the part 140 and boundary layer 152 of active surface 130, there is gap.
The wafer of reconstruct or the panel 153 of reconstruct can be processed to be eurypalynous semiconductor packages perhaps, its comprise fan-in wafer level chip scale encapsulation (WLCSP), reconstruct or embed wafer level chip scale encapsulation (eWLCSP), fan-out WLCSP, Flip-Chip Using, three-dimensional (3D) encapsulation, such as packaging body lamination (PoP) or other semiconductor packages.The panel 153 of reconstruct is configured according to the explanation of the semiconductor packages obtained.In one embodiment, semiconductor element 124 is placed on carrier 150 for the treatment of fan-in device with highdensity layout (namely separate 300 microns (μm) or less).In another embodiment, semiconductor element 124 is separated with the distance of 50 μm ground on carrier 150.Be optimized for minimum unit cost to manufacture semiconductor packages to distance between semiconductor element 124 on carrier 150.The larger surface area of carrier 150 holds more semiconductor element 124 and reduces manufacturing cost, because the panel 153 of each reconstruct processes more semiconductor element 124.The number being installed to the semiconductor element 124 of carrier 150 can be greater than, be less than or equal to the number of the semiconductor element 124 split from semiconductor crystal wafer 120.The panel 153 of carrier 150 and reconstruct provides the semiconductor element 124 of use from the different size of the semiconductor crystal wafer 120 of different size to manufacture the flexibility of many dissimilar semiconductor packages.
In Fig. 4 c, use that cream printing, compression forming, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 154 on semiconductor element 124 and carrier 150.Sealant 154 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 154 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.Especially, sealant 154 is set up along in the side of semiconductor element 124 and the gap between active surface 130 and boundary layer 152, and therefore on the marginal surface of semiconductor element, covers the part 140 of the side of semiconductor element 124 and the exposure of active surface 130 to insulating barrier 134 ground.Therefore, sealant 154 covers or at least five surfaces of contact semiconductor tube core 124, i.e. the part 140 of four side surfaces of semiconductor element and the active surface 130 of semiconductor element.
In figure 4d,, ultraviolet light roasting by chemical etching, mechanical stripping, chemical-mechanical planarization (CMP), mechanical lapping, heat, laser scanning or wet stripping (wet stripping) remove carrier 150 and boundary layer 152, to expose insulating barrier 134 and conductive layer 142.Laser 156 is used to be removed the part of sealant 154 by LDA.Alternatively, removed the part of sealant 154 through the photoresist oxidant layer of patterning by etching technics.Keep being covered to increase rate of finished products, especially when surface mount semiconductor tube core by the sealant 154 as protection panel along the part 140 of the active surface 130 of the marginal surface of semiconductor element 124 and the side of semiconductor element.Sealant 154 also protects semiconductor element 124 to avoid owing to exposing the degeneration produced.Clean by utilizing the plasma of one or more step, wet solution, cupric oxide or dry method and clean insulating barrier 134 and conductive layer 142 for electric test preparation semiconductor element 124.
In figure 4e, evaporation, metallide, chemical plating, globule (ball drop) or silk-screen printing technique deposit conductive bump material on conductive layer 142 is used.In one embodiment, utilize globule masterplate deposit bump material, namely do not need mask.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, lead (Pb), Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 142.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 160.In some applications, projection 160 is refluxed to improve the electrical contact with conductive layer 142 for the second time.Projection 160 can also be joined to conductive layer 142 by compression engagement or hot compression.Projection 160 represents the interconnection structure of a type that can be formed on conductive layer 142.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.Before projection is formed or after projection is formed, or laser labelling can be performed after the removal of carrier 150.
Utilize saw blade or laser cutting tool 162, through sealant 154, semiconductor element 124 is partitioned into indivedual WLCSP 164 embedded.Fig. 5 segmentation is shown after WLCSP 164.In one embodiment, WLCSP 164 has the size of 3.0 × 2.6 × 0.7 millimeter of mm, and wherein pitch is 0.4 mm.Semiconductor element 124 is electrically connected to the projection 160 for external interconnect.Sealant 154 covers the side of semiconductor element 124 and the part 140 of active surface 130 to protect the side of semiconductor element and marginal surface and to increase fabrication yield, especially when surface mount semiconductor tube core.Sealant 154 also protects semiconductor element 124 to avoid owing to exposing the degeneration produced.WLCSP 164 stands electric test before it is split or upon splitting.
Similar with Fig. 3 a, Fig. 6 a-6c diagram has another embodiment of the semiconductor crystal wafer 170 of base substrate material 172 such as silicon, germanium, GaAs, indium phosphide or carborundum for support structure.As described above, by non-active, multiple semiconductor element that wafer area between tube core or saw street 176 are separated or parts 174 are formed on wafer 170.Saw street 176 provides cutting area so that semiconductor crystal wafer 170 is partitioned into individual semiconductor die 174.In one embodiment, the diameter of semiconductor crystal wafer 170 is 200-300 mm.In another embodiment, the diameter of semiconductor crystal wafer 170 is 100-450 mm.Before semiconductor crystal wafer is partitioned into individual semiconductor die 174, semiconductor crystal wafer 170 can have any diameter.
Fig. 6 a illustrates the viewgraph of cross-section of the part of semiconductor crystal wafer 170.Each semiconductor element 174 has surface 178 and the active surface 180 of the back side or non-active, this active surface 180 containing be implemented as formed in tube core according to the electrical design of tube core and function and the analog or digital circuit of the active device be electrically, passive device, conductive layer and dielectric layer.Such as, circuit can be included in interior one or more transistors, diode and other circuit element formed of active surface 180 to implement analog circuit or digital circuit, such as DSP, ASIC, memory or other signal processing circuit.Semiconductor element 174 can also containing the IPD for RF signal transacting, such as inductor, capacitor and resistor.
PVD, CVD, metallide, chemical plating process or other suitable metal deposition process is used to form conductive layer 182 on active surface 180.Conductive layer 182 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.Conductive layer 182 is operating as the contact pad of the circuit be electrically connected on active surface 130.Conductive layer 182 can be formed the contact pad be arranged side by side from edge first distance of semiconductor element 174, as shown in Fig. 6 a.Alternatively, conductive layer 182 can be formed contact pad, this contact pad in multiple row by shift into make the first row of contact pad be set to from tube core edge first apart from and the second row of the contact pad replaced with the first row is set to from tube core edge second distance.
PVD, CVD, evaporation, metallide, chemical plating or other suitable metal deposition process is used to form conductive layer 184 on conductive layer 182.Conductive layer 184 can be Al, Cu, Sn, Ni, Au, Ag, W or other suitable electric conducting material.Conductive layer 184 is the UBM being electrically connected to conductive layer 182.UBM 184 can be have adhesive layer, barrier layer and Seed Layer or wettable layer how metal laminated.Adhesive layer is formed on conductive layer 182 above and can be Ti, TiN, TiW, Al or Cr.Barrier layer to be formed on above adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti or CrCu.Barrier layer forbids that Cu is diffused in the active area of tube core.Seed Layer to be formed on above barrier layer and can be Cu, Ni, NiV, Au or Al.UBM 184 conductive layer 182 provides low resistance interconnect, and for the stop of solder diffusion and the Seed Layer for solder wettable.
In figure 6b, use PVD, CVD, printing, rotary coating, spray application, sintering or thermal oxidation on semiconductor element 174 and conductive layer 184, form the first insulation or passivation layer 186, namely occur at the post-passivation of UBM 184 formation.Insulating barrier 186 containing one or more layers SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer or there is other dielectric substance of similar structural property and insulating property (properties).
Use patterning and metal deposition process such as sputters, metallide and chemical plating form conductive layer or RDL 188 on the first insulating barrier 186.Conductive layer 188 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.A part for conductive layer 188 is electrically connected to the conductive layer 182 of semiconductor element 174.Depend on the Design and Features of semiconductor element 174, the other parts of conductive layer 188 can electrically share or be electrically isolated.
The second insulation or passivation layer 186 is formed on conductive layer 188 and the first insulating barrier 186.Multiple insulating barrier 186 and conductive layer 188 can be formed on the active surface 180 of semiconductor element 174.Actuating surface inspection can detect passivation or RDL defect.
Laser 190 is used to be removed the part of insulating barrier 186 by LDA to expose part 192 and the conductive layer 184 of active surface 180 along the marginal surface of semiconductor element 174.That is exactly lack insulating barrier 186 along the part 192 of the active surface 180 of the marginal surface of semiconductor element 174.Alternatively, the part of insulating barrier 186 is removed to expose part 192 and the conductive layer 182 of active surface 180 along the marginal surface of semiconductor element 174 by etching technics through the photoresist oxidant layer of patterning.
In fig. 6 c, use saw blade or laser cutting tool 194, through saw street 176, semiconductor crystal wafer 170 is partitioned into other semiconductor element 174.Can check other semiconductor element 174 individual and electric test for the identification of the KGD after splitting.
Fig. 7 a-7e illustrate relevant with Fig. 1 and 2 a-2c in WLCSP on the part of the exposure of the active surface of semiconductor element and side another technique of deposit sealant.Fig. 7 a illustrate containing sacrificial substrate material such as silicon, polymer, beryllium oxide, glass or other the suitable low cost for support structure, the viewgraph of cross-section of the firm carrier of material or the part of temporary substrates 200.Boundary layer or two-sided tape 202 are formed on carrier 200 above as temporary adhesive bonding film, etching stop layer or Thermal release layer.
Carrier 200 can be the panel (being greater than 300 mm) with large circle for the capacity of multiple semiconductor element 174 or rectangle.Carrier 200 can have the surface area larger than the surface area of semiconductor crystal wafer 170.Larger carrier reduces the manufacturing cost of semiconductor packages, because can process more semiconductor element on larger carrier, thus reduces the cost of each unit.Size for just processed carrier or wafer designs and configuring semiconductor encapsulation and treatment facility.
In order to reduce manufacturing cost further, select the size of carrier 200 independent of the size of semiconductor crystal wafer 170 or the size of semiconductor element 174.That is exactly that carrier 200 has fixing or standardized size, and it can hold the semiconductor element 174 of the various sizes of segmentation from one or more semiconductor crystal wafer 170.In one embodiment, carrier 200 is circles of the diameter with 330 mm.In another embodiment, carrier 200 is the rectangles with the width of 560 mm and the length of 600 mm.Semiconductor element 174 can have the size of 10 mm × 10 mm, and it is placed on standardized carrier 200.Alternatively, semiconductor element 174 can have the size of 20 mm × 20 mm, and it is placed on identical standardized carrier 140.Therefore, standard carriers 200 can dispose the semiconductor element 174 of any size, and it allows the carrier for sharing to carry out standardization semiconductor processing equipment subsequently, namely independent of the size of tube core or the wafer size of introducing.Can for the carrier design of standard and configuring semiconductor sealed in unit, the carrier of this standard uses a set of handling implement, equipment and the bill of materials shared to process the size of any semiconductor element of the wafer size from any introducing.Share or standardized carrier 200 reduces manufacturing cost and financial risks by the needs reduced or eliminated for the special semiconductor processes line of the wafer size based on die-size or introducing.By selecting the size of the carrier of pre-determining for the semiconductor element from any size of all semiconductor crystal wafers, can implement to manufacture line flexibly.
Such as be oriented to towards using the operation of pickup and placement that the semiconductor element 174 from Fig. 6 c is installed to carrier 200 and boundary layer 202 when carrier at insulating barrier 186.Fig. 7 b illustrate the semiconductor element 174 of the boundary layer 202 being installed to carrier 200 as reconstruct or the wafer 203 that configures again.Attribute due to the insulating barrier 186 of contact interface layer makes the active surface 180 of semiconductor element 174 keep off with boundary layer 202 or offset, and namely between the part 192 and boundary layer 202 of active surface 180, there is gap.
The wafer of reconstruct or the panel 203 of reconstruct can be processed to be eurypalynous semiconductor packages perhaps, its comprise fan-in WLCSP, reconstruct or embed WLCSP or eWLCSP, fan-out WLCSP, 3D encapsulation, such as PoP or other semiconductor packages.The panel 203 of reconstruct is configured according to the explanation of the semiconductor packages obtained.In one embodiment, semiconductor element 174 is placed on carrier 200 for the treatment of fan-in device with highdensity layout (namely separating 300 μm or less).In another embodiment, semiconductor element 174 is separated with the distance of 50 μm on carrier 200.Distance between semiconductor element 174 on carrier 200 is optimized for minimum unit cost to manufacture semiconductor packages.The carrier 200 of larger surface area holds more semiconductor element 174 and reduces manufacturing cost, because the panel 203 of each reconstruct processes more semiconductor element 174.The number being installed to the semiconductor element 174 of carrier 200 can be greater than, be less than or equal to the number of the semiconductor element 174 split from semiconductor crystal wafer 170.The panel 203 of carrier 200 and reconstruct provides the semiconductor element 174 of use from the different size of the semiconductor crystal wafer 170 of different size to manufacture the flexibility of many dissimilar semiconductor packages.
In figure 7 c, use that cream printing, compression forming, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 204 on semiconductor element 174 and carrier 200.Sealant 204 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 204 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.Especially, sealant 204 is set to along in the side of semiconductor element 174 and the gap between active surface 180 and boundary layer 202, and therefore on the marginal surface of semiconductor element, covers the part 192 of the side of semiconductor element 174 and the exposure of active surface 180 to insulating barrier 186 ground.Therefore, sealant 204 covers or at least five surfaces of contact semiconductor tube core 174, i.e. the part 192 of four side surfaces of semiconductor element and the active surface 180 of semiconductor element.
In figure 7d, ultraviolet light roasting by chemical etching, mechanical stripping, CMP, mechanical lapping, heat, laser scanning or wet stripping remove carrier 200 and boundary layer 202, to expose insulating barrier 186 and conductive layer 184.Laser 206 is used to be removed the part of sealant 204 by LDA.Alternatively, removed the part of sealant 204 through the photoresist oxidant layer of patterning by etching technics.Keep being covered to increase rate of finished products, especially when surface mount semiconductor tube core by the sealant 204 as protection panel along the part 192 of the active surface 180 of the marginal surface of semiconductor element 124 and the side of semiconductor element.Sealant 204 also protects semiconductor element 174 to avoid owing to exposing the degeneration produced.Clean by utilizing the plasma of one or more step, wet solution, cupric oxide or dry method and clean insulating barrier 186 and conductive layer 184, prepare semiconductor element 174 for electric test.
In figure 7e, evaporation, metallide, chemical plating, globule or silk-screen printing technique deposit conductive bump material on conductive layer 184 is used.In one embodiment, utilize globule masterplate deposit bump material, namely do not need mask.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 184.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 210.In some applications, projection 210 is refluxed to improve the electrical contact of conductive layer 184 for the second time.Projection 210 can also be joined to conductive layer 184 by compression engagement or hot compression.Projection 210 represents the interconnection structure of a type that can be formed on conductive layer 184.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.Before projection is formed or after projection is formed, or laser labelling can be performed after removal carrier 200.
Utilize saw blade or laser cutting tool 212, through sealant 204, semiconductor element 174 is partitioned into other WLCSP 214.Fig. 8 segmentation is shown after WLCSP 214.In one embodiment, WLCSP 214 has the size of 3.0 × 2.6 × 0.7 millimeter of mm, and wherein pitch is 0.4 mm.Semiconductor element 174 is electrically connected to the projection 210 for external interconnect.Sealant 204 covers the side of semiconductor element 174 and the part 192 of active surface 180 to protect the side of semiconductor element 174 and marginal surface and to increase fabrication yield, especially when surface mount semiconductor tube core.Sealant 204 also protects semiconductor element 174 to avoid owing to exposing the degeneration produced.WLCSP 214 stands electric test before it is split or upon splitting.
Fig. 9 a-9h illustrate relevant with Fig. 1 and 2 a-2c in WLCSP on the part of the exposure of the active surface of semiconductor element and side the technique of deposit MUF material.Fig. 9 a illustrates the semiconductor element 220 from the semiconductor crystal wafer similar with Fig. 3 a, this semiconductor element 220 has surface 222 and the active surface 224 of the back side or non-active, this active surface 224 containing be implemented as formed in tube core according to the electrical design of tube core and function and the analog or digital circuit of the active device be electrically, passive device, conductive layer and dielectric layer.Such as, circuit can be included in interior one or more transistors, diode and other circuit element formed of active surface 224 to implement analog circuit or digital circuit, such as DSP, ASIC, memory or other signal processing circuit.Semiconductor element 220 can also containing the IPD for RF signal transacting, such as inductor, capacitor and resistor.In one embodiment, semiconductor element 220 is semiconductor elements of flip-chip variety.
PVD, CVD, metallide, chemical plating process or other suitable metal deposition process is used to form conductive layer 226 on active surface 224.Conductive layer 226 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.Conductive layer 226 is operating as the contact pad of the circuit be electrically connected on active surface 224.
Use patterning and metal deposition process such as sputters, metallide and chemical plating form conductive layer 228 on conductive layer 226.Conductive layer 228 can be Al, Cu, Sn, Ni, Au, Ag, W or other suitable electric conducting material.Conductive layer 228 is the UBM being electrically connected to conductive layer 226.UBM 228 can be have adhesive layer, barrier layer and Seed Layer or wettable layer how metal laminated.Adhesive layer is formed on conductive layer 226 above and can be Ti, TiN, TiW, Al or Cr.Barrier layer to be formed on above adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti or CrCu.Barrier layer forbids that Cu is diffused in the active area of tube core.Seed Layer to be formed on above barrier layer and can be Cu, Ni, NiV, Au or Al.UBM 228 conductive layer 226 provides low resistance interconnect, and for the stop of solder diffusion and the Seed Layer for solder wettable.
Use evaporation, metallide, chemical plating, globule or silk-screen printing technique deposit conductive bump material on conductive layer 228.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 228.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 230.In some applications, projection 230 is refluxed to improve the electrical contact with conductive layer 228 for the second time.Projection 230 can also be joined to conductive layer 228 by compression engagement or hot compression.Projection 230 represents the interconnection structure of a type that can be formed on conductive layer 228.This interconnection structure can also use stud bumps, miniature projection or other electric interconnections.
Such as use the operation of pickup and placement that semiconductor element 220 is installed to substrate 232 when projection 230 is directed to substrate.Substrate 232 comprise through substrate for conductive trace 234 that the is vertical and interconnection of transverse direction.Fig. 9 b illustrate the semiconductor element 220 that is installed to substrate 232 as reconstruct or the wafer 236 that configures again, wherein projection 230 by metallurgical, bond and electrical engagement to conductive trace 234.Attribute due to projection 230 makes the active surface 224 of semiconductor element 220 keep off with substrate 232 or offset, and namely between the part 238 and substrate 232 of active surface 224, there is gap.Substrate 232 can be the large circle of the capacity had for multiple semiconductor element 220 or the panel (being greater than 300 mm) of rectangle.
In Fig. 9 c, use that cream printing, compression forming, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating, the molded end fills or the deposit on semiconductor element 220 and substrate 232 of other suitable spreading techniques is molded end filling (MUF) material 240.MUF material 240 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.MUF material 240 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.Especially, MUF material 240 is set to along in the side of semiconductor element 220 and the gap between active surface 224 and substrate 232, and therefore along the marginal surface covering side of semiconductor element 220 of semiconductor element and the part 238 of the exposure of active surface 224.
In Fig. 9 d, semiconductor element 220 utilize saw blade or laser cutting tool 239 through MUF material 240 and substrate 232 divided with separating semiconductor tube core and substrate unit.Can check other semiconductor element 220 individual and electric test for the identification of the KGD after splitting.
Fig. 9 e illustrate containing sacrificial substrate material such as silicon, polymer, beryllium oxide, glass or other the suitable low cost for support structure, the viewgraph of cross-section of the firm carrier of material or the part of temporary substrates 242.Boundary layer or two-sided tape 243 are formed on carrier 150 above as temporary adhesive bonding film, etching stop layer or Thermal release layer.
Carrier 242 can be the large circle of the capacity had for multiple semiconductor element 220 and substrate 232 unit or the panel (being greater than 300 mm) of rectangle.Larger carrier reduces the manufacturing cost of semiconductor packages, because can process more semiconductor element on larger carrier, thus reduces the cost of each unit.Size for just processed carrier or wafer designs and configuring semiconductor encapsulation and treatment facility.
In order to reduce manufacturing cost further, the size independent of semiconductor element 220 selects the size of carrier 242.That is exactly that carrier 242 has fixing or standardized size, and it can hold the semiconductor element 220 of the various sizes split from one or more semiconductor crystal wafer.In one embodiment, carrier 242 is circles of the diameter with 330 mm.In another embodiment, carrier 242 is the rectangles with the width of 560 mm and the length of 600 mm.Semiconductor element 220 can have the size of 10 mm × 10 mm, and it is placed on standard carriers 242.Alternatively, semiconductor element 220 can have the size of 20 mm × 20 mm, and it is placed on identical standard carriers 242.Therefore, standard carriers 242 can dispose the semiconductor element 220 of any size, and it allows the carrier for sharing to carry out standardization semiconductor processing equipment subsequently, namely independent of the size of tube core or the wafer size of introducing.Can for the carrier design of standard and configuring semiconductor sealed in unit, the carrier of this standard uses a set of handling implement, equipment and the bill of materials shared to process the size of any semiconductor element of the wafer size from any introducing.Share or standardized carrier 242 reduces manufacturing cost and financial risks by the needs reduced or eliminated for the special semiconductor processes line of the wafer size based on die-size or introducing.By selecting the size of the carrier of pre-determining for the semiconductor element from any size of all semiconductor crystal wafers, can implement to manufacture line flexibly.
Such as be oriented at substrate and in carrier situation, use pickup and the operation of placing by semiconductor element 220 and substrate 232 cellular installation to carrier 242 and boundary layer 243.Fig. 9 f illustrates semiconductor element 220 and substrate 232 unit of the boundary layer 243 being installed to carrier 242.
Use that cream printing, compression forming, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 244 on MUF material 240, substrate 232 and carrier 242.Sealant 244 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 244 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.
In Fig. 9 g, ultraviolet light roasting by chemical etching, mechanical stripping, CMP, mechanical lapping, heat, laser scanning or wet stripping remove carrier 242 and boundary layer 243, to expose substrate 232 and sealant 244.Laser 245 is used to be removed the part of sealant 244 by LDA.Alternatively, removed the part of sealant 244 through the photoresist oxidant layer of patterning by etching technics.
In Fig. 9 h, use evaporation, metallide, chemical plating, globule or silk-screen printing technique deposit conductive bump material on the conductive layer 234 of the substrate 232 relative with semiconductor element 220.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 234.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 246.In some applications, projection 246 is refluxed to improve the electrical contact with conductive layer 234 for the second time.Projection 246 can also be joined to conductive layer 234 by compression engagement or hot compression.Projection 246 represents the interconnection structure of a type that can be formed on conductive layer 234.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.
Before projection is formed or after projection is formed, or laser labelling can be performed after removal carrier 242.Assembly stands plasma clean and solder flux printing.
Utilize saw blade or laser cutting tool 248, through sealant 244, semiconductor element 220 is partitioned into other WLCSP 250.Figure 10 segmentation is shown after WLCSP 250.In one embodiment, WLCSP 250 has the size of 3.0 × 2.6 × 0.7 millimeter of mm, and wherein pitch is 0.4 mm.Semiconductor element 220 is electrically connected to substrate 232 and projection 246 for external interconnect.MUF material 240 covers the side of semiconductor element 220 and the part 238 of active surface 224 to protect the side of semiconductor element and marginal surface and to increase fabrication yield, especially when surface mount semiconductor tube core.MUF material 240 also protects semiconductor element 220 to avoid owing to exposing the degeneration produced.Sealant 244 covers WLCSP 250 with protection device.WLCSP 250 stands electric test before it is split or upon splitting.
The embodiment of Figure 11 diagram and the similar WLCSP 254 of Figure 10, wherein arranges MUF material below semiconductor element 220 and sealant 244 covers the side surface of semiconductor element.
Figure 12 diagram comprises another embodiment of the semiconductor packages of the semiconductor element 260 from the semiconductor crystal wafer similar with Fig. 3 a, this semiconductor element 260 has surface 262 and the active surface 264 of the back side or non-active, this active surface 264 containing be implemented as formed in tube core according to the electrical design of tube core and function and the analog or digital circuit of the active device be electrically, passive device, conductive layer and dielectric layer.Such as, circuit can be included in interior one or more transistors, diode and other circuit element formed of active surface 264 to implement analog circuit or digital circuit, such as DSP, ASIC, memory or other signal processing circuit.Semiconductor element 260 can also containing the IPD for RF signal transacting, such as inductor, capacitor and resistor.In one embodiment, semiconductor element 260 is semiconductor elements of line bond types.
PVD, CVD, metallide, chemical plating process or other suitable metal deposition process is used to form conductive layer 266 on active surface 264.Conductive layer 266 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.Conductive layer 266 is operating as the contact pad of the circuit be electrically connected on active surface 264.
Similar with Fig. 9 a-9b, utilize the die attach adhesive 270 of such as epoxy resin that semiconductor element 260 is installed to substrate 268.Substrate 268 comprise through substrate for conductive trace 272 that the is vertical and interconnection of transverse direction.Closing line 274 is formed between conductive trace 272 on substrate 268 and the conductive layer 266 of semiconductor element 260.Substrate 268 can be the large circle of the capacity had for multiple semiconductor element 260 or the panel (being greater than 300 mm) of rectangle.
Similar with Fig. 9 c, use that cream printing, compression forming, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 276 on semiconductor element 260 and substrate 268.Sealant 276 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 276 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.
Similar with Fig. 9 d, semiconductor element 260 through sealant 276 and substrate 268 divided.Similar with Fig. 9 e, the semiconductor element 260 of segmentation and substrate 268 are installed to carrier.Similar with Fig. 9 f, use that cream printing, compression forming, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 278 on sealant 276 and substrate 268.Sealant 278 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 278 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.Carrier is removed.
Use evaporation, metallide, chemical plating, globule or silk-screen printing technique deposit conductive bump material on the conductive layer 272 of the substrate 268 relative with semiconductor element 260.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 272.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 280.In some applications, projection 280 is refluxed to improve the electrical contact with conductive layer 272 for the second time.Projection 280 can also be joined to conductive layer 272 by compression engagement or hot compression.Projection 280 represents the interconnection structure of a type that can be formed on conductive layer 272.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.
Before projection is formed or after projection is formed, or laser labelling can be performed after removal carrier.Assembly stands plasma clean and solder flux printing.
Semiconductor element 260 is partitioned into other semiconductor packages 282 through sealant 244, and this semiconductor packages 282 has the size of 3.0 × 2.6 × 0.7 millimeter of mm, and wherein pitch is 0.4 mm.Semiconductor element 260 is electrically connected to substrate 268 and projection 280 for external interconnect.Sealant 276 covers the side surface of semiconductor element 260 to protect the marginal surface of semiconductor element and to increase fabrication yield, especially when surface mount semiconductor tube core.
Figure 13 a-13p illustrates the technique of fan-in WLCSP that is that the formation relevant with Fig. 1 and 2 a-2c reconstructs or that embed.Figure 13 a illustrates the semiconductor crystal wafer 290 of the base substrate material 292 had for the such as silicon of support structure, germanium, GaAs, indium phosphide or carborundum.As described above, by non-active, multiple semiconductor element that wafer area between tube core or saw street 296 are separated or parts 294 are formed on wafer 290.Saw street 296 provides cutting area so that semiconductor crystal wafer 290 is partitioned into individual semiconductor die 294.Before semiconductor crystal wafer is partitioned into individual semiconductor die 294, semiconductor crystal wafer 290 can have any diameter.In one embodiment, the diameter of semiconductor crystal wafer 290 is 200-300 mm.In another embodiment, the diameter of semiconductor crystal wafer 290 is 100-450 mm.Semiconductor element 294 can have any size, and in one embodiment, semiconductor element 294 has the size of 10 mm × 10 mm.
Figure 13 a also illustrates the semiconductor crystal wafer 300 similar with semiconductor crystal wafer 290.Semiconductor crystal wafer 300 comprises the base substrate material 302 for support structure, such as silicon, germanium, GaAs, indium phosphide or carborundum.As described above, by non-active, multiple semiconductor element that wafer area between tube core or saw street 306 are separated or parts 304 are formed on wafer 300.Saw street 306 provides cutting area so that semiconductor crystal wafer 300 is partitioned into individual semiconductor die 304.Semiconductor crystal wafer 300 can have the diameter identical from semiconductor crystal wafer 290 or have the diameter different with semiconductor crystal wafer 290.Before semiconductor crystal wafer is partitioned into individual semiconductor die 304, semiconductor crystal wafer 300 can have any diameter.In one embodiment, the diameter of semiconductor crystal wafer 300 is 200-300 mm.In another embodiment, the diameter of semiconductor crystal wafer 300 is 100-450 mm.Semiconductor element 304 can have any size, and in one embodiment, semiconductor element 304 is less than semiconductor element 294 and has the size of 5 mm × 5 mm.
Figure 13 b illustrates the viewgraph of cross-section of the part of semiconductor crystal wafer 290.Each semiconductor element 294 has surface 310 and the active surface 312 of the back side or non-active, this active surface 312 containing be implemented as formed in tube core according to the electrical design of tube core and function and the analog or digital circuit of the active device be electrically, passive device, conductive layer and dielectric layer.Such as, circuit can be included in interior one or more transistors, diode and other circuit element formed of active surface 312 to implement analog circuit or digital circuit, such as DSP, ASIC, memory or other signal processing circuit.Semiconductor element 294 can also containing the IPD for RF signal transacting, such as inductor, capacitor and resistor.
PVD, CVD, metallide, chemical plating process or other suitable metal deposition process is used to form conductive layer 314 on active surface 312.Conductive layer 314 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.Conductive layer 314 is operating as the contact pad of the circuit be electrically connected on active surface 312.Conductive layer 314 can be formed the contact pad be arranged side by side from edge first distance of semiconductor element 294, as shown in Figure 13 b.Alternatively, conductive layer 314 can be formed contact pad, this contact pad is shifted into edge first distance making the first row of contact pad be set to from semiconductor element 294 in multiple row, and the second row of the contact pad replaced with the first row is set to the edge second distance from semiconductor element 294.
Use PVD, CVD, printing, rotary coating, spray application, sintering or thermal oxidation on semiconductor element 294 and conductive layer 314, form the first insulation or passivation layer 316.Insulating barrier 316 containing one or more layers SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer or there is other dielectric substance of similar structural property and insulating property (properties).In one embodiment, insulating barrier 316 is low-temperature setting photosensitive dielectrics polymer, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.Insulating barrier 316 covers active surface 312 and provides protection to active surface 312.Use laser 318 by LDA or use etching technics to remove the part of insulating barrier 316 to expose conductive layer 314 through the surface 320 of insulating barrier 316 and to provide electric interconnection subsequently through the photoresist oxidant layer of patterning.
Semiconductor crystal wafer 290 stands electric test and checks the part as quality control process.Artificial vision checks and automation optical system is used for performing the inspection to semiconductor crystal wafer 290.Software can be used in the automation optical analysis of semiconductor crystal wafer 290.The method of visual inspection can adopt the equipment of such as scanning electron microscopy, high-strength light or ultraviolet light or metallomicroscope.For comprise warpage, varied in thickness, surface particle, irregular, crack, delamination and variable color architectural characteristic semiconductor crystal wafer 290 is checked.
Active parts in semiconductor element 294 and passive component stand the test in wafer scale for electric property and circuit function.Probe or other testing apparatus is used to test each semiconductor element 294 for functional and electric parameter.Probe is used on each semiconductor element 294, reach electrical contact with node or contact pad 314 and provide electric stimulation to contact pad.Semiconductor element 294 is in response to electric stimulation, and this electrically stimulates measured and carry out the functional of measuring semiconductor tube core compared with the response of expection.Electric test can comprise circuit functionality, the integrality of lead-in wire, resistivity, continuity, reliability, the degree of depth of knot, ESD, RF performance, drive current, threshold current, leakage current and the operating parameter specific to unit type.The inspection of semiconductor crystal wafer 290 and electric test make qualified semiconductor element 294 can be designated as the KGD used in semiconductor packages.
In Figure 13 c, saw blade or laser cutting tool 322 is used through saw street 296, semiconductor crystal wafer 290 to be partitioned into other semiconductor element 294 with edge, sidewall or side surface 324.Similarly, use saw blade or laser cutting tool 322, through saw street 306, the semiconductor crystal wafer 300 from Figure 13 a is partitioned into other semiconductor element 304.Can check other semiconductor element 294 and 304 individual and electric test for the identification of the KGD after splitting.
Figure 13 d illustrate containing sacrificial substrate material such as silicon, polymer, beryllium oxide, glass or other the suitable low cost for support structure, the viewgraph of cross-section of the firm carrier of material or the part of temporary substrates 330.Boundary layer or two-sided tape 332 are formed on carrier 330 above as temporary adhesive bonding film, etching stop layer or Thermal release layer.
Carrier 330 is the standardized carriers of the capacity had for multiple semiconductor element, and can hold the semiconductor element of the multiple sizes split from the semiconductor crystal wafer with any diameter.Such as, carrier 330 can be the circular panel of the diameter with 305 mm or larger, can be maybe the rectangular panel with the length of 300 mm or larger and the width of 300 mm or larger.Carrier 330 can have the surface area larger than the surface area of semiconductor crystal wafer 290 or 300.In one embodiment, semiconductor crystal wafer 290 has the semiconductor element 294 of the diameter of 300 mm and the width containing the length and 10 mm with 10 mm.In one embodiment, semiconductor crystal wafer 300 has the semiconductor 304 of the diameter of 200 mm and the width containing the length and 5 mm with 5 mm.Carrier 330 can hold both semiconductor elements 304 of semiconductor element 294 and 5 mm × 5 mm of 10 mm × 10 mm.Carrier 330 loads the semiconductor element 304 of 5 mm × 5 mm of quantity larger than the quantity of the semiconductor element 294 of 10 mm × 10 mm.In another embodiment, semiconductor element 294 and 304 has identical size.Carrier 330 is standardized with the semiconductor element holding any size in size and profile.Larger carrier reduces the manufacturing cost of semiconductor packages, because can process more semiconductor element on larger carrier, thus reduces the cost of each unit.
Size for just processed carrier and semiconductor element designs and configuring semiconductor encapsulation and treatment facility.In order to reduce manufacturing cost further, independent of semiconductor element 294 or 304 size and select the size of carrier 330 independent of the size of semiconductor crystal wafer 290 and 300.That is exactly that carrier 330 has fixing or standardized size, and it can hold the semiconductor element 294 and 304 of the various sizes of segmentation from one or more semiconductor crystal wafer 290 or 300.In one embodiment, carrier 330 is circle or circles of the diameter with 330 mm.In another embodiment, carrier 330 is the rectangles with the width of 560 mm and the length of 600 mm.
In size and the size of the carrier (carrier 330) of the during the design choice criteria for the treatment of facility, so that all rear ends semiconductor manufacturing developed for semiconductor device is unified manufacture line.No matter want size and the type of manufactured semiconductor packages, carrier 330 remains unchanged dimensionally.Such as, semiconductor element 294 can have the size of 10 mm × 10 mm, and is placed on standardized carrier 330.Alternatively, semiconductor element 294 can have the size of 20 mm × 20 mm, and is placed on identical standardized carrier 330.Therefore, standardized carrier 330 can dispose the semiconductor element 294 and 304 of any size, and it allows the carrier for sharing to carry out standardization semiconductor processing equipment subsequently, namely independent of the size of tube core or the wafer size of introducing.Can for the carrier design of standard and configuring semiconductor sealed in unit, the carrier of this standard uses a set of handling implement, equipment and the bill of materials shared to process the size of any semiconductor element of the wafer size from any introducing.Share or standardized carrier 330 reduces manufacturing cost and financial risks by the needs reduced or eliminated for the special semiconductor processes line of the wafer size based on die-size or introducing.By selecting the size of the carrier of pre-determining for the semiconductor element from any size of all semiconductor crystal wafers, can implement to manufacture line flexibly.
In Figure 13 e, such as when insulating barrier 316 be oriented to towards carrier 330 use pickup and place operation the semiconductor element 294 from Figure 13 c is installed to carrier 330 and boundary layer 332.Semiconductor element 294 is installed to the boundary layer 332 of carrier 330 to form wafer 336 that is that reconstruct or that configure again.In one embodiment, insulating barrier 316 is embedded at boundary layer 332.Such as, the active surface 312 of semiconductor element 294 can be coplanar with the surface 334 of boundary layer 332.In another embodiment, on boundary layer 332, installing insulating layer 316 makes the active surface 312 of semiconductor element 294 offset with boundary layer 332.
The wafer of reconstruct or the panel 336 of reconstruct can be processed to be eurypalynous semiconductor packages perhaps, its comprise fan-in WLCSP, reconstruct or eWLCSP, fan-out WLCSP, Flip-Chip Using, 3D encapsulation, such as PoP or other semiconductor packages.The panel 336 of reconstruct is configured according to the explanation of the semiconductor packages obtained.In one embodiment, semiconductor element 294 is placed on carrier 330, for the treatment of fan-in device with highdensity layout (namely separating 300 μm or less).The semiconductor element 294 be separated by the gap between semiconductor element 294 or distance D is placed on carrier 330.Based on the semiconductor packages that will be processed design and the distance D selecting between semiconductor element 294 is described.In one embodiment, the distance D between semiconductor element 294 is 50 μm or less.In another embodiment, the distance D between semiconductor element 294 is 100 μm or less.Distance D between semiconductor element 294 on carrier 330 is optimized for minimum unit cost to manufacture semiconductor packages.
Figure 13 f illustrates the plan view of the panel 336 of the reconstruct with the semiconductor element 294 being installed to carrier 330 or arrange on carrier 330.Carrier 330 is standardized profile and size, and thus forms standardized carrier.Carrier 330 has the capacity of the semiconductor chip for various sizes and quantity, and this semiconductor chip is divided from the semiconductor crystal wafer of various sizes.In one embodiment, carrier 330 is rectangle in shape, and has the length L1 of width W 1 and 600 mm of 560 mm.In another embodiment, carrier 330 is rectangle in shape, and has the length L1 of width W 1 and 330 mm of 330 mm.In another embodiment, carrier 330 is circular in shape, and has the diameter of 330 mm.
The number of the semiconductor element 294 arranged on carrier 330 depends on the distance D between the size of the semiconductor element 294 in the structure of the panel 336 of reconstruct and semiconductor element 294.The number being installed to the semiconductor element 294 of carrier 330 can be greater than, be less than or equal to the number of the semiconductor element 294 of segmentation from semiconductor crystal wafer 290.More the carrier 330 of high surface area holds more semiconductor element 294 and reduces manufacturing cost, because the panel 336 of each reconstruct processes more semiconductor element 294.In one example, semiconductor crystal wafer 290 has the diameter of 300 mm, and the semiconductor element 294 that wherein quantity is approximately other 10 mm × 10 mm of 600 is formed on semiconductor crystal wafer 290.From one or more semiconductor crystal wafer 290, semiconductor element 294 is split.Such as prepare the carrier 330 with the length L1 of the standard of width W 1 and 600 mm of the standard of 560 mm.The width W 1 that the carrier 330 with the width W 1 of 560 mm is resized to stride across carrier 330 is held quantity and is approximately 54 semiconductor elements 294, and semiconductor element 294 has 10 mm × 10 mm sizes and is spaced apart the distance D of 200 μm.The length L1 that the carrier 330 with the length L1 of 600 mm is resized to stride across carrier 330 holds quantity and is approximately 58 semiconductor elements 294, and semiconductor element 294 has the size of 10 mm × 10 mm and is spaced apart the distance D of 200 μm.Therefore, the surface area (width W 1 is multiplied by length L1) of carrier 330 holds quantity and is approximately 3000 semiconductor elements 294, and semiconductor element 294 has the size of 10 mm × 10 mm and the gap between semiconductor element 294 or distance D are 200 μm.Can between semiconductor element 294 be less than gap or the distance D of 200 μm semiconductor element 294 is placed on carrier 330, to increase the density of semiconductor element 294 and reduce further the cost of process semiconductor element 294 on carrier 330.
Automation pickup and place apparatus are used to prepare the quantity of based semiconductor tube core 294 and size and based on the panel 336 of the reconstruct of the size of carrier 330.Such as, the semiconductor element 294 with the size of 10 mm × 10 mm is selected.Such as, carrier 330 has the size of the standard of 560 mm width W 1 and 600 mm length L1.Utilize large young pathbreaker's automation equipment programming of semiconductor element 294 and carrier 330 so that the panel 336 of process reconstruct.After being split by semiconductor crystal wafer 290, automation pickup and place apparatus select the first semiconductor element 294.In by the position in programmable automation pickup and the determined carrier 330 of place apparatus, the first semiconductor element 294 is installed to carrier 330.Second semiconductor element 294 is automated pickup and place apparatus selection, and is placed on carrier 330 and on carrier 330 and is placed in the first row.Distance D between contiguous semiconductor element 294 is programmed in automation pickup and place apparatus, and is selected based on the design and illustrating of the semiconductor packages that will be processed.In one embodiment, the gap between the semiconductor element 294 of the vicinity on carrier 330 or distance D are 200 μm.Be automated pickup and place apparatus of 3rd semiconductor element 294 is selected, and to be placed on carrier 330 and on carrier 330 being that the distance D of 200 μm is placed in the first row from the semiconductor element 294 be close to.Pickup and placement operation are repeated until approximate 54 semiconductor elements 294 of the first row are set to the width W 1 striding across carrier 330.
Be automated pickup and place apparatus of another semiconductor element 294 is selected, and is placed in the second row being placed on carrier 330 and on carrier 330 and being close to the first row.Distance D between the row of the vicinity of semiconductor element 294 is by preselected and be programmed in automation pickup and place apparatus.In one embodiment, the distance D between the first row of semiconductor element 294 and the second row of semiconductor element 294 is 200 μm.Pickup and placement operation are repeated until the semiconductor element 294 of approximate 58 row is set to the length L1 striding across carrier 330.The semiconductor element 294 that standardized carrier (having the carrier 330 of 560 mm width W 1 and 600 mm length L1) holds 10 mm × 10 mm of approximate 54 row and 58 row is approximately 3000 semiconductor elements 294 to arrange total quantity on carrier 330.Pickup and placement operation are repeated until carrier 330 utilizes semiconductor element 294 partially or even wholly to be filled.Utilize the standardized carrier of such as carrier 330, automation pickup and place apparatus can install the semiconductor element 294 of any size to form the panel 336 of reconstruct on carrier 330.Can use for standardized carrier 330 standardized back-end processing equipment come with reprocessing reconstruct panel 336.
Figure 13 g illustrates the plan view of the wafer of the reconstruct with the semiconductor element 304 being installed to carrier 330 or arrange on carrier 330 or the panel 338 of reconstruct.Identical standardized carrier 330 or the standardized carrier with the size identical with carrier 330 are used to process the panel 338 reconstructed, the panel 336 processing reconstruct as being used to.Carrier 330 can support the semiconductor element of any configuration on the wafer of reconstruct or panel.The number of the semiconductor element 304 arranged on carrier 330 depends on the distance D1 between the size of the semiconductor element 304 in the structure of the panel 338 of reconstruct and semiconductor element 304.The number being installed to the semiconductor element 304 of carrier 330 can be greater than, be less than or equal to the number of the semiconductor element 304 of segmentation from semiconductor crystal wafer 300.The carrier 330 of larger surface area holds more semiconductor element 304 and reduces manufacturing cost, because the panel 338 of each reconstruct processes more semiconductor element 304.
In one example, semiconductor crystal wafer 300 has the diameter of 200 mm, and the semiconductor element 304 that wherein quantity is approximately indivedual 5 mm × 5 mm of 1000 is formed on semiconductor crystal wafer 300.From one or more semiconductor crystal wafer 300, semiconductor element 304 is split.Such as prepare the carrier 330 with the length L1 of the standard of width W 1 and 600 mm of the standard of 560 mm.The width W 1 that the carrier 330 with the width W 1 of 560 mm is resized to stride across carrier 330 is held quantity and is approximately 107 semiconductor elements 304, and wherein semiconductor element 304 has the size of 5 mm × 5 mm and is spaced apart the distance D1 of 200 μm.The length L1 that the carrier 330 with the length L1 of 600 mm is resized to stride across carrier 330 holds quantity and is approximately 115 semiconductor elements 304, and wherein semiconductor element 304 has the size of 5 mm × 5 mm and is spaced apart the distance D1 of 200 μm.Therefore, the surface area (width W 1 is multiplied by length L1) of carrier 330 holds approximate 12000 sizes with 5 mm × 5 mm and is spaced apart the semiconductor element 304 of distance D1 of 200 μm.Can between semiconductor element 304 be less than gap or the distance D1 of 200 μm semiconductor element 304 is placed on carrier 330, to increase the density of semiconductor element 304 and reduce further the cost of process semiconductor element 304 on carrier 330.
Automation pickup and place apparatus are used to prepare the quantity of based semiconductor tube core 304 and size and based on the panel 338 of the reconstruct of the size of carrier 330.Such as, the semiconductor element 304 with the size of 5 mm × 5 mm is selected.Such as, carrier 330 has the size of the standard of 560 mm width W 1 and 600 mm length L1.Utilize large young pathbreaker's automation equipment programming of semiconductor element 304 and carrier 330 so that the panel 338 of process reconstruct.After being split by semiconductor crystal wafer 300, automation pickup and place apparatus select the first semiconductor element 304.In by the position in programmable automation pickup and the determined carrier 330 of place apparatus, the first semiconductor element 304 is installed to carrier 330.Second semiconductor element 304 is automated pickup and place apparatus selection, and to be placed on carrier 330 and on carrier 330 to be placed in the first row from the first semiconductor element 304 apart from D1.Distance D1 between contiguous semiconductor element 304 is programmed in automation pickup and place apparatus, and selects based on the design and illustrating of the semiconductor packages that will be processed.In one embodiment, the gap between the semiconductor element 304 of the vicinity on carrier 330 or distance D1 are 200 μm.3rd semiconductor element 304 is automated pickup and place apparatus selection, and is placed on carrier 330 and on carrier 330 and is placed in the first row.Pickup and placement operation are repeated until the row of approximate 107 semiconductor elements 304 is set to the width W 1 striding across carrier 330.
Be automated pickup and place apparatus of another semiconductor element 304 is selected, and to be placed on carrier 330 and to be placed on carrier 330 in the second row be close to the first row.Distance D1 between the row of the vicinity of semiconductor element 304 is by preselected and be programmed in automation pickup and place apparatus.In one embodiment, the distance D1 between the first row of semiconductor element 304 and the second row of semiconductor element 304 is 200 μm.Pickup and placement operation are repeated until the semiconductor element 304 of approximate 115 row is set to the length L1 striding across carrier 330.Be approximately 12000 semiconductor elements 304 for the total quantity arranged on carrier 330, standardized carrier (having the carrier 330 of 560 mm width W 1 and 600 mm length L1) holds the semiconductor element 304 of 5 mm × 5 mm of approximate 107 row and 115 row.Pickup and placement operation are repeated until carrier 330 utilizes semiconductor element 304 partially or even wholly to be filled.Utilize the standardized carrier of such as carrier 330, automation pickup and place apparatus can install the semiconductor element of any size to form the panel 338 of reconstruct on carrier 330.Identical carrier 330 can be used to process the panel 338 of reconstruct with identical back-end processing equipment (processing the panel 336 of reconstruct as being used to).
Panel 336 from the reconstruct of Figure 13 f and the panel 338 from the reconstruct of Figure 13 g both use identical carrier 330 or use the panel 336 and 338 both of carrier for reconstructing with the size of same standardized.It is standardized for the treatment facility designed by the wafer of reconstruct or the back-end processing of panel for carrier 330 and the semiconductor element of any size that can process the wafer of the reconstruct of any configuration formed on carrier 330 or panel and place on carrier 330.Because both panels 336 and 338 of reconstruct use identical standardized carrier 330, so can process the panel of reconstruct on identical manufacture line.Therefore, the object of standardized carrier 330 is reduced to the equipment manufactured needed for semiconductor packages.
In another example, the panel 338 of reconstruct comprises semiconductor element 294 and 304, and wherein each semiconductor element 294 and 304 has identical size, and this semiconductor element derives from the semiconductor crystal wafer 290 and 300 with different-diameter.Semiconductor crystal wafer 290 has the diameter of 450 mm, and the semiconductor element 294 that wherein quantity is approximately other 8 mm × 8 mm of 2200 is formed on semiconductor crystal wafer 290.From one or more semiconductor crystal wafer 290, the semiconductor element 294 of the size with 8 mm × 8 mm is split.Alternatively, semiconductor crystal wafer 300 has the diameter of 300 mm, and the semiconductor element 304 that wherein quantity is approximately other 8 mm × 8 mm of 900 is formed on semiconductor crystal wafer 300.From one or more semiconductor crystal wafer 300, the semiconductor element 304 of the size with 8 mm × 8 mm is split.Such as prepare the carrier 330 with the length L1 of the standard of width W 1 and 600 mm of the standard of 560 mm.The width W 1 that the carrier 330 with the width W 1 of 560 mm is resized to stride across carrier 330 is held quantity and is approximately 69 semiconductor elements 294 or 304, and semiconductor element 294 or 304 has the size of 8 mm × 8 mm and is spaced apart distance D or the D1 of 100 μm.The length L1 that the carrier 330 with the length L1 of 560 mm is resized to stride across carrier 330 holds quantity and is approximately 74 semiconductor elements 294 or 304, and semiconductor element 294 or 304 has the size of 8 mm × 8 mm and is spaced apart distance D or the D1 of 100 μm.The surface area (width W 1 is multiplied by length L1) of carrier 330 holds the size with 8 mm × 8 mm and the distance D of spaced apart 100 μm or the semiconductor element 294 or 304 of D1 of approximate 5000.Semiconductor element 294 and 304 can be placed on carrier 330 with the gap between the semiconductor element 294 or 304 being less than 100 μm or distance D or D1, to increase the density of semiconductor element 294 and 304 and reduce the cost of process semiconductor element 294 and 304 further on carrier 330.
Automation pickup and place apparatus are used to prepare the quantity of based semiconductor tube core 294 and 304 and size and based on the panel 338 of the reconstruct of the size of carrier 330.After being split by semiconductor crystal wafer 300, automation pickup and place apparatus select the first semiconductor element 294 or 304.The semiconductor element 294 or 304 of 8 mm × 8 mm can derive from the semiconductor crystal wafer 290 of the diameter with 450 mm, or derives from the semiconductor crystal wafer 300 of the diameter with 300 mm.Alternatively, the semiconductor element of 8 mm × 8 mm derives from another semiconductor crystal wafer with different-diameter.In by the position in programmable automation pickup and the determined carrier 330 of place apparatus, the first semiconductor element 294 or 304 is installed to carrier 330.Second semiconductor element 294 or 304 is automated and picks up and place apparatus selection, is placed on carrier 330 and on carrier 330 and is placed in the first row.Distance D between contiguous semiconductor element 294 or 304 or D1 is programmed in automation pickup and place apparatus, and selects based on the design of the semiconductor packages that will be processed and explanation.In one embodiment, the gap between the semiconductor element 294 or 304 of the vicinity on carrier 330 or distance D or D1 are 100 μm.Pickup and placement operation are repeated until the row of approximate 69 semiconductor elements 294 or 304 is set to the width W 1 striding across carrier 330.
Another semiconductor element 294 or 304 is automated and picks up and place apparatus selection, is placed on carrier 330 and on carrier 330 and is placed in the second row contiguous with the first row.In one embodiment, the distance D between the first row of semiconductor element 294 or 304 and the second row of semiconductor element 294 or 304 or D1 is 100 μm.Pickup and placement operation are repeated until the semiconductor element 294 or 304 of approximate 74 row is set to the length L1 striding across carrier 330.Standardized carrier (having the carrier 330 of 560 mm width W 1 and 600 mm length L1) holds the semiconductor element 294 and 304 of 8 mm × 8 mm of approximate 69 row and 74 row to arrange the semiconductor element 294 that total quantity is approximately 5000 on carrier 330.Pickup and placement operation are repeated until carrier 330 utilizes semiconductor element 294 or 304 partially or even wholly to be filled.So the panel 338 of reconstruct can comprise the semiconductor element 294 and 304 split from the semiconductor crystal wafer of any size.The size of carrier 330 independent of the size of semiconductor element 294 and 304, and independent of the size of semiconductor crystal wafer 290 and 300.Identical carrier 330 can be used to process the panel 338 of reconstruct with identical back-end processing equipment (processing the panel 336 of reconstruct as being used to).For the wafer of reconstruct or the panel with the same size semiconductor element split from the wafer of the introducing of different size, standardized carrier 330 allows identical material to be used to wafer or the panel of each reconstruct.So the bill of materials for the panel 336 or 338 of the reconstruct on carrier 330 remains unchanged.One makes peace the permission of the predictable bill of materials to the cost analysis of the improvement of semiconductor packages and plan.
In another embodiment, the size of panel 338 containing the various semiconductor elements arranged on carrier 330 of reconstruct.Such as, the semiconductor element 294 of 10 mm × 10 mm is installed to carrier 330, and the semiconductor element 304 of 5 mm × 5 mm is installed to carrier 330 to form the panel 338 of reconstruct.The semiconductor element of panel containing multiple size on the panel of identical reconstruct of reconstruct.In other words, the part of the panel 338 of reconstruct contains the semiconductor element of a size, and another part of the panel of reconstruct contains the semiconductor element of another size.Identical back-end processing equipment (processing the panel 336 of another reconstruct of the semiconductor element with the uniform sizes arranged on carrier 330 as being used to) is used to process the panel 338 of the reconstruct of the semiconductor element 294 and 304 simultaneously containing different size on carrier 330.
In a word, carrier 330 has the capacity of the semiconductor element for various sizes and quantity, and this semiconductor element is divided from the semiconductor crystal wafer of various sizes.The size of carrier 330 does not change along with the size of just processed semiconductor element.Standardized carrier (carrier 330) is fixing dimensionally and can holds the semiconductor element of multiple size.The size of standardized carrier 330 is independent of the size of semiconductor element or semiconductor crystal wafer.On carrier 330, semiconductor element more little compared with larger semiconductor element can be installed.The number of the semiconductor element 294 or 304 that carrier 330 is installed changes along with the interval between the size of semiconductor element 294 or 304 and semiconductor element 294 or 304 or distance D or D1.Such as, the carrier 330 with length L1 and width W 1 holds the semiconductor element 304 of number more 5 mm × 5 mm on the surface area of carrier 330 of big figure than the semiconductor element 294 of 10 mm × 10 mm on the surface area of carrier 330.Such as, carrier 330 holds the semiconductor element of approximate 3000 10 mm × 10 mm or the semiconductor element of approximate 12000 5 mm × 5 mm.The size of carrier 330 and profile keep fixing and independent of the size of semiconductor element 294 or 304 or the size from the semiconductor crystal wafer 290 or 300 wherein split by semiconductor element 294 or 304.Carrier 330 provides the flexibility using a set for the treatment of facility shared the panel 336 and 338 of reconstruct to be created many dissimilar semiconductor packages, and this semiconductor packages has the semiconductor element 294 and 304 of the different size of the semiconductor crystal wafer 290 and 300 from different size.
Figure 13 h illustrates and uses carrier 330 to manufacture the technique of semiconductor packages.Treatment facility 340 is used to perform back end fabrication on a semiconductor die, the deposit of such as sealant and insulating barrier, the deposit of conductive layer, producing lug (bumping), backflow, mark, segmentation and other backend process.Design treatment equipment 340 is carried out for the size of standardized carrier (such as carrier 330) and profile.Treatment facility 340 is compatible with carrier 330, because come the machinery of customized treatment equipment 340 and electric parts for the standardized size of carrier 330 and profile.
Control treatment equipment 340 is carried out by control system 342.Control system 342 can be used to the software program or the algorithm that carry out configuration process equipment 340 according to the size of the semiconductor element on carrier 330 and profile.Programming and custom control system 342 so that treatment facility 340 to dispose on standardized carrier 330 wafer or the panel of each different reconstruct of formation, the panel 336 and 338 such as reconstructed.
By the size of standardized carrier 330, treatment facility 340 can remain unchanged because the size of carrier 330 not along with semi-conductor die size and semiconductor die size variable and change.Control system 342 uses various algorithm for the panel of each reconstruct on carrier 330.Such as, control system 342 can be used to the interval optimizing the semiconductor element 294 on carrier 330 during the operation of initial pickup and placement.The explanation of the panel 336 of reconstruct is input in control system 342.Control system 342 is programmed and picks up other semiconductor element 294 with control treatment equipment 340 and semiconductor element 294 is placed on carrier 330 to form the panel 336 reconstructed with the interval of distance D.Such as, the panel 336 of reconstruct comprises the semiconductor element 294 of 10 mm × 10 mm and the carrier 330 of normal size (width W 1 and length L1).Utilize control system 342 to carry out configuration process equipment 340 to perform backend process on the panel 336 of reconstruct, the panel 336 of described reconstruct is on carrier 330.Control system 342 performs deposit and other manufacturing step according to the semiconductor element 294 of 10 mm × 10 mm sizes and standard-sized carrier 330 guidance of faulf handling equipment 340.
Control system 342 allows to carry out customized treatment equipment 340 for the wafer of each reconstruct on standardized carrier 330 or panel.The semiconductor element for different size is not needed to carry out reconstruction process equipment 340.After the panel 336 of process reconstruct, treatment facility 340 gets out to process panel of another reconstruct at the size with identical or different semiconductor element on carrier 330 and interval.The explanation of the panel 338 of reconstruct is imported in control system 342.Control system 342 is programmed and picks up other semiconductor element 304 with control treatment equipment 340 and semiconductor element 304 is placed on carrier 330 to form the panel 338 reconstructed with the interval of distance D1.Such as, the panel 338 of reconstruct comprises the semiconductor element 304 of 5 mm × 5 mm and the carrier 330 of normal size (width W 1 and length L1).Utilize control system 342 to carry out configuration process equipment 340 to perform backend process on the panel 338 of reconstruct, the panel 338 of described reconstruct is on carrier 330.Control system 342 performs deposit and other manufacturing step according to the semiconductor element 304 of 5 mm × 5 mm sizes and standard-sized carrier 330 guidance of faulf handling equipment 340.
Regardless of panel 336 or 338 or other reconstruction panel of the reconstruct for the treatment of facility 340 just on the carrier 330 of cleanup standard, treatment facility 340 remains unchanged.Control system 342 is programmable and treatment facility 340 easily can be adapted to the wafer of any reconstruct or the panel that use carrier 330.So, the machinery of design treatment equipment 340 and the characteristic of physics hold the characteristic of the physics of standardized carrier 330, and treatment facility 340 utilizes control system 342 to be also programmable with the semiconductor element execution manufacturing process to any configuration on carrier 330 simultaneously.
Treatment facility 340 is used to manufacture various semiconductor packages from the wafer of the reconstruct carrier 330 or panel.Such as, treatment facility 340 can be used to the panel 336 or 338 of reconstruct to be treated as fan-in WLCSP, reconstruct or eWLCSP, fan-out WLCSP, Flip-Chip Using, 3D encapsulation, such as PoP or other semiconductor packages.Control system 342 is used to revise and the operation of control treatment equipment 340 will be performed the manufacturing step of rear end with basis by the semiconductor packages of producing.So treatment facility 340 can be used to manufacture each semiconductor packages described herein.Multiple manufacturing lines of the carrier 330 of shared same size can be striden across to use treatment facility 340.Therefore, it is possible to reduce the cost be associated with the change of the change of the size of semiconductor element, the change of the size of semiconductor crystal wafer and the type of semiconductor packages.Investment risk in treatment facility 340 is reduced, because simplify the design for the treatment of facility 340 under carrier 330 is standardized situation.
In Figure 13 i, use that cream printing, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 344 on semiconductor element 294 and carrier 330.Sealant 344 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 344 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.In another embodiment, sealant 344 is insulating barrier or dielectric layer, it contains use printing, rotary coating, spray application, there is or not have the dielectric resist that the vacuum of heating or pressure lamination or other suitable technique carry out the photosensitive low curing temperature of one or more layers of deposit, photosensitive compound resist, lamination compound film, there is the insulating paste of filler, solder mask resist film, liquid or granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg or there is other dielectric substance of similar insulating property (properties) and structural property.In one embodiment, sealant 344 is low-temperature setting photosensitive dielectrics polymer, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.
Especially, sealant 344 is set to the side surface 324 along semiconductor element 294, and therefore covers each side surface 324 of semiconductor element 294.Therefore, sealant 344 covers or at least four surfaces of contact semiconductor tube core 294, i.e. four side surfaces 324 of semiconductor element 294.Sealant 344 also covers the backside surface 310 of semiconductor element 294.Sealant 344 protects semiconductor element 294 to avoid owing to being exposed to the degeneration produced from light or other photon launched.In one embodiment, sealant 344 is opaque, and is dark-coloured in color or black.Figure 13 i illustrates the panel 336 of the compound substrate that sealant 344 covers or reconstruct.Sealant 344 can be used to the panel 336 of laser labelling reconstruct to carry out aiming at and splitting.Sealant 344 is formed on the backside surface 310 of semiconductor element 294, and can be thinned in back face grinding step subsequently.Sealant 344 can also be deposited, make sealant and backside surface 310 coplanar and do not cover backside surface.
In Figure 13 j, the back surface 346 of sealant 344 stands to utilize the grinding operation of grinder 345 with complanation and the thickness reducing sealant 344.Chemical etching can also be used to remove and complanation sealant 344 and form the back surface 347 of plane.In one embodiment, the thickness of sealant 344 maintains covering on the backside surface 310 of semiconductor element 294.In one embodiment, above the backside surface 310 of the semiconductor element 294 after deposit or grinding back surface, the thickness range of remaining sealant 344 is approximate 170-230 μm or less.In another embodiment, on the backside surface 310 of semiconductor element 294, the thickness range of remaining sealant 344 is approximate 5-150 μm.The surface 348 of the sealant 344 relative with back surface 346 is arranged on above carrier 330 and boundary layer 332 so that the surface 348 of sealant 344 can be coplanar with the active surface 312 of semiconductor element 294.
Figure 13 k illustrates the step of the grinding back surface substituted, and wherein sealant 344 is fully removed from the backside surface 310 of semiconductor element 294.After grinding operation in Figure 13 k is done, expose the backside surface 310 of semiconductor element 294.By grinding operation, the thickness of semiconductor element 294 can also be reduced.In one embodiment, semiconductor element 294 has 225-305 μm or less thickness.
In Figure 13 l, after the back face grinding step in Figure 13 k completes, on the sealant 344 of semiconductor element 294 and backside surface 310, form insulation or passivation layer 349.Insulating barrier 349 contains the dielectric resist of the photosensitive low curing temperature of one or more layers, photosensitive compound resist, lamination compound film, the insulating paste with filler, solder mask resist film, liquid molding compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg or has other dielectric substance of similar insulating property (properties) and structural property.Printing, rotary coating, spray application, the vacuum or do not have with heating or pressure lamination or other suitable technique is used to carry out deposition insulating layer 349.In one embodiment, insulating barrier 349 is low-temperature setting photosensitive dielectrics polymer, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.Insulating barrier 349 is back side protection layer and provides mechanical protection and from the impact of light for semiconductor element 294.In one embodiment, insulating barrier 349 has the thickness that scope is approximate 5-150 μm.
, ultraviolet light roasting by chemical etching, mechanical stripping, CMP, mechanical lapping, heat, laser scanning or wet stripping remove carrier 330 and boundary layer 332, to expose the surface 348 of insulating barrier 316, conductive layer 314 and sealant 344.
In Figure 13 m, use PVD, CVD, printing, rotary coating, spray application, silk screen printing or be laminated to formation insulation or passivation layer 350 above insulating barrier 316 and conductive layer 314.Insulating barrier 350 can be SiO2, Si3N4, SiON, Ta2O5, Al2O3 of one or more layers or have other material of similar insulating property (properties) and structural property.In one embodiment, insulating barrier 350 is being less than 200 ° of C and bends down the photosensitive dielectrics polymer of solidification.In one embodiment, insulating barrier 350 be formed on semiconductor element 294 area occupied in and do not extend beyond the area occupied of semiconductor element 294 and not extension on the surface 348 of sealant 344.In other words, the perimeter region of contiguous with semiconductor element 294 semiconductor element 294 lacks insulating barrier 350.In another embodiment, insulating barrier 350 is formed on above the surface 348 of insulating barrier 316, semiconductor element 294 and sealant 344, and the etching technics of the photoresist oxidant layer of the part by utilizing patterning of insulating barrier 350 above the surface 348 of sealant 344 or be removed by LDA.By utilizing the etching technics of the photoresist oxidant layer of patterning or being removed the part of insulating barrier 350 by LDA, to form the opening 352 exposing conductive layer 314.
In Figure 13 n, such as printing, PVD, CVD, sputtering, the patterning of metallide and chemical plating and metal deposition process is used to form conductive layer 354 on insulating barrier 350 and conductive layer 314.Conductive layer 354 can be Al, Cu, Sn, Ti, Ni, Au, Ag, W or other suitable electric conducting material of one or more layers.The part of conductive layer 354 extends laterally distribute and the electric interconnection of conductive layer 314 again along insulating barrier 350 and with the active surface 312 parallel water level land of semiconductor element 294.Conductive layer 354 is operating as the RDL of the electric signal for semiconductor element 294.Do not extend beyond the area occupied of semiconductor element 294 or do not extend on the surface 348 of sealant 344 above the area occupied that conductive layer 354 is formed on semiconductor element 294.In other words, the perimeter region of the semiconductor element 294 contiguous with semiconductor element 294 lacks conductive layer 354, so that the surface 348 of sealant 344 keeps exposing from conductive layer 354.The part of conductive layer 354 is electrically connected to conductive layer 314.The connectivity that the other parts of conductive layer 354 depend on semiconductor element 294 electrically shares or is electrically isolated.
Use PVD, CVD, printing, rotary coating, spray application, silk screen printing or be laminated to above insulating barrier 350 and conductive layer 354 and form insulation or passivation layer 356.Insulating barrier 356 can be SiO2, Si3N4, SiON, Ta2O5, Al2O3 of one or more layers or have other material of similar insulating property (properties) and structural property.In one embodiment, insulating barrier 356 is being less than 200 ° of C and bends down the photosensitive dielectrics polymer of solidification.In one embodiment, insulating barrier 356 be formed on semiconductor element 294 area occupied in and on sealant 344, do not extend beyond the area occupied of semiconductor element 294.In other words, the perimeter region of the semiconductor element 294 contiguous with semiconductor element 294 lacks insulating barrier 356, so that the surface 348 of sealant 344 keeps exposing from insulating barrier 356.In another embodiment, insulating barrier 356 is formed on above insulating barrier 316, semiconductor element 294 and sealant 344, and the etching technics of the photoresist oxidant layer of the part by utilizing patterning of insulating barrier 350 above sealant 344 or be removed by LDA.The etching technics of the photoresist oxidant layer of the part by utilizing patterning of insulating barrier 350 or be removed by LDA, to form the opening 358 exposing conductive layer 354.
In Figure 13 o, after last passivation again, PVD, CVD, evaporation, metallide, chemical plating or other suitable metal deposition process is used to form conductive layer 360 on the part of the exposure of conductive layer 354 and on insulating barrier 356.Conductive layer 360 can be Al, Cu, Sn, Ti, Ni, Au, Ag, W or other suitable electric conducting material.Conductive layer 360 is the UBM being electrically connected to conductive layer 354 and 314.UBM 360 can be have adhesive layer, barrier layer and Seed Layer or wettable layer how metal laminated.Adhesive layer is formed on conductive layer 354 above and can be Ti, TiN, TiW, Al or Cr.Barrier layer to be formed on above adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti or CrCu.Barrier layer forbids that Cu is diffused in the active surface 312 of semiconductor element 294.Seed Layer to be formed on above barrier layer and can be Cu, Ni, NiV, Au or Al.UBM 360 conductive layer 354 provides low resistance interconnect, and for the stop of solder diffusion and the Seed Layer for solder wettable.
Use evaporation, metallide, chemical plating, globule or silk-screen printing technique deposit conductive bump material on conductive layer 360.In one embodiment, utilize globule masterplate deposit bump material, namely do not need mask.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 360.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 362.In some applications, projection 362 is refluxed to improve the electrical contact with conductive layer 360 for the second time.Projection 362 can also be joined to conductive layer 360 by compression engagement or hot compression.Projection 362 represents the interconnection structure of a type that can be formed on conductive layer 360.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.Before projection is formed or after projection is formed, or laser labelling can be performed after removal carrier 330.
Insulating barrier 350 and 356, conductive layer 354 and 360 and projection 362 are jointly formed in above semiconductor element 294 and lamination type (build-up) interconnection structure 366 formed in the area occupied of semiconductor element 294.The perimeter region of the semiconductor element 294 contiguous with semiconductor element 294 lacks interconnection structure 366, so that the surface 348 of sealant 344 keeps exposing from interconnection structure 366.Lamination type interconnection structure 366 can comprise few to a RDL or conductive layer (such as conductive layer 354) and an insulating barrier (such as insulating barrier 350).Before forming projection 362, additional insulating barrier can be formed with RDL on insulating barrier 356 to stride across the electrical connectivity that encapsulation provides additional vertical and level according to the Design and Features of semiconductor element 294.
In Figure 13 p, utilize saw blade or laser cutting tool 370, through sealant 344, semiconductor element 294 is partitioned into other eWLCSP 372.EWLCSP 372 stands electric test before it is split or after segmentation.The panel 336 of reconstruct is partitioned into eWLCSP 372 to leave the thin layer of sealant 344 on the side surface 324 of semiconductor element 294.Alternatively, the panel 336 of reconstruct is divided fully to remove sealant 344 from side surface 324.
Figure 14 segmentation is shown after on sidewall 324, there is sealant and there is the eWLCSP 372 of insulating barrier 349 on the backside surface 310 of semiconductor element 294.Semiconductor element 294 is electrically connected to projection 362 for the external interconnect through interconnection structure 366 through conductive layer 314,354 and 360.Interconnection structure 366 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Dorsal part insulating barrier 349 is formed for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched on the backside surface 310 of semiconductor element 294.
The side surface 324 that sealant 344 covers semiconductor element 294 avoids owing to being exposed to the degeneration produced from light or other photon launched to protect semiconductor element 294.For eWLCSP 372, the thickness of the sealant 344 above side surface 324 is less than 150 μm.In one embodiment, eWLCSP 372 has 4.595 mm(length) × 4.025 mm(width) × 0.470 mm(height) size, wherein the pitch of projection 362 is 0.4 mm, and wherein semiconductor element 294 has the length of 4.445 mm and the width of 3.875 mm.In another embodiment, the thickness of the sealant 344 above the side surface 324 of semiconductor element 294 is 75 μm or less.EWLCSP 372 has 6.075 mm(length) × 6.075 mm(width) × 0.8 mm(height) size, wherein the pitch of projection 362 is 0.5 mm, and wherein semiconductor element 294 has 6.0 mm(length) × 6.0 mm(width) × 0.470 mm(height) size.In yet another embodiment, eWLCSP 372 has 5.92 mm(length) × 5.92 mm(width) × 0.765 mm(height) size, wherein the pitch of projection 362 is 0.5 mm, and wherein semiconductor element 294 has 5.75 mm(length) × 5.75 mm(width) × 0.535 mm(height) size.In another embodiment, the thickness of the sealant 344 above the side surface 324 of semiconductor element 294 is 25 μm or less.In yet another embodiment, the thickness of the sealant 344 above the side surface 324 of semiconductor element 294 is approximate 50 μm or less.On standardized carrier 330, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 372 by using, which reducing the cost of equipment for eWLCSP 372 and material.Use standardized carrier 330 with higher volume to manufacture eWLCSP 372, thus simplified manufacturing technique and reduce unit cost.
Figure 15 illustrates insulating barrier 349 above the backside surface 310 with semiconductor element 294 and has the eWLCSP 380 substituted of the sidewall 324 of the exposure of semiconductor element 294.Semiconductor element 294 is electrically connected to projection 362 for the external interconnect through interconnection structure 366 through conductive layer 314,354 and 360.Interconnection structure 366 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.The backside surface 310 that dorsal part insulating barrier 349 is formed on semiconductor element 294 is above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.During splitting, sealant 344 is removed completely with exposed side surfaces 324 from the side surface 324 of semiconductor element 294.The length of eWLCSP 380 is identical with width with the length of semiconductor element 294 with width.In one embodiment, eWLCSP 380 has approximate 4.4 mm(length) × 3.9 mm(width) size, wherein the pitch of projection 362 is 0.35-0.50 mm.On standardized carrier 330, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 380 by using, which reducing the cost of equipment for eWLCSP 380 and material.Use standardized carrier 330 with higher volume to manufacture eWLCSP 380, thus simplified manufacturing technique and reduce unit cost.
Figure 16 illustrates another eWLCSP 384, wherein on the backside surface 310 and sidewall 324 of semiconductor element 294, forms sealant 344.Semiconductor element 294 is electrically connected to projection 362 for the external interconnect through interconnection structure 366 through conductive layer 314,354 and 360.Interconnection structure 366 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Sealant 344 remains on above the backside surface 310 of semiconductor element 294 after the grinding operation shown in Figure 13 j.Upon splitting, sealant 344 remain on semiconductor element 294 side surface 324 above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.So sealant 344 is formed on above five sides of semiconductor element 294, namely on four side surfaces 324 and overleaf above surface 310.Sealant 344 above the backside surface 310 of semiconductor element 294 eliminates the needs of back side protection layer or stratum dorsale laminate, thus reduces the cost of eWLCSP 384.
For eWLCSP 384, the thickness of the sealant 344 above side surface 324 is less than 150 μm.In one embodiment, eWLCSP 384 has 4.595 mm(length) × 4.025 mm(width) × 0.470 mm(height) size, the pitch of projection 362 is 0.4 mm, and wherein semiconductor element 294 has the length of 4.445 mm and the width of 3.875 mm.In another embodiment, the thickness of the sealant 344 above the side surface 324 of semiconductor element 294 is 75 μm or less.EWLCSP 384 has 6.075 mm(length) × 6.075 mm(width) × 0.8 mm(height) size, wherein the pitch of projection 362 is 0.5 mm, and wherein semiconductor element 294 has 6.0 mm(length) × 6.0 mm(width) × 0.470 mm(height) size.In yet another embodiment, eWLCSP 384 has 5.92 mm(length) × 5.92 mm(width) × 0.765 mm(height) size, wherein the pitch of projection 362 is 0.5 mm, and wherein semiconductor element 294 has 5.75 mm(length) × 5.75 mm(width) × 0.535 mm(height) size.In another embodiment, the thickness of the sealant 344 above the side surface 324 of semiconductor element 294 is 25 μm or less.In yet another embodiment, the thickness of the sealant 344 above the side surface 324 of semiconductor element 294 is approximate 50 μm or less.On standardized carrier 330, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 384 by using, which reducing the cost of equipment for eWLCSP 384 and material.Use standardized carrier 330 with higher volume to manufacture eWLCSP 384, thus simplified manufacturing technique and reduce unit cost.
Figure 17 illustrates another eWLCSP 386 of the sidewall with dorsal part sealant and exposure.Semiconductor element 294 is electrically connected to projection 362 for the external interconnect through interconnection structure 366 through conductive layer 314,354 and 360.Interconnection structure 366 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Sealant 344 remains on above the backside surface 310 of semiconductor element 294 after the grinding operation shown in Figure 13 j.Sealant 344 above the backside surface 310 of semiconductor element 294 eliminates the needs of back side protection layer or stratum dorsale laminate, thus reduces the cost of eWLCSP 386.During splitting, sealant 344 is removed completely with exposed side surfaces 324 from the side surface 324 of semiconductor element 294.The length of eWLCSP 386 is identical with width with the length of semiconductor element 294 with width.In one embodiment, eWLCSP 386 has approximate 4.445 mm(length) × 3.875 mm(width) size, wherein the pitch of projection 362 is 0.35-0.50 mm.On standardized carrier 330, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 386 by using, which reducing the cost of equipment for eWLCSP 386 and material.Use standardized carrier 330 with higher volume to manufacture eWLCSP 386, thus simplified manufacturing technique and reduce unit cost.
Figure 18 illustrates the backside surface 310 of the exposure with semiconductor element 294 and another eWLCSP 388 of sidewall 324.Semiconductor element 294 is electrically connected to projection 362 for the external interconnect through interconnection structure 366 through conductive layer 314,354 and 360.Interconnection structure 366 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Sealant 344 is removed completely during the grinding operation shown in Figure 13 k from the backside surface 310 of semiconductor element 294.From the side surface 324 of semiconductor element 294, sealant 344 is removed completely with exposed side surfaces 324 during splitting.In eWLCSP 388, sealant 344 is not had to keep covering the surface of semiconductor element 294.The length of eWLCSP 388 is identical with width with the length of semiconductor element 294 with width.In one embodiment, eWLCSP 388 has approximate 4.4 mm(length) × 3.9 mm(width) size, wherein the pitch of projection 362 is 0.35-0.50 mm.On standardized carrier 330, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 388 by using, which reducing the cost of equipment for eWLCSP 388 and material.Use standardized carrier 330 with higher volume to manufacture eWLCSP 388, thus simplified manufacturing technique and reduce unit cost.
Figure 19 a-19k illustrates the technique of fan-in WLCSP that is that the formation relevant with Fig. 1 and 2 a-2c reconstructs or that embed.Continue from Figure 13 b, Figure 19 a illustrates the viewgraph of cross-section of the part of semiconductor crystal wafer 290.Conductive layer 314 is formed on the active surface 312 of semiconductor element 294.Insulating barrier 316 is formed on above active surface 312 and conductive layer 314, wherein forms opening to expose conductive layer 314 through insulating barrier 316.
In Figure 19 a, on insulating barrier 316 and conductive layer 314, form insulating barrier 410.Insulating barrier 410 contains SiO2, Si3N4, SiON, Ta2O5, Al2O3 of one or more layers or has other material of similar insulating property (properties) and structural property.Use PVD, CVD, printing, rotary coating, spray application, sintering, thermal oxidation or other suitable technique deposition insulating layer 410.In one embodiment, insulating barrier 410 is being less than 200 ° of C and bends down the photosensitive dielectrics polymer of solidification.In one embodiment, insulating barrier 410 to be formed on above insulating barrier 316, on semiconductor element 294 and beyond the area occupied of semiconductor element 294 on base semiconductor material 292.In other words, the perimeter region of contiguous with semiconductor element 294 semiconductor element 294 comprises insulating barrier 410.The part of insulating barrier 410 is removed to form the opening 412 exposing conductive welding disk 314 by exposure or developing process, LDA, etching or other suitable technique.
In Figure 19 b, such as printing, PVD, CVD, sputtering, the patterning of metallide and chemical plating and metal deposition process is used to form conductive layer 414 on insulating barrier 410 and conductive layer 314.Conductive layer 414 can be Al, Cu, Sn, Ti, Ni, Au, Ag, W or other suitable electric conducting material of one or more layers.The part of conductive layer 414 extends laterally distribute and the electric interconnection of conductive layer 314 again along insulating barrier 410 and with the active surface 312 parallel water level land of semiconductor element 294.Conductive layer 414 is operating as the RDL of the electric signal for semiconductor element 294.The area occupied of semiconductor element 294 is not extended beyond above the area occupied that conductive layer 414 is formed on semiconductor element 294.In other words, the perimeter region of contiguous with semiconductor element 294 semiconductor element 294 lacks conductive layer 414.The part of conductive layer 414 is electrically connected to conductive layer 314.The connectivity that the other parts of conductive layer 414 depend on semiconductor element 294 electrically shares or is electrically isolated.
Use PVD, CVD, printing, rotary coating, spray application, silk screen printing or be laminated to above insulating barrier 410 and conductive layer 414 and form insulation or passivation layer 416.Insulating barrier 416 can be SiO2, Si3N4, SiON, Ta2O5, Al2O3 of one or more layers or have other material of similar insulating property (properties) and structural property.In one embodiment, insulating barrier 416 is being less than 200 ° of C and bends down the photosensitive dielectrics polymer of solidification.In one embodiment, insulating barrier 416 is formed on beyond the area occupied of the semiconductor element 294 of semiconductor element 294 above and on base semiconductor material 292.In another embodiment, insulating barrier 416 be formed on semiconductor element 294 area occupied in and do not extend beyond the area occupied of semiconductor element 294.By the part that utilizes the etching technics of patterning photoresist oxidant layer or removed insulating barrier 416 by LDA to form the opening 418 exposing conductive layer 414.
In Figure 19 c, use saw blade or laser cutting tool 420, through saw street 296, semiconductor crystal wafer 290 is partitioned into other semiconductor element 294.Also through insulating barrier 316, insulating barrier 410 and insulating barrier 416, semiconductor crystal wafer 290 is split to form sidewall or side surface 422.Side surface 422 comprises the side of semiconductor element 294 and insulating barrier 316,410 and 416.Can check other semiconductor element 294 individual and electric test for the identification of the KGD after splitting.
In Figure 19 d, such as when active surface 312 be oriented to towards carrier 430 use pickup and placement operation the semiconductor element 294 from Figure 19 c is installed to carrier 430 and boundary layer 432.Wafer that is that the semiconductor element 294 being installed to the boundary layer 432 of carrier 430 forms reconstruct or that configure again or panel 436.
Carrier 430 can be the circle of the capacity had for multiple semiconductor element 294 or the panel (being greater than 300 mm) of rectangle.Carrier 430 can have the surface area larger than the surface area of semiconductor crystal wafer 290 or 300.Larger carrier reduces the manufacturing cost of semiconductor packages, because can process more semiconductor element on larger carrier, thus reduces the cost of each unit.Size for just processed carrier or wafer designs and configuring semiconductor encapsulation and treatment facility.
In order to reduce manufacturing cost further, select the size of carrier 430 independent of the size of semiconductor element 294 or the size of semiconductor crystal wafer 290 and 300.That is exactly that carrier 430 has fixing or standardized size, and it can hold the semiconductor element 294 of the various sizes of segmentation from one or more semiconductor crystal wafer 290 and 300.In one embodiment, carrier 430 is circles of the diameter with 330 mm.In another embodiment, carrier 430 is the rectangles with the width of 560 mm and the length of 600 mm.Semiconductor element 294 can have the size of 10 mm × 10 mm, and it is placed on standardized carrier 430.Alternatively, semiconductor element 294 can have the size of 20 mm × 20 mm, and it is placed on identical standardized carrier 430.Therefore, standardized carrier 430 can dispose the semiconductor element 294 of any size, and it allows the carrier for sharing to carry out standardization semiconductor processing equipment subsequently, namely independent of the size of tube core or the wafer size of introducing.Can to the carrier design of standard and configuring semiconductor sealed in unit, the carrier of this standard uses a set of handling implement, equipment and the bill of materials shared to process any semi-conductor die size of the wafer size from any introducing.Share or standardized carrier 430 reduces manufacturing cost and financial risks by the needs reduced or eliminated for the special semiconductor processes line of the wafer size based on die-size or introducing.By selecting the carrier dimensions of pre-determining for the semiconductor element from any size of all semiconductor crystal wafers, can implement to manufacture line flexibly.
The wafer of reconstruct or the panel 436 of reconstruct can be processed to be eurypalynous semiconductor packages perhaps, its comprise fan-in WLCSP, reconstruct or eWLCSP, fan-out WLCSP, Flip-Chip Using, 3D encapsulation, such as PoP or other semiconductor packages.The panel 436 of reconstruct is configured according to the explanation of the semiconductor packages obtained.In one embodiment, semiconductor element 294 is placed on carrier 430, for the treatment of fan-in device with highdensity layout (namely separating 300 μm or less).Be placed on carrier 430 with the semiconductor element 294 that the gap between semiconductor element 294 or distance D2 are separated.Based on the semiconductor packages that will be processed design and the distance D2 selecting between semiconductor element 294 is described.In one embodiment, the distance D2 between semiconductor element 294 is 50 μm or less.In another embodiment, the distance D2 between semiconductor element 294 is 100 μm or less.Distance D2 between semiconductor element 294 on carrier 430 is optimized for minimum unit cost to manufacture semiconductor packages.
Figure 19 e illustrates the plan view of the panel 436 of the reconstruct with the semiconductor element 294 be arranged on above carrier 430.Carrier 430 is standardized profile and size, and this carrier 430 has the capacity of the semiconductor chip for various sizes and quantity, and this semiconductor chip is divided from the semiconductor crystal wafer of various sizes.In one embodiment, carrier 430 is rectangle in shape and has the length L2 of width W 2 and 600 mm of 560 mm.The number being installed to the semiconductor element 294 of carrier 430 can be greater than, be less than or equal to the number of the semiconductor element 294 of segmentation from semiconductor crystal wafer 290.The carrier 430 of larger surface area holds more semiconductor element 294 and reduces manufacturing cost, because the panel 436 of each reconstruct processes more semiconductor element 294.
Standardized carrier (carrier 430) is fixing dimensionally and can holds the semiconductor element of multiple size.The size of standardized carrier 430 is independent of the size of semiconductor element or semiconductor crystal wafer.On carrier 430, semiconductor element more little compared with larger semiconductor element can be installed.Such as, carrier 430 holds the tube core of number more 5 mm × 5 mm on the surface area of carrier 430 of big figure than the tube core of 10 mm × 10 mm on the surface area of carrier 430.
Such as, the semiconductor element 294 with the size of 10 mm × 10 mm is placed on carrier 430, and the distance D2 between wherein contiguous semiconductor element 294 is 200 μm.From semiconductor crystal wafer 290, the number of the semiconductor element 294 of segmentation is approximate 600 semiconductor elements, and wherein semiconductor crystal wafer 290 has the diameter of 300 mm.The number of the semiconductor element 294 of 10 mm × 10 mm that can install on carrier 430 is approximate 3000 semiconductor elements.Alternatively, the semiconductor element 294 with the size of 5 mm × 5 mm is placed on carrier 430, and the distance D2 between wherein contiguous semiconductor element 294 is 200 μm.The number of semiconductor element 294 split from semiconductor crystal wafer 290 is approximate 1000 semiconductor elements, and wherein semiconductor crystal wafer 290 has the diameter of 200 mm.The number of the semiconductor element 294 of 5 mm × 5 mm that can install on carrier 430 is approximate 12000 semiconductor elements.
The size of carrier 430 does not change along with the size of just processed semiconductor element.The number of the semiconductor element 294 that carrier 430 is installed changes along with the interval between the size of semiconductor element 294 and semiconductor element 294 or distance D2.The size of carrier 430 and profile keep fixing and independent of the size of semiconductor element 294 or the size from the semiconductor crystal wafer 290 wherein split by semiconductor element 294.The panel 436 of carrier 430 and reconstruct provides use such as manufactures the many dissimilar semiconductor packages of the semiconductor element 294 of the different size of the semiconductor crystal wafer 290 had from different size flexibility from a set for the treatment of facility shared of the treatment facility 340 of Figure 13 h.
In Figure 19 f, use that cream printing, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 438 on semiconductor element 294 and carrier 430.Sealant 438 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 438 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.In another embodiment, sealant 438 is insulating barrier or dielectric layer, it contains use printing, rotary coating, spray application, there is or not have the dielectric resist that the vacuum of heating or pressure lamination or other suitable technique carry out the photosensitive low curing temperature of one or more layers of deposit, photosensitive compound resist, lamination compound film, there is the insulating paste of filler, solder mask resist film, liquid or granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg or there is other dielectric substance of similar insulating property (properties) and structural property.In one embodiment, sealant 438 is the photosensitive dielectrical polymers of low-temperature setting, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.
Especially, sealant 438 is set to the side surface 422 along semiconductor element 294, and therefore covers each side surface 422 of semiconductor element 294 and insulating barrier 316,410 and 416.Therefore, sealant 438 covers or at least four surfaces of contact semiconductor tube core 294, i.e. four side surfaces 422 of semiconductor element 294.Sealant 438 also covers the backside surface 310 of semiconductor element 294.Sealant 438 protects semiconductor element 294 to avoid owing to being exposed to the degeneration produced from light or other photon launched.In one embodiment, sealant 438 is opaque, and is dark-coloured in color or black.Sealant 438 can be used to the panel 436 of laser labelling reconstruct to carry out aiming at and splitting.In another embodiment, sealant 438 is deposited and makes sealant 438 and the backside surface 310 of semiconductor element 294 coplanar and do not cover backside surface 310.
In Figure 19 g, the back surface 440 of sealant 344 stands to utilize the grinding operation of grinder 442 with complanation and the thickness reducing sealant 438.Chemical etching can also be used to remove and complanation sealant 438 and form the back surface 444 of plane.In one embodiment, the thickness of sealant 438 maintains covering on the backside surface 310 of semiconductor element 294.In another embodiment, the backside surface 310 of semiconductor element 294 is exposed overleaf during grinding steps.The thickness of semiconductor element 294 can also be reduced by grinding operation.In one embodiment, semiconductor element 294 has 225-305 μm or less thickness.
Figure 19 h illustrates the panel 436 of the reconstruct that sealant 438 covers.In one embodiment, above the backside surface 310 of the semiconductor element 294 after deposit or grinding back surface, the thickness range of remaining sealant 438 is approximate 170-230 μm or less.In another embodiment, on the backside surface 310 of semiconductor element 294, the thickness range of remaining sealant 438 is approximate 5-150 μm.The surface 448 of the sealant 438 relative with back surface 440 is arranged on above carrier 430 and boundary layer 432.
In Figure 19 i, ultraviolet light roasting by chemical etching, mechanical stripping, CMP, mechanical lapping, heat, laser scanning or wet stripping remove carrier 430 and boundary layer 432, to expose the surface 448 of insulating barrier 416, conductive layer 414 and sealant 438.
In Figure 19 j, after last passivation again, PVD, CVD, evaporation, metallide, chemical plating or other suitable metal deposition process is used to form conductive layer 460 on the part of the exposure of conductive layer 414 and on insulating barrier 416.Conductive layer 460 can be Al, Cu, Sn, Ti, Ni, Au, Ag, W or other suitable electric conducting material.Conductive layer 460 is the UBM being electrically connected to conductive layer 414 and 314.UBM 460 can be have adhesive layer, barrier layer and Seed Layer or wettable layer how metal laminated.Adhesive layer is formed on conductive layer 414 above and can be Ti, TiN, TiW, Al or Cr.Barrier layer to be formed on above adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti or CrCu.Barrier layer forbids that Cu is diffused in the active surface 312 of semiconductor element 294.Seed Layer to be formed on above barrier layer and can be Cu, Ni, NiV, Au or Al.UBM 460 conductive layer 414 provides low resistance interconnect, and for the stop of solder diffusion and the Seed Layer for solder wettable.
Use evaporation, metallide, chemical plating, globule or silk-screen printing technique deposit conductive bump material on conductive layer 460.In one embodiment, utilize globule masterplate deposit bump material, namely do not need mask.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 460.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 462.In some applications, projection 462 is refluxed to improve the electrical contact with conductive layer 460 for the second time.Projection 462 can also be joined to conductive layer 460 by compression engagement or hot compression.Projection 462 represents the interconnection structure of a type that can be formed on conductive layer 460.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.Before projection is formed or after projection is formed, or laser labelling can be performed after removal carrier 430.
Insulating barrier 410 and 416, conductive layer 414 and 460 and projection 462 are jointly formed in above semiconductor element 294 and the lamination type interconnection structure 466 formed in the area occupied of semiconductor element 294.The perimeter region of the semiconductor element 294 contiguous with semiconductor element 294 lacks interconnection structure 466, and the surface 448 of sealant 438 keeps exposing from interconnection structure 466.Lamination type interconnection structure 466 can comprise few to a RDL or conductive layer (such as conductive layer 414) and an insulating barrier (such as insulating barrier 410).Before forming projection 462, additional insulating barrier can be formed with RDL on insulating barrier 416 to stride across the electrical connectivity that encapsulation provides additional vertical and level according to the Design and Features of semiconductor element 294.
In Figure 19 k, utilize saw blade or laser cutting tool 470, through sealant 438, semiconductor element 294 is partitioned into other eWLCSP 472.The panel 436 of reconstruct is partitioned into eWLCSP 472 to leave the thin layer of sealant 438 on the side surface 422 of semiconductor element 294 and insulating barrier 316,410 and 416.Alternatively, the panel 436 of reconstruct is divided fully to remove sealant 438 from side surface 422.EWLCSP 472 stands electric test before it is split or after segmentation.
Figure 20 illustrates eWLCSP 472, wherein on the backside surface 310 and sidewall 422 of semiconductor element 294, forms sealant.Semiconductor element 294 is electrically connected to projection 462 for the external interconnect through interconnection structure 466 through conductive layer 314,414 and 460.Interconnection structure 466 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Sealant 438 remains on above the backside surface 310 of semiconductor element 294 after the grinding operation shown in Figure 19 g.The side surface 422 that sealant 438 remains on semiconductor element 294 and insulating barrier 316,410 and 416 is above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.So sealant 438 is formed on above five sides of semiconductor element 294, namely on four side surfaces 422 and overleaf above surface 310.Sealant 438 above the backside surface 310 of semiconductor element 294 eliminates the needs of back side protection layer or stratum dorsale laminate, thus reduces the cost of eWLCSP 472.
For eWLCSP 472, the thickness of the sealant 438 above side surface 422 is less than 150 μm.In one embodiment, eWLCSP 472 has 4.595 mm(length) × 4.025 mm(width) × 0.470 mm(height) size, wherein the pitch of projection 462 is 0.4 mm, and wherein semiconductor element 294 has the length of 4.445 mm and the width of 3.875 mm.In another embodiment, the thickness of the sealant 438 above the side surface 324 of semiconductor element 294 is 75 μm or less.EWLCSP 472 has 6.075 mm(length) × 6.075 mm(width) × 0.8 mm(height) size, wherein the pitch of projection 462 is 0.5 mm, and wherein semiconductor element 294 has 6.0 mm(length) × 6.0 mm(width) × 0.470 mm(height) size.In yet another embodiment, eWLCSP 472 has 5.92 mm(length) × 5.92 mm(width) × 0.765 mm(height) size, wherein the pitch of projection 462 is 0.5 mm, and wherein semiconductor element 294 has 5.75 mm(length) × 5.75 mm(width) × 0.535 mm(height) size.In another embodiment, the thickness of the sealant 438 above side surface 422 is 25 μm or less.In yet another embodiment, the thickness of the sealant 438 above side surface 422 is approximate 50 μm or less.On standardized carrier 430, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 472 by using, which reducing the cost of equipment for eWLCSP 472 and material.Use standardized carrier 430 with higher volume to manufacture eWLCSP 472, thus simplified manufacturing technique and reduce unit cost.
Figure 21 illustrates another eWLCSP 480 of the sidewall 422 of the sealant 438 had on the backside surface 310 of semiconductor element 294 and the exposure with semiconductor element 294.Semiconductor element 294 is electrically connected to projection 462 for the external interconnect through interconnection structure 466 through conductive layer 314,414 and 460.Interconnection structure 466 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Sealant 438 remains on above the backside surface 310 of semiconductor element 294 after the grinding operation shown in Figure 19 g.Sealant 438 above the backside surface 310 of semiconductor element 294 eliminates the needs of back side protection layer or stratum dorsale laminate, thus reduces the cost of eWLCSP 480.During splitting, sealant 438 is removed completely with exposed side surfaces 422 from the side surface 422 of semiconductor element 294 and insulating barrier 316,410 and 416.The length of eWLCSP 480 is identical with width with the length of semiconductor element 294 with width.In one embodiment, eWLCSP 480 has approximate 4.445 mm(length) × 3.875 mm(width) size, wherein the pitch of projection 462 is 0.35-0.50 mm.On standardized carrier 430, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 480 by using, which reducing the cost of equipment for eWLCSP 480 and material.Use standardized carrier 430 with higher volume to manufacture eWLCSP 480, thus simplified manufacturing technique and reduce unit cost.
Figure 22 segmentation is shown after the sidewall 422 with semiconductor element 294 above sealant 438 and the eWLCSP 482 of dorsal part insulating barrier 484.Semiconductor element 294 is electrically connected to projection 462 for the external interconnect through interconnection structure 466 through conductive layer 314,414 and 460.Interconnection structure 466 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Sealant 438 is completely removed from the backside surface 310 of semiconductor element 294.The backside surface 310 that dorsal part insulating barrier 484 is formed on semiconductor element 294 is above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.Dorsal part insulating barrier 484 contains the dielectric resist of the photosensitive low curing temperature of one or more layers, photosensitive compound resist, lamination compound film, the insulating paste with filler, solder mask resist film, liquid molding compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg or has other dielectric substance of similar insulating property (properties) and structural property.Printing, rotary coating, spray application, the vacuum or do not have with heating or pressure lamination or other suitable technique is used to carry out deposit dorsal part insulating barrier 484.In one embodiment, dorsal part insulating barrier 484 is low-temperature setting photosensitive dielectrics polymer, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.Dorsal part insulating barrier 484 is back side protection layer and provides mechanical protection and the impact from light for semiconductor element 294.In one embodiment, dorsal part insulating barrier 484 has the thickness that scope is approximate 5-150 μm.
The side surface 422 that sealant 438 covers semiconductor element 294 avoids owing to being exposed to the degeneration produced from light or other photon launched to protect semiconductor element 294.For eWLCSP 482, the thickness of the sealant 438 above side surface 422 is less than 150 μm.In one embodiment, eWLCSP 482 has 4.595 mm(length) × 4.025 mm(width) × 0.470 mm(height) size, wherein the pitch of projection 462 is 0.4 mm, and wherein semiconductor element 294 has the length of 4.445 mm and the width of 3.875 mm.In another embodiment, the thickness of the sealant 438 above side surface 422 is 75 μm or less.EWLCSP 482 has 6.075 mm(length) × 6.075 mm(width) × 0.8 mm(height) size, wherein the pitch of projection 462 is 0.5 mm, and wherein semiconductor element 294 has 6.0 mm(length) × 6.0 mm(width) × 0.470 mm(height) size.In yet another embodiment, eWLCSP 482 has 5.92 mm(length) × 5.92 mm(width) × 0.765 mm(height) size, wherein the pitch of projection 462 is 0.5 mm, and wherein semiconductor element 294 has 5.75 mm(length) × 5.75 mm(width) × 0.535 mm(height) size.In another embodiment, the thickness of the sealant 438 above side surface 422 is 25 μm or less.In yet another embodiment, the thickness of the sealant 438 above side surface 422 is approximate 50 μm or less.On standardized carrier 430, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 482 by using, which reducing the cost of equipment for eWLCSP 482 and material.Use standardized carrier 430 with higher volume to manufacture eWLCSP 482, thus simplified manufacturing technique and reduce unit cost.
Figure 23 illustrates similar with eWLCSP 482 but does not have the eWLCSP 486 of conductive layer 460.Conductive layer 414 directly forms projection 462.Suitable attachment or joint technology is used to join bump material to conductive layer 414.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 462.In some applications, projection 462 is refluxed to improve the electrical contact with conductive layer 414 for the second time.Projection 462 can also be joined to conductive layer 414 by compression engagement or hot compression.Projection 462 represents the interconnection structure of a type that can be formed on conductive layer 414.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.
Semiconductor element 294 is electrically connected to projection 462 for the external interconnect through interconnection structure 466 through conductive layer 314 and 414.Interconnection structure 466 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Sealant 438 is removed completely from the backside surface 310 of semiconductor element 294.The backside surface 310 that dorsal part insulating barrier 484 is formed on semiconductor element 294 is above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.The side surface 422 that sealant 438 covers semiconductor element 294 avoids owing to being exposed to the degeneration produced from light or other photon launched to protect semiconductor element 294.For eWLCSP 486, the thickness of the sealant 438 above side surface 422 is less than 150 μm.On standardized carrier 430, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 486 by using, which reducing the cost of equipment for eWLCSP 486 and material.Use standardized carrier 430 with higher volume to manufacture eWLCSP 486, thus simplified manufacturing technique and reduce unit cost.
Figure 24 illustrates the eWLCSP 488 substituted of the sidewall 422 with dorsal part insulating barrier 484 and exposure.Semiconductor element 294 is electrically connected to projection 462 for the external interconnect through interconnection structure 466 through conductive layer 314,414 and 460.Interconnection structure 466 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.Sealant 438 is removed completely from the backside surface 310 of semiconductor element 294.The backside surface 310 that dorsal part insulating barrier 484 is formed on semiconductor element 294 is above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.During splitting, sealant 438 is removed completely with exposed side surfaces 422 from the side surface 324 of semiconductor element 294.The length of eWLCSP 488 is identical with width with the length of semiconductor element 294 with width.In one embodiment, eWLCSP 488 has approximate 4.4 mm(length) × 3.9 mm(width) size, wherein the pitch of projection 462 is 0.35-0.50 mm.On standardized carrier 430, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 488 by using, which reducing the cost of equipment for eWLCSP 488 and material.Use standardized carrier 430 with higher volume to manufacture eWLCSP 488, thus simplified manufacturing technique and reduce unit cost.
Figure 25 illustrates the backside surface 310 of the exposure with semiconductor element 294 and another eWLCSP 490 of sidewall 422.Semiconductor element 294 is electrically connected to projection 462 for the external interconnect through interconnection structure 466 through conductive layer 314,414 and 460.Interconnection structure 466 does not extend beyond the area occupied of semiconductor element 294, and therefore forms fan-in encapsulation.During the grinding operation shown by Figure 19 g, sealant 438 is removed completely from the backside surface 310 of semiconductor element 294.During splitting, sealant 438 is removed completely with exposed side surfaces 422 from the side surface 422 of semiconductor element 294.The length of eWLCSP 490 is identical with width with the length of semiconductor element 294 with width.In one embodiment, eWLCSP 490 has approximate 4.4 mm(length) × 3.9 mm(width) size, wherein the pitch of projection 462 is 0.35-0.50 mm.On standardized carrier 430, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 490 by using, which reducing the cost of equipment for eWLCSP 490 and material.Use standardized carrier 430 with higher volume to manufacture eWLCSP 490, thus simplified manufacturing technique and reduce unit cost.
Figure 26 a-26k illustrates the technique of fan-in WLCSP that is that the formation relevant with Fig. 1 and 2 a-2c reconstructs or that embed.Figure 26 a illustrates the semiconductor crystal wafer 500 of base substrate material 502 such as silicon, germanium, GaAs, indium phosphide or the carborundum had for support structure.As described above, by non-active, multiple semiconductor element that wafer area between tube core or saw street 506 are separated or parts 504 are formed on wafer 500.Saw street 506 provides cutting area semiconductor crystal wafer 500 to be partitioned into other semiconductor element 504.In one embodiment, the diameter of semiconductor crystal wafer 500 is 200-300 mm.In another embodiment, the diameter of semiconductor crystal wafer 500 is 100-450 mm.Before semiconductor crystal wafer being partitioned into other semiconductor element 504, semiconductor crystal wafer 500 can have any diameter.
Figure 26 a illustrates the viewgraph of cross-section of the part of semiconductor crystal wafer 500.Each semiconductor element 504 has surface 508 and the active surface 510 of the back side or non-active, this active surface 510 containing be implemented as formed in tube core according to the electrical design of tube core and function and the analog or digital circuit of the active device be electrically, passive device, conductive layer and dielectric layer.Such as, circuit can be included in interior one or more transistors, diode and other circuit element formed of active surface 510 to implement analog circuit or digital circuit, such as DSP, ASIC, memory or other signal processing circuit.Semiconductor element 504 can also containing the IPD for RF signal transacting, such as inductor, capacitor and resistor.
PVD, CVD, metallide, chemical plating process or other suitable metal deposition process is used to form conductive layer 512 on active surface 510.Conductive layer 512 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.Conductive layer 512 is operating as the contact pad of the circuit be electrically connected on active surface 510.Conductive layer 512 can be formed the contact pad be arranged side by side from edge first distance of semiconductor element 504, as shown in Figure 26 a.Alternatively, conductive layer 512 can be formed contact pad, this contact pad in multiple row by shift into make the first row of contact pad be set to from tube core edge first apart from and the second row of the contact pad replaced with the first row is set to from tube core edge second distance.
Use PVD, CVD, printing, rotary coating, spray application, sintering or thermal oxidation on semiconductor element 504 and conductive layer 512, form the first insulation or passivation layer 514.Insulating barrier 514 containing one or more layers SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer or there is other dielectric substance of similar structural property and insulating property (properties).In one embodiment, insulating barrier 514 is the photosensitive dielectrical polymers of low-temperature setting, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.Insulating barrier 514 covers active surface 510 and provides protection to active surface 510.Insulating barrier 514 by be conformally applied to conductive layer 512 and semiconductor element 504 active surface 510 above and do not extend beyond the edge of semiconductor element 504 or sidewall 516 or do not extend beyond the area occupied of semiconductor element 504.In other words, the perimeter region of contiguous with semiconductor element 504 semiconductor element 504 lacks conductive layer 514.By using the LDA of laser 518 or removing the part of insulating barrier 514 to expose conductive layer 512 through insulating barrier 514 and to provide electric interconnection subsequently by etching technics through the photoresist oxidant layer of patterning.
Semiconductor crystal wafer 500 stands electric test and checks the part as quality control process.Artificial vision checks and automation optical system is used for performing the inspection to semiconductor crystal wafer 500.Software can be used in the automation optical analysis of semiconductor crystal wafer 500.The method of visual inspection can adopt the equipment of such as scanning electron microscopy, high-strength light or ultraviolet light or metallomicroscope.For comprise warpage, varied in thickness, surface particle, irregular, crack, delamination and variable color architectural characteristic semiconductor crystal wafer 500 is checked.
Active parts in semiconductor element 504 and passive component stand the test in wafer scale for electric property and circuit function.Probe or other testing apparatus is used to test each semiconductor element 504 for functional and electric parameter.Probe is used on each semiconductor element 504 reaches electrical contact with node or contact pad 512, and provides electric stimulation to contact pad.Semiconductor element 504 is in response to electric stimulation, and this electrically stimulates measured and carry out the functional of measuring semiconductor tube core compared with the response of expection.Electric test can comprise circuit functionality, the integrality of lead-in wire, resistivity, continuity, reliability, the degree of depth of knot, ESD, RF performance, drive current, threshold current, leakage current and the operating parameter specific to unit type.The inspection of semiconductor crystal wafer 500 and electric test make qualified semiconductor element 504 can be designated as the KGD used in semiconductor packages.
In Figure 26 b, use saw blade or laser cutting tool 520, through saw street 506, semiconductor crystal wafer 500 is partitioned into other semiconductor element 504.Part along the base substrate material 502 in saw street district 506 utilizes to be split semiconductor crystal wafer 500 along the thin cutting of base substrate side surface 522, and this thin cutting allows the part of base substrate material 502 to keep being arranged on the sidewall 516 of semiconductor element 504.This thin cutting exceeds the size of semiconductor element 504 a little according to the distance D3 between semiconductor side wall 516 and base substrate side surface 522.Broken by minimizing dielectric substance during the division process of base substrate material 502 above the sidewall 516 of semiconductor element 504 during reconstructing with below and strengthen device.In one embodiment, the distance D3 between sidewall 516 and base substrate side surface 522 is at least 10 μm.In another embodiment, the distance D3 scope between sidewall 516 and base substrate side surface 522 is 14-36 μm.Can check other semiconductor element 504 individual and electric test for the identification of the KGD after splitting.
Figure 26 c illustrate containing sacrificial substrate material such as silicon, polymer, beryllium oxide, glass or other the suitable low cost for support structure, the viewgraph of cross-section of the firm carrier of material or the part of temporary substrates 530.Boundary layer or two-sided tape 532 are formed on carrier 530 above as temporary adhesive bonding film, etching stop layer or Thermal release layer.
Carrier 530 can be the circle of the capacity had for multiple semiconductor element 504 or the panel (being greater than 300 mm) of rectangle.Carrier 530 can have the surface area larger than the surface area of semiconductor crystal wafer 500.Larger carrier reduces the manufacturing cost of semiconductor packages, because can process more semiconductor element on larger carrier, thus reduces the cost of each unit.Size for just processed carrier or wafer designs and configuring semiconductor encapsulation and treatment facility.
In order to reduce manufacturing cost further, select the size of carrier 530 independent of the size of semiconductor crystal wafer 500 or the size of semiconductor element 504.That is exactly that carrier 530 has fixing or standardized size, and it can hold the semiconductor element 504 of the various sizes of segmentation from one or more semiconductor crystal wafer 500.In one embodiment, carrier 530 is circles of the diameter with 330 mm.In another embodiment, carrier 530 is the rectangles with the width of 560 mm and the length of 600 mm.Semiconductor element 504 can have the size of 10 mm × 10 mm, and it is placed on standardized carrier 530.Alternatively, semiconductor element 504 can have the size of 20 mm × 20 mm, and it is placed on identical standardized carrier 530.Therefore, standardized carrier 530 can dispose the semiconductor element 504 of any size, and it allows the carrier for sharing to carry out standardization semiconductor processing equipment subsequently, namely independent of the size of tube core or the wafer size of introducing.Can to the carrier design of standard and configuring semiconductor sealed in unit, the carrier of standard uses a set of handling implement, equipment and the bill of materials shared to process the size of any semiconductor element of the wafer size from any introducing.Share or standardized carrier 530 reduces manufacturing cost and financial risks by the needs reduced or eliminated for the special semiconductor processes line of the wafer size based on die-size or introducing.By selecting the size of the carrier of pre-determining for the semiconductor element from any size of all semiconductor crystal wafers, can implement to manufacture line flexibly.
In Figure 26 d, such as when insulating barrier 514 be oriented to towards carrier 530 use pickup and place operation the semiconductor element 504 from Figure 26 b is installed to carrier 530 and boundary layer 532.
At Figure 26 e, semiconductor element 504 is shown, this semiconductor element 504 is installed to the boundary layer 532 of carrier 530 to form wafer 536 that is that reconstruct or that configure again.In one embodiment, insulating barrier 514 is embedded at boundary layer 532.Such as, the active surface 510 of semiconductor element 504 can be coplanar with the surface 534 of boundary layer 532.In another embodiment, on boundary layer 532, installing insulating layer 514 makes the active surface 510 of semiconductor element 504 offset with boundary layer 532.
The wafer of reconstruct or the panel 536 of reconstruct can be processed to be eurypalynous semiconductor packages perhaps, its comprise fan-in WLCSP, reconstruct or eWLCSP, fan-out WLCSP, Flip-Chip Using, 3D encapsulation, such as PoP or other semiconductor packages.The panel 536 of reconstruct is configured according to the explanation of the semiconductor packages obtained.In one embodiment, semiconductor element 504 is placed on carrier 530 for the treatment of fan-in device with highdensity layout (namely separating 300 μm or less).The semiconductor element 504 be separated by the gap between semiconductor element 504 or distance D4 is placed on carrier 530.Based on the semiconductor packages that will be processed design and the distance D4 selecting between semiconductor element 304 is described.In one embodiment, the distance D4 between semiconductor element 504 is 50 μm or less.In another embodiment, the distance D4 between semiconductor element 504 is 100 μm or less.Distance D4 between semiconductor element 504 on carrier 530 is optimized for minimum unit cost to manufacture semiconductor packages.
Figure 26 f illustrates the plan view of the panel 536 of the reconstruct with the semiconductor element 504 be arranged on above carrier 530.Carrier 530 is standardized profile and size, and this carrier 530 has the capacity of the semiconductor chip for various sizes and quantity, and this semiconductor chip is divided from the semiconductor crystal wafer of various sizes.In one embodiment, carrier 530 is rectangle in shape and has the length L3 of width W 3 and 600 mm of 560 mm.The number being installed to the semiconductor element 504 of carrier 530 can be greater than, be less than or equal to the number of the semiconductor element 504 of segmentation from semiconductor crystal wafer 500.The carrier 530 of larger surface area holds more semiconductor element 504 and reduces manufacturing cost, because the panel 536 of each reconstruct processes more semiconductor element 504.
Standardized carrier (carrier 530) is fixing dimensionally and can holds the semiconductor element of multiple size.The size of standardized carrier 530 is independent of the size of semiconductor element or semiconductor crystal wafer.On carrier 530, semiconductor element more little compared with larger semiconductor element can be installed.Such as, carrier 530 holds the tube core of number more 5 mm × 5 mm on the surface area of carrier 530 of big figure than the tube core of 10 mm × 10 mm on the surface area of carrier 530.
Such as, the semiconductor element 504 with the size of 10 mm × 10 mm is placed on carrier 530, and the distance D4 between wherein contiguous semiconductor element 504 is 200 μm.The number of semiconductor element 504 split from semiconductor crystal wafer 500 is approximate 600 semiconductor elements, and wherein semiconductor crystal wafer 500 has the diameter of 300 mm.The number of the semiconductor element 504 of 10 mm × 10 mm that can install on carrier 530 is above 3000 semiconductor elements.Alternatively, the semiconductor element 504 with the size of 5 mm × 5 mm is placed on carrier 530, and the distance D4 between wherein contiguous semiconductor element 504 is 200 μm.The number of semiconductor element 504 split from semiconductor crystal wafer 500 is approximate 1000 semiconductor elements, and wherein semiconductor crystal wafer 500 has the diameter of 200 mm.The number of the semiconductor element 504 of 5 mm × 5 mm that can install on carrier 530 is above 12000 semiconductor elements.
The size of carrier 530 does not change along with the size of just processed semiconductor element.The number of the semiconductor element 504 that carrier 530 is installed changes along with the interval between the size of semiconductor element 504 and semiconductor element 504 or distance D4.The size of carrier 530 and profile keep fixing and independent of the size of semiconductor element 504 or the size from the semiconductor crystal wafer 500 wherein split by semiconductor element 504.The panel 536 of carrier 530 and reconstruct provides use such as manufactures the many dissimilar semiconductor packages of the semiconductor element 504 of the different size of the semiconductor crystal wafer 500 had from different size flexibility from a set for the treatment of facility shared of the treatment facility 340 of Figure 13 h.
In Figure 26 g, use that cream printing, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 550 on semiconductor element 504 and carrier 530.Sealant 550 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 550 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.In another embodiment, sealant 550 is insulating barrier or dielectric layer, it contains use printing, rotary coating, spray application, there is or not have the dielectric resist that the vacuum of heating or pressure lamination or other suitable technique carry out the photosensitive low curing temperature of one or more layers of deposit, photosensitive compound resist, lamination compound film, there is the insulating paste of filler, solder mask resist film, liquid or granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg or there is other dielectric substance of similar insulating property (properties) and structural property.In one embodiment, sealant 550 is low-temperature setting photosensitive dielectrics polymer, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.
Especially, sealant 550 is set to the side surface 522 along base substrate.Sealant 550 also covers the backside surface 508 of semiconductor element 504.In one embodiment, sealant 550 is opaque, and is dark-coloured in color or black.Sealant 550 can be used to the panel 536 of laser labelling reconstruct to carry out aiming at and splitting.Sealant 550 can be thinned in back face grinding step subsequently.Sealant 550 can also be deposited and makes sealant 550 and the backside surface 508 of semiconductor element 504 coplanar and do not cover backside surface 508.The surface 554 of the sealant 550 relative with back surface 552 is arranged on carrier 530 and boundary layer 532 and makes the surface 554 of sealant 550 can be coplanar with the active surface 510 of semiconductor element 504 above.
In Figure 26 h, ultraviolet light roasting by chemical etching, mechanical stripping, CMP, mechanical lapping, heat, laser scanning or wet stripping remove carrier 530 and boundary layer 532, to expose the surface 554 of insulating barrier 514, conductive layer 512 and sealant 550.
Such as printing, PVD, CVD, sputtering, the patterning of metallide and chemical plating and metal deposition process is used to form conductive layer 560 on insulating barrier 514 and conductive layer 512.Conductive layer 560 can be Al, Cu, Sn, Ti, Ni, Au, Ag, W or other suitable electric conducting material of one or more layers.The part of conductive layer 560 extends laterally distribute and the electric interconnection of conductive layer 512 again along insulating barrier 514 and with the active surface 510 parallel water level land of semiconductor element 504.Conductive layer 560 is operating as the RDL of the electric signal for semiconductor element 504.Do not extend beyond the area occupied of semiconductor element 504 and do not extend on sealant 550 above the area occupied that conductive layer 560 is formed on semiconductor element 504.In other words, the perimeter region of the semiconductor element 504 contiguous with semiconductor element 504 lacks conductive layer 560, makes sealant 550 keep lacking conductive layer 560.In one embodiment, form conductive layer 560 with the sidewall 516 from semiconductor element 504 apart from D5, and distance D5 is at least 1 μm.The part of conductive layer 560 is electrically connected to conductive layer 512.Depend on the connectivity of semiconductor element 504, the other parts of conductive layer 560 electrically share or are electrically isolated.
In Figure 26 i, use PVD, CVD, printing, rotary coating, spray application, silk screen printing or be laminated to formation insulation or passivation layer 562 above insulating barrier 514 and conductive layer 560.Insulating barrier 562 can be SiO2, Si3N4, SiON, Ta2O5, Al2O3 of one or more layers or have other material of similar insulating property (properties) and structural property.In one embodiment, insulating barrier 562 is being less than 200 ° of C and bends down the photosensitive dielectrics polymer of solidification.In one embodiment, insulating barrier 562 be formed on semiconductor element 504 area occupied in and on sealant 550, do not extend beyond the area occupied of semiconductor element 504.In other words, the perimeter region of the semiconductor element 504 contiguous with semiconductor element 504 lacks insulating barrier 562, so that sealant 550 keeps lacking insulating barrier 562.In another embodiment, insulating barrier 562 is formed on above insulating barrier 514, semiconductor element 504 and sealant 550.The etching technics of the photoresist oxidant layer of the part by utilizing patterning of insulating barrier 562 or be removed by LDA, to form the opening exposing conductive layer 560.
Use evaporation, metallide, chemical plating, globule or silk-screen printing technique deposit conductive bump material on conductive layer 560.In one embodiment, utilize globule masterplate deposit bump material, namely do not need mask.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 560.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 564.In some applications, projection 564 is refluxed to improve the electrical contact with conductive layer 560 for the second time.Projection 564 can also be joined to conductive layer 560 by compression engagement or hot compression.Projection 564 represents the interconnection structure of a type that can be formed on conductive layer 560.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.Before projection is formed or after projection is formed, or laser labelling can be performed after the removal of carrier 530.
Insulating barrier 562, conductive layer 560 and projection 564 are jointly formed in the lamination type interconnection structure 566 formed above the inherent semiconductor element 504 of area occupied of semiconductor element 504 and sealant 550.The perimeter region of the semiconductor element 504 contiguous with semiconductor element 504 lacks interconnection structure 566, so that the surface 554 of sealant 550 keeps exposing about interconnection structure 566.Lamination type interconnection structure 566 can comprise few to a RDL or conductive layer (such as conductive layer 560) and an insulating barrier (such as insulating barrier 562).Before forming projection 564, additional insulating barrier can be formed with RDL on insulating barrier 562 to stride across the electrical connectivity that encapsulation provides additional vertical and level according to the Design and Features of semiconductor element 504.
In Figure 26 j, saw blade or laser cutting tool 570 is utilized semiconductor element 504 to be partitioned into other eWLCSP 572.The panel 536 of reconstruct along side surface 580 through sealant 550 and base substrate material 502 divided with the side from semiconductor element 504 in remove sealant 550 and from the side of semiconductor element 504, remove the part of base substrate material 502.Therefore, during formation eWLCSP 572, base substrate material 502 is cut or splits twice, the panel level once once reconstructed in wafer scale.As a result, dielectric substance not too easily breaks, and improves the reliability of eWLCSP 572.
The part of base substrate material 502 keeps arranging along the sidewall 516 of semiconductor element 504 upon splitting.The thickness of the base substrate material 502 contiguous with semiconductor element 504 above sidewall 516 is at least 1 μm.In other words, the distance D6 between the side surface 580 of semiconductor element 504 and sidewall 516 is at least 1 μm.EWLCSP 572 stands electric test before it is split or upon splitting.
Figure 26 k segmentation is shown after the eWLCSP 572 with the sealant that the backside surface 508 of semiconductor element 504 is covered.Semiconductor element 504 is electrically connected to projection 564 for the external interconnect through interconnection structure 566 through conductive layer 512 and 560.Interconnection structure 566 does not extend beyond the area occupied of semiconductor element 504, and therefore forms fan-in encapsulation.Sealant 550 remains on above the backside surface 508 of semiconductor element 504.Sealant 550 above the backside surface 508 of semiconductor element 504 eliminates the needs of back side protection layer or stratum dorsale laminate, thus reduces the cost of eWLCSP 572.During splitting, sealant 550 is removed the side surface 580 exposing base substrate material 502 completely from the side of semiconductor element 504.In one embodiment, eWLCSP 572 has approximate 4.445 mm(length) × 3.875 mm(width) size, wherein the pitch of projection 564 is 0.35-0.50 mm.On standardized carrier 530, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 572 by using, which reducing the cost of equipment for eWLCSP 572 and material.Use standardized carrier 530 with higher volume to manufacture eWLCSP 572, thus simplified manufacturing technique and reduce unit cost.
Figure 27 illustrates the eWLCSP 590 of dorsal part and the sidewall with exposure.Semiconductor element 504 is electrically connected to projection 564 for the external interconnect through interconnection structure 566 through conductive layer 512 and 560.Interconnection structure 566 does not extend beyond the area occupied of semiconductor element 504, and therefore forms fan-in encapsulation.During grinding operation, sealant 550 is removed completely from the backside surface 508 of semiconductor element 504.During splitting, sealant 550 is removed the side surface 580 exposing base substrate material 502 completely from the side of semiconductor element 504.In one embodiment, eWLCSP 590 has approximate 4.4 mm(length) × 3.9 mm(width) size, wherein the pitch of projection 564 is 0.35-0.50 mm.On standardized carrier 530, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 590 by using, which reducing the cost of equipment for eWLCSP 590 and material.Use standardized carrier 530 with higher volume to manufacture eWLCSP 590, thus simplified manufacturing technique and reduce unit cost.
Figure 28 illustrate have UBM 594, dorsal part insulating barrier 596 and expose side surface 580 substitute eWLCSP 592.After last passivation again, use PVD, CVD, evaporation, metallide, chemical plating or other suitable metal deposition process to form conductive layer 594 on the part of the exposure of conductive layer 560 and on insulating barrier 562.Conductive layer 594 can be Al, Cu, Sn, Ti, Ni, Au, Ag, W or other suitable electric conducting material.Conductive layer 594 is the UBM being electrically connected to conductive layer 560 and 512.UBM 594 can be have adhesive layer, barrier layer and Seed Layer or wettable layer how metal laminated.Adhesive layer is formed on conductive layer 560 above and can be Ti, TiN, TiW, Al or Cr.Barrier layer to be formed on above adhesive layer and can be Ni, NiV, Pt, Pd, TiW, Ti or CrCu.Barrier layer forbids that Cu is diffused in the active surface 510 of semiconductor element 504.Seed Layer to be formed on above barrier layer and can be Cu, Ni, NiV, Au or Al.UBM 594 conductive layer 512 provides low resistance interconnect, and for the stop of solder diffusion and the Seed Layer for solder wettable.
Semiconductor element 504 is electrically connected to projection 564 for the external interconnect through interconnection structure 566 through conductive layer 512,560 and 594.Conductive layer 560 and 594 and insulating barrier 514 and 562 do not extend beyond the area occupied of semiconductor element 504, and therefore form fan-in encapsulation.The backside surface 508 that dorsal part insulating barrier 596 is formed on semiconductor element 504 is above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.Dorsal part insulating barrier 596 contains the dielectric resist of the photosensitive low curing temperature of one or more layers, photosensitive compound resist, lamination compound film, the insulating paste with filler, solder mask resist film, liquid molding compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg or has other dielectric substance of similar insulating property (properties) and structural property.Printing, rotary coating, spray application, the vacuum or do not have with heating or pressure lamination or other suitable technique is used to carry out deposit dorsal part insulating barrier 596.In one embodiment, dorsal part insulating barrier 596 is the photosensitive dielectrical polymers of low-temperature setting, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.Dorsal part insulating barrier 596 is back side protection layer and provides mechanical protection and the impact from light for semiconductor element 504.In one embodiment, dorsal part insulating barrier 596 has the thickness that scope is approximate 5-150 μm.
During splitting, sealant 550 is removed the side surface 580 exposing base substrate material 502 completely from the side of semiconductor element 504.In one embodiment, eWLCSP 592 has approximate 4.4 mm(length) × 3.9 mm(width) size, wherein the pitch of projection 564 is 0.35-0.50 mm.On standardized carrier 530, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 592 by using, which reducing the cost of equipment for eWLCSP 592 and material.Use standardized carrier 530 with higher volume to manufacture eWLCSP 592, thus simplified manufacturing technique and reduce unit cost.
Figure 29 a-29i illustrates the technique of fan-in WLCSP that is that the formation relevant with Fig. 1 and 2 a-2c reconstructs or that embed.Figure 29 a illustrates the viewgraph of cross-section of the part of semiconductor crystal wafer 600.Semiconductor crystal wafer 600 comprises the base substrate material 602 for support structure, such as silicon, germanium, GaAs, indium phosphide or carborundum.As described above, by non-active, multiple semiconductor element that wafer area between tube core or saw street 606 are separated or parts 604 are formed on wafer 600.Saw street 606 provides cutting area semiconductor crystal wafer 600 to be partitioned into other semiconductor element 604.Semiconductor element 604 has edge or sidewall 608.In one embodiment, the diameter of semiconductor crystal wafer 600 is 200-300 mm.In another embodiment, the diameter of semiconductor crystal wafer 600 is 100-450 mm.Before semiconductor crystal wafer being partitioned into other semiconductor element 604, semiconductor crystal wafer 600 can have any diameter.
Each semiconductor element 604 has surface 610 and the active surface 612 of the back side or non-active, this active surface 612 containing be implemented as formed in tube core according to the electrical design of tube core and function and the analog or digital circuit of the active device be electrically, passive device, conductive layer and dielectric layer.Such as, circuit can be included in interior one or more transistors, diode and other circuit element formed of active surface 612 to implement analog circuit or digital circuit, such as DSP, ASIC, memory or other signal processing circuit.Semiconductor element 604 can also containing the IPD for RF signal transacting, such as inductor, capacitor and resistor.
PVD, CVD, metallide, chemical plating process or other suitable metal deposition process is used to form conductive layer 614 on active surface 612.Conductive layer 614 can be Al, Cu, Sn, Ni, Au, Ag or other suitable electric conducting material of one or more layers.Conductive layer 614 is operating as the contact pad of the circuit be electrically connected on active surface 612.Conductive layer 614 can be formed the contact pad be arranged side by side from edge 608 first distance of semiconductor element 604, as shown in Figure 29 a.Alternatively, conductive layer 614 can be formed contact pad, and this contact pad is made the first row of contact pad be set to edge 608 first distance from semiconductor element 604 by shifting into and the second row of the contact pad replaced with the first row is set to from semiconductor element 604 edge 608 second distance in multiple row.
Use PVD, CVD, printing, rotary coating, spray application, sintering or thermal oxidation on semiconductor element 604 and conductive layer 614, form the first insulation or passivation layer 616.Insulating barrier 616 containing one or more layers SiO2, Si3N4, SiON, Ta2O5, Al2O3, HfO2, BCB, PI, PBO, polymer or there is other dielectric substance of similar structural property and insulating property (properties).In one embodiment, insulating barrier 616 is the photosensitive dielectrical polymers of low-temperature setting, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.Insulating barrier 616 covers active surface 612 and provides protection to active surface 612.Insulating barrier 616 by be conformally applied to conductive layer 614 and semiconductor element 604 active surface 612 above and do not extend beyond the sidewall 608 of semiconductor element 604 or do not extend beyond the area occupied of semiconductor element 604.The perimeter region of the semiconductor element 604 contiguous with semiconductor element 604 lacks insulating barrier 616.By using the LDA of laser 618 or removing the part of insulating barrier 616 to expose conductive layer 614 through insulating barrier 616 and to provide electric interconnection subsequently by etching technics through the photoresist oxidant layer of patterning.
Semiconductor crystal wafer 600 stands electric test and checks the part as quality control process.Artificial vision checks and automation optical system is used for performing the inspection to semiconductor crystal wafer 600.Software can be used in the automation optical analysis of semiconductor crystal wafer 600.The method of visual inspection can adopt the equipment of such as scanning electron microscopy, high-strength light or ultraviolet light or metallomicroscope.For comprise warpage, varied in thickness, surface particle, irregular, crack, delamination and variable color architectural characteristic semiconductor crystal wafer 600 is checked.
Active parts in semiconductor element 604 and passive component stand the test in wafer scale for electric property and circuit function.Probe or other testing apparatus is used to test each semiconductor element 604 for functional and electric parameter.Probe is used to reach electrical contact with node or contact pad 614 on each semiconductor element 604, and provides electric stimulation to contact pad.Semiconductor element 604 is in response to electric stimulation, and this electrically stimulates measured and carry out the functional of measuring semiconductor tube core compared with the response of expection.Electric test can comprise circuit functionality, the integrality of lead-in wire, resistivity, continuity, reliability, the degree of depth of knot, ESD, RF performance, drive current, threshold current, leakage current and the operating parameter specific to unit type.The inspection of semiconductor crystal wafer 600 and electric test make qualified semiconductor element 604 can be designated as the KGD used in semiconductor packages.
In Figure 29 b, use saw blade or laser cutting tool 620, through saw street 606, semiconductor crystal wafer 600 is partitioned into other semiconductor element 604.Semiconductor crystal wafer 600 is split by the part in the following way along the base substrate material 602 in saw street district 606: cut to allow the part of base substrate material 602 to keep being arranged on the sidewall 608 of semiconductor element 604 along base substrate side surface 622.Distance D7 between semiconductor side wall 608 and base substrate side surface 622 is at least 1 μm.Can check other semiconductor element 604 individual and electric test for the identification of the KGD after splitting.
Figure 29 c illustrate containing sacrificial substrate material such as silicon, polymer, beryllium oxide, glass or other the suitable low cost for support structure, the viewgraph of cross-section of the firm carrier of material or the part of temporary substrates 630.Boundary layer or two-sided tape 632 are formed on carrier 630 above as temporary adhesive bonding film, etching stop layer or Thermal release layer.Such as be oriented to towards using pickup and placement operation that the semiconductor element 604 from Figure 29 b is installed to carrier 630 and boundary layer 632 when carrier at active surface 612.
Carrier 630 can be the circle of the capacity had for multiple semiconductor element 604 or the panel (being greater than 300 mm) of rectangle.Carrier 630 can have the surface area larger than the surface area of semiconductor crystal wafer 600.Larger carrier reduces the manufacturing cost of semiconductor packages, because can process more semiconductor element on larger carrier, thus reduces the cost of each unit.Size for just processed carrier or wafer designs and configuring semiconductor encapsulation and treatment facility.
In order to reduce manufacturing cost further, select the size of carrier 630 independent of the size of semiconductor crystal wafer 600 or the size of semiconductor element 604.That is exactly that carrier 630 has fixing or standardized size, and it can hold the semiconductor element 604 of the various sizes of segmentation from one or more semiconductor crystal wafer 600.In one embodiment, carrier 630 is circles of the diameter with 330 mm.In another embodiment, carrier 630 is the rectangles with the width of 560 mm and the length of 600 mm.Semiconductor element 604 can have the size of 10 mm × 10 mm, and it is placed on standardized carrier 630.Alternatively, semiconductor element 604 can have the size of 20 mm × 20 mm, and it is placed on identical standardized carrier 630.Therefore, standardized carrier 630 can dispose the semiconductor element 604 of any size, and it allows the carrier for sharing to carry out standardization semiconductor processing equipment subsequently, namely independent of the size of tube core or the wafer size of introducing.Can for the carrier design of standard and configuring semiconductor sealed in unit, the carrier of this standard uses a set of handling implement, equipment and the bill of materials shared to process the size of any semiconductor element of the wafer size from any introducing.Share or standardized carrier 630 reduces manufacturing cost and financial risks by the needs reduced or eliminated for the special semiconductor processes line of the wafer size based on die-size or introducing.By selecting the carrier dimensions of pre-determining for the semiconductor element from any size of all semiconductor crystal wafers, can implement to manufacture line flexibly.
Figure 29 c illustrates semiconductor element 604, and this semiconductor element 604 is installed to the boundary layer 632 of carrier 630 to form wafer 640 that is that reconstruct or that configure again.In one embodiment, insulating barrier 616 is embedded at boundary layer 632.Such as, the active surface 612 of semiconductor element 604 can be coplanar with the surface 634 of boundary layer 632.In another embodiment, on boundary layer 632, installing insulating layer 616 makes the active surface 612 of semiconductor element 604 offset with boundary layer 632.
The wafer of reconstruct or the panel 640 of reconstruct can be processed to be eurypalynous semiconductor packages perhaps, its comprise fan-in WLCSP, reconstruct or eWLCSP, fan-out WLCSP, Flip-Chip Using, 3D encapsulation, such as PoP or other semiconductor packages.The panel 640 of reconstruct is configured according to the explanation of the semiconductor packages obtained.In one embodiment, semiconductor element 604 is placed on carrier 630, for the treatment of fan-in device with highdensity layout (namely separating 300 μm or less).Be placed on carrier 630 with the semiconductor element 604 that the gap between semiconductor element 604 or distance D8 are separated.Based on the semiconductor packages that will be processed design and the distance D8 selecting between semiconductor element 604 is described.In one embodiment, the distance D8 between semiconductor element 604 is 50 μm or less.In another embodiment, the distance D8 between semiconductor element 604 is 100 μm or less.Distance D8 between semiconductor element 604 on carrier 630 is optimized for minimum unit cost to manufacture semiconductor packages.
Figure 29 d illustrates the plan view of the panel 640 of the reconstruct with the semiconductor element 604 be arranged on above carrier 630.Carrier 630 is standardized profile and size, and this carrier 630 has the capacity of the semiconductor chip for various sizes and quantity, and this semiconductor chip is divided from the semiconductor crystal wafer of various sizes.In one embodiment, carrier 630 is rectangle in shape and has the length L4 of width W 4 and 600 mm of 560 mm.The number being installed to the semiconductor element 604 of carrier 630 can be greater than, be less than or equal to the number of the semiconductor element 604 split from semiconductor crystal wafer 600.The carrier 630 of larger surface area holds more semiconductor element 604 and reduces manufacturing cost, because the panel 640 of each reconstruct processes more semiconductor element 604.
Standardized carrier (carrier 630) is fixing dimensionally and can holds the semiconductor element of multiple size.The size of standardized carrier 630 is independent of the size of semiconductor element or semiconductor crystal wafer.On carrier 630, semiconductor element more little compared with larger semiconductor element can be installed.Such as, carrier 630 holds the tube core of number more 5 mm × 5 mm on the surface area of carrier 630 of big figure than the tube core of 10 mm × 10 mm on the surface area of carrier 630.
Such as, the semiconductor element 604 with the size of 10 mm × 10 mm is placed on carrier 630, and the distance D8 between wherein contiguous semiconductor element 604 is 200 μm.The number of semiconductor element 604 split from semiconductor crystal wafer 600 is approximate 600 semiconductor elements, and wherein semiconductor crystal wafer 600 has the diameter of 300 mm.The number of the semiconductor element 604 of 10 mm × 10 mm that can install on carrier 630 is above 3000 semiconductor elements.
Alternatively, the semiconductor element 604 with the size of 5 mm × 5 mm is placed on carrier 630, and the distance D8 between wherein contiguous semiconductor element 604 is 200 μm.The number of semiconductor element 604 split from semiconductor crystal wafer 600 is approximate 1000 semiconductor elements, and wherein semiconductor crystal wafer 600 has the diameter of 200 mm.The number of the semiconductor element 604 of 5 mm × 5 mm that can install on carrier 630 is above 12000 semiconductor elements.
The size of carrier 630 does not change along with the size of just processed semiconductor element.The number of the semiconductor element 604 that carrier 630 is installed changes along with the interval between the size of semiconductor element 604 and semiconductor element 604 or distance D8.The size of carrier 630 and profile keep fixing and independent of the size of semiconductor element 604 or the size from the semiconductor crystal wafer 600 wherein split by semiconductor element 604.The panel 640 of carrier 630 and reconstruct provides use such as manufactures the many dissimilar semiconductor packages of the semiconductor element 604 of the different size of the semiconductor crystal wafer 600 had from different size flexibility from a set for the treatment of facility shared of the treatment facility 340 of Figure 13 h.
In Figure 29 e, use that cream printing, transfer molding, fluid sealant are shaping, vacuum lamination, rotary coating or other suitable applicators deposit sealant or mold compound 644 on semiconductor element 604 and carrier 630.Sealant 644 can be polymer composites, the epoxy resin such as with filler, the epoxy acrylate with filler or have the polymer of suitable filler.Sealant 644 is non-conductive and environmentally protects semiconductor device to avoid outside element and pollutant.In another embodiment, sealant 644 is insulating barrier or dielectric layer, it contains use printing, rotary coating, spray application, there is or not have the dielectric resist that the vacuum of heating or pressure lamination or other suitable technique carry out the photosensitive low curing temperature of one or more layers of deposit, photosensitive compound resist, lamination compound film, there is the insulating paste of filler, solder mask resist film, liquid or granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg or there is other dielectric substance of similar insulating property (properties) and structural property.In one embodiment, sealant 644 is the photosensitive dielectrical polymers of low-temperature setting, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.
Especially, sealant 644 is set to along base substrate side surface 622.Sealant 644 also covers the backside surface 610 of semiconductor element 604.In one embodiment, sealant 644 is opaque, and is dark-coloured in color or black.Sealant 644 can be used to the panel 640 of laser labelling reconstruct to carry out aiming at and splitting.Sealant 644 can be thinned in back face grinding step subsequently.Sealant 644 can also be deposited and makes the backside surface 646 of sealant and the backside surface 610 of semiconductor element 604 coplanar and do not cover backside surface 610.The surface 648 of the sealant 644 relative with back surface 646 is arranged on above carrier 630 and boundary layer 632 so that the surface 648 of sealant 644 can be coplanar with the active surface 612 of semiconductor element 604.
In Figure 29 f, ultraviolet light roasting by chemical etching, mechanical stripping, CMP, mechanical lapping, heat, laser scanning or wet stripping remove carrier 630 and boundary layer 632, to expose the surface 648 of insulating barrier 616, conductive layer 614 and sealant 644.
Such as printing, PVD, CVD, sputtering, the patterning of metallide and chemical plating and metal deposition process is used to form conductive layer 650 on insulating barrier 616 and conductive layer 614.Conductive layer 650 can be Al, Cu, Sn, Ti, Ni, Au, Ag, W or other suitable electric conducting material of one or more layers.The part of conductive layer 650 extends laterally distribute and the electric interconnection of conductive layer 614 again along insulating barrier 616 and with the active surface 612 parallel water level land of semiconductor element 604.Conductive layer 650 is operating as the RDL of the electric signal for semiconductor element 604.Do not extend beyond the area occupied of semiconductor element 604 or do not extend on sealant 644 above the area occupied that conductive layer 650 is formed on semiconductor element 604.In other words, the perimeter region of contiguous with semiconductor element 604 semiconductor element 604 lacks conductive layer 650.In one embodiment, conductive layer 650 be formed on semiconductor element 604 area occupied in and the distance D9 of sidewall 608 at least 1 μm from semiconductor element 604.The part of conductive layer 650 is electrically connected to conductive layer 614.Depend on the connectivity of semiconductor element 604, the other parts of conductive layer 650 electrically share or are electrically isolated.
In Figure 29 g, use PVD, CVD, printing, rotary coating, spray application, silk screen printing or be laminated to formation insulation or passivation layer 660 above insulating barrier 616 and conductive layer 650.Insulating barrier 660 can be SiO2, Si3N4, SiON, Ta2O5, Al2O3 of one or more layers or have other material of similar insulating property (properties) and structural property.In one embodiment, insulating barrier 660 is being less than 200 ° of C and bends down the photosensitive dielectrics polymer of solidification.In one embodiment, insulating barrier 660 is formed on above insulating barrier 616 and semiconductor element 604, and extends beyond the area occupied of semiconductor element 604 and extend 1 μm or larger distance D10 on the surface 648 of sealant 644.Insulating barrier 660 covers interface between semiconductor element 604 and sealant 644 to protect this interface and improve the reliability of device during processing.The etching technics of the photoresist oxidant layer of the part by utilizing patterning of insulating barrier 660 or be removed by LDA, to form the opening exposing conductive layer 650.
Use evaporation, metallide, chemical plating, globule or silk-screen printing technique deposit conductive bump material on conductive layer 650.In one embodiment, utilize globule masterplate deposit bump material, namely do not need mask.Bump material can be have Al, the Sn of optional flux solution, Ni, Au, Ag, Pb, Bi, Cu, solder and combination thereof.Such as, bump material can be the Sn/Pb of congruent melting, high plumbous solder or unleaded solder.Suitable attachment or joint technology is used to join bump material to conductive layer 650.In one embodiment, by more than heating bump material to its fusing point bump material being refluxed to form ball or projection 662.In some applications, projection 662 is refluxed to improve the electrical contact with conductive layer 650 for the second time.Projection 662 can also be joined to conductive layer 650 by compression engagement or hot compression.Projection 662 represents the interconnection structure of a type that can be formed on conductive layer 650.This interconnection structure can also use closing line, conductive paste, stud bumps, miniature projection or other electric interconnections.Before projection is formed or after projection is formed, or laser labelling can be performed after removal carrier 630.
Insulating barrier 660, conductive layer 650 and projection 662 are jointly formed in the lamination type interconnection structure 664 formed above semiconductor element 604 and sealant 644.Alternatively, in the area occupied of semiconductor element 604, lamination type interconnection structure 664 is formed completely.Lamination type interconnection structure 664 can comprise few to a RDL or conductive layer (such as conductive layer 650) and an insulating barrier (such as insulating barrier 660).Before forming projection 662, additional insulating barrier can be formed with RDL on insulating barrier 660 to stride across the electrical connectivity that encapsulation provides additional vertical and level according to the Design and Features of semiconductor element 604.
In Figure 29 h, saw blade or laser cutting tool 670 is utilized semiconductor element 604 to be partitioned into other eWLCSP 672.Split through the panel 640 of sealant 644 by reconstruct.Upon splitting, the part of sealant 644 keeps arranging along the side of semiconductor element 604.EWLCSP 672 stands electric test before it is split or after segmentation.
In Figure 29 i, the eWLCSP 672 with the sealant 644 formed on the backside surface 610 and sidewall 608 of semiconductor element 604 is shown.Semiconductor element 604 is electrically connected to projection 662 for the external interconnect through interconnection structure 664 through conductive layer 614 and 650.The conductive layer of interconnection structure 664 does not extend beyond the area occupied of semiconductor element 604, and therefore forms fan-in encapsulation.In one embodiment, conductive layer 650 be formed on semiconductor element 604 area occupied in and the distance D9 of sidewall 608 at least 1 μm from semiconductor element 604.Insulating barrier 660 covers interface between semiconductor element 604 and sealant 644 to protect this interface and improve the reliability of device during processing.In one embodiment, insulating barrier 660 extends beyond the area occupied of semiconductor element 604 and extend 1 μm or larger distance D10 on the surface 648 of sealant 644.
Sealant 644 remains on above the backside surface 610 of semiconductor element 604 after optional grinding operation.Sealant 644 remains on base substrate side surface 622 above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.Therefore, sealant 644 is formed on above five sides of semiconductor element 604, namely on four base substrate side surfaces 622 and overleaf above surface 610.Sealant 644 above the backside surface 610 of semiconductor element 604 eliminates the needs of back side protection layer or stratum dorsale laminate, thus reduces the cost of eWLCSP 672.
For eWLCSP 672, the thickness of the sealant 644 above base substrate side surface 622 is less than 150 μm.In one embodiment, eWLCSP 672 has 4.595 mm(length) × 4.025 mm(width) × 0.470 mm(height) size, wherein the pitch of projection 662 is 0.4 mm, and wherein semiconductor element 294 has the length of 4.445 mm and the width of 3.875 mm.In another embodiment, the thickness of the sealant 644 above base substrate side surface 622 is 75 μm or less.EWLCSP 672 has 6.075 mm(length) × 6.075 mm(width) × 0.8 mm(height) size, wherein the pitch of projection 662 is 0.5 mm, and wherein semiconductor element 604 has 6.0 mm(length) × 6.0 mm(width) × 0.470 mm(height) size.In yet another embodiment, eWLCSP 672 has 5.92 mm(length) × 5.92 mm(width) × 0.765 mm(height) size, wherein the pitch of projection 662 is 0.5 mm, and wherein semiconductor element 604 has 5.75 mm(length) × 5.75 mm(width) × 0.535 mm(height) size.In another embodiment, the thickness of the sealant 644 above base substrate side surface 622 is 25 μm or less.In yet another embodiment, the thickness of the sealant 644 above base substrate side surface 622 is approximate 50 μm or less.On standardized carrier 630, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 672 by using, which reducing the cost of equipment for eWLCSP 672 and material.Use standardized carrier 630 with higher volume to manufacture eWLCSP 672, thus simplified manufacturing technique and reduce unit cost.
Figure 30 segmentation is shown after there is the sealant 644 above sidewall 608 and there is the eWLCSP 674 of dorsal part insulating barrier 676.Semiconductor element 604 is electrically connected to projection 662 for the external interconnect through interconnection structure 664 through conductive layer 614 and 650.The conductive layer of interconnection structure 664 does not extend beyond the area occupied of semiconductor element 604, and therefore forms fan-in encapsulation.Insulating barrier 660 covers interface between semiconductor element 604 and sealant 644 to protect this interface and improve the reliability of device during processing.
The backside surface 610 that dorsal part insulating barrier 676 is formed on semiconductor element 604 is above for mechanical protection with from owing to being exposed to the degeneration produced from light or other photon launched.Dorsal part insulating barrier 676 contains the dielectric resist of the photosensitive low curing temperature of one or more layers, photosensitive compound resist, lamination compound film, the insulating paste with filler, solder mask resist film, liquid molding compound, granular mold compound, polyimides, BCB, PBO, SiO2, Si3N4, SiON, Ta2O5, Al2O3, prepreg or has other dielectric substance of similar insulating property (properties) and structural property.Printing, rotary coating, spray application, the vacuum or do not have with heating or pressure lamination or other suitable technique is used to carry out deposit dorsal part insulating barrier 676.In one embodiment, dorsal part insulating barrier 676 is the photosensitive dielectrical polymers of low-temperature setting, and it has or do not have and is being less than the insulation filler of solidifying under 200 ° of C.Dorsal part insulating barrier 676 is back side protection layer and provides mechanical protection and the impact from light for semiconductor element 604.In one embodiment, dorsal part insulating barrier 676 has the thickness that scope is approximate 5-150 μm.
Sealant 644 covers base substrate side surface 622 and avoids owing to being exposed to the degeneration produced from light or other photon launched to protect semiconductor element 604.For eWLCSP 674, the thickness of the sealant 644 above base substrate side surface 622 is less than 150 μm.In one embodiment, eWLCSP 674 has 4.595 mm(length) × 4.025 mm(width) × 0.470 mm(height) size, wherein the pitch of projection 662 is 0.4 mm, and wherein semiconductor element 604 has the length of 4.445 mm and the width of 3.875 mm.In another embodiment, the thickness of the sealant 644 above base substrate side surface 622 is 75 μm or less.EWLCSP 674 has 6.075 mm(length) × 6.075 mm(width) × 0.8 mm(height) size, wherein the pitch of projection 662 is 0.5 mm, and wherein semiconductor element 604 has 6.0 mm(length) × 6.0 mm(width) × 0.470 mm(height) size.In yet another embodiment, eWLCSP 674 has 5.92 mm(length) × 5.92 mm(width) × 0.765 mm(height) size, wherein the pitch of projection 662 is 0.5 mm, and wherein semiconductor element 604 has 5.75 mm(length) × 5.75 mm(width) × 0.535 mm(height) size.In another embodiment, the thickness of the sealant 644 above base substrate side surface 622 is 25 μm or less.In yet another embodiment, the thickness of the sealant 644 above base substrate side surface 622 is approximate 50 μm or less.On standardized carrier 630, forming the wafer of reconstruct for the equipment designed by single standardized carrier dimensions or panel manufactures eWLCSP 674 by using, which reducing the cost of equipment for eWLCSP 674 and material.Use standardized carrier 630 with higher volume to manufacture eWLCSP 674, thus simplified manufacturing technique and reduce unit cost.
Although illustrated one or more embodiment of the present invention in detail, those skilled in the art will recognize that and can make the amendment of these embodiments and adaptive and do not depart from scope of the present invention illustrated in the appended claims.

Claims (15)

1. make a method for semiconductor device, comprising:
There is provided carrier, described carrier comprises fixed dimension; And
Face arranges multiple first semiconductor element on the carrier, and the fixed dimension of described carrier is independent of the size of described first semiconductor element.
2. the described method of claim 1, comprises further:
There is provided the first semiconductor crystal wafer, described first semiconductor crystal wafer comprises described multiple first semiconductor element; And
By described first semiconductor crystal wafer segmentation to be separated described first semiconductor element, the number of the first semiconductor element that wherein said carrier is arranged above is independent of the number of the first semiconductor element split from described first semiconductor crystal wafer.
3. the described method of claim 2, comprises further:
There is provided the second semiconductor crystal wafer, described second semiconductor crystal wafer comprises multiple second semiconductor element;
Described second semiconductor crystal wafer segmentation is separated described second semiconductor element; And
Face arranges the second semiconductor element on the carrier, and the number of the second semiconductor element that wherein said carrier is arranged above is independent of the number of the second semiconductor element split from described second semiconductor crystal wafer.
4. the described method of claim 1, is included in further above described carrier and arranges the second semiconductor element, and the fixed dimension of described carrier is independent of the size of described second semiconductor element.
5. the described method of claim 1, is included in further above described carrier and arranges the second semiconductor element, and described second semiconductor element comprises the size different from the size of described first semiconductor element.
6. make a method for semiconductor device, comprising:
Semiconductor element is provided;
On described semiconductor element and around described semiconductor element, deposit sealant forms the panel of reconstruct;
On the panel of described reconstruct, form interconnection structure, make described sealant lack described interconnection structure simultaneously; And
Through sealant, the panel of described reconstruct is split.
7. the described method of claim 6, comprises further:
There is provided carrier, described carrier comprises the fixed dimension of the size independent of described semiconductor element; And
Face arranges described semiconductor element on the carrier.
8. the described method of claim 7, comprises further:
There is provided semiconductor crystal wafer, described semiconductor crystal wafer comprises multiple semiconductor element; And
The segmentation of described semiconductor crystal wafer is separated described semiconductor element, and the number of the semiconductor element that wherein said carrier is arranged above is independent of the number of the semiconductor element on described semiconductor crystal wafer.
9. the described method of claim 6, wherein removes described sealant by the segmentation of the panel of described reconstruct completely through sealant from the side of described semiconductor element.
10. the described method of claim 6, wherein through sealant, the segmentation of the panel of described reconstruct is left the part of sealant, the part of described sealant covers the side of described semiconductor element.
The described method of 11. claims 6, comprises further:
Described sealant is removed from the surface of the semiconductor element relative with active surface; And
Insulating barrier is formed on the surface of described semiconductor element.
12. 1 kinds of semiconductor device, comprising:
Semiconductor element;
Sealant, is deposited on above described semiconductor element and in the perimeter region contiguous with described semiconductor element; And
Interconnection structure, be formed in above described semiconductor element, described perimeter region lacks described interconnection structure.
The described semiconductor device of 13. claims 12, wherein said sealant is arranged on above the side surface of described interconnection structure.
The described semiconductor device of 14. claims 12, wherein said sealant covers the side of described semiconductor element.
The described semiconductor device of 15. claims 14, the described sealant wherein covering the side of described semiconductor element has 150 microns (μm) or less thickness.
CN201410741338.2A 2013-12-05 2014-12-05 Semiconductor device and method of using a standardized carrier in semiconductor packaging Pending CN104701194A (en)

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Application publication date: 20150610