TWI427717B - A method of flip chip package - Google Patents

Description

Flip chip packaging method

The present invention generally relates to a method of fabricating a semiconductor device package, and more particularly to a method of packaging a flip chip of a power device.

In advanced chip packaging, Wafer Level Chip Scale Packaging is the first package and test on a whole wafer, and covers one side of the wafer with polyimide material before cutting it. The individual IC package particles, so the volume of the package is almost equal to the original size of the bare die, the package has good heat dissipation and electrical parameter performance.

Often, one of the most important steps in a complex process flow for wafer level packaging is to thin the wafer to a certain thickness. The thinner the wafer, the easier it is to break. This requires that any form of damage to the wafer be avoided in any process step. For example, wafer cutting can easily cause cracking at the edge of the wafer. One of the consequences That is, the bad wafer obtained is not angled.

On the other hand, a package called a Flat Bump Package (FBP) is currently prepared by the process flow shown in FIG. 1A-1I.

1A is a lead frame 100 including a contact terminal 101 and a pad 102, as shown in FIG. 1B-1C, soldering the wafer 110 to the pad 102 through a conductive material 103, and The electrode connecting the internal circuit of the wafer 110 is electrically connected to the contact terminal 101 through the bonding wire 104 as shown in FIG. 1D. After that, the wafer 110 and the bonding wires 104 are molded by the molding compound 120, and the lead frame 100 is etched, so that the obtained contact terminals 101 and pads 102 are exposed to the molding compound 120 as shown in FIG. 1E-1F. Then, the outer surface of the contact terminal 101 and the pad 102 is plated with a layer of gold to form a gold plating layer 105, as shown in FIG. 1G; finally, a film 130 is adhered to the top surface of the molding body, and the molding compound 120 is cut to complete the molding. The body 120' plastic encapsulates the package 150 of the coated wafer 110 and the bonding wires 104, as shown in FIG. 1H-1J.

The pad 102 is used as a heat sink or an electrode, and the contact terminal 101 and the pad 102 are both soldered to a substrate such as a printed circuit board PCB and connected to an external circuit. The pad 102 is generally bulky because it is to carry the wafer 110; the bonding wires such as the bonding wires 104 are prone to negative effects of discrete inductance, and the bonding wires 104 are guaranteed to have a certain arc height, which is also It is not conducive to reducing the thickness of the molded body 120'. The size and electrical performance of the package 150 shown in FIG. 1J are not satisfactory.

As such, the present application is based on the following considerations: first, the wafer is packaged and then thinned, so that the package obtained after the wafer is packaged has a better size, and has good heat dissipation and electrical parameter performance; In the process, efforts are made to reduce the risk of chip cornering and to obtain a thinner wafer thickness.

In view of the above problems, the present invention provides a flip chip packaging method comprising the steps of: providing a lead frame on which a plurality of interconnecting guide rods protruding from a top surface of the lead frame are disposed; Soldering a wafer having a bonding pad disposed on the front surface thereof to the lead frame, wherein the bonding pad is soldered to the interconnecting lead; molding is performed on a top surface of the lead frame to form a plastic sealing material Coating the wafer and the interconnecting guide rod; etching the lead frame on the bottom surface of the lead frame to form a contact terminal connected to the interconnecting guide rod and protruding from the bottom surface of the molding compound; and providing a metal protective layer on the surface of the contact terminal Laying a film to the top surface of the thinned molding compound; cutting the molding compound and removing the film to form a plurality of packages that encapsulate the wafer with a plastic molding body.

The above method, wherein the bonding pad is soldered to the interconnecting lead by a conductive material coated on an interconnecting guide.

The above method, wherein the bonding pad is eutectic soldered to the interconnecting lead by a conductive material plated on the interconnecting lead and a metal plating plated on the bonding pad.

The above method further comprises the steps of: grinding the thinned molding compound and the wafer after the wafer molding, and exposing the back surface of the thinned wafer to the top surface of the thinned molding compound.

The above method, further comprising the step of depositing a back metal layer to the back side of the thinned wafer.

The above method, wherein before depositing a back metal layer to the back side of the thinned wafer, the following process steps are performed on the back side of the thinned wafer: etching is performed; And ion implantation and laser annealing are performed.

The above method, wherein the contact terminal protrudes beyond the bottom surface of the molding body, and the back metal layer is exposed on the top surface of the molding body.

In the above method, in one embodiment, the wafer is a metal oxide semiconductor field effect transistor, and the bonding pad comprises at least a gate bonding pad constituting a gate electrode of the wafer and a source electrode constituting the wafer. The source bonds the pads and the back metal layer constitutes the drain electrode of the wafer.

And further bonding the package to a pedestal, wherein the back metal layer is adhered to the pedestal through the conductive material, and the contact terminal connecting the gate bonding pad is electrically connected to the base through a metal conductor On the gate pad around the socket, the contact terminal connected to the source bonding pad is electrically connected to the source pad disposed around the pedestal through another metal conductor; and an electrical connection is also disposed around the pedestal To the drain pad of the pedestal.

In the above method, in an alternative embodiment, the wafer is a conjugated bimetal oxide semiconductor field effect transistor, wherein the back metal layer constitutes a conjugated bimetal oxide semiconductor field effect transistor The first and second MOSFETs of the first and second MOSFETs are included; and the first and second MOSFETs are electrically connected to each other through the back metal layer.

And, the bonding pad comprises at least a first gate bonding pad constituting the first metal oxide semiconductor field effect transistor gate electrode, and a first source constituting the first metal oxide semiconductor field effect transistor source electrode a pole bonding pad; and the bonding pad further comprises a second metal oxide semiconductor field effect transistor a second gate bonding pad of the gate electrode, and a second source bonding pad constituting the second metal oxide semiconductor field effect transistor source electrode.

In the above method, in an alternative embodiment, the wafer is a high-side metal oxide semiconductor field effect transistor and a low-end metal oxide semiconductor field effect transistor integrated bimetal oxide semiconductor field effect transistor, wherein The back metal layer constitutes a source electrode of a high side metal oxide semiconductor field effect transistor and a drain electrode of a low side metal oxide semiconductor field effect transistor; and a source electrode of the high side metal oxide semiconductor field effect transistor and The drain electrodes of the low-end metal oxide semiconductor field effect transistor are electrically connected to each other through the back metal layer.

And, the bonding pad comprises at least a first gate bonding pad constituting a gate electrode of the high side metal oxide semiconductor field effect transistor, and a first gate key constituting the drain electrode of the high side metal oxide semiconductor field effect transistor And the bonding pad further comprises a second gate bonding pad constituting the low-end MOSFET field-effect transistor gate electrode, and constituting the low-end MOSFET field-effect transistor source electrode The second source is bonded to the pad.

In the above method, in an alternative embodiment, the wafer is a conjugated bimetal oxide semiconductor field effect transistor, wherein the back side of the wafer constitutes a conjugated bimetal oxide semiconductor field effect transistor Including the respective drains of the first and second metal oxide semiconductor field effect transistors; and optionally, a back metal layer is disposed on the back surface of the wafer, the first and second metal oxide semiconductor field effect transistors Crystals each of the drain electrodes pass through the back metal The layers are electrically connected to each other.

In the above method, in an alternative embodiment, the wafer is a high-side metal oxide semiconductor field effect transistor and a low-end metal oxide semiconductor field effect transistor integrated bimetal oxide semiconductor field effect transistor, wherein The back side of the wafer constitutes a source electrode of a high side metal oxide semiconductor field effect transistor and a drain electrode of a low side metal oxide semiconductor field effect transistor; and optionally, a back metal layer is disposed on the back side of the wafer The source electrode of the high side metal oxide semiconductor field effect transistor and the drain electrode of the low side metal oxide semiconductor field effect transistor are electrically connected to each other through the back metal layer.

These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

205, 305‧‧‧ metal protective layer

101, 200', 300'‧‧‧ contact terminals

120, 220', 320'‧‧‧ plastic enclosure

201, 301‧‧‧Interconnecting guides

203‧‧‧Electrical materials

250, 350‧‧‧ package

110, 210, 310‧‧‧ wafers

210b, 210c, 310b‧‧‧ back

211, 311‧‧‧ back metal layer

210a, 310a‧‧‧ positive

200a, 220'c, 220a, 220c, 320a, 320'a‧‧‧ top

200b, 220'b, 220b, 320b, 320'b‧‧‧ bottom

100, 200, 300‧‧‧ lead frame

102‧‧‧ pads

103‧‧‧Electrical materials

104‧‧‧bonding wire

150, 250‧‧‧ package

120, 220, 320‧‧‧ molding materials

105‧‧‧ gold plating

130, 230, 330‧‧‧ film

220d, 320d‧‧‧ cutting trough

212‧‧‧Source Bonding Pad

213‧‧‧Gate Bonding Pads

212A, 213A, 312A, 313A, 314A, 315A‧‧‧ dotted box

200'a‧‧‧Source contact terminal

200'b‧‧‧gate contact terminal

240‧‧‧Base

240a‧‧‧Source pad

240b‧‧‧Gate pad

240c‧‧‧汲pad

250'‧‧‧ secondary package

251, 252‧‧‧ metal pieces

251a, 252a‧‧‧ bends

312‧‧‧First bungee bonding pad

313‧‧‧First Gate Bonding Pad

314‧‧‧Second source bond pad

315‧‧‧Second gate bonding pad

300'a‧‧‧First bungee contact terminal

300'b‧‧‧first gate contact terminal

300'c‧‧‧Second source contact terminal

300'd‧‧‧second gate contact terminal

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.

1A-1J is a schematic diagram of a preparation flow of a planar bump package in the background art.

2A-2K is a schematic view showing a preparation flow of the package of the present application.

3A-3D are schematic views showing a preparation flow of another embodiment of the package of the present application.

Figure 4 is a schematic top plan view of the MOSFET of the present application before it is packaged.

FIG. 5 is a schematic top plan view of the package after the MOSFET of the present application is packaged.

Figure 6 is a schematic top plan view showing the package being bonded to a pedestal.

FIG. 7 is a schematic top plan view showing the gate bonding pad and the source bonding pad electrically connected to the gate pad and the source pad respectively by the bent metal piece.

8A-8F are schematic diagrams showing the preparation process of another chip package of the present application.

Figure 9 is a schematic top plan view of the dual MOSFET of the present application before being packaged.

FIG. 10 is a schematic top plan view of the dual MOSFET after the package is completed.

Referring to FIG. 2A, the top surface 200a of the lead frame 200 is provided with a plurality of interconnecting guides 201, wherein the interconnecting guides 201 protrude from the top surface 200a of the lead frame 200, the lead frame 200, and the interconnecting guide 201 Metallic copper can be used. As shown in FIG. 2A-2C, a layer of conductive material 203 is first disposed on the interconnecting lead 201, and the wafer 210 is flip-chip bonded to the lead frame 200 through the conductive material 203.

The front surface 210a of the wafer 210 is usually provided with a bonding pad that is electrically connected to the outside. The bonding pad is generally used as an input/output contact terminal (I/O Pad) of the internal circuit of the chip 210, and can be used as a signal. Input/output, or the interface between Power and Ground. Taking the wafer structure of a metal oxide semiconductor field effect transistor shown in FIG. 4 as an example, the bonding pad provided on the front surface 210a of the wafer 210 includes at least a gate bonding pad 213 constituting the gate electrode of the wafer 210, a source bonding pad 212 constituting a source electrode of the wafer 210; wherein the gate bonding pad 213 contacts a gate region not shown by the wafer 210, and the source bonding pad 212 contacts a source region not shown by the wafer 210 . In one embodiment, the back side 210b of the wafer 210 is provided with a germanium region, not shown. In this embodiment, the wafer 210 is a vertical power device.

Referring to FIG. 2C, the wafer 210 on which the front surface 210a is provided with a bonding pad (not shown) is flip-chip bonded to the lead frame 200, wherein the bonding pads are soldered to the interconnecting guide 201. For example, the source bond pad 212 and the gate bond pad 213 in FIG. 4 are soldered to the interconnecting lead 201. There are a variety of welding processes to choose from, one embodiment is by coating on the interconnecting guide 201 The conductive material 203 solders the bonding pad to the interconnecting lead 201, and the conductive material 203 can be selected from any one of solder paste, conductive silver paste or conductive film. Another embodiment is to bond the lining by a conductive material 203 plated on the interconnecting conductor 201 and a metal plating (not shown) plated on the source bonding pad 212 and the gate bonding pad 213. The pads (source bond pads 212, gate bond pads 213) are eutectic soldered to the interconnecting leads 201. At this time, the conductive material 203 may be plated with gold or silver, plated with the source bond pads 212, and gated. The metal plating on the pole bonding pad 213 may be an alloy material such as pure tin (Sn) or gold tin (AuSn), gold bismuth (AuSi) or gold bismuth (AuGe) for contact surface plating, when the lead frame 200, interconnect When the guide rod 201 is heated to a suitable eutectic temperature, the gold or silver element penetrates into the metal plating layer, and the change of the melting point is related to the alloy layer composition of the metal plating layer, so that the eutectic layer of the metal plating layer is cured and the source bonding pad is bonded. 212. Welding of the grid bonding pads 213 to the interconnecting guide bars 201.

As shown in FIG. 2D, the top surface 200a of the lead frame 200 is plastically encapsulated, and the packaged substrate 210 and the interconnecting guide 201 are molded by the molding compound 220. The voids around the wafer 210 are filled with the molding compound 220. At this time, the plastic package is filled. The bottom surface 220b of the material 220 is bonded to the top surface 200a of the lead frame 200, and the molding compound 220 is usually an epoxy molding compound.

Referring to FIG. 2E, after the molding process is completed in FIG. 2D, the top surface 220a of the molding compound 220 is ground until the wafer 210 is exposed in the molding compound 220. One of the advantages of the grinding process is that since the wafer 210 is surrounded by the molding compound 220 and is not easily broken during the thinning process, the wafer 210 can obtain 6 mils, 4 mils, 2 mils. Even thinner thickness. At this time, the molding compound 220 and the wafer 210 are both ground and thinned to obtain the back surface 210c of the thinned wafer 210 exposed in the top surface 220c of the thinned molding compound 220; and the crotch portion of the wafer 210 It is ground and its thickness is also reduced. In FIG. 2E, an optional step is to perform etching on the back surface 210c of the thinned wafer 210, such as wet etching, to remove the after polishing. The stress layer remaining on the back surface 210c of the wafer 210 repairs the lattice damage caused by the back surface 210c of the thinned wafer 210 during the polishing process; thereafter, ion implantation is performed on the back surface 210c of the thinned wafer 210, and Some low-level annealing or laser annealing is used after ion implantation to eliminate some of the lattice defects generated in the back surface 210c of the thinned wafer 210. In FIG. 2F, a back metal layer 211 (such as an alloy of Ti/Ni/Ag) is deposited onto the back surface 210c of the thinned wafer 210. In the embodiment of FIG. 4, the wafer 210 is a MOSFET, and the back side The metal layer 211 electrically contacts the germanium region of the wafer 210 and constitutes the drain electrode of the wafer 210.

Referring to FIG. 2F-2G, the lead frame 200 is etched on the bottom surface 200b of the lead frame 200, and the lead frame 200 can be etched using a hard mask not shown in the drawing, leaving only the second FF and the interconnect guide. The contact terminal 200' to which the rod 201 is connected, wherein the contact terminal 200' is originally a part of the lead frame 200. Thereby, a contact terminal 200' which is connected to the interconnecting guide 201 and protrudes from the bottom surface 220b of the molding compound 220 is formed as shown in Fig. 2G. After that, as shown in FIG. 2H, a metal protective layer 205 is disposed on the surface of the contact terminal 200', such as a metal protective layer 205. The material of the metal protective layer 205 has various options, such as Ti/Ni/Au. alloy.

Referring to FIG. 2I-2J, a film 230 is adhered to the top surface 220c of the thinned molding compound 220. The film 230 functions as a dicing film, and may be a UV tape or a blue film. Then, the plastic seal 220 is cut, and the cutting groove 220d shown in FIG. 2J is the mark left by the cutting blade cutting plastic seal 220, and the wafer 210 for completing all the packaging process processes described above is removed from the molding compound. 220 off. During this process, the film 230 may optionally be partially cut in the longitudinal direction but not completely cut. After the cutting molding material 220 is completed, the molding compound 220 is cut into a plurality of molding bodies 220' as shown in FIG. 2K, and the film 230 is removed from the top surface 220'c of the molding body 220', thereby forming a plurality of plastic sealing bodies. The package 250 of the coated wafer 210 is plastically sealed. in In the package body 250, the back metal layer 211 is exposed on the top surface 220'c of the molding body 220', and the contact terminal 200' provided with the metal protection layer 205 on the surface protrudes from the bottom surface 220'b of the molding body 220'.

According to the above, in an embodiment, the following steps may be included: Step 1: provide a lead frame, and set a plurality of interconnecting guide rods protruding from the top surface of the lead frame on the lead frame; Step 2: set the front side a wafer with a bonding pad is flip-chip bonded to the lead frame, wherein the bonding pad is soldered to the interconnecting lead; step 3: molding the top surface of the lead frame to form a plastic molding compound Coating the wafer and the interconnecting guide rod; Step 4: grinding the thinned molding compound and the wafer, and exposing the back surface of the thinned wafer to the top surface of the thinned molding compound; Step 5: depositing a back surface a metal layer to the back side of the thinned wafer; Step 6: etching the lead frame on the bottom surface of the lead frame to form a contact terminal connected to the interconnecting guide bar and protruding from the bottom surface of the molding compound; Step 7: at the contact terminal A metal protective layer is disposed on the surface; Step 8: attaching a film to the top surface of the thinned molding compound; Step 9: cutting the molding compound and removing the film to form a plurality of packages for molding the wafer with the plastic sealing body.

The wafer may be a single transistor wafer as shown in FIG. 4 or a dual transistor wafer as shown in FIG.

In order to obtain the package 250 shown in FIG. 2K, other embodiments may be implemented. For example, after the process preparation process shown in FIG. 2D has been completed, the 3A-3D image is implemented. The package 250 can also be obtained by a process preparation process. In FIG. 3A, the etched lead frame 200 in the 2D drawing is etched first, and the lead frame 200 is etched on the bottom surface 200b of the lead frame 200, leaving only the contact terminal 200' connected to the interconnecting guide 201 in FIG. 3A. Wherein, the contact terminal 200' is originally a part of the lead frame 200, thereby forming a contact terminal 200' which is connected to the interconnecting guide 201 and protrudes from the bottom surface 220b of the molding compound 220, as shown in FIG. 3B. The top surface 220a of the molding compound 220 is then ground until the wafer 210 is exposed in the molding compound 220. At this time, both the molding compound 220 and the wafer 210 are ground and thinned, and the back surface 210c of the thinned wafer 210 is exposed in the top surface 220c of the thinned molding compound 220, and the thickness of the crucible region of the wafer 210 is simultaneously exposed. Also reduced. In FIG. 3C, an optional step is to perform etching on the back surface 210c of the thinned wafer 210, such as wet etching, to remove the stress layer remaining on the back surface 210c of the wafer 210 after the polishing, and repair the polishing process. Lattice damage caused by the back surface 210c of the wafer 210; subsequent ion implantation is performed on the back surface 210c of the wafer 210, and after ion implantation, low temperature annealing or laser annealing is used to eliminate some lattices generated in the back surface 210c of the wafer 210. defect. Thereafter, in FIG. 3D, a back metal layer 211 (such as an alloy of Ti/Ni/Ag) is deposited onto the back surface 210c of the thinned wafer 210. In the embodiment of FIG. 4, the wafer 210 is a MOSFET. The back metal layer 211 electrically contacts the germanium region of the wafer 210 and constitutes the drain electrode of the wafer 210. Comparing the 3D and 2G, the structure of the two is not different, but the production process steps are different. After the preparation process of the 3D drawing is completed, the preparation process of the 2H-2K drawing is taken, and the package 250 can also be obtained.

According to the above, in an embodiment, the following steps may be included: Step 1: provide a lead frame, and set a plurality of interconnecting guide rods protruding from the top surface of the lead frame on the lead frame; Step 2: set the front side a wafer with a bonding pad is flip-chip bonded to the lead frame, The bonding pad is soldered to the interconnecting lead; step 3: molding the top surface of the lead frame, and molding the wafer and the interconnecting guide with a plastic molding; step 4: in the lead frame The bottom surface etches the lead frame to form a contact terminal connected to the interconnecting guide bar and protruding from the bottom surface of the molding compound; Step 5: grinding and thinning the molding compound and the wafer, and thinning the back surface of the wafer to the thinned molding compound The top surface is exposed; step 6: depositing a back metal layer to the back side of the thinned wafer; step 7: providing a metal protective layer on the surface of the contact terminal; step 8: pasting a film to thinning The top surface of the molding compound; Step 9: Cutting the molding compound and removing the film to form a plurality of packages that are plastically encapsulated to cover the wafer.

The wafer may be a single transistor wafer as shown in FIG. 4 or a dual transistor wafer as shown in FIG.

In the fourth drawing, the wafer 210 is a schematic plan view of the original wafer, and FIG. 5 is a schematic plan view of the package 250 obtained by performing the process flow of the wafer 210 of FIG. 4 on the 2A-2K or 3A-3D. Comparing the cross-sectional view of the package 2 of FIG. 2K and the top view of the package 250 of FIG. 5, the back metal layer 211 exposed on the top surface 220'c of the molded body 220' is not shown in FIG. 5, and The contact terminal 200' provided with the metal protective layer 205 in FIG. 2A includes at least the source contact terminal 200'a and the gate contact terminal 200'b in FIG. 5, wherein the metal protective layer 205 is not added in FIG. Label. In FIG. 5, the contact terminals 200' in the range of the broken line frame 212A are all the source contact terminals 200'a, and the contact terminals 200' in the range of the broken line frame 213A are the gate contact terminals 200'b; The source bonding pad 212 and the gate bonding pad 213 are not shown after being covered by the molding material 220' in FIG. 5, and the position of the broken line frame 212A is directly above the source bonding pad 212. The position of the broken line frame 213A is directly above the gate bonding pad 213, so the source contact terminals 200'a are electrically connected to the source bonding pad 212 through the interconnecting guide 201, and the gate contact terminal 200 'b is electrically connected to the gate bonding pad 213 through the interconnecting guide 201 (refer to FIG. 2K).

One of the uses of the package 250 is to perform secondary packaging as a carrier of the wafer 210. As shown in FIG. 6, the package 250 in FIG. 5 is bonded to the susceptor 240 by a conductive material (such as solder paste, conductive silver paste), and the back metal layer 210 (not shown) passes through the conductive material and the pedestal. The bumps of the wafer 210 are electrically connected to the susceptor 240. The susceptor 240 is further provided with a drain pad 240c electrically connected to the susceptor 240. In order to obtain the secondary package 250' as shown in FIG. 7, the gate contact terminal 200'b is further electrically connected to the gate pad 240b disposed around the susceptor 240 through a bent metal piece 252. The bent portion 252a of the metal piece 252 is soldered to the gate pad 240b, that is, the contact terminal 200' connecting the gate bonding pad 213 is electrically connected to the gate pad 240b through the metal piece 252; The source contact terminal 200'a is electrically connected to the source pad 240a disposed around the susceptor 240 through another bent metal piece 251, that is, the contact terminal 200 connected to the source bonding pad 212. 'The metal piece 251 is electrically connected to the source pad 240a, wherein the bent portion 251a of the metal piece 251 is soldered to the source pad 240a. When the source pad 240a, the gate pad 240b, and the drain pad 240c are coplanar, the secondary package 250' can be molded again, and the source pad 240a, the gate pad 240b, and the drain pad 240c are used as The pins are respectively connected to the external circuit, and are respectively embodied as the source, the gate and the drain of the wafer 210. The metal sheets 251 and 252 may be replaced by metal leads, metal strips or other metal conductors for semiconductor packaging.

In another embodiment, both the molding compound and the wafer do not require abrasive thinning. See The preparation flow illustrated in Figures 8A-8F, it should be noted that the preparation of the 2A-2D pattern can obtain the structure shown in Figure 8A. The wafer used may be a dual MOSFET structure wafer as shown in Fig. 9 or any wafer without an electrode at the bottom or any bottom electrode without being exposed. The preparation flow of the 8A-8F diagram is illustrated by the wafer 310 shown in FIG. 9. One alternative wafer type of the wafer 310 is a high side metal oxide semiconductor field effect transistor and a low side metal oxide semiconductor field effect transistor integration. The bimetal oxide semiconductor field effect transistor device, for example, the first metal oxide semiconductor field effect transistor in FIG. 9 is a high side metal oxide semiconductor field effect transistor, and the second metal oxide semiconductor field effect transistor is low. End metal oxide semiconductor field effect transistor. The back side 310b of the wafer 310 in Fig. 9 originally has a back metal layer 311. In an alternative embodiment, the back side 310b of the wafer 310 does not have a back metal layer 311. The front surface 310a of the wafer 310 is provided with a bonding pad. As shown in FIG. 9, the bonding pad includes at least a first gate bonding pad 313 constituting the first metal oxide semiconductor field effect transistor gate electrode. a first gate bond pad 312 of a metal oxide semiconductor field effect transistor drain electrode, wherein the first gate bond pad 313 electrically contacts a gate region of the first metal oxide semiconductor field effect transistor, The first drain bond pad 312 electrically contacts the germanium region of the first metal oxide semiconductor field effect transistor; and the bond pad further includes a second gate constituting the gate electrode of the second metal oxide semiconductor field effect transistor a pole bonding pad 315, a second source bonding pad 314 constituting a second metal oxide semiconductor field effect transistor source electrode, wherein the second gate bonding pad 315 electrically contacts the second metal oxide A gate region of the semiconductor field effect transistor, the second source bond pad 314 electrically contacts the source region of the second metal oxide semiconductor field effect transistor. Since the first and second MOSFETs are integrated on the wafer 310, the first and second metal oxides are not clearly labeled separately in FIG. Wherein the source region of the first metal oxide semiconductor field effect transistor is located on the wafer 310 The back surface 310b is in electrical contact with the back metal layer 311, and the second metal oxide semiconductor field effect transistor is located on the back surface 310b side of the wafer 310 and is in electrical contact with the back metal layer 311, and the back metal layer 311 is formed. a source electrode of the first metal oxide semiconductor field effect transistor, a drain electrode of the second metal oxide semiconductor field effect transistor, and a source electrode of the first metal oxide semiconductor field effect transistor The drain electrodes of the second metal oxide semiconductor field effect transistor are electrically connected to each other through the back metal layer 311. When the back surface 310b of the wafer 310 does not have the back metal layer 311, the source region of the first metal oxide semiconductor field effect transistor and the germanium region of the second metal oxide semiconductor field effect transistor pass through the bottom semiconductor substrate on the back side of the wafer. Electrically connected to each other.

The wafer 310 of the above structure has a first MOSFET as a high side or a high side MOSFET (High Side MOSFET) and a second MOSFET as a low side or low side MOSFET (Low Side MOSFET).

In the preparation method of the 2A-2D drawing, the wafer 310 is molded by the molding compound 320. As shown in Fig. 8A, the back metal layer 311 of the wafer 310 is also completely molded. The lead frame 300 is then etched on the bottom surface 300b of the lead frame 300, and the lead frame 300 can be etched using a hard mask not shown in the drawing, leaving only the contact terminal 300' connected to the interconnecting guide 301 in FIG. 8A. The contact terminal 300' is originally part of the lead frame 300. Thereby, a contact terminal 300' is formed which is connected to the interconnecting guide 301 and protrudes from the bottom surface 320b of the molding compound 320. Thereafter, as shown in FIG. 8C, a metal protective layer 305 is disposed on the surface of the contact terminal 300', such as a metal protective layer 305. The material of the metal protective layer 305 has various options, such as Ti/Ni/Au. alloy. In this process, it is not necessary to polish the top surface 320a of the molding compound 320, and it is not necessary to reduce the thickness of the wafer 310. Then, a film 330 is directly pasted to the top surface 320a of the molding compound 320 as shown in FIG. 8D, and the plastic is applied to the plastic The sealing 320 is cut, and the cutting groove 320d as shown in FIG. 8E is a mark left by the cutting for detaching the wafer 310 which completes all of the above packaging processes from the molding compound 320.

After the molding of the molding compound 320 is completed, the molding compound 320 is cut into a plurality of molding bodies 320' as shown in FIG. 8F, and the film 330 is removed from the top surface 320'a of the molding body 320', thereby forming a plurality of plastic sealing bodies. The package 350 of the packaged wafer 310 is plastically sealed. In the package 350, the contact terminal 300' having the surface provided with the metal protective layer 305 protrudes from the bottom surface 320'b of the molded body 320'. FIG. 10 is a top schematic structural view of the package 350 in the 8F view obtained after the wafer 310 of FIG. 9 completes the above packaging process. The contact terminal 300' provided with the metal protective layer 305 in FIG. 8F includes at least the first drain contact terminal 300'a, the first gate contact terminal 300'b, and the second source contact terminal 300' in FIG. c. The second gate contact terminal 300'd, wherein the metal protective layer 305 is not labeled in FIG. In FIG. 10, the contact terminals 300' in the range of the broken line frame 312A are all the first drain contact terminals 300'a, and the contact terminals 300' in the range of the broken line frame 313A are the first gate contact terminals 300'b, The contact terminals 300' in the range of the broken line frame 314A are both the second source contact terminals 300'c, and the contact terminals 300' in the range of the broken line frame 315A are the second gate contact terminals 300'd. The first drain bond pad 312, the first gate bond pad 313, the second source bond pad 314, and the second gate bond pad 315 in FIG. 9 are encapsulated in FIG. The material 320' is not shown after being covered. The position of the broken line frame 312A is directly above the first gate bonding pad 312, and the position of the broken line frame 313A is directly above the first gate bonding pad 313. The position of the dashed box 314A is directly above the second source bond pad 314, while the position of the dashed box 315A is directly above the second gate bond pad 315. Therefore, the first gate contact terminals 300'a are electrically connected to the first drain bond pads 312 through the interconnecting guides 301, and the first gate contact terminals 300'b are each connected through the interconnecting guides 301 and the first The gate bonding pad 313 is electrically connected (refer to FIG. 8F), and the second source contact terminal 300'c passes through the interconnecting guide 301 and the second The source bonding pads 314 are electrically connected, and the second gate contact terminals 300 d are electrically connected to the second gate bonding pads 315 through the interconnecting guides 301.

Another alternative wafer type of wafer 310 in Figure 9 is a common drain dual MOSFET device. Wherein the gate region and the source region of the first and second MOSFETs are located on one side of the front surface 310a of the wafer 310, and the germanium regions of the first and second MOSFETs are located The back side 310b of the wafer 310 is in electrical contact with the back metal layer 311. The bonding pad disposed on the front surface includes at least a first gate bonding pad constituting the gate electrode of the first metal oxide semiconductor field effect transistor, and a first electrode constituting the source electrode of the first metal oxide semiconductor field effect transistor. a source bonding pad; and a second gate bonding pad constituting the gate electrode of the second metal oxide semiconductor field effect transistor, and a second electrode constituting the source electrode of the second metal oxide semiconductor field effect transistor Source bond pad. The back metal layer 311 constitutes a drain electrode of the first and second metal oxide semiconductor field effect transistors included in the wafer 310; and the drain electrode of the first and second metal oxide semiconductor field effect transistors passes through the back metal The layers 311 are electrically connected to each other. When the back surface 310b of the wafer 310 does not have the back metal layer 311, the germanium regions of the first and second metal oxide semiconductor field effect transistors are electrically connected to each other through the semiconductor substrate on the back surface of the wafer. In other words, in the ninth embodiment, in the embodiment in which the above-mentioned wafer 310 is a dual MOSFET integrated with a high-side MOSFET and a low-side MOSFET, its first gate bonding pad 313 is a common-drain double MOSFET on the wafer 310. a first gate bond pad that is converted to a common drain MOSFET in an embodiment; its first drain bond pad 312 is converted to a common drain dual MOSFET in an embodiment where the die 310 is a common drain dual MOSFET a first source bonding pad; the second source bonding pad 314 is conjugated on the wafer 310 The embodiment of the pole dual MOSFET is converted to a second source bond pad of the common drain double MOSFET; the second gate bond pad 315 is converted to a common embodiment in which the die 310 is a common drain dual MOSFET The second gate bonding pad of the bungee double MOSFET.

The package 350 in FIG. 10 is different from the package 250 in FIG. 5. The package 350 does not need to be additionally provided with the metal sheets 251, 252 in FIG. 7 to design the input/output contact terminals on one side of the wafer. The contact terminal 300' of the package body 350 can be directly mounted on other substrates such as a PCB. Therefore, as shown in FIG. 9, if the input/output bonding pads of the internal circuit of the wafer 310 are on the side of the front surface 310a of the wafer 310, even if the wafer 310 is not a double MOSFET, the method of the 8A-8F method can be utilized. A package structure similar to the package 350 is prepared.

According to the above, in an embodiment, the following steps may be included: Step 1: provide a lead frame, and set a plurality of interconnecting guide rods protruding from the top surface of the lead frame on the lead frame; Step 2: set the front side a wafer with a bonding pad is flip-chip bonded to the lead frame, wherein the bonding pad is soldered to the interconnecting lead; step 3: molding the top surface of the lead frame to form a plastic molding compound Coating the wafer and the interconnecting guide rod; Step 4: etching the lead frame on the bottom surface of the lead frame to form a contact terminal connected to the interconnecting guide bar and protruding from the bottom surface of the molding compound; Step 5: at the contact terminal A metal protective layer is disposed on the surface; Step 6: attaching a film to the top surface of the molding compound; Step 7: cutting the molding compound and removing the film to form a plurality of packages which are plastically encapsulated and coated with the wafer.

In the above process flow, the back thinning of the wafer is performed based on fixing the wafer in the molding compound, so that the wafer does not easily collapse and not be cut even if it is maintained at 2 mil or even thinner, so the final wafer that completes the packaging maintains a comparison. High level of yield, which is difficult to achieve in a typical wafer level package.

In the above process, the contact terminals are made by etching the back surface of the lead frame, and one of the beneficial effects is that the absolute coplanarity of the contact terminals is ensured, and the bump-like pin design of the contact terminals makes the use of solder paste The contact terminals are simpler and stronger when soldered to the board to ensure good bonding with the PCB. In addition to the advantages of high-purity copper material, the contact terminal has a special heat-dissipating capability, and the special structure of the connection with the bonding pad determines that the package can also indirectly dissipate heat through the contact terminal gap, and the overall heat dissipation effect is good. On the other hand, in the background art, the pad 102 shown in FIG. 1C must be kept in a size similar to that of the wafer 110, so that when the wafer 110 is eutectic soldered on the pad 102, the wafer 110 is present. The potential danger of cracking, while the present invention replaces the pad 102 with a plurality of discrete contact terminals, this defect can be effectively avoided.

Exemplary embodiments of specific structures of the specific embodiments are given by way of illustration and the accompanying drawings. For example, the present invention is illustrated by MOSFETs, dual MOSFETs, and other types of conversions can be made based on the spirit of the present invention. Although the above invention proposes a prior preferred embodiment, these are not intended to be limiting.

Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are to cover all such modifications and modifications Any and all equivalent ranges and contents within the scope of the claims are considered to be within the spirit and scope of the invention.

205‧‧‧ metal protective layer

200'‧‧‧Contact terminal

220'‧‧‧plastic body

201‧‧‧Interconnecting guides

203‧‧‧Electrical materials

250‧‧‧Package

210‧‧‧ wafer

210c‧‧‧Back

211‧‧‧Back metal layer

210a‧‧‧ positive

220'c‧‧‧ top

220'b‧‧‧ bottom

Claims (16)

A flip chip packaging method includes the steps of: providing a lead frame, wherein the lead frame is provided with a plurality of interconnecting guide rods protruding from a top surface of the lead frame; and flipping the wafer with the front surface of the bonding pad Soldering to the lead frame, wherein the bonding pad is soldered to the interconnecting lead; plastic molding is performed on a top surface of the lead frame, and the wafer and the interconnecting guide are encapsulated by a molding compound; Grinding the top surface of the molding compound until the wafer is exposed in the molding compound; etching the lead frame on the bottom surface of the lead frame to form a contact terminal connected to the interconnecting guide bar and protruding from the bottom surface of the molding compound; The surface of the terminal is provided with a metal protective layer; a film is adhered to the top surface of the thinned molding compound; the molding compound is cut and the film is removed to form a plurality of packages which are plastically encapsulated to cover the wafer. The method of claim 1, wherein the bonding pad is welded to the interconnecting lead by a conductive material coated on the interconnecting guide. The method of claim 1, wherein the bonding pad is interposed with the conductive material by a conductive material plated on the interconnecting guide and a metal plating plated on the bonding pad. Guide rod eutectic welding. The method of claim 1, further comprising: grinding the thinned molding compound and the wafer after the wafer is molded, and exposing the back surface of the thinned wafer to the top surface of the thinned molding compound; step. The method of claim 4, further comprising depositing a back metal The step of laminating the layer to the back side of the thinned wafer. The method of claim 5, wherein before depositing a back metal layer to the back side of the thinned wafer, the following process steps are performed on the back side of the thinned wafer: etching is performed; Injection and laser annealing. The method of claim 5, wherein the contact terminal protrudes beyond the bottom surface of the molding body, and the back metal layer is exposed on the top surface of the molding body. The method of claim 7, wherein the wafer is a metal oxide semiconductor field effect transistor, and the bonding pad comprises at least a gate bonding pad constituting a gate electrode of the wafer, constituting the wafer The source of the source electrode is bonded to the pad, and the back metal layer constitutes the drain electrode of the wafer. The method of claim 8, wherein the package is further adhered to a pedestal, wherein the back metal layer is adhered to the pedestal through a conductive material, and the gate bonding pad is connected The contact terminal is electrically connected to the gate pad disposed around the pedestal through a metal conductor, and the contact terminal connected to the source bonding pad is electrically connected to the source solder disposed around the pedestal through another metal conductor On the disk; and a drain pad electrically connected to the base is disposed around the base. The method of claim 7, wherein the wafer is a conjugated bimetal oxide semiconductor field effect transistor, wherein the back metal layer constitutes a conjugated bimetal oxide semiconductor field effect transistor a respective drain electrode of the first and second metal oxide semiconductor field effect transistors included in the crystal; and a drain electrode of each of the first and second metal oxide semiconductor field effect transistors passes through the back gold The genus layers are electrically connected to each other. The method of claim 10, wherein the bonding pad comprises at least a first gate bonding pad constituting the first metal oxide semiconductor field effect transistor gate electrode, constituting the first metal oxide a first source bonding pad of the semiconductor field effect transistor source electrode; and the bonding pad further comprising a second gate bonding pad constituting the second metal oxide semiconductor field effect transistor gate electrode A second source bond pad of the second metal oxide semiconductor field effect transistor source electrode. The method of claim 7, wherein the wafer is a high-end metal oxide semiconductor field effect transistor and a low-end metal oxide semiconductor field effect transistor integrated bimetal oxide semiconductor field effect transistor, Wherein the back metal layer constitutes a source electrode of a high side metal oxide semiconductor field effect transistor and a drain electrode of a low side metal oxide semiconductor field effect transistor; and a source of a high side metal oxide semiconductor field effect transistor The electrodes and the drain electrodes of the low-end metal oxide semiconductor field effect transistor are electrically connected to each other through the back metal layer. The method of claim 12, wherein the bonding pad comprises at least a first gate bonding pad constituting a gate electrode of the high side metal oxide semiconductor field effect transistor to constitute a high side metal oxide semiconductor field. a first drain bond pad of the effect transistor drain electrode; and the bond pad further includes a second gate bond pad constituting the low side metal oxide semiconductor field effect transistor gate electrode to form a low end A second source bond pad of the metal oxide semiconductor field effect transistor source electrode. The method of claim 1, wherein the wafer is a conjugated bimetal oxide semiconductor field effect transistor, wherein a back side of the wafer constitutes a conjugated bimetal oxide semiconductor field effect transistor The respective drains of the first and second metal oxide semiconductor field effect transistors included in the crystal. The method of claim 14, wherein the back surface of the wafer is provided with a back metal layer, and the respective drain electrodes of the first and second MOSFETs pass through the back metal layer Electrically connected to each other. The method of claim 1, wherein the wafer is a high-end metal oxide semiconductor field effect transistor and a low-end metal oxide semiconductor field effect transistor integrated bimetal oxide semiconductor field effect transistor, Wherein, the back side of the wafer constitutes a source electrode of a high-end MOSFET and a drain electrode of a low-end MOSFET. The method of claim 16, wherein the back side of the wafer is provided with a back metal layer, a source electrode of the high side metal oxide semiconductor field effect transistor and a low side metal oxide semiconductor field effect. The gate electrodes of the transistor are electrically connected to each other through the back metal layer.