JP2001060658A - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2001060658A JP2001060658A JP11235620A JP23562099A JP2001060658A JP 2001060658 A JP2001060658 A JP 2001060658A JP 11235620 A JP11235620 A JP 11235620A JP 23562099 A JP23562099 A JP 23562099A JP 2001060658 A JP2001060658 A JP 2001060658A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor
- semiconductor device
- electrode
- protective resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
Abstract
Description
【0001】[0001]
【発明の属する技術分野】この発明は、半導体チップ上
に別の半導体チップを接合したチップ・オン・チップ構
造の半導体装置およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a chip-on-chip structure in which another semiconductor chip is bonded on a semiconductor chip, and a method of manufacturing the same.
【0002】[0002]
【従来の技術】チップ・オンチップ構造の半導体装置
は、たとえば、図6に示すように、親チップ1の表面に
子チップ2をフェースダウンで接合するとともに、親チ
ップ2の裏面に外部接続電極3を設けた構造となってい
る。このようなチップ・オン・チップ構造は、素子の高
集積化を図るうえで有利な構造であるが、親チップ1お
よび子チップ2の厚さa,bのほかに、外部接続電極3
の高さcが必要であり、全体の高さ(a+b+c)が比
較的高くなるのが欠点である。2. Description of the Related Art In a semiconductor device having a chip-on-chip structure, for example, as shown in FIG. 3 is provided. Such a chip-on-chip structure is an advantageous structure for achieving high integration of the element. However, in addition to the thicknesses a and b of the parent chip 1 and the child chip 2, the external connection electrodes 3
Is a disadvantage that the overall height (a + b + c) is relatively high.
【0003】[0003]
【発明が解決しようとする課題】そこで、この発明の目
的は、チップ・オン・チップ構造を有し、かつ、薄型化
された半導体装置およびその製造方法を提供することで
ある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a chip-on-chip structure and having a reduced thickness, and a method of manufacturing the same.
【0004】[0004]
【課題を解決するための手段および発明の効果】上記の
目的を達成するための請求項1記載の発明は、第1の半
導体チップと、この第1の半導体チップの表面に接合さ
れた第2の半導体チップと、前記第1の半導体チップの
表面に形成され、外部との接続のための突起電極と、前
記突起電極の頭部を露出させた状態で上記第1の半導体
チップの表面を封止する保護樹脂とを含むことを特徴と
する半導体装置である。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor chip and a second semiconductor chip bonded to a surface of the first semiconductor chip; And a projection electrode formed on the surface of the first semiconductor chip for connection to the outside, and sealing the surface of the first semiconductor chip with the head of the projection electrode exposed. And a protective resin for stopping the semiconductor device.
【0005】この構成によれば、第1の半導体チップの
表面に第2の半導体チップが接合され、そして、その同
じ表面に突起電極が形成され、第1の半導体チップの表
面は、突起電極の頭部を露出させた状態で保護樹脂で封
止されている。したがって、第1の半導体チップの裏面
側に外部接続電極を設ける場合に比較して、半導体装置
全体の高さを低くすることができ、チップ・オン・チッ
プ構造の薄型半導体装置を実現できる。According to this structure, the second semiconductor chip is bonded to the surface of the first semiconductor chip, and the protruding electrode is formed on the same surface. The surface of the first semiconductor chip is formed on the surface of the protruding electrode. It is sealed with a protective resin with its head exposed. Therefore, the height of the entire semiconductor device can be reduced as compared with the case where external connection electrodes are provided on the back surface side of the first semiconductor chip, and a thin semiconductor device having a chip-on-chip structure can be realized.
【0006】なお、突起電極の頭部は、保護樹脂と面一
になっていてもよいし、保護樹脂の表面から突起電極の
頭部が突出していてもよい。また、突起電極の頭部が露
出している限りにおいて、突起電極の頭部が保護樹脂の
表面よりも内方に陥没していてもよい。また、第2の半
導体チップは、保護樹脂内に埋設されていてもよいし、
その非活性表面や側面の一部が保護樹脂から露出してい
てもよい。[0006] The head of the protruding electrode may be flush with the protective resin, or the head of the protruding electrode may protrude from the surface of the protective resin. Further, as long as the head of the projecting electrode is exposed, the head of the projecting electrode may be depressed inward from the surface of the protective resin. The second semiconductor chip may be embedded in the protective resin,
A part of the inactive surface or side surface may be exposed from the protective resin.
【0007】請求項2記載の発明は、半導体基板の表面
に、複数の半導体チップを、それらの活性表面を前記半
導体基板の表面に対向させたフェースダウン状態で接合
するチップ接合工程と、前記半導体基板の表面に複数の
突起電極を形成する電極形成工程と、前記半導体チップ
および前記突起電極の形成後に露出する前記半導体基板
の表面を、前記突起電極の頭部を露出させた状態で、保
護樹脂で封止する樹脂封止工程と、前記半導体基板を予
め定める切断ラインに沿って切断することにより、チッ
プ・オン・チップ構造の半導体装置の個片を取り出す切
り出し工程とを含むことを特徴とする半導体装置の製造
方法である。According to a second aspect of the present invention, there is provided a chip bonding step of bonding a plurality of semiconductor chips to a surface of a semiconductor substrate in a face-down state with their active surfaces facing the surface of the semiconductor substrate; An electrode forming step of forming a plurality of projecting electrodes on the surface of the substrate; and protecting the surface of the semiconductor substrate, which is exposed after the formation of the semiconductor chip and the projecting electrodes, with the head of the projecting electrode exposed. And a cutting step of cutting out the semiconductor device having a chip-on-chip structure by cutting the semiconductor substrate along a predetermined cutting line. 6 shows a method for manufacturing a semiconductor device.
【0008】この方法により、請求項1記載の構造の薄
型のチップ・オン・チップ型半導体装置を製造すること
ができる。そして、この方法では、半導体基板の表面に
複数の半導体チップを接合するとともに、複数の突起電
極をその同じ表面に形成するようにしているので、半導
体基板(半導体ウエハ)の状態で、チップの接合と電極
の形成を行うことができ、その後に、チップ・オン・チ
ップ構造の半導体装置の個片に切り出すことによって、
複数個のチップ・オン・チップ型半導体装置を効率良く
製造することができる。According to this method, a thin chip-on-chip type semiconductor device having the structure described in claim 1 can be manufactured. In this method, a plurality of semiconductor chips are bonded to the surface of the semiconductor substrate, and a plurality of protruding electrodes are formed on the same surface. Therefore, the bonding of the chips in the state of the semiconductor substrate (semiconductor wafer) is performed. And electrodes can be formed, and then cut into individual pieces of semiconductor devices with a chip-on-chip structure,
A plurality of chip-on-chip semiconductor devices can be manufactured efficiently.
【0009】半導体基板の表面は、保護樹脂で樹脂封止
され、また、半導体チップはフェースダウンで半導体基
板の表面に接合されるので、半導体基板または半導体チ
ップの各表面(活性表面)の保護は十分である。したが
って、半導体基板とこれに搭載された半導体チップとの
厚さの和に近い高さの薄型半導体パッケージが実現され
る。なお、必要であれば、切り出し工程よりも前に、半
導体基板の裏面や半導体チップの裏面側(非活性表面
側)をグラインダーなどで研磨または研削すれば、さら
なる薄型化が達成される。The surface of the semiconductor substrate is resin-sealed with a protective resin, and the semiconductor chip is bonded face-down to the surface of the semiconductor substrate. It is enough. Therefore, a thin semiconductor package having a height close to the sum of the thicknesses of the semiconductor substrate and the semiconductor chip mounted thereon is realized. If necessary, the back surface of the semiconductor substrate or the back surface (inactive surface side) of the semiconductor chip may be polished or ground with a grinder or the like before the cutting step, so that a further reduction in thickness can be achieved.
【0010】請求項3記載の発明は、前記樹脂封止工程
は、前記保護樹脂の表層部を除去して前記突起電極の頭
部をを露出させる電極露出工程を含むことを特徴とする
請求項2記載の半導体装置の製造方法である。この発明
によれば、保護樹脂の表層部を除去して突起電極の頭部
を露出させる工程が含まれることにより、突起電極を確
実に露出させることができる。保護樹脂の表層部の除去
は、グラインダーなどによる研削により行えばよいが、
エッチングなどの他の手法を用いてもよい。According to a third aspect of the present invention, the resin sealing step includes an electrode exposing step of exposing a head portion of the projecting electrode by removing a surface layer of the protective resin. 3. A method for manufacturing a semiconductor device according to item 2. According to the present invention, the step of removing the surface layer of the protective resin to expose the head of the projecting electrode is included, so that the projecting electrode can be reliably exposed. The surface portion of the protective resin may be removed by grinding with a grinder or the like,
Other techniques such as etching may be used.
【0011】請求項4記載の発明は、前記電極露出工程
は、前記保護樹脂と前記半導体チップの非活性表面側と
を同時に研磨または研削するチップ研削工程を含むこと
を特徴とする請求項3記載の半導体装置の製造方法であ
る。この発明によれば、保護樹脂と半導体チップの非活
性表面とを同時に研磨または研削することにより、突起
電極の頭部が確実に露出させられ、かつ、半導体チップ
の薄型化も図られる。According to a fourth aspect of the present invention, the electrode exposing step includes a chip grinding step of simultaneously polishing or grinding the protective resin and the non-active surface side of the semiconductor chip. Is a method for manufacturing a semiconductor device. According to the present invention, by simultaneously polishing or grinding the protective resin and the non-active surface of the semiconductor chip, the head of the protruding electrode is reliably exposed, and the semiconductor chip can be made thinner.
【0012】[0012]
【発明の実施の形態】以下では、この発明の実施の形態
を、添付図面を参照して詳細に説明する。図1は、この
発明の一実施形態に係る半導体装置の構成を示す斜視図
である。この半導体装置10は、親チップM(第1の半
導体チップ)の表面(活性表面)に、子チップD(第2
の半導体チップ)を、その表面(活性表面)を対向させ
たフェースダウン状態で接合したチップ・オン・チップ
構造を有している。親チップMおよび子チップDは、た
とえば、いずれもシリコンチップからなり、それぞれの
表面には、トランジスタなどの能動素子、抵抗やコンデ
ンサなどの受動素子および配線などが形成されている。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a perspective view showing a configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device 10 includes a child chip D (second semiconductor chip) on a surface (active surface) of a parent chip M (first semiconductor chip).
Semiconductor chip) is bonded in a face-down state with its surface (active surface) facing the chip. Each of the parent chip M and the child chip D is formed of, for example, a silicon chip, and has an active element such as a transistor, a passive element such as a resistor or a capacitor, and a wiring formed on each surface.
【0013】この実施形態においては、親チップMおよ
び子チップDは、いずれも、平面視において矩形形状に
成形されていて、子チップDは、親チップMよりも、平
面視において若干小さく成形されている。そして、子チ
ップDの周囲の領域には、親チップMの表面(活性表
面)に、外部接続電極としての突起電極(この実施形態
では柱状の電極)Tが複数個形成されている。親チップ
Mの表面において子チップDまたは突起電極Tが形成さ
れていない領域は、保護樹脂(たとえばエポキシ樹脂な
ど)11で樹脂封止されており、親チップMの表面の保
護が図られている。子チップDの表面は、親チップMに
対向しており、かつ、その側面が保護樹脂11で封止さ
れていることにより、外部から保護されている。In this embodiment, the parent chip M and the child chip D are both formed in a rectangular shape in plan view, and the child chip D is formed to be slightly smaller than the parent chip M in plan view. ing. In the area around the child chip D, a plurality of protruding electrodes (in this embodiment, columnar electrodes) T as external connection electrodes are formed on the surface (active surface) of the parent chip M. A region of the surface of the parent chip M where the child chip D or the protruding electrode T is not formed is resin-sealed with a protective resin (for example, epoxy resin) 11 to protect the surface of the parent chip M. . The surface of the child chip D is opposed to the parent chip M, and is protected from the outside by sealing the side surface with the protective resin 11.
【0014】この実施形態では、保護樹脂11、突起電
極Tの頭部および子チップDの非活性表面は、面一をな
している。このような構成の半導体装置10は、親チッ
プMと子チップDとの各厚さの和に近い高さを有する極
めて薄型に作成することができるので、薄型のチップ・
オン・チップ型半導体装置を実現することができる。図
2は、上述のような半導体装置10の製造工程を工程順
に示す断面図である。半導体基板としての半導体ウエハ
W(以下単に「ウエハW」という。)の表面(活性表
面)Waには、窒化膜などからなる保護膜(パッシベー
ション膜)が形成されており、この保護膜には、外部と
の接続が必要な複数箇所において、内部配線のパッドが
露出させられている。これらのパッド上には、図2(a)
に示すように、複数の突起電極Tおよび複数のバンプB
が形成される(電極形成工程)。突起電極Tは、外部接
続用のパッド上に形成され、バンプBは、子チップDと
接続すべきチップ間接続用のパッド上に形成される。突
起電極TおよびバンプBは、いずれも同じ材料で形成す
ることができ、たとえば、金などの耐酸化性金属で構成
されることが好ましい。また、突起電極Tは、バンプB
よりも高く形成されることが好ましい。In this embodiment, the protective resin 11, the head of the protruding electrode T, and the non-active surface of the daughter chip D are flush with each other. The semiconductor device 10 having such a configuration can be made extremely thin having a height close to the sum of the respective thicknesses of the parent chip M and the child chip D.
An on-chip semiconductor device can be realized. FIG. 2 is a cross-sectional view showing the steps of manufacturing the semiconductor device 10 as described above in the order of steps. A protective film (passivation film) made of a nitride film or the like is formed on a surface (active surface) Wa of a semiconductor wafer W (hereinafter, simply referred to as “wafer W”) as a semiconductor substrate. At a plurality of locations that need to be connected to the outside, the pads of the internal wiring are exposed. Fig. 2 (a)
As shown in FIG.
Is formed (electrode forming step). The protruding electrode T is formed on a pad for external connection, and the bump B is formed on a pad for inter-chip connection to be connected to the child chip D. Both the protruding electrode T and the bump B can be formed of the same material, and for example, are preferably formed of an oxidation-resistant metal such as gold. Further, the bump electrode T is connected to the bump B
It is preferably formed higher than the above.
【0015】続いて、図2(b)に示すように、子チップ
Dを、その表面(活性表面)DaをウエハWの表面Wa
に対向させてフェースダウンで接合した後に(チップ接
合工程)、ウエハWの表面Wa、突起電極Tおよびバン
プBが保護樹脂11で樹脂封止される(樹脂封止工
程)。このとき、突起電極Tの頭部および/または子チ
ップDの裏面(非活性表面)Dbが保護樹脂11から露
出するようにされてもよく、ウエハWの表面Waの露出
部が保護樹脂11で覆われていればよい。Subsequently, as shown in FIG. 2B, the child chip D is replaced with its surface (active surface) Da by the surface Wa of the wafer W.
After bonding face down (chip bonding step), the surface Wa of the wafer W, the protruding electrodes T, and the bumps B are resin-sealed with the protective resin 11 (resin sealing step). At this time, the head of the protruding electrode T and / or the back surface (inactive surface) Db of the child chip D may be exposed from the protective resin 11, and the exposed portion of the front surface Wa of the wafer W is covered with the protective resin 11. It only needs to be covered.
【0016】続いて、図2(c)に示すように、ウエハW
の裏面(非活性表面)Wbがグラインダーを用いて研磨
または研削され、さらなる薄型化が図られる。次に、保
護樹脂11をグラインダーを用いて研磨または研削する
ことにより、図2(d)に示すように、突起電極Tを露出
させる(電極露出工程)。さらに研削位置が子チップD
の非活性表面Dbに達した後には、保護樹脂11および
子チップDの非活性表面Dbが同時に研磨または研削さ
れ(チップ研削工程)、子チップDおよび保護樹脂11
がさらに薄型化される。Subsequently, as shown in FIG.
Back surface (inactive surface) Wb is polished or ground using a grinder to further reduce the thickness. Next, the protruding electrodes T are exposed as shown in FIG. 2D by polishing or grinding the protective resin 11 using a grinder (electrode exposing step). In addition, the grinding position is child chip D
Is reached, the protective resin 11 and the non-active surface Db of the secondary chip D are simultaneously polished or ground (chip grinding step), and the secondary chip D and the protective resin 11 are removed.
Is further reduced in thickness.
【0017】この後、図2(e)に示すように、スクライ
ブラインL(切断ライン)に沿ってウエハWを保護樹脂
11とともにダイシングソー15で切断することによ
り、ウエハWから切り出された親チップM上に子チップ
Dが接合された、図1の構造の半導体装置10の個片が
切り出される。なお、図2(c)の工程と図2(d)の工程と
は、いずれが先に行われてもよく、また、不要であれ
ば、図2(c)の工程は省かれてもよい。Thereafter, as shown in FIG. 2E, the wafer W is cut along with the protective resin 11 by a dicing saw 15 along a scribe line L (cutting line), so that the parent chip cut out from the wafer W is cut. An individual piece of the semiconductor device 10 having the structure shown in FIG. In addition, any of the step of FIG. 2C and the step of FIG. 2D may be performed first, and if unnecessary, the step of FIG. 2C may be omitted. .
【0018】以上のようにこの実施形態の方法によれ
ば、ウエハWから親チップMを切り出す前に子チップD
の接合を行うようにしており、この子チップDが接合さ
れるウエハWの表面Wa側に外部接続電極としての突起
電極Tを形成するようにしている。そして、保護樹脂1
1で表面Waが保護されたウエハWを切り出すことによ
り、パッケージ化されたチップ・オン・チップ構造の半
導体装置10の個片が得られる。したがって、薄型のチ
ップ・オン・チップ型半導体装置を効率的に生産するこ
とができる。As described above, according to the method of this embodiment, before cutting out the parent chip M from the wafer W,
And a protruding electrode T as an external connection electrode is formed on the front surface Wa side of the wafer W to which the child chip D is bonded. And the protective resin 1
By cutting out the wafer W whose front surface Wa is protected in step 1, a semiconductor chip 10 having a packaged chip-on-chip structure can be obtained. Therefore, a thin chip-on-chip type semiconductor device can be efficiently produced.
【0019】この発明の一実施形態について説明した
が、この発明は他の形態で実施することも可能である。
たとえば、上述の実施形態では、保護樹脂11、突起電
極Tおよび子チップDの非活性表面Dbが面一になるよ
うにしているが、図3に示すように、突起電極Tの頭部
が保護樹脂11の表面から突出していてもよいし、図4
に示すように、保護樹脂11の表面から子チップDの非
活性表面Db側が突出していてもよい。図3または図4
の構造は、たとえば、保護樹脂11を十分に薄く形成す
ることにより作製可能である。この場合に、突起電極T
の頭部に保護樹脂11が付着するおそれがあれば、グラ
インダーなどによる研磨または研削やエッチングによっ
て、突起電極Tの頭部に付着した保護樹脂を除去すれば
よい。Although one embodiment of the present invention has been described, the present invention can be embodied in other forms.
For example, in the above-described embodiment, the protective resin 11, the protruding electrode T, and the non-active surface Db of the child chip D are flush with each other. However, as shown in FIG. It may be protruded from the surface of the resin 11 or as shown in FIG.
As shown in (2), the inactive surface Db side of the child chip D may protrude from the surface of the protective resin 11. FIG. 3 or FIG.
Can be manufactured by forming the protective resin 11 to be sufficiently thin, for example. In this case, the projection electrode T
If there is a possibility that the protective resin 11 adheres to the head of the projection electrode T, the protective resin adhered to the head of the protruding electrode T may be removed by polishing, grinding, or etching with a grinder or the like.
【0020】また、上記の実施形態では、突起電極Tが
子チップDの非活性表面Dbよりも高く形成される例に
ついて説明したが、図5に示すように、突起電極Tの高
さは、子チップDの非活性表面Dbよりも低くても構わ
ない(たとえば、100μm未満)。この場合でも、裏
面研削(実線の位置まで研削)および表面研削(二点鎖
線の位置まで研削)の両工程を経た後には、上述の第1
の実施形態の場合と同様な構造を得ることができる。そ
して、突起電極Tの高さを低くしておくことにより、突
起電極Tの形成を短時間で容易に行うことができ、ま
た、材料も削減できるので、生産性を向上でき、かつ、
コストの低減に寄与できる。ただし、子チップDと突起
電極Tとを同時研削して、これらの表面を面一にするた
めには、始めに形成される突起電極Tの高さは、子チッ
プDの活性表面Daよりも高くしておくことが好まし
い。Further, in the above embodiment, the example in which the protruding electrode T is formed higher than the non-active surface Db of the sub chip D has been described. However, as shown in FIG. It may be lower than the non-active surface Db of the child chip D (for example, less than 100 μm). Even in this case, after both the back grinding (grinding to the position indicated by the solid line) and the surface grinding (grinding to the position indicated by the two-dot chain line), the above-mentioned first grinding is performed.
A structure similar to that of the embodiment can be obtained. By reducing the height of the projecting electrode T, the projecting electrode T can be easily formed in a short time, and the material can be reduced, so that productivity can be improved, and
It can contribute to cost reduction. However, in order to simultaneously grind the daughter chip D and the protruding electrode T to make their surfaces flush, the height of the protruding electrode T formed first is higher than the active surface Da of the daughter chip D. It is preferable to keep it high.
【0021】また、上記の実施形態では、1つの親チッ
プMに1つの子チップDが接合される例について説明し
たが、1つの親チップMに2つ以上の子チップDが接合
されてもよい。さらに、上述の実施形態では、突起電極
Tは、柱状のものとしたが、バンプ形状のものであって
も構わない。また、上述の実施形態では、親チップMと
子チップDとは、いずれもシリコン半導体からなってい
ることとしたが、シリコンの他にも、ガリウム砒素半導
体やゲルマニウム半導体などの他の任意の半導体材料を
用いた半導体チップをこの発明の半導体装置に適用する
ことができる。この場合に、親チップMと子チップDと
の半導体材料は、同じでもよいし異なっていてもよい。In the above embodiment, an example in which one child chip D is joined to one parent chip M has been described. However, even if two or more child chips D are joined to one parent chip M, Good. Further, in the above-described embodiment, the protruding electrodes T are columnar, but may be bump-shaped. Further, in the above-described embodiment, the parent chip M and the child chip D are both made of a silicon semiconductor. However, besides silicon, any other semiconductor such as a gallium arsenide semiconductor or a germanium semiconductor may be used. A semiconductor chip using a material can be applied to the semiconductor device of the present invention. In this case, the semiconductor materials of the parent chip M and the child chip D may be the same or different.
【0022】その他、特許請求の範囲に記載された事項
の範囲で種々の設計変更を施すことが可能である。In addition, various design changes can be made within the scope of the matters described in the claims.
【図1】この発明の一実施形態に係る半導体装置の構成
を示す斜視図である。FIG. 1 is a perspective view showing a configuration of a semiconductor device according to an embodiment of the present invention.
【図2】上記半導体装置の製造方法を工程順に示す断面
図である。FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device in the order of steps.
【図3】この発明の他の実施形態に係る半導体装置の構
成を示す断面図である。FIG. 3 is a cross-sectional view illustrating a configuration of a semiconductor device according to another embodiment of the present invention.
【図4】この発明のさらに他の実施形態に係る半導体装
置の構成を示す断面図である。FIG. 4 is a sectional view showing a configuration of a semiconductor device according to still another embodiment of the present invention.
【図5】この発明のさらに他の実施形態に係る半導体装
置の製造工程を説明するための断面図である。FIG. 5 is a cross-sectional view for explaining a manufacturing step of a semiconductor device according to still another embodiment of the present invention.
【図6】従来のチップ・オン・チップ型半導体装置の構
造を説明するための図解図である。FIG. 6 is an illustrative view for explaining a structure of a conventional chip-on-chip type semiconductor device;
10 半導体装置 11 保護樹脂 M 親チップ D 子チップ T 突起電極 B バンプ W 半導体ウエハ L スクライブライン Reference Signs List 10 semiconductor device 11 protective resin M parent chip D child chip T projecting electrode B bump W semiconductor wafer L scribe line
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01L 23/28 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/28
Claims (4)
体チップと、 前記第1の半導体チップの表面に形成され、外部との接
続のための突起電極と、 前記突起電極の頭部を露出させた状態で上記第1の半導
体チップの表面を封止する保護樹脂とを含むことを特徴
とする半導体装置。A first semiconductor chip; a second semiconductor chip bonded to a surface of the first semiconductor chip; and a second semiconductor chip formed on a surface of the first semiconductor chip for connection to the outside. A semiconductor device comprising: a protruding electrode; and a protective resin for sealing a surface of the first semiconductor chip with a head of the protruding electrode exposed.
を、それらの活性表面を前記半導体基板の表面に対向さ
せたフェースダウン状態で接合するチップ接合工程と、 前記半導体基板の表面に複数の突起電極を形成する電極
形成工程と、 前記半導体チップおよび前記突起電極の形成後に露出す
る前記半導体基板の表面を、前記突起電極の頭部を露出
させた状態で、保護樹脂で封止する樹脂封止工程と、 前記半導体基板を予め定める切断ラインに沿って切断す
ることにより、チップ・オン・チップ構造の半導体装置
の個片を取り出す切り出し工程とを含むことを特徴とす
る半導体装置の製造方法。2. A chip bonding step of bonding a plurality of semiconductor chips on a surface of a semiconductor substrate in a face-down state with their active surfaces facing the surface of the semiconductor substrate; An electrode forming step of forming a projecting electrode; and a resin sealing step of sealing a surface of the semiconductor substrate exposed after the formation of the semiconductor chip and the projecting electrode with a protective resin while exposing a head of the projecting electrode. A method for manufacturing a semiconductor device, comprising: a stopping step; and a cutting step of cutting out the semiconductor device having a chip-on-chip structure by cutting the semiconductor substrate along a predetermined cutting line.
部を除去して前記突起電極の頭部をを露出させる電極露
出工程を含むことを特徴とする請求項2記載の半導体装
置の製造方法。3. The semiconductor device according to claim 2, wherein said resin sealing step includes an electrode exposing step of exposing a head portion of said protruding electrode by removing a surface layer portion of said protective resin. Production method.
半導体チップの非活性表面側とを同時に研磨または研削
するチップ研削工程を含むことを特徴とする請求項3記
載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 3, wherein said electrode exposing step includes a chip grinding step of simultaneously polishing or grinding said protective resin and an inactive surface side of said semiconductor chip. .
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23562099A JP3833858B2 (en) | 1999-08-23 | 1999-08-23 | Semiconductor device and manufacturing method thereof |
KR1020017004814A KR100699649B1 (en) | 1999-08-23 | 2000-08-22 | Semiconductor device and method of manufacture thereof |
EP00953542A EP1154474A4 (en) | 1999-08-23 | 2000-08-22 | Semiconductor device and method of manufacture thereof |
US09/830,092 US7129110B1 (en) | 1999-08-23 | 2000-08-22 | Semiconductor device and method for manufacturing the same |
PCT/JP2000/005596 WO2001015223A1 (en) | 1999-08-23 | 2000-08-22 | Semiconductor device and method of manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23562099A JP3833858B2 (en) | 1999-08-23 | 1999-08-23 | Semiconductor device and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2001060658A true JP2001060658A (en) | 2001-03-06 |
JP3833858B2 JP3833858B2 (en) | 2006-10-18 |
Family
ID=16988717
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23562099A Expired - Lifetime JP3833858B2 (en) | 1999-08-23 | 1999-08-23 | Semiconductor device and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3833858B2 (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001257310A (en) * | 2000-03-09 | 2001-09-21 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing therefor, and testing method for the same |
JP2002299496A (en) * | 2001-03-30 | 2002-10-11 | Fujitsu Ltd | Semiconductor device and its fabricating method |
US6798121B2 (en) | 2000-03-17 | 2004-09-28 | Matsushita Electric Industrial Co., Ltd. | Module with built-in electronic elements and method of manufacture thereof |
US6870248B1 (en) | 1999-06-07 | 2005-03-22 | Rohm Co., Ltd. | Semiconductor chip with external connecting terminal |
US6944370B2 (en) | 2002-01-28 | 2005-09-13 | Disco Corporation | Method of processing a semiconductor wafer |
JP2007013716A (en) * | 2005-06-30 | 2007-01-18 | Kyocera Kinseki Corp | Manufacturing method of piezoelectric oscillator |
JP2007123362A (en) * | 2005-10-25 | 2007-05-17 | Disco Abrasive Syst Ltd | Method of manufacturing device |
JP2007214152A (en) * | 2006-02-07 | 2007-08-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
KR100810673B1 (en) * | 2002-05-24 | 2008-03-07 | 후지쯔 가부시끼가이샤 | Semiconductor device and manufacturing method thereof |
JP2009088350A (en) * | 2007-10-01 | 2009-04-23 | Denso Corp | Production method for electronic circuit device, and electronic circuit device |
JP2013004836A (en) * | 2011-06-20 | 2013-01-07 | Disco Abrasive Syst Ltd | Processing method of semiconductor wafer |
-
1999
- 1999-08-23 JP JP23562099A patent/JP3833858B2/en not_active Expired - Lifetime
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7262490B2 (en) | 1999-06-07 | 2007-08-28 | Rohm Co., Ltd. | Semiconductor chip with external connecting terminal |
US6870248B1 (en) | 1999-06-07 | 2005-03-22 | Rohm Co., Ltd. | Semiconductor chip with external connecting terminal |
US7138298B2 (en) | 1999-06-07 | 2006-11-21 | Rohm Co., Ltd. | Semiconductor chip with external connecting terminal |
US7339264B2 (en) | 1999-06-07 | 2008-03-04 | Rohm Co., Ltd. | Semiconductor chip with external connecting terminal |
US6765299B2 (en) | 2000-03-09 | 2004-07-20 | Oki Electric Industry Co., Ltd. | Semiconductor device and the method for manufacturing the same |
JP2001257310A (en) * | 2000-03-09 | 2001-09-21 | Oki Electric Ind Co Ltd | Semiconductor device and method of manufacturing therefor, and testing method for the same |
US7528005B2 (en) | 2000-03-09 | 2009-05-05 | Oki Semiconductor Co., Ltd. | Method of manufacturing chip size package semiconductor device without intermediate substrate |
US6798121B2 (en) | 2000-03-17 | 2004-09-28 | Matsushita Electric Industrial Co., Ltd. | Module with built-in electronic elements and method of manufacture thereof |
US7134198B2 (en) | 2000-03-17 | 2006-11-14 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing electric element built-in module with sealed electric element |
JP2002299496A (en) * | 2001-03-30 | 2002-10-11 | Fujitsu Ltd | Semiconductor device and its fabricating method |
US6944370B2 (en) | 2002-01-28 | 2005-09-13 | Disco Corporation | Method of processing a semiconductor wafer |
KR100810673B1 (en) * | 2002-05-24 | 2008-03-07 | 후지쯔 가부시끼가이샤 | Semiconductor device and manufacturing method thereof |
JP2007013716A (en) * | 2005-06-30 | 2007-01-18 | Kyocera Kinseki Corp | Manufacturing method of piezoelectric oscillator |
JP2007123362A (en) * | 2005-10-25 | 2007-05-17 | Disco Abrasive Syst Ltd | Method of manufacturing device |
JP2007214152A (en) * | 2006-02-07 | 2007-08-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
JP4637761B2 (en) * | 2006-02-07 | 2011-02-23 | パナソニック株式会社 | Semiconductor device and manufacturing method thereof |
JP2009088350A (en) * | 2007-10-01 | 2009-04-23 | Denso Corp | Production method for electronic circuit device, and electronic circuit device |
JP4518127B2 (en) * | 2007-10-01 | 2010-08-04 | 株式会社デンソー | Electronic circuit device manufacturing method and electronic circuit device |
KR101065525B1 (en) | 2007-10-01 | 2011-09-19 | 가부시키가이샤 덴소 | Electronic circuit device and method of making the same |
JP2013004836A (en) * | 2011-06-20 | 2013-01-07 | Disco Abrasive Syst Ltd | Processing method of semiconductor wafer |
Also Published As
Publication number | Publication date |
---|---|
JP3833858B2 (en) | 2006-10-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100699649B1 (en) | Semiconductor device and method of manufacture thereof | |
JP3339838B2 (en) | Semiconductor device and method of manufacturing the same | |
US8063493B2 (en) | Semiconductor device assemblies and packages | |
JP3405456B2 (en) | Semiconductor device, method of manufacturing semiconductor device, stack type semiconductor device, and method of manufacturing stack type semiconductor device | |
CN107403733A (en) | Three layer laminate encapsulating structures and forming method thereof | |
JP4103896B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
JP2004140037A (en) | Semiconductor device and its manufacturing process | |
JP3833858B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2002270720A (en) | Semiconductor device and its manufacturing method | |
JP2002043356A (en) | Semiconductor wafer, semiconductor device and manufacturing method therefor | |
JP2000243904A (en) | Semiconductor device in chip-on-chip structure | |
JP6116846B2 (en) | Semiconductor device and manufacturing method of semiconductor device | |
JP2001060591A (en) | Manufacture of semiconductor device | |
CN109860065B (en) | Fan-out type packaging method | |
JP2001267470A (en) | Semiconductor device and its manufacturing method | |
JP3803214B2 (en) | Manufacturing method of semiconductor device | |
CN110931441A (en) | Package structure and method for manufacturing the same | |
JP4422380B2 (en) | Manufacturing method of semiconductor device | |
CN109920765B (en) | Fan-out type packaging device | |
JP3476186B2 (en) | Method for manufacturing semiconductor device | |
TWI830528B (en) | Package and method forming same | |
TWI555159B (en) | Battery protection package and process of making the same | |
US20220278075A1 (en) | Packaging structure and formation method thereof | |
US20240055315A1 (en) | Semiconductor package and manufacturing method thereof | |
JP3904538B2 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040316 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060425 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060622 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060718 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060720 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 3833858 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090728 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100728 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110728 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110728 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120728 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130728 Year of fee payment: 7 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |