CN109860065A - A kind of fan-out package method - Google Patents
A kind of fan-out package method Download PDFInfo
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- CN109860065A CN109860065A CN201910113228.4A CN201910113228A CN109860065A CN 109860065 A CN109860065 A CN 109860065A CN 201910113228 A CN201910113228 A CN 201910113228A CN 109860065 A CN109860065 A CN 109860065A
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- chip
- disk
- load plate
- back side
- packaging method
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
This application discloses a kind of fan-out package method, the packaging method includes: offer load plate, and the load plate includes the first side being disposed opposite to each other and second side；The back side of at least one chip is fixed on first side of the load plate, wherein the chip is provided with front and the back side, and the front is provided with pad, and the position of the corresponding pad is provided with photoresist；Plastic packaging layer is formed on first side of the load plate, the plastic packaging layer covers the chip and the photoresist.By the above-mentioned means, the application can enhance the protection to chip front side.
Description
Technical field
This application involves technical field of semiconductor encapsulation, more particularly to a kind of fan-out package method.
Background technique
Fan-out package is quickly becoming novel semi-conductor due to having many advantages, such as miniaturization, low cost and high integration
Hot spot in encapsulation technology.
Existing fan-out package is usually then to be formed and be situated between in the front of chip in the back side insertion plastic packaging layer by chip
Electric layer and rewiring layer, reroute and are electrically connected between layer and the positive pad of chip.
Present inventor has found that existing fan-out package device is in four sides of chip in chronic study procedure
There is plastic packaging material protection at face and the back side, but only have dielectric layer protection in the front of chip, are easy when its impact by stress
It causes the front route of chip impaired, and then leads to disabler, reduce the yield of chip, influence the quality of product.
Summary of the invention
The application can enhance to chip front side mainly solving the technical problems that provide a kind of fan-out package method
Protection.
In order to solve the above technical problems, the technical solution that the application uses is: a kind of fan-out package method is provided,
Wherein, the packaging method includes: offer load plate, and the load plate includes the first side being disposed opposite to each other and second side；To at least one
The back side of a chip is fixed on first side of the load plate, wherein the chip is provided with front and the back side, institute
It states front and is provided with pad, and the position of the corresponding pad is provided with photoresist；It is formed on first side of the load plate
Plastic packaging layer, the plastic packaging layer cover the chip and the photoresist.
Wherein, it is described on first side that the back side of at least one chip is fixed on the load plate before, it is described
Packaging method further include: provide at least one disk, the disk is equipped with front and the back side, and the disk is arranged equipped with several matrixes
The chip of column is equipped with scribe line between the chip；The front of the chip, that is, disk front, the back side of the chip
The back side of the i.e. described disk；The photoresist is formed on the pad of the chip；The back side of the disk is ground, with
So that the thickness of the disk is less than or equal to threshold value；The scribe line of the disk is cut, to obtain described in single
Chip.
Wherein, the disk includes the first disk and the second disk, and the scribe line to the disk is cut
Cutting includes: to cut to obtain the first chip to first disk, cuts to second disk and obtains the second chip；It is described near
The back side of a few chip is fixed on first side of the load plate, comprising: by the back of at least one first chip
Face and the back side of at least one second chip are fixed on first side of the load plate.
Wherein, the packaging method further include: grind the plastic packaging layer back to the surface of the chip, so that described
Photoresist exposes.
Wherein, the grinding plastic packaging layer is back to the surface of the chip, so that the photoresist exposes, later, institute
State packaging method further include: remove the photoresist；Patterned metal wiring layer again is formed in the front of the chip,
In, wiring layer is electrically connected the metal with the pad again, the metal again side of the wiring layer far from the chip same
On horizontal plane.
Wherein, the front in the chip forms metal again before wiring layer, the packaging method further include:
The first dielectric layer is formed far from the chip-side in the plastic packaging layer, and first dielectric layer corresponds to the position of the pad
It is provided with the first opening；The front in the chip forms metal wiring layer again, comprising: in first dielectric layer
Upper formation metal wiring layer again.
Wherein, described that metal is formed on first dielectric layer again after wiring layer, the packaging method further include:
The metal forms the second dielectric layer on wiring layer again, and is provided with the second opening on second dielectric layer；Described second
Be open interplantation soldered ball, and wiring layer is electrically connected again for the soldered ball, the metal.
Wherein, before the grinding surface of the plastic packaging layer far from the chip, the packaging method further include: removal
The load plate.
Wherein, after the removal load plate, the packaging method further include: protection is set at the back side of the chip
Film.
Wherein, described that the back side of at least one chip is fixed on first side of the load plate, comprising: will at least
The back side of two chips is fixed on first side of the load plate；Protective film is arranged in the back side in the chip
Later, the packaging method further include: cutting at least two chips between region to form single package device,
In, it include at least one described chip in the single packaging.
The beneficial effect of the application is: being in contrast to the prior art, fan-out package method provided herein
The back side of middle chip is fixed on the first side of load plate, and the front of chip is provided with pad, and the position of corresponding pad is provided with
Photoresist；The plastic packaging layer covering chip and photoresist formed on first side of load plate, region of the front of chip in addition to photoresist is equal at this time
It is covered by plastic packaging layer；To chip front side line when the plastic packaging layer of chip front side can largely reduce chip by stress impact
The influence on road, improves the yield of chip, and improves the quality of product.
Further, since the positive extra plastic packaging layer of chip is removed by way of grinding, chip front side can be made
Plastic packaging layer in same level, to reduce difference in height existing for the intersection of chip in the prior art and plastic packaging layer；
The metal that later period is formed in the plastic packaging layer surface can also be in same level side of the wiring layer far from chip again, thus
Reduce metal difference of height existing for wiring layer again in the prior art.
Detailed description of the invention
In order to more clearly explain the technical solutions in the embodiments of the present application, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, the drawings in the following description are only some examples of the present application, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.Wherein:
Fig. 1 is the flow diagram of one embodiment of fan-out package method in the prior art；
Fig. 2 is the structural schematic diagram of the corresponding embodiment of step S101- step S106 in Fig. 1；
Fig. 3 is the structural schematic diagram of one embodiment of fan-out package device in the prior art；
Fig. 4 is the flow diagram of one embodiment of the application fan-out package method；
Fig. 5 is the structural schematic diagram of the corresponding embodiment of step S201- step S207 in Fig. 4；
Fig. 6 is the structural schematic diagram of corresponding one embodiment of fan-out package device after step S207 in Fig. 4；
Fig. 7 is the flow diagram of another embodiment of the application fan-out package method before step S202 in Fig. 4；
Fig. 8 is the structural schematic diagram of the corresponding embodiment of step S301- step S304 in Fig. 7；
Fig. 9 is the structural schematic diagram of one embodiment of the application fan-out package device；
Figure 10 is the structural schematic diagram of another embodiment of the application fan-out package device；
Figure 11 is the structural schematic diagram of another embodiment of the application fan-out package device；
Figure 12 is the structural schematic diagram of another embodiment of the application fan-out package device.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, rather than whole embodiments.Based on this
Embodiment in application, those of ordinary skill in the art are obtained every other under the premise of not making creative labor
Embodiment shall fall in the protection scope of this application.
Fan-out package method in the prior art and the structure of fan-out package device are first introduced below.
Fig. 1-Fig. 2 is please referred to, Fig. 1 is the flow diagram of one embodiment of fan-out package method in the prior art, Fig. 2
For the structural schematic diagram of the corresponding embodiment of step S101- step S106 in Fig. 1, which includes:
S101: providing load plate 10, and load plate 10 includes the first side 100 being disposed opposite to each other and second side 102.Specifically, please join
Read Fig. 2 a.Under normal circumstances, 100 surface of the first side of load plate 10 is additionally provided with glue film 12, for example, double-sided adhesive etc., so that after
Phase chip 14 can be tentatively fixed with load plate 10.
S102: the front 140 of at least one chip 14 is fixed on the first side 100 of load plate 10, wherein chip 14 is set
It is equipped with front 140 and the back side 142, front 140 is provided with pad 144.Specifically, Fig. 2 b is please referred to, the front 140 of chip 14 can
With fixed with glue film 12, so it is fixed with load plate 10.
S103: plastic packaging layer 16 is formed in the first side 100 of load plate 10, plastic packaging layer 16 covers the side (not indicating) of chip 14
And the back side 142.Specifically, Fig. 2 c is please referred to.
S104: load plate 10 is removed.Specifically, Fig. 2 d is please referred to, when being covered with glue film 12 on the first side 100 of load plate 10
When, can by directly by throwing off glue film 12 in a manner of realize removal load plate 10.
S105: the first insulating layer 18, the position of the corresponding pad 144 of the first insulating layer 18 are formed in the front 140 of chip 14
Form the first via hole (not indicating).Specifically, Fig. 2 e is please referred to.
S106: forming metal wiring layer 11 again far from 14 side of chip in the first insulating layer 18, metal again wiring layer 11 with
Pad 144 is electrically connected.Specifically, Fig. 2 f is please referred to.
Certainly, in the prior art, referring to Fig. 3, Fig. 3 is one embodiment of fan-out package device in the prior art
Structural schematic diagram.The fan-out package device can also include second insulating layer 13 on the basis of above-mentioned Fig. 2 f, be located at metal
Wiring layer 11 deviates from 14 side of chip again, and the second via hole (not indicating) is provided in second insulating layer 13；Soldered ball 15 is located at the
In two via holes, wiring layer 11 is electrically connected soldered ball 15 again with metal.
From the above, it is seen that in the prior art, the front 140 of chip 14 is just coated with the first insulating layer 18, or
First insulating layer 18 and second insulating layer 13, when its impact by stress, the route in the front 140 of chip 14 is easy impaired
Lead to disabler, reduces chip yield, influence the quality of product.
In addition, when being fitted with glue film 12 on load plate 10, when forming plastic packaging layer 16 in above-mentioned steps S103, if load plate 10
On be provided at least two chips 14, and the height of two chips 14 is different, then under the action of the pressure of plastic package die, two
For chip 14 by different stress, the chip 14 of different height falls into the difference of the depth in glue film 12, after the formation of plastic packaging layer 16,
The intersection (for example, arrow meaning region in Fig. 2 c) of chip 14 and plastic packaging layer 16 can have difference of height, the presence of the difference of height
To subsequent processing procedure, for example, being formed, the first insulating layer 18, forming metal, wiring layer 11 etc. can all cause adverse effect again.
Start to introduce fan-out package method provided herein below, please refer to Fig. 4-Fig. 5, Fig. 4 is the application fan
The flow diagram of one embodiment of type packaging method out, Fig. 5 are the corresponding embodiment party of step S201- step S207 in Fig. 4
The structural schematic diagram of formula, the packaging method include:
S201: providing load plate 20, and load plate 20 includes the first side 200 being disposed opposite to each other and second side 202.
Specifically, as shown in Figure 5 a, the material of load plate 20 can be the partially rigid material such as metal, silicon, plastics, and load plate
The horizontality of 20 the first side 200 is preferable.
In addition, in the present embodiment, after above-mentioned steps S201 further include: be arranged on 200 surface of the first side of load plate 20
Glue film 22, glue film 22 is that can remove glue film, and it is with adhesiveness, for example, glue film 22 is double-sided adhesive etc.；Later period chip 24 can be with
It adheres to, and then realizes tentatively fixed with the position of load plate 20 with glue film 22.
S202: the back side 240 of at least one chip 24 is fixed on the first side 200 of load plate 20, wherein chip 24 is set
It is equipped with front 242 and the back side 240, front 242 is provided with pad 244, and the position of corresponding pad 244 is provided with photoresist 26.
It specifically, as shown in Figure 5 b, in the present embodiment, can be by multiple (for example, one, two, three etc.) chips
24 uniformly paste on load plate 20.The type of multiple chips 24 can be same or different, for example, wrapping on load plate 20 in Fig. 5 b
Containing two kinds of chip 24, respectively the first chip 24a and the second chip 24b.
In one embodiment, Fig. 7-Fig. 8 is please referred to, Fig. 7 is the application fan-out package before step S202 in Fig. 4
The flow diagram of another embodiment of method, Fig. 8 are the knot of the corresponding embodiment of step S301- step S304 in Fig. 7
Structure schematic diagram, before above-mentioned steps S202, packaging method provided herein further include:
S301: providing at least one disk 30, and disk 30 is equipped with front 300 and the back side 302, and disk 30 is equipped with several matrixes
The chip 24 of arrangement is equipped with scribe line 304 between chip 24；Front (not indicating) the i.e. front 300 of disk 30 of chip 24, core
The back side (not indicating) the i.e. back side 302 of disk 30 of piece 24.
Specifically, as shown in Figure 8 a, chip 24 is silicon base, germanium substrate etc..Semiconductor devices (figure is formed in chip 24
Do not show) and pad 244, semiconductor devices and pad 244 can be located at the same side surface of chip 24, can also be located at chip 24
Not same surface.When semiconductor devices and pad 244 are located at the not same surface of chip 24, using through the logical of chip 24
Pad 24 is electrically connected by hole with semiconductor devices.
In addition, in the present embodiment, 30 numbers of disk can be with for one, two, three etc., for example, disk 30 can wrap
Include the first disk and the second disk, the type difference of the first disk and the second disk.
S302: photoresist 26 is formed on the pad 244 of chip 24.
Specifically, as shown in Figure 8 b, light blockage coating, exposure, developing procedure can be carried out in the front 300 of disk 30, with
Photoresist 26 is formed on the pad 244 of chip 24.Photoresist 26 can be positive photoresist or negative sense photoresist.
S303: the back side 302 of abrasive disk 30, so that the thickness of disk 30 is less than or equal to threshold value.
Specifically, as shown in Figure 8 c, above-mentioned threshold value can be 100 microns, and it is micro- to can be 50 for the thickness of disk 30 after grinding
Rice, 80 microns, 100 microns etc., by reducing the thickness of disk 30 to reduce the conducting resistance of later period chip 24.
S304: cutting the scribe line 304 of disk 30, to obtain single chip 24.
It specifically, as shown in figure 8d, in the present embodiment, can be using plasma, laser or blade drawing in disk 30
Primary or repeatedly cutting is carried out at film trap 304, to obtain multiple single chips 24.
In another embodiment, when disk 30 includes the first disk and the second disk, above-mentioned steps S304 includes: pair
The cutting of first disk obtains the first chip 24a, cuts to the second disk and obtains the second chip 24b.Above-mentioned steps S202 is specifically wrapped
It includes: the back side (not indicating) of at least one the first chip 24a and the back side (not indicating) of at least one the second chip 24b is fixed
On the first side 200 of load plate 20.Since the type of the first chip 24a and the second chip 24b may be different, load plate 20
Upper all photoresists 26 backwards to one end of load plate 20 may not in same level,
S203: forming plastic packaging layer 28 on the first side 200 of load plate 20, and plastic packaging layer 28 covers chip 24 and photoresist 26.
Specifically, as shown in Figure 5 c, the material of plastic packaging layer 28 can be epoxy resin etc..In the present embodiment, chip 24
Region of the front 242 in addition to photoresist 26 covered by plastic packaging layer 28；The plastic packaging layer 28 in 24 front 242 of chip can be largely
Positive 242 routes of chip 24 are influenced when upper reduction chip 24 is by stress impact, improve the yield of chip 24, and improve
The quality of product.It should be noted that Fig. 5 c, which is formed by fan-out package device architecture, individually to be sold, after can also carrying out
It is sold after continuous processing.
In other embodiments, please continue to refer to Fig. 4, packaging method provided herein may further comprise: S204:
Remove load plate 20.
Specifically, as fig 5d, when being provided with glue film 22 on load plate 20, load plate can be made by removing glue film 22
20 removals.It should be noted that fan-out package device architecture formed in Fig. 5 d can individually be sold, subsequent place can also be carried out
It is sold after reason.
In yet another embodiment, please continue to refer to Fig. 4, encapsulation side provided herein further include: S205: grinding modeling
Sealing 28 is back to the surface of chip 24, so that photoresist 26 exposes.
Specifically, as depicted in fig. 5e, in the present embodiment, all photoresists 26 may not be same backwards to one end of chip 24
On horizontal plane, all photoresists 26 can be made to expose by way of grinding plastic packaging layer 28；It, can be with after the exposing of all photoresists 26
Stop grinding, or continues to grind a distance.In addition, in the present embodiment, it, can be in chip 24 when grinding plastic packaging layer 28
The back side adhere to a support plate, alternatively, the sequence of above-mentioned steps S205 and step S204 are exchanged, that is, ground after plastic packaging layer 28 again
Remove load plate 20.Since the extra plastic packaging layer 28 in the front 242 of chip 24 is removed by way of grinding, chip can be made
The plastic packaging layer 28 in 24 fronts 242 is in same level, to reduce the boundary of chip 24 and plastic packaging layer 28 in the prior art
Locate existing difference in height.It, can also be into it should be noted that fan-out package device architecture formed in Fig. 5 e can individually be sold
It is sold after row subsequent processing.
In yet another embodiment, please continue to refer to Fig. 4, encapsulation side provided herein further include:
S206: removal photoresist 26.
Specifically, as shown in figure 5f, for example, photoresist 26 can be made to remove by way of removing.After photoresist 26 removes, modeling
It is equivalent to form via etch (not indicating) on sealing 28.
S207: patterned metal wiring layer 21 again are formed in the front 242 of chip 24, wherein metal wiring layer 21 again
Be electrically connected with pad 244, metal again side of the wiring layer 21 far from chip 24 in same level.
Specifically, as shown in fig. 5g, in the present embodiment, made by way of grinding plastic packaging layer 28 far from chip 24 one
Side in same level, then make the subsequent metal formed on the plastic packaging layer 28 again wiring layer 21 far from chip 24 one
Side is in same level.
In another embodiment, please continue to refer to Fig. 5 g, before above-mentioned steps S207, encapsulation side provided herein
Method further include: form the first dielectric layer 23 far from 24 side of chip in plastic packaging layer 28, and the first dielectric layer 23 corresponds to pad 244
Position is provided with the first opening (not indicating)；In the present embodiment, the first dielectric layer 23 can cover the etched of plastic packaging layer 28
The side wall in hole, and covering part pad 244.Above-mentioned steps S207 is specifically included: in the first dielectric layer 23 far from 24 side of chip
Patterned metal wiring layer 21 again are formed, wiring layer 21 fills via etch to metal again, and is electrically connected with pad 244.It needs
Illustrate, fan-out package device architecture formed in Fig. 5 g can individually be sold, which can directly lead to
Crossing metal, wiring layer 21 is electrically connected with external devices again.
Certainly, in other embodiments, referring to Fig. 6, Fig. 6 is corresponding fan-out package after step S207 in Fig. 4
The structural schematic diagram of one embodiment of device.After above-mentioned steps S207, packaging method provided herein further include:
A, Fig. 6 a is please referred to, forms the second dielectric layer 25 on metal again wiring layer 21, and be arranged on the second dielectric layer 25
There is the second opening (not indicating)；Wiring layer 21 forms the effect wrapped up again by metal for first dielectric layer 23 and the second dielectric layer 25
Fruit.And when the first dielectric layer 23 and the second dielectric layer 25 are using low dielectric constant materials, metal wiring layer 21 again can be reduced
Leakage current, reduce conducting wire between capacity effect；Further, it is also possible to reduce metal, wiring layer 21 generates heat again, enhances chip
24 function improves the quality of packaging.
B, Fig. 6 b is please referred to, in the second opening interplantation soldered ball 27, wiring layer 21 is electrically connected again for soldered ball 27, metal.In this reality
It applies in example, it can be using ball attachment machine in the second opening interplantation soldered ball 27.It should be noted that fan-out-type formed in Fig. 6 b seals
Dress device architecture can individually be sold, which can be directly electrically connected by soldered ball 27 with external devices.
In yet another embodiment, to enhance the protection to above-mentioned fan-out package device, Fig. 6 c, the application are please referred to
Provided packaging method further include: protective film 29 is set at the back side of chip 24 240.The material of protective film 29 can be similar
In the material of plastic packaging layer 28, for example, epoxy resin etc., can form what six bread covered for fan-out package device by the step
Form, to enhance the protection to fan-out package device.It should be noted that the step of above-mentioned setting protective film 29, can go
Except the either step after support plate 20.
In another embodiment, the back side 240 of at least one chip 24 is fixed on load plate in step S202 in Fig. 4
On 20 the first side 200, comprising: the back side 240 of at least two chips 24 is fixed on the first side 200 of load plate 20；It is above-mentioned
After protective film 29 is arranged in the back side of chip 24 240, packaging method provided herein further include: please refer to Fig. 6 d, cut
The region between at least two chips 24 is cut to form single package device, wherein include at least one in single package device
(for example, one, two, three etc.) chip 24.
Below from configuration aspects, the fan-out package device that the application is formed using above-mentioned steps is described further.
Referring to Fig. 9, Fig. 9 is the structural schematic diagram of one embodiment of the application fan-out package device.Provided herein is fanned out to
Type packaging includes:
At least one chip 24, chip 24 include front 242 and the back side 240, and front 242 is provided with pad 244, and corresponding
The position of pad 244 is provided with photoresist 26；The quantity of the present embodiment chip 24 can be to be multiple, and the type of multiple chips 24
Can be same or different, for example, chip 24 includes the first chip 24a and the second chip 24b.The thickness of chip 24 is less than or equal to
100 microns, such as 50 microns, 80 microns, 100 microns etc..
Plastic packaging layer 28, covers the side and front 242 of chip 24, and does not cover the back side 240 of chip 24.In the present embodiment
In, the material of plastic packaging layer 28 can be epoxy resin etc..In the present embodiment, area of the front 242 of chip 24 in addition to photoresist 26
Domain is covered by plastic packaging layer 28；The plastic packaging layer 28 in 24 front 242 of chip can largely reduce chip 24 and be rushed by stress
To the influence of positive 242 routes of chip 24 when hitting, the yield of chip 24 is improved, and improve the quality of product.
In one embodiment, side of the plastic packaging layer 28 far from chip 24 is in same level.As shown in figure 9, plastic packaging layer
28 can cover photoresist 26.Certainly, in other embodiments, as shown in Figure 10, Figure 10 is that the application fan-out package device is another
The structural schematic diagram of one embodiment, plastic packaging layer 28a and photoresist 26a are in same level, and photoresist 26a is from plastic packaging layer 28a
Middle exposing.In the present embodiment, since the plastic packaging layer 28/28a in 24 front 242 of chip is in same level, to reduce
Difference in height existing for the intersection of chip 24 and plastic packaging layer 28/28a in the prior art.
In yet another embodiment, Figure 11 is please referred to, Figure 11 is the structural representation of another embodiment party of the application packaging,
The packaging further include: load plate 20, positioned at the back side of chip 24 240；Glue film 22 is used between load plate 20 and chip 24
In fixed load plate 20 and chip 24.
It should be noted that the structure of packaging provided by above-mentioned Fig. 9-Figure 11 can directly be sold, the purchase of downstream producer
It can continue subsequent processing to it after buying above-mentioned packaging.
Certainly, in this application, complete packaging can also be prepared into be sold.Please refer to Figure 12, Figure 12
For the structural schematic diagram of another embodiment of the application fan-out package device.
The fan-out package device includes:
At least one chip 24, chip 24 include front 242 and the back side 240, and front 242 is provided with pad 244；In this reality
It applies in example, the quantity of chip 24 can be multiple, and the type of multiple chips 24 can be same or different.The thickness of chip 24
Less than or equal to 100 microns, such as 50 microns, 80 microns, 100 microns etc..
Plastic packaging layer 28 covers the side and front 242 of chip 24, and the position of corresponding pad 244 is provided with connection pad
244 and extraneous via etch (not indicating).In the present embodiment, the material of plastic packaging layer 28 can be epoxy resin etc., plastic packaging
28 side far from chip 24 of layer are in same level.In the present embodiment, corresponding pad 244 is removed in the front 242 of chip 24
Outer region is covered by plastic packaging layer 28；The plastic packaging layer 28 in 24 front 242 of chip can largely reduce chip 24 by
To the influence of positive 242 routes of chip 24 when stress impact, the yield of chip 24 is improved, and improve the quality of product.
Please continue to refer to Figure 12, packaging provided herein further include: metal wiring layer 21 again are located at plastic packaging layer
28 are electrically connected far from 24 side of chip, and with pad 244；Metal again side of the wiring layer 24 far from chip 24 in same level
On.In the present embodiment, since the plastic packaging layer 28 in 24 front 242 of chip is in same level, to reduce the prior art
Difference in height existing for the intersection of middle chip 24 and plastic packaging layer 28.
In another embodiment, packaging provided herein further include: the first dielectric layer 23 is located at metal again
Between wiring layer 21 and plastic packaging layer 28, and the position of the corresponding pad 244 of the first dielectric layer 23 is provided with the first opening (not indicating),
In the present embodiment, the first dielectric layer 23 also extends to the inner wall of the via etch of plastic packaging layer 28, and covering part pad 244.
Second dielectric layer 25, being located at metal, wiring layer 21 is far from 24 side of chip again, and the corresponding metal of the second dielectric layer 25 wiring layer again
21 sides are provided with the second opening (not indicating)；Soldered ball 27 is located in the second opening, and wiring layer 21 is electrically connected again for soldered ball 27, metal
It connects.In the present embodiment, when the first dielectric layer 23 and the second dielectric layer 25 are using low dielectric constant materials, metal can be reduced
The leakage current of wiring layer 21 again reduces the capacity effect between conducting wire；Further, it is also possible to reduce metal, wiring layer 21 is sent out again
Heat enhances the function of chip 24, improves the quality of packaging.
In yet another embodiment, referring to Figure 12, packaging provided herein further include: protective film
29, positioned at the back side of chip 24 240.The material of protective film 29 can be the material similar to plastic packaging layer 28, for example, epoxy resin
Deng the form that the setting of the protective film 29 can cover fan-out package device six bread of formation, to enhance to fan-out package
The protection of device.
The foregoing is merely presently filed embodiments, are not intended to limit the scope of the patents of the application, all to utilize this
Equivalent structure or equivalent flow shift made by application specification and accompanying drawing content, it is relevant to be applied directly or indirectly in other
Technical field similarly includes in the scope of patent protection of the application.
Claims (10)
1. a kind of fan-out package method, which is characterized in that the packaging method includes:
Load plate is provided, the load plate includes the first side being disposed opposite to each other and second side；
The back side of at least one chip is fixed on first side of the load plate, wherein the chip is provided with front
And the back side, the front is provided with pad, and the position of the corresponding pad is provided with photoresist；
Plastic packaging layer is formed on first side of the load plate, the plastic packaging layer covers the chip and the photoresist.
2. packaging method according to claim 1, which is characterized in that described to be fixed on by the back side of at least one chip
Before on first side of the load plate, the packaging method further include:
At least one disk is provided, the disk is equipped with front and the back side, and the disk is equipped with the chip of several matrix arrangements, institute
It states and is equipped with scribe line between chip；The front of the chip, that is, disk front, the back side, that is, disk of the chip
The back side；
The photoresist is formed on the pad of the chip；
The back side of the disk is ground, so that the thickness of the disk is less than or equal to threshold value；
The scribe line of the disk is cut, to obtain the single chip.
3. packaging method according to claim 2, which is characterized in that
The disk includes the first disk and the second disk, and it includes: pair that the scribe line to the disk, which carries out cutting,
The first disk cutting obtains the first chip, cuts to second disk and obtains the second chip；
It is described that the back side of at least one chip is fixed on first side of the load plate, comprising: described at least one
The back side of first chip and the back side of at least one second chip are fixed on first side of the load plate.
4. packaging method according to claim 1, which is characterized in that the packaging method further include:
The plastic packaging layer is ground back to the surface of the chip, so that the photoresist exposes.
5. packaging method according to claim 4, which is characterized in that described to grind the plastic packaging layer back to the chip
Surface, so that the photoresist exposes, later, the packaging method further include:
Remove the photoresist；
Form patterned metal wiring layer again in the front of the chip, wherein the metal again wiring layer with it is described
Pad electrical connection, the metal again side of the wiring layer far from the chip in same level.
6. packaging method according to claim 5, which is characterized in that
The front in the chip forms metal again before wiring layer, the packaging method further include: in the modeling
Sealing forms the first dielectric layer far from the chip-side, and first dielectric layer position that corresponds to the pad is provided with the
One opening；
The front in the chip forms metal wiring layer again, comprising: forms metal on first dielectric layer
Wiring layer again.
7. packaging method according to claim 6, which is characterized in that described to form metal again on first dielectric layer
After wiring layer, the packaging method further include:
The second dielectric layer is formed on the metal again wiring layer, and is provided with the second opening on second dielectric layer；
In the second opening interplantation soldered ball, wiring layer is electrically connected again for the soldered ball, the metal.
8. packaging method according to claim 4, which is characterized in that the grinding plastic packaging layer is far from the chip
Before surface, the packaging method further include:
Remove the load plate.
9. packaging method according to claim 8, which is characterized in that after the removal load plate, the encapsulation side
Method further include:
At the back side of the chip, protective film is set.
10. packaging method according to claim 9, which is characterized in that described to be fixed on the back side of at least one chip
On first side of the load plate, comprising: the back side of at least two chips is fixed on described the first of the load plate
On side；
The back side in the chip is arranged after protective film, the packaging method further include: at least two cores of cutting
Region between piece is to form single package device, wherein includes at least one described chip in the single packaging.
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