CN105226036B - The packaging method and encapsulating structure of image sensing chip - Google Patents
The packaging method and encapsulating structure of image sensing chip Download PDFInfo
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- CN105226036B CN105226036B CN201510649774.1A CN201510649774A CN105226036B CN 105226036 B CN105226036 B CN 105226036B CN 201510649774 A CN201510649774 A CN 201510649774A CN 105226036 B CN105226036 B CN 105226036B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The present invention provides image sensing chip packaging method and encapsulating structure, the packaging method include：Wafer is provided, the wafer has first surface and the second surface opposite with the first surface, there is the wafer image sensing chip of more grids arrangement, image sensing chip to have image sensing area and weld pad, and the image sensing area and weld pad are located at the first surface side；Cutting groove is formed in the second surface of the wafer and trepanning corresponding with the weld pad, the trepanning expose the weld pad；The first photosensitive-ink is filled in the cutting groove；It is coated with the second photosensitive-ink in the second surface of the wafer, so that the second photosensitive-ink is covered the trepanning and forms cavity in the trepanning, effectively the second photosensitive-ink is avoided to be contacted with the bottom of trepanning, the encapsulation yield for improving image sensing chip, improves the reliability of image sensing chip-packaging structure.
Description
Technical field
The present invention relates to technical field of semiconductors more particularly to the packaging methods of wafer level semiconductor chip.
Background technology
The semiconductor chip packaging technology of mainstream is crystal wafer chip dimension encapsulation technology (Wafer Level Chip now
Size Packaging, WLCSP), it is to be packaged to full wafer wafer and cut to obtain the skill of single finished product chip again after testing
Art.Single finished product chip size and single crystallite dimension after being encapsulated using such encapsulation technology is similar, has complied with market pair
Microelectronic product is increasingly light, small, short, thinning and low priceization requirement.Crystal wafer chip dimension encapsulation technology is current encapsulation field
Hot spot and future development trend.
Referring to FIG. 1, disclosing a kind of encapsulating structure of wafer scale image sensing chip, wafer 1 is pressed with the contraposition of protective substrate 2
It closes, support unit 3 makes to form gap between the two between wafer 1 and protective substrate 2, avoids protective substrate 2 straight with wafer 1
Contact, wafer 1 include the image sensing chip 10 of more latticed arrangements, and image sensing chip 10 includes image sensing area 11
And weld pad 12, multiple support units 3 are latticed to be arranged on protective substrate 2 and corresponding with image sensing chip 10, works as protection
After the contraposition pressing of substrate 2 and wafer 1, support unit 3 surrounds image sensing area 11, wafer 1 have first surface and with it is described
The opposite second surface of first surface, image sensing area 11 and weld pad 12 are located at the first surface side of wafer.
In order to realize that weld pad 12 is electrically connected with other circuits, it is provided with towards first surface in the second surface side of wafer 1
The trepanning 22 of extension, trepanning 22 is corresponding with weld pad 12 and the bottom-exposed of trepanning 22 goes out weld pad 12, is arranged in the side wall of trepanning 22
There is an insulating layer 23, on the insulating layer 23 and bottom of trepanning 22 is provided with wiring layer 24 again, then wiring layer 24 is electrically connected with weld pad 12
It connects, soldered ball 25 is electrically connected with wiring layer 24 again, and being electrically connected other circuits by soldered ball 25 realizes between weld pad 12 and other circuits
Form electrical connection.
Image sensing chip cutting for the ease of completing encapsulation is got off, and the second surface of wafer 1 is provided with direction
The cutting groove 21 that first surface extends.
To the second surface of wafer 1 arrange soldered ball 25 before, need be coated with anti-solder ink 26, usually cutting groove 21 with
And anti-solder ink 26 is also filled in trepanning 22 to achieve the effect that protection, insulation.
However, since anti-solder ink 26 fills up trepanning 22, in subsequent Reflow Soldering and reliability test, anti-solder ink
26 power to be formed and act on again wiring layer 24 of expanding with heat and contract with cold, under the pullling of this power, then wiring layer 24 is easy and weld pad 12
It is detached from, causes bad, become those skilled in the art and bite technical problem to be solved.
Invention content
Problems solved by the invention is the wafer scale image sensing chip packaging method and image provided through the invention
Sensing chip encapsulating structure eliminates again the case where wiring layer is detached from weld pad, solves bad, raising image sensing chip package knot
The reliability of structure.
To solve the above problems, the present invention provides a kind of packaging method of image sensing chip, including：Wafer, institute are provided
Stating wafer, there is first surface and the second surface opposite with the first surface, the wafer there are more grids to arrange
Image sensing chip, image sensing chip have image sensing area and weld pad, and the image sensing area and weld pad are located at institute
State first surface side；Cutting groove and trepanning corresponding with the weld pad, the trepanning are formed in the second surface of the wafer
Expose the weld pad；The first photosensitive-ink is filled in the cutting groove；In the second sense of second surface coating of the wafer
Light ink makes the second photosensitive-ink cover the trepanning and forms cavity in the trepanning.
Preferably, the step of filling the first photosensitive-ink in the cutting groove include：In the second surface of the wafer
Whole face, which is coated with the first photosensitive-ink, makes the cutting groove fill the first photosensitive-ink；By cutting groove area by way of exposure imaging
The first photosensitive-ink removal other than domain.
Preferably, the first photosensitive-ink is filled in the cutting groove by the way of spin coating, by the way of spin coating
The second surface of the wafer is coated with the second photosensitive-ink, and the spin coating rate of the first photosensitive-ink of spin coating is photosensitive less than spin coating second
The spin coating rate of ink.
Preferably, the viscosity of first photosensitive-ink is less than the viscosity of the second photosensitive-ink.
Preferably, the viscosity of first photosensitive-ink is less than 8Kcps, and the viscosity of second photosensitive-ink is more than
12Kcps。
Preferably, further include before the wafer second surface forms cutting groove and trepanning：Protective substrate, institute are provided
The support unit that grid arrangement is provided on protective substrate is stated, each support unit corresponds to an image sensing chip；It will be described
The contraposition of the first surface of wafer and the protective substrate presses, the support unit be located at the wafer and the protective substrate it
Between；The second surface of the wafer is ground thinned.
Preferably, include the step of the second surface of the wafer forms cutting groove and trepanning：Using etching technics
Simultaneously precut slot and trepanning are formed in the second surface of the wafer；It is cut along the precut slot using cutter, it is described
The first surface that cutter cuts through the wafer forms cutting groove.
Preferably, further include before being coated with the second photosensitive-ink：Insulating layer is formed in the side wall of the trepanning；In described
Wiring layer again is formed on the insulating layer and bottom of the trepanning, and the wiring layer again is made to be electrically connected with the weld pad；Using silk
The mode of wire mark brush makes to be formed in second photosensitive-ink multiple in the second photosensitive-ink of second surface coating of the wafer
Through-hole, the through-hole expose the wiring layer again；Soldered ball, the soldered ball and the wiring layer again electricity are formed in the through-hole
Connection.
Preferably, further include before being coated with the second photosensitive-ink：Insulating layer is formed in the side wall of the trepanning；In described
Wiring layer again is formed on the insulating layer and bottom of the trepanning, and the wiring layer again is made to be electrically connected with the weld pad；Using rotation
The mode of painting is coated with the second photosensitive-ink in the second surface whole face of the wafer；Described second by way of exposure imaging
Multiple through-holes are formed in photosensitive-ink makes the through-hole expose the wiring layer again；Soldered ball is formed in the through-hole, it is described
Soldered ball is electrically connected with the wiring layer again.
The present invention also provides a kind of image sensing chip-packaging structures, including：Substrate has the first face and with described the
The second opposite face on one side；Image sensing area positioned at the first face of the substrate and weld pad；Positioned at second face and to institute
The trepanning of first surface extension is stated, the trepanning is corresponding with the weld pad and exposes the weld pad；Coat the substrate side
The first photosensitive-ink；The encapsulating structure further includes the second photosensitive-ink, and second photosensitive-ink covers the trepanning simultaneously
Cavity is formed in the trepanning.
Preferably, the encapsulating structure further includes：The protective substrate of position pressing is faced with the substrate first；Positioned at described
Support unit between protective substrate and the substrate, the support unit surround the image sensing area；Described first is photosensitive
The side of support unit described in ink covered section.
Preferably, the viscosity of first photosensitive-ink is less than the viscosity of the second photosensitive-ink.
Preferably, the viscosity of first photosensitive-ink is less than 8Kcps, and the viscosity of second photosensitive-ink is more than
12Kcps。
Preferably, the encapsulating structure further includes：Insulating layer in the trepanning；On the insulating layer and
The wiring layer again of aperture bottom, the wiring layer again are electrically connected with the weld pad；Cloth again described in second photosensitive-ink covering
Line layer, and through-hole is provided in second photosensitive-ink, the through-hole exposes the wiring layer again；It is provided in through-hole
Soldered ball, the soldered ball are electrically connected with the wiring layer again.
The beneficial effects of the invention are as follows cavity is formed in trepanning, the feelings that wiring layer is detached from weld pad are effectively prevented again
Condition improves the encapsulation yield of image sensing chip, improves the reliability of image sensing chip-packaging structure.
Description of the drawings
Fig. 1 is the encapsulating structure schematic diagram of wafer scale image sensing chip in the prior art；
The structural schematic diagram of Fig. 2 wafer scale image sensing chips；
Fig. 3 is the diagrammatic cross-section of wafer scale image sensing chip-packaging structure；
Fig. 4 to Figure 12 is the schematic diagram of wafer scale image sensing chip packaging method of the present invention；
Figure 13 is single image sensing chip-packaging structure schematic diagram of the invention.
Specific implementation mode
The specific implementation mode of the present invention is described in detail below with reference to attached drawing.But these embodiments are simultaneously unlimited
The system present invention, structure that those skilled in the art are made according to these embodiments, method or transformation functionally
It is included within the scope of protection of the present invention.
Anti-solder ink fills trepanning in the prior art so that anti-solder ink is completely attached to wiring layer again, is caused follow-up
Reflow Soldering and reliability test in, the power that the convergent-divergent of anti-solder ink is formed pulls wiring layer again, is easy to make to connect up again
Layer is detached from weld pad.
To solve the above problems, the present invention by forming cavity in trepanning, make anti-solder ink not with the cloth of aperture bottom
Line layer contacts, and wiring layer can be effectively prevent again to be detached from weld pad.
Referring to FIG. 2, for the structural schematic diagram of wafer scale image sensing chip, there are wafer 100 more grids to arrange
Image sensing chip 110 is reserved with gap between image sensing chip 110, after follow-up completion packaging technology and test,
Image sensing chip is detached along gap.
There is each image sensing chip 110 image sensing area 111 and multiple weld pads 112, weld pad 112 to be located at image biography
The side of sensillary area 111 and the same surface side for being located at wafer 100 with image sensing area 111.
Referring to FIG. 3, for the diagrammatic cross-section of one embodiment of the invention wafer scale image sensing chip-packaging structure.Protection
The multiple support units 210 for being wherein provided with grid arrangement on one side of substrate 200, when wafer 100 and the contraposition of protective substrate 200 are pressed
After conjunction, support unit 210 makes to form gap between the two between wafer 100 and protective substrate 200, and support unit 210
It is corresponded with image sensing chip 110, support unit 210 surrounds image sensing area 111.
Wafer 100 has first surface 101 and the second surface 102 opposite with first surface 101, image sensing area
111 and weld pad 112 be located at 101 side of first surface, have in the second surface 102 of wafer and extend towards first surface 101
Cutting groove 103 and trepanning 113, each trepanning 113 is corresponding with the position of each weld pad 112, and the bottom-exposed of trepanning 113 goes out
Weld pad 112.
Weld pad 112 is facilitated to be connect with All other routes using wiring layer 115 again and soldered ball 116, specifically, trepanning 113
The second surface 102 of side wall and wafer 100 has insulating layer 114, and on insulating layer 114 and the bottom of trepanning 113 is formed
Wiring layer 115 again, then wiring layer 115 are electrically connected with weld pad 112, and are provided with soldered ball on the second surface of wafer 100 102
116, soldered ball 116 is electrically connected with wiring layer 115 again, and being electrically connected other circuits by soldered ball 116 realizes weld pad 112 and other circuits
Between formed electrical connection.
The first photosensitive-ink 117 is filled in cutting groove 103, the second photosensitive-ink 118 covers trepanning 113 and in trepanning
Cavity 119 is formed in 113, in the second photosensitive-ink 118 there is through-hole, through-hole to expose wiring layer 115 again, soldered ball 116 is located at
It is electrically connected in through-hole and with wiring layer 115 again.
In this present embodiment, refering to Fig. 3, cutting groove 103 is overflowed in 117 part of the first photosensitive-ink, and certainly, the present invention is unlimited
Fixed first photosensitive-ink 117 must be full of or overflow cutting groove 103, and the first photosensitive-ink 117 fills the lower half of cutting groove 103
Part, the top half of the second photosensitive-ink 118 filling cutting groove 103 simultaneously cover cutting groove 103.First in the present invention is photosensitive
Ink filling cutting groove be interpreted as the lower half portion that the first photosensitive-ink at least fill cutting groove, without restriction must be full of or
Person overflows cutting groove.
Corresponding, in order to form cavity 119 in trepanning 113, specific packaging technology is as follows.
Wafer 100 is provided, the structural schematic diagram of wafer 100 please refers to Fig.1；
There is provided protective substrate 200, protective substrate 200 wherein have on one side grid arrange multiple support units 210, in
In the present embodiment, the material of support unit 210 is photosensitive-ink, and protective substrate 200 is formed in by way of exposure imaging
Wherein one side.
Referring to FIG. 4, wafer 100 and the contraposition of protective substrate 200 are pressed, using adhesive glue by wafer 100 and protecting group
Plate 200 bonds, and between wafer 100 and protective substrate 200, three surrounds to form multiple grid arrangements support unit 210
Sealing space.Each sealing space corresponds to an image sensing chip 110, and support unit 210 surrounds image sensing chip 110
Image sensing area 111.
Referring to FIG. 5, being ground to the second surface 102 of wafer 100 thinned.The thickness of wafer 100 is D before being thinned,
The thickness of wafer 100 is d after being thinned.
Referring to FIG. 6, being etched towards 100 first surface of wafer in the second surface 102 of wafer 100 using etching technics
101 precut slot 103 ' and trepanning 113.113 bottom-exposed of trepanning goes out weld pad 112.In this present embodiment, slot is precut
103 ' is identical as the depth of trepanning 113.Certainly, trepanning 113 can also be only etched in this step without etching pre-cut
Cut slot 103 '.
Referring to FIG. 7, from the second surface 102 of wafer 100 towards the direction of first surface 101, using cutter along pre-cut
The cutting of slot 103 ' is cut, until the first surface 101 for cutting through wafer 100 forms cutting groove 103, i.e. cutter cuts support unit 210
A part.Since the material of wafer 100 is more crisp, toughness, ductility are poor, and cutter is using the larger knife of hardness, such as steel edge.
Fig. 8 (a) is please referred to, in the second surface 102 of wafer 100, the side wall of trepanning 113 and bottom and cutting groove 103
Inner wall form insulating layer 114, in this present embodiment, insulating layer 114 is organic insulating material, has insulation and certain soft
Property, using spraying, either then spin coating proceeding formation insulating layer 114 exposes weld pad by way of radium-shine or exposure imaging
112。
Fig. 8 (b) is please referred to, it can also be in the second surface 102 of wafer 100, the side wall of trepanning 113 and bottom and cutting
The material of the inner wall depositing insulating layer 114 ' of slot 103, insulating layer 114 ' is inorganic material, usually silica.Due to dioxy
SiClx impact resistance be not so good as organic insulating material 114, it is also necessary to by exposure imaging technique wafer 101 second surface shape
At buffer layer 1140 to facilitate subsequently upper soldered ball, the insulating layer that etching technics etches away 113 bottom of trepanning is then used to expose weldering
Pad 112.
Referring to FIG. 9, form wiring layer 115 again on insulating layer 114 (or insulating layer 114 '), then wiring layer 115 with
Weld pad 112 is electrically connected.
The present invention is critical to be full of photosensitive-ink in cutting groove 103, and cavity 119 is formed in trepanning 113 makes photosensitive oil
Ink does not contact 113 bottom of trepanning, and photosensitive-ink is avoided to be full of trepanning 113.Critical process is as follows.
Referring to FIG. 10, fill the first photosensitive-ink 117 in cutting groove 103 passes through spin coating proceeding in this present embodiment
From 102 the first photosensitive-ink of whole face spin coating 117 of second surface of wafer 100, then use exposure imaging technique by 103rd area of cutting groove
The first photosensitive-ink 117 removal other than domain.
In order to ensure that the first photosensitive-ink 117 is at least full of the lower half portion of cutting groove 103, it is lower that viscosity may be used
Spin coating rate in photosensitive-ink or reduction spin coating proceeding, makes the first photosensitive-ink be sufficiently filled to the bottom of cutting groove 103.
The viscosity of photosensitive-ink can be reduced by adding diluent, it is preferred that the viscosity of the first photosensitive-ink 117 is less than 8Kcps.
1 is please referred to Fig.1, the second photosensitive-ink 118 is coated in the second surface 102 of wafer 100, makes the second photosensitive-ink
118 covering trepannings 113 simultaneously form cavity 119 in trepanning 113.Second photosensitive-ink 118 forms solder mask, convenient follow-up upper weldering
Ball technique plays welding resistance, protection chip.
Subsequently upper soldered ball for convenience needs the position for corresponding to again wiring layer 115 in the second photosensitive-ink 118 to be formed logical
Hole, specifically, by being coated with the second photosensitive-ink 118, resolidification, exposure imaging technique from 100 second surface of wafer, 102 whole face
Through-hole is formed, through-hole exposes wiring layer 115 again.It is of course also possible to by the second photosensitive oily 118 ink by way of silk-screen printing
It is applied to the second surface 102 of wafer 100 and forms the through-hole for exposing again wiring layer 115.
In order to ensure to form cavity 119 in trepanning 113, the higher photosensitive-ink of viscosity may be used or improve spin coating
The spin coating rate of second photosensitive-ink 118 makes the second photosensitive-ink 118 that can not fill the bottom of trepanning 113 and only be covered in
The top half of trepanning 113.Preferably, the viscosity of the second photosensitive-ink 118 is more than 12Kcps.
Preferably, the spin coating rate of the first photosensitive-ink of spin coating 117 is less than the spin coating speed of the second photosensitive-ink of spin coating 118
Rate.
Preferably, the viscosity of the first photosensitive-ink 117 is less than the viscosity of the second photosensitive-ink 118.
2 are please referred to Fig.1, using upper soldered ball technique, forming soldered ball 116 in through-holes makes soldered ball 116 be electrically connected with wiring layer again
It connects.
Finally, along cutting groove 103 crystalline substance is cut from the first surface 101 of second surface 102 towards the wafer 100 of wafer 100
Circle 100 and protective substrate 200, obtain single image sensing chip-packaging structure.
3 are please referred to Fig.1, single image sensing chip-packaging structure 300 includes the substrate cut from wafer 100
310, there is the first face 301 and second face 302 opposite with the first face 301, image sensing area 111 and weld pad 112
In the first face 301, trepanning 113 and soldered ball 116 are located at the second face 302, and the side wall of substrate 310 is coated by photosensitive-ink.
In this present embodiment, the side wall of substrate 310 is by the first photosensitive-ink 117 cladding completely, certainly, the side of substrate 310
Partial sidewall of the wall close to the second face 302 can also be covered by the second photosensitive-ink 118 to be coated, i.e. the first photosensitive-ink 117 packet
Cover part support unit 210 side wall and substrate close to the part of substrate side wall in the first face of substrate 301, substrate is close to the second face
302 partial sidewall is covered by the second photosensitive-ink 118 and is coated.
When insulating layer 114 is organic insulating material, then the position of soldered ball 116 is corresponded between wiring layer 115 and insulating layer 114
Buffer layer 1140 can be not provided with by setting.
When insulating layer 114 ' is inorganic material, then the position of soldered ball 116 is corresponded between wiring layer 115 and insulating layer 114
It is provided with buffer layer 1140, buffer layer 1140 is photoresist, and exposure imaging technique may be used and formed.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiment of understanding.
The series of detailed descriptions listed above only for the present invention feasible embodiment specifically
Bright, they are all without departing from equivalent implementations made by technical spirit of the present invention not to limit the scope of the invention
Or change should all be included in the protection scope of the present invention.
Claims (14)
1. a kind of packaging method of image sensing chip, including：
Wafer is provided, the wafer has first surface and the second surface opposite with the first surface, the wafer tool
There are the image sensing chip that more grids are arranged, image sensing chip that there is image sensing area and weld pad, the image sensing
Area and weld pad are located at the first surface side；
Cutting groove and trepanning corresponding with the weld pad are formed in the second surface of the wafer, the trepanning exposes described
Weld pad；
It is characterized in that, the packaging method further includes：
The first photosensitive-ink is filled in the cutting groove；
It is coated with the second photosensitive-ink in the second surface of the wafer, so that the second photosensitive-ink is covered the trepanning and is opened described
Cavity is formed in hole, the viscosity of second photosensitive-ink is more than 12Kcps.
2. image sensing chip packaging method according to claim 1, which is characterized in that fill in the cutting groove
The step of one photosensitive-ink includes：
Being coated with the first photosensitive-ink in the second surface whole face of the wafer makes the cutting groove fill the first photosensitive-ink；
The first photosensitive-ink other than cutting groove region is removed by way of exposure imaging.
3. image sensing chip packaging method according to claim 1, which is characterized in that described by the way of spin coating
The first photosensitive-ink is filled in cutting groove, and the second photosensitive-ink is coated in the second surface of the wafer by the way of spin coating,
The spin coating rate of the first photosensitive-ink of spin coating is less than the spin coating rate of the second photosensitive-ink of spin coating.
4. image sensing chip packaging method according to claim 1, which is characterized in that first photosensitive-ink is glued
Viscosity of the degree less than the second photosensitive-ink.
5. image sensing chip packaging method according to claim 4, which is characterized in that first photosensitive-ink is glued
Degree is less than 8Kcps.
6. image sensing chip packaging method according to claim 1, which is characterized in that in the wafer second surface shape
Further include before at cutting groove and trepanning：
Protective substrate is provided, the support unit of grid arrangement is provided on the protective substrate, each support unit corresponds to one
Image sensing chip；
By the first surface of the wafer and the protective substrate contraposition press, the support unit be located at the wafer with it is described
Between protective substrate；
The second surface of the wafer is ground thinned.
7. image sensing chip packaging method according to claim 1 or 6, which is characterized in that in the second of the wafer
Surface forms cutting groove and the step of trepanning includes：
Precut road and trepanning are formed in the second surface of the wafer using etching technics simultaneously；
It is cut along the precut road using cutter, the first surface that the cutter cuts through the wafer forms cutting groove.
8. image sensing chip packaging method according to claim 1, which is characterized in that
Further include before being coated with the second photosensitive-ink：
Insulating layer is formed in the side wall of the trepanning；
Wiring layer again is formed on the insulating layer and bottom of the trepanning, the wiring layer again is made to be electrically connected with the weld pad
It connects；Being coated with the second photosensitive-ink in the second surface of the wafer by the way of silk-screen printing makes in second photosensitive-ink
Multiple through-holes are formed, the through-hole exposes the wiring layer again；
Soldered ball is formed in the through-hole, the soldered ball is electrically connected with the wiring layer again.
9. image sensing chip packaging method according to claim 1, which is characterized in that
Further include before being coated with the second photosensitive-ink：
Insulating layer is formed in the side wall of the trepanning；
Wiring layer again is formed on the insulating layer and bottom of the trepanning, the wiring layer again is made to be electrically connected with the weld pad
It connects；By the way of spin coating the second photosensitive-ink is coated in the second surface whole face of the wafer；
Formed in second photosensitive-ink by way of exposure imaging multiple through-holes make the through-hole expose it is described again
Wiring layer；
Soldered ball is formed in the through-hole, the soldered ball is electrically connected with the wiring layer again.
10. a kind of image sensing chip-packaging structure, including：
Substrate has the first face and second face opposite with first face；
Image sensing area positioned at the first face of the substrate and weld pad；
Positioned at second face and to the trepanning that the first surface extends, the trepanning is corresponding with the weld pad and exposes institute
State weld pad；
Coat the first photosensitive-ink of the substrate side；
It is characterized in that：
The encapsulating structure further includes the second photosensitive-ink, and second photosensitive-ink covers the trepanning and in the trepanning
Cavity is formed, the viscosity of second photosensitive-ink is more than 12Kcps.
11. image sensing chip-packaging structure according to claim 10, which is characterized in that the encapsulating structure also wraps
It includes：The protective substrate of position pressing is faced with the substrate first；
Support unit between the protective substrate and the substrate, the support unit surround the image sensing area；
The side of support unit described in the first photosensitive-ink covered section.
12. image sensing chip-packaging structure according to claim 10, which is characterized in that first photosensitive-ink
Viscosity is less than the viscosity of the second photosensitive-ink.
13. image sensing chip-packaging structure according to claim 12, which is characterized in that first photosensitive-ink
Viscosity is less than 8Kcps.
14. image sensing chip-packaging structure according to claim 10, which is characterized in that the encapsulating structure also wraps
It includes：Insulating layer in the trepanning；
On the insulating layer and the wiring layer again of aperture bottom, the wiring layer again are electrically connected with the weld pad；
Second photosensitive-ink covering wiring layer again, and through-hole is provided in second photosensitive-ink, it is described to lead to
Hole exposes the wiring layer again；
Soldered ball is provided in through-hole, the soldered ball is electrically connected with the wiring layer again.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510649774.1A CN105226036B (en) | 2015-10-10 | 2015-10-10 | The packaging method and encapsulating structure of image sensing chip |
| PCT/CN2016/100559 WO2017059777A1 (en) | 2015-10-10 | 2016-09-28 | Packaging method and package structure for image sensing chip |
| JP2018537708A JP6503518B2 (en) | 2015-10-10 | 2016-09-28 | Image sensing chip packaging method and package structure |
| US15/765,968 US10325946B2 (en) | 2015-10-10 | 2016-09-28 | Packaging method and package structure for image sensing chip |
| KR1020187007798A KR102082714B1 (en) | 2015-10-10 | 2016-09-28 | Packaging Method and Package Structure for Image Sensing Chips |
| TW105131852A TWI698989B (en) | 2015-10-10 | 2016-10-03 | A packaging method and structure for an image sensing chip |
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| CN201510649774.1A CN105226036B (en) | 2015-10-10 | 2015-10-10 | The packaging method and encapsulating structure of image sensing chip |
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| CN105226036A CN105226036A (en) | 2016-01-06 |
| CN105226036B true CN105226036B (en) | 2018-09-28 |
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| US10325946B2 (en) | 2015-10-10 | 2019-06-18 | China Wafer Level Csp Co., Ltd. | Packaging method and package structure for image sensing chip |
| CN106409771B (en) * | 2016-05-25 | 2019-09-17 | 苏州晶方半导体科技股份有限公司 | The packaging method and encapsulating structure of semiconductor chip |
| CN106024819B (en) * | 2016-07-01 | 2020-04-21 | 格科微电子（上海）有限公司 | Wafer level packaging method of CMOS image sensor |
| CN106098668A (en) * | 2016-08-15 | 2016-11-09 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip package and method for packing |
| CN107068629B (en) * | 2017-04-24 | 2019-11-26 | 华天科技（昆山）电子有限公司 | Wafer stage chip encapsulating structure and preparation method thereof |
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