CN205984968U - Packaging structure of semiconductor chip - Google Patents
Packaging structure of semiconductor chip Download PDFInfo
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- CN205984968U CN205984968U CN201620483572.4U CN201620483572U CN205984968U CN 205984968 U CN205984968 U CN 205984968U CN 201620483572 U CN201620483572 U CN 201620483572U CN 205984968 U CN205984968 U CN 205984968U
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- hole
- wiring layer
- solder mask
- metal wiring
- semiconductor chip
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Abstract
The utility model provides a packaging structure of semiconductor chip, include: the basement, be located the functional areas and the weld pad of basement first surface side, be located the through -hole of basement second surface, the through -hole bottom exposes the weld pad, set up in the bottom of through -hole and the metal wiring layer of lateral wall, the metal wiring layer with the weld pad electricity is connected, set up in the second surface of basement and solder mask in the through -hole, be provided with the opening on the solder mask, the opening bottom exposes the metal wiring layer, it is protruding to be provided with the welding in the opening, the welding protruding with metal wiring layer electricity is connected, the position that the solder mask corresponds the through -hole has the recess, the degree of depth of recess with is difference between the degree of depth of through -hole 0 20 the micron, the condition that metal wiring layer and weld pad layering break away from has been avoided to the stress that acts on the metal wiring layer that has reduced effectively that the solder mask produces in the test of subsequent reliability.
Description
Technical field
This utility model is related to technical field of semiconductors, the more particularly, to encapsulation technology of wafer level semiconductor chip.
Background technology
The semiconductor die package technology of main flow is crystal wafer chip dimension encapsulation technology (Wafer Level Chip now
Size Packaging, WLCSP), be full wafer wafer is packaged and tests after cut the skill obtaining single finished product chip again
Art.Using the single finished product chip size after the encapsulation of this kind of encapsulation technology with single crystallite dimension almost, complied with market pair
Microelectronic product is increasingly light, little, short, thinning and low priceization require.Crystal wafer chip dimension encapsulation technology is current encapsulation field
Focus and future development trend.
Refer to Fig. 1, disclose a kind of encapsulating structure of wafer level semiconductor chip, wafer 1 and protective substrate 2 para-position pressure
Close, support unit 3 is located at and makes to be formed between the two gap between wafer 1 and protective substrate 2, it is to avoid protective substrate 2 is straight with wafer 1
Contact, wafer 1 includes the semiconductor chip 10 of many latticed arrangements, and semiconductor chip 10 includes functional areas 11 and weld pad
12, multiple support units 3 are latticed be arranged on protective substrate 2 and corresponding with semiconductor chip 10, when protective substrate 2 and wafer
After 1 para-position pressing, functional areas 11 are located at support unit 3 and surround in the annular seal space 13 being formed, and wafer 1 has relative to each other first
Surface and second surface, functional areas 11 and weld pad 12 are located at the first surface side of wafer.
Electrically connect with other circuit to realize weld pad 12, be provided with towards first surface in the second surface side of wafer 1
The through hole 22 extending, through hole 22 is corresponding with weld pad 12 and bottom-exposed of through hole 22 goes out weld pad 12, through hole 22 side wall and
Insulating barrier 23 is provided with the second surface of wafer, on the insulating barrier 23 and bottom of through hole 22 is provided with metal wiring layer 24,
Metal wiring layer 24 is electrically connected with weld pad 12, arranges soldered ball 25, soldered ball 25 and metal wiring layer 24 on the second surface of wafer
Electrical connection, is formed between weld pad 12 and other circuit by soldered ball 25 other circuit realiration of electrical connection and electrically connects.
Image sensing chip cutting for the ease of completing encapsulation is got off, and the second surface in wafer 1 is provided with direction
The cutting groove 21 that first surface extends.
Before the second surface setting soldered ball 25 to wafer 1, need to set on the second surface of wafer and in through hole
Put solder mask 26, the material of solder mask is photoresists herein, can be in photoresists by photoresists are exposed with developing process
Upper formation opening, open bottom exposing metal wiring layer 24, soldered ball 25 is arranged in opening and is electrically connected with metal wiring layer 24,
Generally, photoresists almost fill out through hole 22 and cutting groove 21.
However, because photoresists fill up through hole 22, in follow-up reliability is tested, the photoresists flatulence of heat type in through hole 22 is cold
Contracting forms the stress acting on metal wiring layer 24, and under the pullling of this kind of stress, metal wiring layer 24 is easily taken off with weld pad 12
From leading to metal wiring layer 24 and weld pad 12 loose contact, become those skilled in the art and bite technical problem to be solved.
Utility model content
The problem that this utility model solves be the wafer level semiconductor chip packaging method that provided by this utility model with
And semiconductor chip package, eliminate the situation that metal wiring layer is departed from weld pad layering, solve metal wiring layer and weld pad
Loose contact, improves quality and the reliability of semiconductor chip package.
For solving the above problems, this utility model provides a kind of semiconductor chip package, including：Substrate, has that
This relative first surface and second surface；Functional areas and weld pad positioned at described substrate first surface side；Positioned at described
Second surface the through hole extending to described first surface, described via bottoms expose described weld pad；It is arranged at described through hole
Bottom and the metal wiring layer of side wall, described metal wiring layer extends to the second surface of described substrate, described metal line
Layer is electrically connected with described weld pad；It is arranged at the solder mask in the second surface of described substrate and described through hole, described solder mask
Cover described metal wiring layer；On described solder mask, the position of the second surface of corresponding described substrate is provided with opening, described opens
Metal wiring layer described in mouth bottom-exposed；It is provided with solder-bump, described solder-bump and described metal line in described opening
Layer electrical connection；The position of the corresponding through hole of described solder mask has groove, between the depth of the depth of described groove and described through hole
Difference be 0-20 micron.
Preferably, described encapsulating structure also includes：Protective substrate with described substrate first surface para-position pressing；Positioned at institute
State the support unit between protective substrate and described substrate, described functional areas are located at described support unit and surround the annular seal space being formed
Interior.
Preferably, second of the side wall of through hole, the bottom of through hole and described substrate described in described solder mask uniform fold
Surface.
Preferably, the thickness range of described solder mask is 5-20 micron.
Preferably, described solder mask material is photoresists.
Preferably, described semiconductor chip is image sensing chip, and described functional areas have image sensing function.
The beneficial effects of the utility model are by reducing solder mask loading in through-holes, effectively reducing solder mask
Act on the stress on metal wiring layer in follow-up reliability test, it is to avoid metal wiring layer and weld pad layering depart from
Situation, improves the encapsulation yield of semiconductor chip, improves quality and the reliability of semiconductor chip package.
Brief description
Fig. 1 is the encapsulating structure schematic diagram of wafer level semiconductor chip in prior art；
The structural representation of Fig. 2 wafer level semiconductor chip；
Fig. 3 is the generalized section of this utility model preferred embodiment wafer level semiconductor chip-packaging structure；
Fig. 4 is the structural representation of this utility model preferred embodiment wafer and protective substrate para-position pressing；
Fig. 5 structural representation after thinning for this utility model preferred embodiment wafer；
Fig. 6 forms the structural representation of through hole and cutting groove for this utility model preferred embodiment；
Fig. 7 forms the structural representation of insulating barrier for this utility model preferred embodiment；
Fig. 8 forms the structural representation of metal wiring layer for this utility model preferred embodiment；
Fig. 9 (a) forms the structural representation of solder mask for this utility model preferred embodiment；
Fig. 9 (b) is the structural representation that another embodiment of this utility model forms solder mask；
Figure 10 forms the structural representation of opening for this utility model preferred embodiment on solder mask；
Figure 11 forms the structural representation of solder-bump for this utility model preferred embodiment；
Figure 12 is single semiconductor chip package schematic diagram of this utility model preferred embodiment.
Specific embodiment
Below with reference to accompanying drawing, specific embodiment of the present utility model is described in detail.But these embodiments are simultaneously
Do not limit this utility model, structure, method or function that those of ordinary skill in the art is made according to these embodiments
On conversion be all contained in protection domain of the present utility model.
In prior art, solder mask almost fills out through hole, leads in follow-up reliability is tested, the contraction of solder mask is swollen
The stress that bulging becomes pulls metal wiring layer, so that metal wiring layer is departed from weld pad layering.
For solving the above problems, this utility model passes through to reduce the loading of solder mask in through hole, effectively reduces welding resistance
Stress that layer produces in follow-up reliability test, it is to avoid the situation that metal wiring layer is departed from weld pad layering, improves
The encapsulation yield of semiconductor chip, improves the reliability of semiconductor chip package.
Refer to Fig. 2, be the structural representation of wafer level semiconductor chip, wafer 100 has the half of many grid arrangements
Conductor chip 110, is reserved with space between semiconductor chip 110, after subsequently completing packaging technology and test, along space
Separating semiconductor chip.
Each semiconductor chip 110 has functional areas 111 and multiple weld pad 112, and weld pad 112 is located at functional areas 111
Side and with functional areas 111 be located at wafer 100 same face side.
Refer to Fig. 3, be the generalized section of this utility model preferred embodiment wafer level semiconductor chip-packaging structure.
The multiple support units 210 being wherein simultaneously provided with grid arrangement of protective substrate 200, when wafer 100 is right with protective substrate 200
After the pressing of position, support unit 210 is located at and makes to form gap between the two between wafer 100 and protective substrate 200, and support unit
210 are corresponded with semiconductor chip 110, and functional areas 111 are located at support unit 210 and surround the annular seal space 220 being formed.
Wafer 100 has each other relative first surface 101 and second surface 102, functional areas 111 and weld pad 112
Positioned at first surface 101 side, in the second surface 102 of wafer, there is the cutting groove 103 towards first surface 101 extension and lead to
Hole 113, each through hole 113 is corresponding with the position of each weld pad 112, and the bottom-exposed of through hole 113 goes out weld pad 112.
Realize weld pad 112 using metal wiring layer 115 and solder-bump 116 to connect with outside line, specifically, through hole
113 side wall and the second surface 102 of wafer 100 have insulating barrier 114, and in the present embodiment, the material of insulating barrier 114 is
Silicon dioxide, its thickness range is 2-5 micron, the metal electrically connecting with weld pad 112 in the bottom of through hole 113 and the formation of side wall
Wiring layer 115, metal wiring layer 115 extends to the second surface 102 of wafer 100, and metal wiring layer 115 is located at insulating barrier 114
Top, is provided with solder-bump 116 on the second surface 102 of wafer 100, and solder-bump 116 is electrically connected with metal wiring layer 115
Connect, the connection that external circuit realizes weld pad 112 and external circuit is electrically connected by solder-bump 116.
Solder mask 117 covers the side wall of the second surface 102, cutting groove 103 side wall and bottom, through hole 113 of wafer 100
And bottom, solder mask 117 is located at the top of metal wiring layer 115, the second surface 102 of corresponding wafer 100 on solder mask 117
Position be provided with opening, open bottom exposes metal wiring layer 115, solder-bump 116 be located at opening in and and hardware cloth
Line layer 115 electrically connects.
Form groove 118 in the position of the corresponding through hole 113 of solder mask 117, thus reducing the solder mask in through hole 113
The loading of 117 materials, reduces solder mask 117 and acts on answering on metal wiring layer 115 in follow-up reliability test
Power, it is to avoid the situation that metal wiring layer 115 is departed from weld pad 112 layering.
Depth h of groove 118 is roughly equal with the depth H of through hole, and the depth H of through hole 113 can be more than the depth of groove 118
Degree, difference range between the two, between 0-20 micron, can effectively be eliminated metal wiring layer 115 and be departed from weld pad 112 layering
Situation.
Corresponding, in order to form groove 118 on solder mask 117, specific packaging technology is as follows.
There is provided wafer 100, the structural representation of wafer 100 refer to Fig. 2；
There is provided protective substrate 200, protective substrate 200 wherein simultaneously have grid arrangement multiple support units 210, in
In the present embodiment, the material of support unit 210 is photoresists.Being coated with photoresists by whole face then will using exposure imaging technique
Support unit 210 is formed at the wherein one side of protective substrate 200.Or, support grid arranged by silk-screen printing technique
Unit 210 is formed at the wherein one side of protective substrate 200.
Refer to Fig. 4, by wafer 100 and protective substrate 200 para-position pressing, using adhesive glue by wafer 100 and protection group
Plate 200 bonds, and support unit 210 is located between wafer 100 and protective substrate 200, and each support unit 210 corresponding one and half is led
Body chip 110, the functional areas 111 of semiconductor chip 110 are located at support unit 210 and surround in the annular seal space 220 being formed.
Refer to Fig. 5, the second surface 102 of wafer 100 is ground thinning.The thickness of thinning front wafer 100 is D
(refer to Fig. 4), the thickness of thinning rear wafer 100 is d.
Refer to Fig. 6, etched towards wafer 100 first surface in the second surface 102 of wafer 100 using etching technics
The through hole 113 of 101 extensions.The depth of through hole is H.Cut out towards crystalline substance in the second surface 102 of wafer 100 using cutting technique
The cutting groove 103 that circle 100 first surface 101 extends.It is also possible to first cut out cutting in another embodiment of the present utility model
Then groove 103 etches through hole 113.
Refer to Fig. 7, in the side of the second surface 102 of wafer 100, the side wall of through hole 113 and bottom and cutting groove 103
Insulating barrier 114 is formed on wall and bottom, and in the present embodiment, insulating barrier 114 is organic insulation, has and insulate and certain
Flexibility, forms insulating barrier 114 using spraying or spin coating proceeding, then exposes weldering by way of radium-shine or exposure imaging
Pad 112.
In another embodiment of the present utility model, the material of insulating barrier 114 is inorganic material, the second of wafer 100
The inwall depositing insulating layer 114 on surface 102, the side wall of through hole 113 and bottom and cutting groove 103, usually silicon dioxide.Excellent
Choosing, due to silicon dioxide impact resistance be not so good as organic insulation, by exposure imaging technique wafer 101 the second table
The position of the corresponding solder-bump in face forms cushion.Can be exposed using the insulating barrier that etching technics etches away through hole 113 bottom
Weld pad 112.
Refer to Fig. 8, metal wiring layer 115 is formed on insulating barrier 114, metal wiring layer 115 is located at the side of through hole 113
Wall and bottom simultaneously extend to the second surface 102 of wafer 100, and metal wiring layer 115 is electrically connected with weld pad 112.Preferably, gold
The thickness range belonging to wiring layer 115 is 1-5 micron.
Refer to Fig. 9 (a), using spraying coating process in the side wall of cutting groove 103 and bottom, the side wall of through hole 113 and bottom
And the second surface 102 of wafer 100 forms solder mask 117 in uniform thickness, conveniently subsequently go up soldered ball technique, play welding resistance, guarantor
The effect of shield chip.
In the present embodiment, the material of solder mask 117 is the conventional photoresists of technical field of semiconductors.
Because of solder mask 117 thickness uniformly, therefore, define groove 118 in the position of the corresponding through hole 113 of solder mask 117, recessed
The depth of groove 118 is h, and in this embodiment, depth h of groove 118 is almost roughly equal with the depth H of through hole.
Second surface because of the side wall, the bottom of through hole 113 and wafer 100 of solder mask 117 uniform fold through hole 113
102, thus reducing the loading of solder mask 117 material in through hole 113, reduce solder mask 117 in follow-up reliability
The stress on metal wiring layer 115 is acted on, it is to avoid the situation that metal wiring layer 115 is departed from weld pad 112 layering in test.
Preferably, the thickness range of solder mask 117 is 5-20 micron.
Refer to Fig. 9 (b) is the another way forming groove in the position of the corresponding through hole of solder mask.Using spin coating proceeding
Solder mask 117 ', cutting groove 103 and through hole are formed on the second surface 102 of cutting groove 103, through hole 113 and wafer 100
It is almost full with soldermask material in 113, then adopt etching technics or laser boring technique upper corresponding logical in solder mask 117 '
The position in hole 113 forms groove 118 '.
Depth h of groove 118 (or groove 118 ') is roughly equal with the depth H of through hole 113, and the depth H of through hole 113 can
With the depth (or groove 118 ') more than groove 118, difference range between the two, between 0-20 micron, can effectively eliminate
The situation that metal wiring layer 115 is departed from weld pad 112 layering.
Refer to Figure 10, be subsequently formed solder-bump for convenience, need the second surface of corresponding wafer on solder mask
Position formed opening, specifically, on solder mask 117 (or on solder mask 117 ') by exposure imaging technique formed opening
1170, opening 1170 bottom-exposed metal wiring layer 115.
Refer to Figure 11, using planting ball technique, forming solder-bump 116 in opening 1170 makes solder-bump 116 and gold
Belong to wiring layer 115 to electrically connect.
Finally, cut crystalline substance along cutting groove 103 from the second surface 102 of wafer 100 towards the first surface 101 of wafer 100
Circle 100 and protective substrate 200, obtain the semiconductor chip package of single.
Refer to Figure 12, single semiconductor chip package 300 includes cutting the substrate 310 obtaining from wafer 100,
It has each other relative first surface 301 and second surface 302, and functional areas 111 and weld pad 112 are located at first surface
301, through hole 113 and solder-bump 116 are located at second surface 302, and the side wall of substrate 310 is coated by solder mask 117.
When insulating barrier 114 is organic insulation, corresponding solder-bump between metal wiring layer 115 and insulating barrier 114
116 position can be not provided with cushion.
When insulating barrier 114 ' is inorganic material, corresponding solder-bump 116 between metal wiring layer 115 and insulating barrier 114
Position be provided with cushion, cushion can be photoresists, can be formed using exposure imaging technique.
Solder mask 117 covers the side wall of the second surface 102, cutting groove 103 side wall and bottom, through hole 113 of wafer 100
And bottom, solder mask 117 is located at the top of metal wiring layer 115, the second surface 102 of corresponding wafer 100 on solder mask 117
Position be provided with opening, open bottom exposes metal wiring layer 115, solder-bump 116 be located at opening in and and hardware cloth
Line layer 115 electrically connects.
Form groove 118 in the position of the corresponding through hole 113 of solder mask 117, thus reducing the solder mask in through hole 113
The loading of 117 materials, reduces solder mask 117 and acts on answering on metal wiring layer 115 in follow-up reliability test
Power, it is to avoid the situation that metal wiring layer 115 is departed from weld pad 112 layering.
Depth h of groove 118 is roughly equal with the depth H of through hole, and the depth H of through hole 113 can be more than the depth of groove 118
Degree, difference range between the two, between 0-20 micron, can effectively be eliminated metal wiring layer 115 and be departed from weld pad 112 layering
Situation.
Semiconductor chip in the present embodiment is image sensing chip, and functional areas are image sensing area.Certainly, this practicality is new
Type is not limited to image sensing chip.
It should be understood that although this specification is been described by according to embodiment, but not each embodiment only comprises one
Individual independent technical scheme, only for clarity, those skilled in the art should will say this narrating mode of description
As an entirety, the technical scheme in each embodiment can also be through appropriately combined, and forming those skilled in the art can for bright book
With the other embodiment understanding.
The a series of detailed description of those listed above is only for the tool of feasibility embodiment of the present utility model
Body illustrates, they are simultaneously not used to limit protection domain of the present utility model, all is made without departing from this utility model skill spirit
Equivalent implementations or change should be included within protection domain of the present utility model.
Claims (6)
1. a kind of semiconductor chip package, including：
Substrate, has each other relative first surface and the second surface；
Functional areas and weld pad positioned at described substrate first surface side；
The through hole extending positioned at described second surface and to described first surface, described via bottoms expose described weld pad；
It is arranged at the bottom of described through hole and the metal wiring layer of side wall, described metal wiring layer extends to the of described substrate
Two surfaces, described metal wiring layer is electrically connected with described weld pad；
It is arranged at the solder mask in the second surface of described substrate and described through hole, described solder mask covers described metal line
Layer；
On described solder mask, the position of the second surface of corresponding described substrate is provided with opening, and described open bottom exposes described gold
Belong to wiring layer；
It is provided with solder-bump, described solder-bump is electrically connected with described metal wiring layer in described opening；
It is characterized in that,
The position of the corresponding through hole of described solder mask has groove, the difference between the depth of the depth of described groove and described through hole
For 0-20 micron.
2. semiconductor chip package according to claim 1 is it is characterised in that described encapsulating structure also includes：
Protective substrate with described substrate first surface para-position pressing；
Support unit between described protective substrate and described substrate, described functional areas are located at described support unit and surround shape
The sealing intracavity becoming.
3. semiconductor chip package according to claim 1 is it is characterised in that described in described solder mask uniform fold
The second surface of the side wall, the bottom of through hole and described substrate of through hole.
4. semiconductor chip package according to claim 3 is it is characterised in that the thickness range of described solder mask is
5-20 micron.
5. semiconductor chip package according to claim 1 is it is characterised in that described solder mask material is photosensitive
Glue.
6. semiconductor chip package according to claim 1 is it is characterised in that described semiconductor chip passes for image
Sense chip, described functional areas have image sensing function.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620483572.4U CN205984968U (en) | 2016-05-25 | 2016-05-25 | Packaging structure of semiconductor chip |
| PCT/CN2017/085450 WO2017202288A1 (en) | 2016-05-25 | 2017-05-23 | Packaging method and packaging structure for semiconductor chip |
| US16/303,722 US20200395399A1 (en) | 2016-05-25 | 2017-05-23 | Packaging method and packaging structure for semiconductor chip |
| TW106117060A TWI655696B (en) | 2016-05-25 | 2017-05-23 | Packaging method and packaging structure for semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620483572.4U CN205984968U (en) | 2016-05-25 | 2016-05-25 | Packaging structure of semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205984968U true CN205984968U (en) | 2017-02-22 |
Family
ID=58019778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620483572.4U Active CN205984968U (en) | 2016-05-25 | 2016-05-25 | Packaging structure of semiconductor chip |
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| CN (1) | CN205984968U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057763A (en) * | 2016-05-25 | 2016-10-26 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging method and semiconductor chip packaging structure |
-
2016
- 2016-05-25 CN CN201620483572.4U patent/CN205984968U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106057763A (en) * | 2016-05-25 | 2016-10-26 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging method and semiconductor chip packaging structure |
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| GR01 | Patent grant |