CN109801883A - A kind of fan-out-type stacking encapsulation method and structure - Google Patents
A kind of fan-out-type stacking encapsulation method and structure Download PDFInfo
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- CN109801883A CN109801883A CN201811640485.5A CN201811640485A CN109801883A CN 109801883 A CN109801883 A CN 109801883A CN 201811640485 A CN201811640485 A CN 201811640485A CN 109801883 A CN109801883 A CN 109801883A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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Abstract
The invention discloses a kind of fan-out-type stacking encapsulation method and structures, wherein this method comprises: the first surface in the first support plate attaches conducting bridge and the first chip；Conducting bridge is the internal block at least one conductive metal wire, and conducting bridge makes obtain by the following method: predetermined position punches and fills conductive metal in hole on the substrate of inorganic as needed；According to design requirement cutting substrate, conducting bridge is obtained；The first support plate first surface formed the first molding layer, the first molding layer coat the first chip and conducting bridge side wall, and expose the first chip pad and conducting bridge in conductive metal wire both ends；The second chip is set toward or away from the side of the first support plate in the first molding layer.The present invention program can be improved the wiring density for rerouting layer；Simultaneously can provide unlike material substrate be prepared into conducting bridge for stack it is integrated, reduce plastic packaging wafer warpage, improve reroute technique yield.
Description
Technical field
The present invention relates to integrated circuit Advanced Packaging fields, and in particular to a kind of fan-out-type stacking encapsulation method and knot
Structure.
Background technique
At least layers of chips it will stack setting and be encapsulated, the size of encapsulating structure can be substantially reduced.Stacking envelope
Dress method realizes that the electric signal between each layer connects by being embedded in conductive structure in packaging body, to reduce required inbuilt conduction
The quantity of structure generallys use rewiring layer or routing for chip bonding pad and is fanned out to setting.
In existing fan-out-type stacking encapsulation method, the conductive structure connected for realizing electric signal between each layer is often used
Conductive metal column.For example, with reference to Fig. 1, existing fan-out-type stacking encapsulation method includes the following steps: first the first table in support plate 1
Interim bonded layer 2 is arranged in face；First is formed on interim bonded layer 2 reroutes layer 3；It is rerouted first and attaches conduction on layer 3
Metal column 4 and the first chip 5；The first molding layer 6 is formed in the first surface that first reroutes layer 3, the first molding layer 6 is at least
The side wall of coated with conductive metal column 4 and the first chip 5, and expose one end of conductive metal column 4；On the surface of the first molding layer 6
It forms second and reroutes layer 7；The second chip 8 is attached on the surface that second reroutes layer 7；In the surface shape that second reroutes layer 7
At the second molding layer 9.
Inventors have found that, for the ease of attaching, often requiring that and leading when first reroutes and attach conductive metal column 4 on layer 3
The larger namely conductive metal column of end cross-sectional product of electric metal column is thicker.However, thicker conductive metal column is but increased and is led
The wiring difficulty for the rewiring layer that electric metal column 4 is electrically connected.For example, in the rewiring for having electrical connection with conductive metal column 4
On layer, for two conducting wires not being electrically connected near the end of conductive metal column 4 but with the conductive metal column 4, wire spacing is extremely
It is greater than the end diameter of conductive metal column 4 less, can guarantees that the electric current of this two conducting wires will not influence each other, this is certain
The wiring density for rerouting layer is reduced in degree, the surface area for rerouting layer is increased, if therefore making encapsulating structure surface
Product is smaller, and the conductor layouts' difficulty for rerouting layer further increases.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of fan-out-type stacking encapsulation method and structure, to solve existing skill
The larger problem of conductor layouts' difficulty of layer is rerouted in art.
According in a first aspect, the embodiment of the invention provides a kind of fan-out-type stacking encapsulation methods, comprising: in the first support plate
First surface attach conducting bridge and the first chip；The conducting bridge is the internal block at least one conductive metal wire,
And the conducting bridge makes obtain by the following method: predetermined position punches and in institute on the substrate of inorganic as needed
State filling conductive metal in hole；The substrate is cut as needed, obtains the conducting bridge；In the first table of first support plate
Face forms the first molding layer, and the first molding layer coats the side wall of first chip and the conducting bridge, and described in exposing
The both ends of conductive metal wire in the pad of first chip and the conducting bridge；In the first molding layer toward or away from described
The second chip is arranged in the side of one support plate.
Optionally, the first surface in the first support plate attaches conducting bridge and the first chip, in first support plate
The step of first surface the first molding layer of formation includes: that the one end for exposing conductive metal wire on conducting bridge is attached to described first
The first surface of support plate；Dielectric layer is formed in the first surface of first support plate, the dielectric layer coats the conducting bridge side
The partial region of wall；The first chip, the weldering of first chip are attached backwards to the surface of first support plate in the dielectric layer
Disk is directed away from the direction of first support plate；The first molding is formed backwards to the surface of first support plate in the dielectric layer
Layer, the first molding layer coats the side wall of first chip, and coats the remaining area of the conducting bridge side wall, and expose
The both ends of conductive metal wire in the pad and the conducting bridge of first chip.
Optionally, described that the second chip is set toward or away from the side of first support plate in the first molding layer
Step includes: to remove first support plate；The second chip is attached in the side surface for originally attaching first support plate；Described
The pad of two chips is directed away from the direction of first chip；Reveal in the pad of second chip and described conducting bridge one end
Metal routing is set between conductive metal wire out.
Optionally, described that the second chip is set toward or away from the side of first support plate in the first molding layer
After step, further includes: form the second molding layer, the second molding layer cladding on the surface for originally attaching first support plate
Metal routing between second chip and the pad and the conducting bridge of second chip.
Optionally, described that the second chip is set toward or away from the side of first support plate in the first molding layer
Step includes: the plate body that production is provided with the second chip and the second rewiring layer；Wherein, described second layer is rerouted positioned at described
Plate body surface, and at least one conducting wire of the second rewiring layer is electrically connected with the pad of second chip；By the plate
Body is welded on the first molding layer toward or away from a side surface of the support plate；Wherein, described second layer is rerouted extremely
A few conducting wire is electrically connected with the one end for the conductive metal wire that the first molding layer surface is exposed.
Optionally, after the step of first surface in first support plate forms the first molding layer, further includes:
The predetermined surface setting first of the first molding layer reroutes layer and/or soldered ball, wherein the predetermined surface and described second
Chip is located at the two sides of the first molding layer.
According to second aspect, the embodiment of the invention provides a kind of fan-out-type stack package structures, comprising: the first chip；
First molding layer coats the side wall of first chip；And expose the pad of first chip；Conducting bridge has for inside
The block of at least one conductive metal wire, and the conducting bridge makes obtain by the following method: as needed in inorganic
Substrate on predetermined position punch and fill conductive metal in the hole, it is described to obtain to cut the substrate as needed
Conducting bridge；The conducting bridge penetrates through the first molding layer, and in the conducting bridge conductive metal wire both ends respectively described
The both side surface of first molding layer is exposed；Second chip, is set to the side of the first molding layer, and with first chip
Stack setting.
Optionally, the fan-out package structure further include: dielectric layer is set to first chip and second core
Between piece, and coat the partial region of the conducting bridge side wall.
Optionally, it is provided with and leads between the conductive metal wire that the pad of second chip and described conducting bridge one end are exposed
Line；The encapsulating structure further include: the second molding layer is set to the side of the first molding layer, and coats second core
Conducting wire between piece and the pad and the conducting bridge of second chip.
Optionally, the fan-out package structure further include: first reroutes layer and/or soldered ball, is set to described first
The predetermined surface of molding layer, wherein the predetermined surface and second chip are located at the two sides of the first molding layer.
Fan-out-type stacking encapsulation method and structure provided by the embodiment of the present invention, in the prior art using conducting bridge replacement
Conductive metal column realize the connection of electric signal between each layer, on the one hand, since conducting bridge is on the substrate of inorganic
Punch and simultaneously fill conductive metal in hole and obtain, therefore its internal conductive metal wire can be made relatively thin, therefore, with lead
Electric metal line has in the wiring of electrical connection, for not being electrically connected near the end of conductive metal wire but with conductive metal wire
Two conducting wires, wire spacing, which is arranged, compared with urine can guarantee that the electric current of two conducting wires will not influence each other；On the other hand, in nothing
Punching and when filling conductive metal in hole on the substrate of machine material, can according to need the distribution situation or again of chip bonding pad
The layout scenarios of wiring layer determine the layout in hole, and above-mentioned two aspect can be improved the wiring density for rerouting layer, so that weight cloth
The layout of line is more reasonable；Simultaneously because the substrate for being capable of providing unlike material is prepared into, conducting bridge is integrated for stacking, and reduction is moulded
The warpage degree for sealing wafer improves the yield for rerouting technique；Furthermore using the stacking knot of the system integration of patch form
Structure, manufacturing cost are lower.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 shows the package structure diagram that existing fan-out-type stacking encapsulation method obtains；
Fig. 2 shows a kind of flow charts of fan-out-type stacking encapsulation method according to an embodiment of the present invention；
Fig. 3 shows the flow chart of another fan-out-type stacking encapsulation method according to an embodiment of the present invention；
Fig. 4 shows the flow chart of another fan-out-type stacking encapsulation method according to an embodiment of the present invention；
Fig. 5 shows the flow chart of another fan-out-type stacking encapsulation method according to an embodiment of the present invention；
Fig. 6 A to Fig. 6 F is shown in a kind of fan-out-type stacking encapsulation method of the embodiment of the present invention obtained by part steps
Structural schematic diagram；
Fig. 6 G shows the encapsulating structure that another fan-out-type stacking encapsulation method according to an embodiment of the present invention obtains and shows
It is intended to；
Fig. 7 A to Fig. 7 F is shown in another fan-out-type stacking encapsulation method of the embodiment of the present invention obtained by part steps
The structural schematic diagram arrived；
Fig. 7 G shows the encapsulating structure that another fan-out-type stacking encapsulation method according to an embodiment of the present invention obtains and shows
It is intended to；
Appended drawing reference:
10 --- the first support plate；20 --- interim bonded layer；30 --- conducting bridge；
31 --- conductive metal wire；32 --- inorganic；40 --- the first chip；
50 --- the first molding layer；60 --- reroute layer；70 --- soldered ball；
80 --- the second chip；90 --- metal routing；100 --- the second molding layer；
110 --- glue film；120 --- reroute layer；130 --- dielectric layer.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those skilled in the art are not having
Every other embodiment obtained under the premise of creative work is made, shall fall within the protection scope of the present invention.
Embodiment one
The embodiment of the invention provides a kind of fan-out-type stack package structures, and as shown in Fig. 6 F, Fig. 6 G, which is stacked
Encapsulating structure includes the first chip 40, the first molding layer 50, conducting bridge 30 and the second chip 80.
First molding layer 50 coat the first chip 40 side wall, and expose the first chip 40 pad (in Fig. 6 F, the first core
The pad of piece 40 is directed away from the direction of the second chip 80).
Conducting bridge 30 is the internal block at least one conductive metal wire, and conducting bridge 30 makes by the following method
Obtain: predetermined position is punched and is filled out in hole on the substrate of inorganic (for example, silicon, silica, glass) as needed
Fill conductive metal；Then cutting substrate as needed, obtains conducting bridge.The longitudinal sectional view of conducting bridge 30 refers in Fig. 6 A
30, top view refers to Fig. 6 B.It can be seen that conducting bridge 30 consists of two parts: conductive metal wire 31 and coated with conductive metal
The inorganic 32 of line 31.
Conducting bridge 30 penetrate through the first molding layer 50, and in conducting bridge 30 conductive metal wire 31 both ends respectively in the first molding
The both side surface of layer 50 is exposed.
Second chip 80 is set to the side of the first molding layer 50, and stacks and be arranged with the first chip 40.
The pad of first chip 40 both can be set in the side surface towards the second chip 80, also can be set backwards
One side surface of the second chip 80, Fig. 6 F, Fig. 6 G show the situation of the latter.When the pad of the first chip 40 is set to backwards to the
When one side surface of two chips 80, the weldering of entire packaging body can be set in the first molding layer 50 far from the side of the second chip 80
Disk (for example, pad of the soldered ball 70 as entire packaging body on layer 60 will be rerouted), at this point, the pad of the second chip 80 with lead
Electrical connection between the conductive metal wire 31 of electric bridge 30, can be by metal routing (90 in such as Fig. 6 F) Lai Shixian, can also be with
It is realized by rewiring layer (120 in such as Fig. 6 G) connection between the first molding layer 50 and the second chip 80.It requires supplementation with
Illustrate, those skilled in the art Fig. 6 F, Fig. 6 G introduction or enlightenment under it is conceivable that the first chip 40 pad direction
Specific set-up mode when the direction of separate second chip 80, details are not described herein by the application.
Above-mentioned fan-out-type stack package structure replaces conductive metal column in the prior art using conducting bridge to realize each layer
Between electric signal connection, on the one hand, since conducting bridge is punching and to fill in hole conductive gold on the substrate of inorganic
What category obtained, therefore its internal conductive metal wire can be made relatively thin, therefore, have electrical connection with conductive metal wire
In wiring, for two conducting wires not being electrically connected near the end of conductive metal wire but with conductive metal wire, wire spacing setting
It can guarantee that the electric current of two conducting wires will not influence each other compared with urine；On the other hand, on the substrate of inorganic punching and
When filling conductive metal in hole, it can according to need the distribution situation of chip bonding pad or reroute the layout scenarios of layer to determine
The layout in hole.Above-mentioned two aspect can be improved the wiring density for rerouting layer, subtract so that the layout rerouted is more reasonable；While by
Conducting bridge, which is prepared into, in the substrate for being capable of providing unlike material is used to stack integrated, the warpage degree of reduction plastic packaging wafer, raising
Reroute the yield of technique；Furthermore the stacked structure of the system integration using patch form, manufacturing cost are lower.
Optionally, metal is provided between the conductive metal wire 31 that the pad of the second chip 80 and 30 one end of conducting bridge are exposed
Routing 90, as fig 6 f illustrates.The encapsulating structure further includes the second molding layer 100, is set to the side of the first molding layer 50, and is wrapped
Cover the metal routing 90 between the second chip 80 and the pad and conducting bridge 30 of the second chip 80.
Optionally, which further includes the first rewiring layer 60 and/or soldered ball 70, is set to the first molding
The predetermined surface of layer 50, wherein predetermined surface and the second chip 80 are located at the two sides of the first molding layer 50.It can be first
It reroutes and soldered ball 70 is set on layer 60, it can also setting soldered ball 70.A kind of replacement embodiment party as the optional embodiment
Formula, rerouting also can be set other structures on the position of layer 60 and soldered ball 70, such as stacks and more chip layers etc. are arranged.It leads
One end of conductive metal wire in electric bridge 30 can be electrically connected at least one conducting wire for rerouting layer 60, and the other end can be with the
The pad of two chips 80 is electrically connected, and is rerouted on layer 60 so as to which the pad of the second chip 80 to be drawn out to, so as to further
The soldered ball of second chip 80 is set.When one end of the conductive metal wire in conducting bridge 30 is electrically connected with the pad of the second chip 80
When, the conducting wire rerouted on layer 60 can be electrically connected with one end with the conductive metal wire, and the other end is connect with the pad of chip 40,
To realize being electrically connected for the first chip 40 and the second chip 80.
Embodiment two
The embodiment of the invention provides another fan-out-type stack package structure, the difference with embodiment one is, such as schemes
Further include dielectric layer 130 shown in 7F, Fig. 7 G, be set between the first chip 40 and the second chip 80, and 30 side of coated with conductive bridge
The partial region of wall.
As shown in Figure 7 F, being electrically connected between the pad of the second chip 80 and the conductive metal wire 31 of conducting bridge 30, passes through
Plain conductor 90 is realized；Alternatively, as shown in Figure 7 G, passing through the rewiring layer between the first molding layer 50 and the second chip 80
120 conducting wire is realized.
Above-mentioned fan-out-type stack package structure can be improved the wiring density for rerouting layer, subtract so that rerouting layout more
Rationally；Simultaneously because the substrate for being capable of providing unlike material is prepared into, conducting bridge is integrated for stacking, and reduces sticking up for plastic packaging wafer
Qu Chengdu improves the yield for rerouting technique；Furthermore the stacked structure of the system integration using patch form, manufacturing cost
It is lower.Specifically refer to embodiment one.
Embodiment three
Fig. 2 shows a kind of flow chart of fan-out-type stacking encapsulation method according to an embodiment of the present invention, the packaging methods
It can be used for making encapsulating structure described in embodiment one, embodiment two or its any one optional embodiment.Such as Fig. 2 institute
Show, this method comprises the following steps:
S101: conducting bridge and the first chip are attached in the first surface of the first support plate；Conducting bridge is internal at least one
The block of root conductive metal wire, and conducting bridge makes obtain by the following method: it is pre- on the substrate of inorganic as needed
Positioning, which is set, punches and fills conductive metal in hole；Cutting substrate as needed, obtains conducting bridge.
As shown in Figure 6 C, 10 be the first support plate, and 30 be conducting bridge, and 40 be the first chip.In step S101, attach conductive
The method of bridge 30 and the first chip 40 can be such as Fig. 6 A: interim bonded layer 20 first be arranged on the surface of the first support plate 10, then will
Conducting bridge 30 and the first chip 40 are attached on interim bonded layer 20；It can also be by other means by conducting bridge 30 and first
40 Direct Bonding of chip is on the first support plate 10.The application does not limit specific attaching method herein.
Specific descriptions about conducting bridge 30 refer to embodiment one.
S102: the first molding layer is formed in the first surface of the first support plate, the first molding layer coats the first chip and conduction
The side wall of bridge, and expose the first chip pad and conducting bridge in conductive metal wire both ends.
As shown in Figure 6 C, 50 be the first molding layer.The pad of first chip 40 can be towards the first support plate 10, can also be with
It is directed away from the direction of the first support plate 10, the present embodiment is it is not limited here.
It should be pointed out that step S102 is after the first surface of the first support plate 10 forms the first molding layer 50, this
One molding layer 50 may not necessarily expose the both ends of conductive metal wire 31 in the pad and conducting bridge 30 of the first chip 40, can borrow at this time
Help other means to make its exposing, for example, first pass through grind be thinned (as shown in Figure 6 D) mode remove most of molding material, so
It removes at 40 pad of the first chip in such a way that laser (as shown in the arrow in Fig. 6 D) drills and is led in conducting bridge 30 afterwards
The first molding layer material that 31 end of electric metal line is covered.The application is to making " in 40 pad of the first chip and conducting bridge 30
The method that 31 end of conductive metal wire " is exposed is without limitation.
S103: the second chip is set toward or away from the side of the first support plate in the first molding layer.
For example, can in figure 6 c shown in the first molding layer 50 upper surface be arranged the second chip 80, in the first support plate
10 remove before or remove after it is settable；Can also in figure 6 c shown in the first molding layer 50 lower surface be arranged the second chip
80, it must be arranged after the dismounting of the first support plate 10 at this time.The mode of second chip is set, can be direct attaching, be also possible to
By other means, the present embodiment does not limit this.The pad of second chip can be set one in the first molding layer of direction
Side surface also can be set in the side surface backwards to the first molding layer, and the present embodiment does not limit this.
Above-mentioned fan-out-type stacking encapsulation method replaces conductive metal column in the prior art using conducting bridge to realize each layer
Between electric signal connection, on the one hand, since conducting bridge is punching and to fill in hole conductive gold on the substrate of inorganic
What category obtained, therefore its internal conductive metal wire can be made relatively thin, therefore, have electrical connection with conductive metal wire
In wiring, for two conducting wires not being electrically connected near the end of conductive metal wire but with conductive metal wire, wire spacing setting
It can guarantee that the electric current of two conducting wires will not influence each other compared with urine；On the other hand, on the substrate of inorganic punching and
When filling conductive metal in hole, it can according to need the distribution situation of chip bonding pad or reroute the layout scenarios of layer to determine
The layout in hole.Above-mentioned two aspect can be improved the wiring density for rerouting layer, subtract so that the layout rerouted is more reasonable；While by
Conducting bridge, which is prepared into, in the substrate for being capable of providing unlike material is used to stack integrated, the warpage degree of reduction plastic packaging wafer, raising
Reroute the yield of technique；Furthermore the stacked structure of the system integration using patch form, manufacturing cost are lower.
Optionally, after step s 102, further includes: reroute layer in the predetermined surface setting first of the first molding layer
And/or soldered ball, wherein predetermined surface and the second chip are located at the two sides of the first molding layer.As illustrated in fig. 6e, 60 be first
Layer is rerouted, 70 be soldered ball.
Example IV
Fig. 3 shows the flow chart of another fan-out-type stacking encapsulation method according to an embodiment of the present invention, the encapsulation side
Method can be used for making encapsulating structure described in embodiment one or its any one optional embodiment.As shown in figure 3, the party
Method includes the following steps:
S201: conducting bridge and the first chip are attached in the first surface of the first support plate；Conducting bridge is internal at least one
The block of root conductive metal wire, and conducting bridge makes obtain by the following method: it is pre- on the substrate of inorganic as needed
Positioning, which is set, punches and fills conductive metal in hole；Cutting substrate as needed, obtains conducting bridge.
The step specifically refers to step S101.
S202: the first molding layer is formed in the first surface of the first support plate, the first molding layer coats the first chip and conduction
The side wall of bridge, and expose the first chip pad and conducting bridge in conductive metal wire both ends.
The step specifically refers to step S102.
S203: rerouting layer and/or soldered ball in the predetermined surface setting first of the first molding layer, wherein predetermined surface and the
Two chips are located at the two sides of the first molding layer.
As illustrated in fig. 6e, 60 layer is rerouted for first, 70 be the soldered ball being arranged on the first rewiring layer.
S204: the first support plate is removed.
S205: the second chip is attached in the side surface for originally attaching the first support plate；The pad of second chip is directed away from
The direction of first chip.
For example, first pasting double-sided adhesive on the surface of the second chip 80, then cutting obtains table before the cutting of the second chip 80
Face has the second chip 80 of double-sided adhesive, can be by double-sided adhesive (in such as Fig. 6 F between the first chip 40 and the second chip 80
Heavy black line shown in) directly attach the second chip 80.
Step S204 and S205 give a kind of specific embodiment of step S103 in embodiment one, refer to Fig. 6 E and
Fig. 6 F.Wherein, 80 be the second chip.
S206: metal routing is set between the conductive metal wire that the pad of the second chip and conducting bridge one end expose.
S207: the second molding layer is formed in the side surface for originally attaching the first support plate, the second molding layer coats the second core
Metal routing between piece and the pad and conducting bridge of the second chip.
Step S204 and S205 refer to Fig. 6 F.Wherein, 90 be metal routing, and 100 be the second molding layer.
Above-mentioned fan-out-type stacking encapsulation method can be improved the wiring density for rerouting layer, subtract the layout so that rerouting
More rationally；Simultaneously because the substrate for being capable of providing unlike material is prepared into, conducting bridge is integrated for stacking, and reduces plastic packaging wafer
Warpage degree improves the yield for rerouting technique；Furthermore the stacked structure of the system integration using patch form, manufacture at
This is lower.Specifically refer to embodiment three.
It needs to add explanation, the structure as fig 6 f illustrates obtained by the embodiment the method, due to the first chip
40 and second do not have separation layer between chip 80, therefore anti-interference is poor between each other.
Embodiment five
Fig. 4 shows the flow chart of another fan-out-type stacking encapsulation method according to an embodiment of the present invention, the encapsulation side
Method can be used for making encapsulating structure described in embodiment one or its any one optional embodiment.As shown in figure 4, the party
Method includes the following steps:
S301: conducting bridge and the first chip are attached in the first surface of the first support plate；Conducting bridge is internal at least one
The block of root conductive metal wire, and conducting bridge makes obtain by the following method: it is pre- on the substrate of inorganic as needed
Positioning, which is set, punches and fills conductive metal in hole；Cutting substrate as needed, obtains conducting bridge.
The step specifically refers to step S101.
S302: the first molding layer is formed in the first surface of the first support plate, the first molding layer coats the first chip and conduction
The side wall of bridge, and expose the first chip pad and conducting bridge in conductive metal wire both ends.
The step specifically refers to step S102.
S303: production is provided with the second chip and second and reroutes the plate body of layer；Wherein, the second rewiring layer is located at plate body
Surface, and at least one conducting wire of the second rewiring layer is electrically connected with the pad of the second chip.
The method that production is provided with the plate body of the second chip and the second rewiring layer, can be and first make on the second support plate
Second reroutes layer, then the setting of the second chip is rerouted on layer second, so that second reroutes at least one conducting wire of layer
It is electrically connected with the pad of the second chip, then remove the second support plate (can also form the second molding layer, this second before dismounting
Molding layer coats the second chip)；Alternatively, first the second chip is attached on the second support plate, wherein the pad direction of the second chip
Second support plate, then the second molding layer is formed on the second support plate surface, which coats the second chip, then removes and carries
Plate, and layer is rerouted in the surface setting second for originally attaching support plate, so that second reroutes at least one conducting wire and the of layer
The pad of two chips is electrically connected.
The obtained structure of step S303, can be as shown in the structure of 110 layers of top in Fig. 6 G.
S304: plate body is welded on the first molding layer toward or away from a side surface of support plate；Wherein, second layer is rerouted
One end of conductive metal wire for exposing of at least one conducting wire and the first molding layer surface be electrically connected.
In the obtained structure of step S303 surface can be set soldered ball (soldered ball and second rewiring layer conducting wire be electrically connected
Connect) or the surface of the first molding layer 50 soldered ball (soldered ball is electrically connected with the conductive metal wire in conducting bridge), step can be set
S304, which may is that, is placed on the surface that the first molding layer is used to be arranged the second chip for the obtained structure of step S303, passes through
The technique of Reflow Soldering connect soldered ball with pad, so that second is rerouted the conductive metal wire in the conducting wire and conducting bridge of layer
Electrical connection forms glue film after solidification then in interlayer spacings filler (as shown in 110 in Fig. 6 G).
S305: rerouting layer and/or soldered ball in the predetermined surface setting first of the first molding layer, wherein predetermined surface and the
Two chips are located at the two sides of the first molding layer.
As shown in Figure 6 G, 60 layer is rerouted for first, 70 be the soldered ball being arranged on the first rewiring layer.
Above-mentioned fan-out-type stacking encapsulation method can be improved the wiring density for rerouting layer, subtract the layout so that rerouting
More rationally；Simultaneously because the substrate for being capable of providing unlike material is prepared into, conducting bridge is integrated for stacking, and reduces plastic packaging wafer
Warpage degree improves the yield for rerouting technique；Furthermore the stacked structure of the system integration using patch form, manufacture at
This is lower.Specifically refer to embodiment three.
It needs to add explanation, the structure as shown in Figure 6 G obtained by the embodiment the method, due to the first chip
40 and second have between chip 80 second to reroute layer, can play the role of signal isolation, therefore, phase to a certain extent
Compared with structure shown in Fig. 6 F, the anti-interference of the first chip 40 and the second chip 80 is preferable.
Embodiment six
Fig. 5 shows the flow chart of another fan-out-type stacking encapsulation method according to an embodiment of the present invention, the encapsulation side
Method can be used for making encapsulating structure described in embodiment two or its any one optional embodiment.As shown in figure 5, the party
Method includes the following steps:
S401: the one end for exposing conductive metal wire on conducting bridge is attached to the first surface of the first support plate；Conducting bridge is
Inside has the block of at least one conductive metal wire, and conducting bridge makes obtain by the following method: as needed inorganic
Predetermined position is punched on the substrate of material and metal is led in filling in hole；Cutting substrate as needed, obtains conducting bridge.
The step specifically refers to step S101.
S402: dielectric layer, the partial region of dielectric layer coated with conductive bridge side wall are formed in the first surface of the first support plate.
Encapsulating structure after above-mentioned steps S401 and S402, longitudinal sectional view is as shown in Figure 7 A, 10 be the first support plate, 30
It is dielectric layer for conducting bridge, 51；Top view is as shown in Figure 7 B.Dielectric layer can be selected as needed, and the application is to dielectric layer
Specific material is without limitation.
S403: the first chip is attached backwards to the surface of the first support plate in dielectric layer, the pad of the first chip is directed away from the
The direction of one support plate.
As seen in figure 7 c, 40 be the first chip, and the pad of the first chip 40 is directed away from the direction of the first support plate 10, namely
It is directed away from the direction of the first molding layer 51.
S404: the first molding layer is formed backwards to the surface of the first support plate in dielectric layer, the first molding layer coats the first chip
Side wall, and the remaining area of coated with conductive bridge side wall, and expose conductive metal wire in the pad and conducting bridge of the first chip
Both ends.
As seen in figure 7 c, 52 be the first molding layer.As can be seen from the figure dielectric layer 130 and the second molding straton 52 cladding
The side wall of first chip 40 and conducting bridge 30, and expose conductive metal wire 31 in the pad and conducting bridge 30 of the first chip 40
Both ends.
S405: the second chip is set toward or away from the side of the first support plate in the first molding layer.
The step specifically refers to the step S303 and S304 of step S103 and embodiment five.
Above-mentioned fan-out-type stacking encapsulation method, additionally it is possible to improve the wiring density for rerouting layer, subtract the cloth so that rerouting
Office is more reasonable；Simultaneously because the substrate for being capable of providing unlike material, which is prepared into conducting bridge, is used to stack integrated, reduction plastic packaging wafer
Warpage degree, improve reroute technique yield；Furthermore the stacked structure of the system integration using patch form, manufacture
Cost is relatively low.Specifically refer to embodiment three.
It needs to add explanation, the structure as shown in Figure 7 F obtained by the embodiment the method, due to the first chip
40 and second have dielectric layer between chip 80, and the material of dielectric layer can according to need the material for choosing signal isolation better performances
Matter, therefore, compared to structure shown in Fig. 6 F and Fig. 6 G, the anti-interference of the first chip 40 and the second chip 80 is more preferable.
Although being described in detail about example embodiment and its advantage, those skilled in the art can not departed from
Various change, replacement are carried out to these embodiments in the case where spirit of the invention and protection scope defined in the appended claims
And modification, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples, ability
The those of ordinary skill in domain should be readily appreciated that the order of processing step can become while keeping in the scope of the present invention
Change.
In addition, application range of the invention is not limited to the technique, mechanism, system of specific embodiment described in specification
It makes, material composition, means, method and step.From the disclosure, will be easy as those skilled in the art
Ground understands, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means, method or
Step, wherein they execute the function that the corresponding embodiment described with the present invention is substantially the same or the knot that acquisition is substantially the same
Fruit can apply them according to the present invention.Therefore, appended claims of the present invention are intended to these techniques, mechanism, system
It makes, material composition, means, method or step are included in its protection scope.
Claims (10)
1. a kind of fan-out-type stacking encapsulation method characterized by comprising
Conducting bridge and the first chip are attached in the first surface of the first support plate；The conducting bridge is internal conductive at least one
The block of metal wire, and the conducting bridge makes obtain by the following method: make a reservation on the substrate of inorganic as needed
It punches and fills conductive metal in the hole in position；The substrate is cut as needed, obtains the conducting bridge；
The first molding layer is formed in the first surface of first support plate, the first molding layer coats first chip and institute
The side wall of conducting bridge is stated, and exposes the both ends of conductive metal wire in the pad and the conducting bridge of first chip；
The second chip is set toward or away from the side of first support plate in the first molding layer.
2. fan-out-type stacking encapsulation method according to claim 1, which is characterized in that first table in the first support plate
The attached conducting bridge of face paste and the first chip include: in the step of first surface of first support plate forms the first molding layer
The one end for exposing conductive metal wire on conducting bridge is attached to the first surface of first support plate；
Dielectric layer is formed in the first surface of first support plate, the dielectric layer coats the part area of the conducting bridge side wall
Domain；
The first chip is attached backwards to the surface of first support plate in the dielectric layer, the pad of first chip is directed away from
The direction of first support plate；
The first molding layer is formed backwards to the surface of first support plate in the dielectric layer, the first molding layer cladding described the
The side wall of one chip, and coat the remaining area of the conducting bridge side wall, and expose the pad of first chip and described lead
The both ends of conductive metal wire in electric bridge.
3. fan-out-type stacking encapsulation method according to claim 1, which is characterized in that described in the first molding layer court
To or backwards to first support plate side be arranged the second chip the step of include:
Remove first support plate；
The second chip is attached in the side surface for originally attaching first support plate；The pad of second chip is directed away from institute
State the direction of the first chip；
Metal routing is set between the conductive metal wire that the pad of second chip and described conducting bridge one end expose.
4. fan-out-type stacking encapsulation method according to claim 3, which is characterized in that described in the first molding layer court
To or backwards to first support plate side be arranged the second chip the step of after, further includes:
The second molding layer is formed on the surface for originally attaching first support plate, the second molding layer coats second core
Metal routing between piece and the pad and the conducting bridge of second chip.
5. fan-out-type stacking encapsulation method according to claim 1, which is characterized in that described in the first molding layer court
To or backwards to first support plate side be arranged the second chip the step of include:
Production is provided with the second chip and second and reroutes the plate body of layer；Wherein, the second rewiring layer is located at the plate body
Surface, and at least one conducting wire of the second rewiring layer is electrically connected with the pad of second chip；
The plate body is welded on the first molding layer toward or away from a side surface of the support plate；Wherein, described second
The one end for the conductive metal wire that at least one conducting wire of rewiring layer and the first molding layer surface are exposed is electrically connected.
6. fan-out-type stacking encapsulation method according to claim 1, which is characterized in that described the of first support plate
One surface was formed after the step of the first molding layer, further includes:
Layer and/or soldered ball are rerouted in the predetermined surface setting first of the first molding layer, wherein the predetermined surface and institute
State the two sides that the second chip is located at the first molding layer.
7. a kind of fan-out-type stack package structure characterized by comprising
First chip；
First molding layer coats the side wall of first chip；And expose the pad of first chip；
Conducting bridge has the block of at least one conductive metal wire for inside, and the conducting bridge is made to by the following method
To: predetermined position punches and fills conductive metal in the hole on the substrate of inorganic as needed, cuts as needed
The substrate is cut to obtain the conducting bridge；The conducting bridge penetrates through the first molding layer, and conductive in the conducting bridge
Expose respectively in the both side surface of the first molding layer at the both ends of metal wire；
Second chip is set to the side of the first molding layer, and stacks and be arranged with first chip.
8. fan-out-type stack package structure according to claim 7, which is characterized in that further include:
Dielectric layer is set between first chip and second chip, and coats the part area of the conducting bridge side wall
Domain.
9. fan-out-type stack package structure according to claim 7, which is characterized in that the pad of second chip and institute
It states and is provided with conducting wire between the conductive metal wire of conducting bridge one end exposing；The encapsulating structure further include:
Second molding layer, is set to the side of the first molding layer, and coats second chip and second chip
Pad and the conducting bridge between conducting wire.
10. fan-out-type stack package structure according to claim 7, which is characterized in that further include:
First reroutes layer and/or soldered ball, the predetermined surface of the first molding layer is set to, wherein the predetermined surface and institute
State the two sides that the second chip is located at the first molding layer.
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| CN201811640485.5A CN109801883A (en) | 2018-12-29 | 2018-12-29 | A kind of fan-out-type stacking encapsulation method and structure |
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| CN201811640485.5A CN109801883A (en) | 2018-12-29 | 2018-12-29 | A kind of fan-out-type stacking encapsulation method and structure |
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| WO2020248902A1 (en) * | 2019-06-12 | 2020-12-17 | 上海先方半导体有限公司 | Fan-out packaging structure and fabrication method therefor |
| CN112259518A (en) * | 2020-01-08 | 2021-01-22 | 王之奇 | Fan-out packaging structure of chip and fan-out packaging method thereof |
| WO2021189292A1 (en) * | 2020-03-25 | 2021-09-30 | 华为技术有限公司 | Chip structure and chip preparation method |
| CN113488447A (en) * | 2021-09-03 | 2021-10-08 | 中矽科技股份有限公司 | High stability packaging structure for semiconductor |
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Application publication date: 20190524 |