CN208655635U - Stack embedded packaging structure - Google Patents

Stack embedded packaging structure Download PDF

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Publication number
CN208655635U
CN208655635U CN201821544238.0U CN201821544238U CN208655635U CN 208655635 U CN208655635 U CN 208655635U CN 201821544238 U CN201821544238 U CN 201821544238U CN 208655635 U CN208655635 U CN 208655635U
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China
Prior art keywords
layer
chip
package substrate
electrode
several
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CN201821544238.0U
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Chinese (zh)
Inventor
蔡亲佳
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Zhejiang Rongcheng Semiconductor Co Ltd
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Individual
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model discloses a kind of stacking embedded packaging structure, and encapsulating structure includes: package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and package substrate has chamber；First chip, is set in chamber, and the first lower surface has several first electrodes；Second chip, is set to the top of package substrate, and the second lower surface has several second electrodes；Several interconnection structures, for several first electrodes and several second electrodes to be connected, and first electrode is connected through the first chip in part interconnection structure.The utility model is using encapsulation technology by two different chip packages in same package substrate, the highly integrated of multi-chip may be implemented, improve the utilization rate of package substrate, and semiconductor chip packaging and semiconductor package body are completed into encapsulation process in package substrate simultaneously, complicated the two, cumbersome standard and technique docking is omitted, the circulation transfer for reducing electronic manufacture, saves human and material resources, can further decrease the cost of electronic product.

Description

Stack embedded packaging structure
Technical field
The utility model relates to field of semiconductor package more particularly to a kind of stacking embedded packaging structures.
Background technique
Packaging for stacked semiconductor chip is a kind of important 3D packing forms for realizing miniature high-density systems grade encapsulation, it Be conducive to improve encapsulation integrated level and packaging performance.
Currently, thering is following primary structure and process to realize stacked chips interconnection in the industry:
(1) complete the multiple-level stack of bare chip first, then carried out by way of lead related multi-chip electric interconnection with Complete basic stacked chips system interconnection；
(2) assembling of semiconductor packing device in the circuit board generallys use surface mount process completion.
It is disadvantageous in that existing for above-mentioned prior art: (1) between semiconductor electronic package and semiconductor packing device Docking standard and technique are complicated and cumbersome；(2) it in surface mount, is usually connected by scolding tin by semiconductor packing device Electric interconnection is carried out with wiring board；(3) surface-pasted scolding tin connection at present needs the pad and pad of semiconductor packing device Spacing is larger, not accurate enough if pad/spacing is respectively 280 microns/400 microns, and scolding tin connection needs progress more multiple Miscellaneous solder reflow technology controlling and process；(4) semiconductor packing device is assembled using surface-pasted mode in the circuit board, by It is increased in semiconductor packing device area, the biggish surface area of wiring board will be occupied, hinder semiconductor packing device assembling Miniaturization.
Summary of the invention
The purpose of this utility model is to provide a kind of stacking embedded packaging structures.
To realize that one of above-mentioned purpose of utility model, one embodiment of the utility model provide a kind of embedded encapsulation of stacking Structure, comprising:
Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber；
First chip is set in the chamber, and first chip has the first upper surface and first being oppositely arranged Lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first lower surface has several first electricity Pole；
Second chip, is set to the top of the package substrate, and second chip has table on second be oppositely arranged Face and the second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second lower surface has Several second electrodes；
Several interconnection structures, for several first electrodes and several second electrodes to be connected, and the part interconnection structure passes through It wears first chip and first electrode is connected.
As the further improvement of one embodiment of the utility model, first upper surface and the upper surface of base plate are neat It is flat.
As the further improvement of one embodiment of the utility model, the side of the base lower surface has several outsides Pin, the package substrate have several through-holes, and the first electrode, described is connected by the through-hole in the interconnection structure Second electrode and the external pin.
As the further improvement of one embodiment of the utility model, the interconnection structure includes metal column and electroplated layer knot Structure, the metal column are connected to the lower section of the second electrode, and the electroplated layer structure includes the upper rewiring layer of mutual conduction And lower rewiring layer, upper top and the connection metal column for rerouting layer and being located at the package substrate, and it is described heavy The first electrode is connected by the hole on first chip in wiring layer, and the lower rewiring layer is connected by the through-hole The upper rewiring layer, and the lower rewiring layer extends to the lower section of the package substrate and the first electrode and institute is connected State external pin.
As the further improvement of one embodiment of the utility model, the lower rewiring layer includes the first lower rewiring layer And layer is rerouted under second, the encapsulating structure includes the first insulating layer, second insulating layer and third insulating layer, and described first absolutely Edge layer coats the base lower surface and first lower surface, and the described first lower rewiring layer is located at first insulating layer Simultaneously the first electrode and the upper rewiring layer is connected by the hole of first insulating layer and through-hole in lower section, and described second Insulating layer coats first insulating layer and the first lower rewiring layer, and the described second lower layer that reroutes is located at described second absolutely Simultaneously the described first lower rewiring layer is connected by the hole of the second insulating layer in the lower section of edge layer, and the external pin connects institute The second lower rewiring layer is stated, the third insulating layer cladding described second is lower to reroute layer and the second insulating layer and expose The external pin.
As the further improvement of one embodiment of the utility model, the upper rewiring layer connects the upper surface of base plate And first upper surface, the encapsulating structure further include being located at side of the package substrate far from the base lower surface First plastic packaging layer, the first plastic packaging layer coat the peripheral region of second chip.
As the further improvement of one embodiment of the utility model, the gap location of first chip and the chamber is set There is the second plastic packaging layer.
Compared with prior art, the utility model has the beneficial effects that: one embodiment of the utility model utilizes envelope In same package substrate, the highly integrated of multi-chip may be implemented in two different chip packages by dress technology, improves encapsulation base The utilization rate of plate, and then realize the miniaturization of encapsulating structure, the first chip is embedded to be set in chamber, so that the table of package substrate Face area is sufficiently discharged, and system assembles area may be implemented and substantially reduce, and reduction ratio can be more than 50%, by semiconductor Chip package and semiconductor package body complete encapsulation process in package substrate simultaneously, are omitted previous complicated, cumbersome between the two Standard and technique docking, reduce the circulation transfer of electronic manufacture, save human and material resources, can further decrease electronic product at This.
Detailed description of the invention
Fig. 1 is the stacking embedded packaging structure schematic diagram of one embodiment of the utility model；
Fig. 2 is the manufacturing method block diagram of the stacking embedded packaging structure of one embodiment of the utility model；
Fig. 3 a to Fig. 3 z-5 is showing for the manufacturing method of the stacking embedded packaging structure of one embodiment of the utility model It is intended to.
Specific embodiment
The utility model is described in detail below with reference to specific embodiment shown in the drawings.But these embodiment party Formula is not intended to limit the utility model, structure that those skilled in the art are made according to these embodiments, method or Transformation functionally is all contained in the protection scope of the utility model.
In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.
In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty Between relevant description language.
Join Fig. 1, is the cross-sectional view of the stacking embedded packaging structure 100 of one embodiment of the utility model.
Encapsulating structure 100 includes package substrate 10, the first chip 20, the second chip 30 and several interconnection structures 40.
Encapsulating structure 100 is semiconductor package body.
Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, and package substrate 10 has chamber 101。
Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin Circuit board is also possible to glass substrate or ceramic substrate etc..
Chamber 101 can be the through hole through package substrate 10, and but not limited to this.
First chip 20 is set in chamber 101, and the first chip 20 has the first upper surface 21 and first being oppositely arranged Lower surface 22, the first upper surface 21 and upper surface of base plate 11 are located at ipsilateral, and the first lower surface 22 has several first electrodes 221。
First electrode 221 protrudes out the first lower surface 22 towards the direction far from the first upper surface 21, and but not limited to this.
Second chip 30 is set to the top of package substrate 10, and the second chip 30 has the second upper surface 31 being oppositely arranged And second lower surface 32, the second lower surface 32 are arranged face-to-face with upper surface of base plate 11, and the second lower surface 32 has several the Two electrodes 321.
Second electrode 321 protrudes out the second lower surface 32 towards the direction far from the second upper surface 31, and but not limited to this.
Several interconnection structures 40 are for being connected several first electrodes 221 and several second electrodes 321, and part interconnection structure 40 are connected first electrode 221 through the first chip 20.
Here, " several interconnection structures 40 are for being connected several first electrodes 221 and several second electrodes 321 " refers to first It is electrically connected between electrode 221 and second electrode 321, that is, realizes the interconnection of the second chip 30 and the first chip 20.
" first electrode 221 is connected through the first chip 20 in part interconnection structure 40 " refers at least partly interconnection structure 40 It is to extend to the first lower surface 22 by the first upper surface 21 and at least partly first electrode 221 is connected.
Two different chips (the first chip 20 and the second chip 30) are packaged in by present embodiment using encapsulation technology The highly integrated of multi-chip may be implemented in same package substrate 10, improves the utilization rate of package substrate 10, and then realizes encapsulation knot The miniaturization of structure 100.
In addition, the second chip 30 and the first chip 20 are distributed in upper and lower, the second chip 30 above package substrate 10 And it is not take up the space of package substrate 10, it can be further improved the utilization rate of package substrate 10, and the second chip 30 and first Spacing between chip 20 becomes smaller, the interconnection being easy to implement between the second chip 30 and the first chip 20, simplifies interconnection structure；The One chip 20 is embedded to be set in chamber 101, so that the surface area of package substrate 10 is sufficiently discharged, system may be implemented Assembling area substantially reduces, and reduction ratio can be more than 50%.
Moreover, semiconductor chip packaging and semiconductor package body are completed encapsulation in package substrate 10 simultaneously by present embodiment Processing is omitted previous complicated between the two, cumbersome standard and technique docking, reduces the circulation transfer of electronic manufacture, saves Manpower and material resources can further decrease the cost of electronic product.
It should be noted that the encapsulating structure 100 of present embodiment is with second chip 30 and first chip 20 It is loaded into for package substrate 10, it is possible to understand that, in practice, it may include multiple second chips 30 and multiple first Chip 20, (including up and down all around three-dimensional) can be electrically connected with multiple first cores for example, around the second chip 30 Piece 20 etc..
In the present embodiment, the second chip 30 is located at the top of chamber 101, several first electrodes 221 and several second Electrode 321 is in face of back setting.
That is, the second chip 30 and the first about 20 chip are correspondingly arranged, first electrode 221 and second electrode 321 are located at the opposite two sides of package substrate 10, and the size of the second chip 30 can be greater than the size of the first chip 20.
In the present embodiment, the side of package substrate 10 has several external pins 121, and interconnection structure 40 is for being connected First electrode 221, second electrode 321 and external pin 121.
External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., and encapsulating structure 100 is logical Crossing external pin 121 can be electrically connected with realizations such as other chips or substrates, and here, external pin 121 is with ball grid array 121 For, external pin 121 protrudes out the lower surface of encapsulating structure 100.
In addition, but not limited to this, outside here by taking several external pins 121 are located at the side of base lower surface 12 as an example Portion's pin 121 may be alternatively located at other regions.
Package substrate 10 has several through-holes 13, and the 221, second electricity of first electrode is connected by through-hole 13 in interconnection structure 40 Pole 321 and external pin 121.
Here, through-hole 13 is located at the periphery of chamber 101.
In the present embodiment, interconnection structure 40 includes metal column 41 and electroplated layer structure 42.
Metal column 41 is connected to the lower section of second electrode 321.
Here, metal column 41 is copper post, and but not limited to this.
Electroplated layer structure 42 includes the upper rewiring layer 421 and lower rewiring layer 422 of mutual conduction.
Upper top and the connection metal column 41 for rerouting layer 421 and being located at package substrate 10, and upper rewiring layer 421 passes through the First electrode 221 is connected in the first hole 201 on one chip 20.
Specifically, the first hole 201 on the first chip 20 is V-type opening, the first hole 201 runs through the first upper surface 21 And towards 22 direction of the first lower surface extend and expose first electrode 221, upper 421 connecting substrate upper surface 11 of rewiring layer and First upper surface 21, that is to say, that above reroute layer 421 and be close to upper surface of base plate 11 and the extension of the first upper surface 21, and one Divide the upper layer 421 that reroutes to extend along the inner wall of the first hole 201 and first electrode 221 is connected, layer is rerouted on another part The upper area of 421 covering through-holes 13.
First upper surface 21 is flushed with upper surface of base plate 11, realizes the planarization of package substrate 10 and the first chip 20, Convenient for the upper laying for rerouting layer 421.
Here it is possible to first on the gap location of the first chip 20 and chamber 101, the first upper surface 21 and upper surface of base plate 11 Side is respectively formed the second plastic packaging layer 52, then grinds the second plastic packaging layer 52, package substrate 10 or the first chip 20 by grinding technics And the first upper surface 21 and upper surface of base plate 11 are exposed, the first upper surface 21 at this time is absolutely to flush with upper surface of base plate 11 , and the gap location of the first chip 20 and chamber 101 after grinding is equipped with the second plastic packaging layer 52, the second plastic packaging layer 52 can rise To the effect of the first chip 20 of protection and the relative position for fixing the first chip 20 and chamber 101.
Present embodiment setting metal column 41 and the upper advantage for rerouting layer 421 are: (1) metal column 41 and upper rewiring Layer 421 is directly connected, and simplifies technique, and fastly, with wide, time delay is small for signal transmission；(2) 41 appearance of metal column is significant, can To improve recognition efficiency as identification part, and then convenient for the detection of automatic aspect and possible defect recognition.
Lower rewiring layer 422 is by rerouting layer 421 in the conducting of through-hole 13, and lower rewiring layer 422 extends to encapsulation base The lower section of plate 10 and first electrode 221 and external pin 121 is connected.
Specifically, lower rewiring layer 422 includes that the first lower reroute reroutes layer 4222 under layer 4221 and second, encapsulation knot Structure 100 includes the first insulating layer 61, second insulating layer 62 and third insulating layer 63.
First insulating layer 61 coats base lower surface 11 and the first lower surface 21.
First lower the second hole for rerouting layer 4221 and being located at the lower section of the first insulating layer 61 and passing through the first insulating layer 61 611 and through-hole 13 first electrode 221 and upper rewiring layer 421 is connected.
Here, the lower layer 4221 that reroutes of a part first fills through-hole 13 and extends to 13 upper area of through-hole and lead Logical upper rewiring layer 421, the lower layer 4221 that reroutes of another part first extend towards 221 direction of first electrode and pass through the second hole Hole 611 and first electrode 221 is connected.
First insulating layer of the cladding of second insulating layer 62 61 and the first lower rewiring layer 4221.
The second lower third hole for rerouting layer 4222 and being located at the lower section of second insulating layer 62 and passing through second insulating layer 63 621 the first lower rewiring layers 4221 of conducting.
The connection of external pin 121 second is lower to reroute layer 4222, and the cladding of third insulating layer 63 second is lower to reroute layer 4222 And second insulating layer 62 and expose external pin 121.
Here, lower rewiring layer 422 include first it is lower reroute layer 4221 and second it is lower reroute layer 4222, not only can be with Expand and reroute range, improves the freedom degree that subsequent external pin 121 is laid, acceptable further accessory external pin 121 Outer shifting, convenient for arranging other chip buried spaces in advance, consequently facilitating realize high-performance and small size multi-chip 2.5D or 3D stacks integration packaging and mould group.
Upper rewiring layer 421 and lower rewiring layer 422 are layers of copper, and but not limited to this.
The electrical connection of present embodiment encapsulating structure 100 uses succinct rewiring without structures such as scolding tin (RDL) scheme realizes the electric connection between first electrode 221, second electrode 321 and external pin 121, process stabilizing and High reliablity.
The metal line materials of rewiring are copper (above reroute layer 421 and lower rewiring layer 422 is layers of copper), are rerouted Enhancing can be set between copper and chip electrode (including first electrode 221 and second electrode 321) and reroute copper and chip electrode It is attached to each other the metal or alloy film of power, which can be nickel, titanium, nickel chromium triangle, titanium tungsten etc..
It is exhausted that the first insulating layer 61, second insulating layer 62 and third are folded between package substrate 10 and lower rewiring layer 422 Edge layer 63, to realize the electrical isolation between all parts.
It should be understood that the upper rewiring layer 421 in rewiring scheme is not limited with above-mentioned one layer, lower rewiring layer 422 are not also limited with above-mentioned two layers, can according to the actual situation depending on.
Present embodiment encapsulating structure 100 can meet the assembling demand of more accurate semiconductor package part, as pad/ Away from 150 microns/200 microns or less can be narrowed down to respectively.
In the present embodiment, encapsulating structure 100 further includes being located at side of the package substrate 10 far from base lower surface 12 The first plastic packaging layer 51, the first plastic packaging layer 51 coat the second chip 30 peripheral region.
That is, the first plastic packaging layer 51 coats open area all around the second chip 30, including upper surface of base plate 11, the first upper surface 21 and the upper region rerouted between 421 upper area of layer and several metal columns 41.
First plastic packaging layer 51 can be EMC (Epoxy Molding Compound) plastic packaging layer, here, directly utilize first Plastic packaging layer 51 replaces the soldermask layer that layer 421 is rerouted in barrier, enormously simplifies technique.
One embodiment of the utility model also provides a kind of production method for stacking embedded packaging structure 100, in conjunction with preceding State stack embedded packaging structure 100 explanation and Fig. 2, Fig. 3 a to Fig. 3 z-5, production method comprising steps of
S1: ginseng Fig. 3 a provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；
S2: ginseng Fig. 3 b, in formation chamber 101 on package substrate 10；
S3: ginseng Fig. 3 c, the first chip 20 is provided, the first chip 20 has under the first upper surface 21 and first being oppositely arranged Surface 22, the first lower surface 22 have several first electrodes 221；
S4: ginseng Fig. 3 d to Fig. 3 h, the first chip 20 is loaded to chamber 101, the first upper surface 21 and upper surface of base plate 11 Positioned at ipsilateral；
Step S4 is specific as follows:
Join Fig. 3 d, an interim jointing plate 70 is provided, the base lower surface 12 of package substrate 10 is fitted in into interim jointing plate 70；
Join Fig. 3 e, the first chip 20 is loaded to chamber 101, the first upper surface 21 is located at ipsilateral with upper surface of base plate 11；
Here, the first lower surface 22 also fits in interim jointing plate 70, so, it can be achieved that under the first lower surface 22 and substrate Surface 12 flushes.
Join Fig. 3 f, forms the gap for coating the first chip 20 and chamber 101, upper surface of base plate 11 and the first upper surface 21 Second plastic packaging layer 52；
Join Fig. 3 g, removes interim jointing plate 70；
Join Fig. 3 h, a temporary support plate 80 is provided, the base lower surface 12 of package substrate 10, the first lower surface 22 are bonded In temporary support plate 80；
Join Fig. 3 i, grinds the second plastic packaging layer 52 and expose upper surface of base plate 11 and the first upper surface 21, upper surface of base plate 11 flush with the first upper surface 21, remove temporary support plate 80.
Here, since package substrate 10 is not easy to grind, the height of the first chip 20 can be made to be greater than package substrate 10 Height, in this way, upon grinding, the second plastic packaging layer 52 and the first chip 20 of easy grinding can be ground, when exposing encapsulation base When plate 10, that is, shows that grinding is completed, the planarization of upper surface of base plate 11 and the first upper surface 21 is realized by grinding technics, just In the realization of subsequent technique.
S5: ginseng Fig. 3 j to Fig. 3 v, in forming the first interconnection structure on package substrate 10, the first interconnection structure conducting first is electric Pole 221, and first electrode 221 is connected through the first chip 20 in the first interconnection structure of part；
Step S5 is specific as follows:
Join Fig. 3 j, in forming several through-holes 13 on package substrate 10；
Join Fig. 3 k, forms the first insulating layer 61 in the first lower surface 22 and base lower surface 12；
Join Fig. 3 l, form the second hole 611 in exposure development on the first insulating layer 61, the second hole 611 exposes the One electrode 221 and through-hole 13；
Join Fig. 3 m, is formed in the lower section of the first insulating layer 61 by the second hole 611 conducting on the first insulating layer 61 the The first of one electrode 221 is lower to reroute layer 4221, and the first lower rewiring layer 4221 fills up through-hole 13；
Here, the lower layer 4221 that reroutes of a part first fills through-hole 13 and extends to 13 upper area of through-hole, the The upper surface for once rerouting layer 4221 is flushed with upper surface of base plate 11, and another part first is lower to reroute layer 4221 towards first 221 direction of electrode extends and first electrode 221 is connected by the second hole 611.
Join Fig. 3 n, forms the lower second insulating layer 62 for rerouting layer 4221 and the first insulating layer 61 of cladding first；
Join Fig. 3 o, form third hole 621 in exposure development in second insulating layer 62, third hole 621 exposes the Once reroute layer 4221；
Join Fig. 3 p, interim loading plate 90 is set in the lower section of second insulating layer 62, and formed and run through at the first chip 20 First chip 20 and the first hole 201 for exposing first electrode 221；
Here, the first hole 201 on the first chip 20 is V-type opening, and the first hole 201 runs through the first upper surface 21 simultaneously Extend towards 22 direction of the first lower surface and exposes first electrode 221.
Join Fig. 3 q to Fig. 3 u, is formed in the first upper surface 21 and upper surface of base plate 11 and reroute layer 421, upper rewiring layer The first lower rewiring layer 4221 in 421 connection through-holes 13, and upper the first hole for rerouting layer 421 and passing through the first chip 20 201 conducting first electrodes 221；
It is specific as follows:
Join Fig. 3 q, forms the first photoresist layer 91 in the first upper surface 21 and upper surface of base plate 11；
Join Fig. 3 r, forms several first apertures 911, the first aperture 911 exposure in 91 exposure and imaging of the first photoresist layer 13 region of first hole 201 and through-hole out；
Join Fig. 3 s, reroutes layer 421 in being formed in the first aperture 911, upper for rerouting layer 421 and being connected in through-hole 13 Layer 4221 is once rerouted, and upper the first hole 201 conducting first electrode 221 for rerouting layer 421 and passing through the first chip 20；
Join Fig. 3 t, removes the first photoresist layer 91；
Join Fig. 3 u, removes interim loading plate 90.
S6: ginseng Fig. 3 v, the second chip 30 is provided, the second chip 30 has under the second upper surface 31 and second being oppositely arranged Surface 32, and the second lower surface 32 has several second electrodes 321；
S7: ginseng Fig. 3 w to Fig. 3 z-3 is loaded into the second chip 30 in the top of package substrate 10, the second lower surface 32 and base Plate upper surface 11 is arranged face-to-face, and forms the second interconnection structure of conducting second electrode 321 and the first interconnection structure；
S8: ginseng Fig. 3 z-4 and Fig. 3 z-5 forms external pin 121 in the first interconnection structure.
Step S7, S8 is specifically included:
Join Fig. 3 w, forms metal column 41 in the lower section of second electrode 321；
Join Fig. 3 x, the second chip 30 is loaded into the top of package substrate 10, the second lower surface 32 and upper surface of base plate 11 Setting face-to-face, and layer 421 is rerouted in the conducting of metal column 41；
Join Fig. 3 y, forms the first plastic packaging layer 51, the first plastic packaging layer far from the side of base lower surface 12 in package substrate 10 The peripheral region of 51 the second chips 30 of cladding；
Join Fig. 3 z, forms the conducting of third hole 621 first Jing Guo second insulating layer 62 in the lower section of second insulating layer 62 Lower the second lower rewiring layer 4222 for rerouting layer 4221；
It is specific as follows:
Join Fig. 3 z, forms the second photoresist layer 92 in the lower section of second insulating layer 62；
Join Fig. 3 z-1, forms several second apertures 921 in 92 exposure and imaging of the second photoresist layer, the second aperture 921 is sudden and violent Expose third hole 621 and part second insulating layer 62；
Join Fig. 3 z-2, in forming the second lower rewiring layer 4222 in the second aperture 921, the second lower layer 4222 that reroutes is connected First lower rewiring layer 4221；
Join Fig. 3 z-3, removes the second photoresist layer 92.
Join Fig. 3 z-4, forms cladding second insulating layer 62 and the second lower third insulating layer 63 for rerouting layer 4222, third Insulating layer 63 exposes the second lower rewiring layer 4222；
Join Fig. 3 z-5, outer second is lower to reroute the formation ball grid array 121 of layer 4222 in being exposed to.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book With the other embodiments of understanding.
Tool of the series of detailed descriptions listed above only for the feasible embodiment of the utility model Body explanation, they are all without departing from made by the utility model skill spirit not to limit the protection scope of the utility model Equivalent implementations or change should be included within the scope of protection of this utility model.

Claims (7)

1. a kind of stacking embedded packaging structure characterized by comprising
Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber；
First chip is set in the chamber, and first chip has the first upper surface being oppositely arranged and the first following table Face, first upper surface and the upper surface of base plate are located at ipsilateral, and first lower surface has several first electrodes；
Second chip, is set to the top of the package substrate, second chip have the second upper surface being oppositely arranged and Second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second lower surface is with several Second electrode；
Several interconnection structures, for several first electrodes and several second electrodes to be connected, and the part interconnection structure runs through institute It states the first chip and first electrode is connected.
2. stacking embedded packaging structure according to claim 1, which is characterized in that first upper surface and the base Plate upper surface flushes.
3. stacking embedded packaging structure according to claim 1, which is characterized in that the side of the base lower surface has There are several external pins, the package substrate has several through-holes, and the interconnection structure is connected described the by the through-hole One electrode, the second electrode and the external pin.
4. stacking embedded packaging structure according to claim 3, which is characterized in that the interconnection structure includes metal column And electroplated layer structure, the metal column are connected to the lower section of the second electrode, the electroplated layer structure includes mutual conduction Upper rewiring layer and lower rewiring layer, upper top and the connection metal column for rerouting layer and being located at the package substrate, And the upper layer that reroutes, by the hole conducting first electrode on first chip, the lower rewiring layer passes through institute It states through-hole and is connected the upper rewiring layer, and the lower rewiring layer extends to the lower section of the package substrate and is connected described the One electrode and the external pin.
5. stacking embedded packaging structure according to claim 4, which is characterized in that the lower rewiring layer includes first Lower rewiring layer and the second lower rewiring layer, the encapsulating structure include the first insulating layer, second insulating layer and third insulating layer, First insulating layer coats the base lower surface and first lower surface, and the described first lower layer that reroutes is located at described the Simultaneously the first electrode and the upper rewiring is connected by the hole of first insulating layer and through-hole in the lower section of one insulating layer Layer, the second insulating layer coat first insulating layer and the first lower rewiring layer, reroute layer position under described second In the second insulating layer lower section and by the hole of the second insulating layer be connected described first it is lower reroute layer, it is described outer Portion's pin connection described second is lower to reroute layer, and the third insulating layer cladding described second is lower to reroute layer and described second absolutely Edge layer simultaneously exposes the external pin.
6. stacking embedded packaging structure according to claim 4, which is characterized in that described in the upper rewiring layer connection Upper surface of base plate and first upper surface, the encapsulating structure further include being located at the package substrate far from the substrate following table First plastic packaging layer of the side in face, the first plastic packaging layer coat the peripheral region of second chip.
7. stacking embedded packaging structure according to claim 1, which is characterized in that first chip and the chamber Gap location be equipped with the second plastic packaging layer.
CN201821544238.0U 2018-09-20 2018-09-20 Stack embedded packaging structure Active CN208655635U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109300882A (en) * 2018-09-20 2019-02-01 蔡亲佳 Stack embedded packaging structure and preparation method thereof
CN110444527A (en) * 2019-07-23 2019-11-12 中国科学技术大学 A kind of chip-packaging structure, device and method
CN111952284A (en) * 2020-07-01 2020-11-17 江苏长电科技股份有限公司 Stack packaging structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109300882A (en) * 2018-09-20 2019-02-01 蔡亲佳 Stack embedded packaging structure and preparation method thereof
CN110444527A (en) * 2019-07-23 2019-11-12 中国科学技术大学 A kind of chip-packaging structure, device and method
CN111952284A (en) * 2020-07-01 2020-11-17 江苏长电科技股份有限公司 Stack packaging structure and manufacturing method thereof

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Effective date of registration: 20200617

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Patentee after: Zhejiang Rongcheng Semiconductor Co., Ltd

Address before: 215000 No. 99 Jinjihu Avenue, Suzhou Industrial Park, Jiangsu Province

Patentee before: Cai Qinjia