CN208655637U

CN208655637U - The multi-core encapsulation module structure with filter chip of build-in cavities

Info

Publication number: CN208655637U
Application number: CN201821289570.7U
Authority: CN
Inventors: 付伟
Original assignee: 付伟
Current assignee: Zhejiang Rongcheng Semiconductor Co., Ltd
Priority date: 2018-08-10
Filing date: 2018-08-10
Publication date: 2019-03-26
Anticipated expiration: 2028-08-10

Abstract

The utility model discloses a kind of multi-core encapsulation module structure with filter chip of build-in cavities, and encapsulation modular structure includes: package substrate, with chamber；Filter chip is set in chamber, and the first upper surface and upper surface of base plate are located at ipsilateral, and the first upper surface has several first electrodes；Functional chip is set to the top of package substrate, and the second lower surface is arranged face-to-face with upper surface of base plate, and the second upper surface has several second electrodes；Several interconnection structures, for several first electrodes and several second electrodes to be connected.The utility model utilizes encapsulation technology that in same package substrate, the highly integrated of multi-chip is may be implemented in two different chip packages；In being distributed up and down, the functional chip above package substrate and the space for being not take up package substrate can be improved substrate utilization, simplify interconnection structure for filter chip and functional chip；Filter chip is embedded to be set in chamber, so that encapsulation modular structure is more frivolous.

Description

The multi-core encapsulation module structure with filter chip of build-in cavities

Technical field

The utility model relates to the more with filter chip of field of semiconductor package more particularly to a kind of build-in cavities Chip encapsulation module structure.

Background technique

To cater to the increasingly light and short development trend of electronic product, filter and radio-frequency transmissions component, receiving unit are needed It is highly integrateable in the encapsulating structure of limited areal, forms system in package (SystemInPackage, SIP) structure, To reduce the size of hardware system.

For the filter and RF front-end module encapsulation integration technology in system-in-package structure, there are still suitable in the industry More technical problem urgent need to resolve, for example, connection structure, multiple chips between the protection structure of filter, multiple chips Layout etc..

Summary of the invention

The purpose of this utility model is to provide a kind of multi-core encapsulation modules with filter chip of build-in cavities Structure.

To realize one of above-mentioned purpose of utility model, one embodiment of the utility model provides a kind of having for build-in cavities The multi-core encapsulation module structure of filter chip, comprising:

Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber；

Filter chip is set in the chamber, the filter chip have the first upper surface for being oppositely arranged and First lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first upper surface has several the One electrode；

Functional chip, is set to the top of the package substrate, and the functional chip has table on second be oppositely arranged Face and the second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second upper surface has Several second electrodes；

Several interconnection structures, for several first electrodes and several second electrodes to be connected.

As the further improvement of one embodiment of the utility model, the side of the base lower surface has several outsides Pin, the package substrate have several through-holes, and the first electrode, described is connected by the through-hole in the interconnection structure Second electrode and the external pin.

As the further improvement of one embodiment of the utility model, the through-hole and the second electrode are spaced apart from each other point Cloth.

As the further improvement of one embodiment of the utility model, the interconnection structure includes electroplated layer structure and draws Line, the first electrode is connected in the electroplated layer structure, and the electroplated layer structure extends to the encapsulation by the through-hole The lower section of substrate and the external pin is connected, the lead is for being connected the second electrode and the electroplated layer structure.

As the further improvement of one embodiment of the utility model, the electroplated layer structure includes the upper heavy of mutual conduction Wiring layer, intermediate wiring layer and lower rewiring layer, the upper rewiring layer are located at described in top and the conducting of the package substrate First electrode, the lower rewiring layer are located at the lower section of the package substrate and the external pin are connected, the intermediate wiring Layer includes connected the first electroplated layer positioned at the upper surface of base plate, the second electroplated layer of the inner wall positioned at the through-hole and position In the third electroplated layer of the base lower surface, wherein first electroplated layer connects the upper rewiring layer, and the lead connects The second electrode and the upper rewiring layer are connect, the third electroplated layer connects the lower rewiring layer.

As the further improvement of one embodiment of the utility model, the multi-core encapsulation module structure includes being located at institute It states the first insulating layer above the first upper surface of upper surface of base plate, be connected described first by the hole of first insulating layer The upper rewiring layer of electroplated layer and the first electrode and connect the second of first insulating layer and second lower surface Insulating layer, the second insulating layer have fluting, and the fluting exposes the upper rewiring layer and the lead is supplied to connect.

As the further improvement of one embodiment of the utility model, first insulating layer and the second insulating layer are matched Conjunction forms cofferdam, and the cofferdam and second lower surface, the first upper surface cooperate and enclose to set to form cavity, and the cofferdam includes The first cofferdam on the inside of several first electrodes and the second cofferdam on the outside of several first electrodes, first cofferdam with Second lower surface, first upper surface cooperate and enclose to set to form cavity, and second cofferdam is towards far from described the The lateral border that the direction in one cofferdam extends up to second cofferdam is flushed with the lateral border of the package substrate, and described second Cofferdam exposes the through-hole.

As the further improvement of one embodiment of the utility model, the multi-core encapsulation module structure further includes being located at First plastic packaging layer of side of the package substrate far from the base lower surface, the first plastic packaging layer coat described simultaneously Two cofferdam are exposed to outer surface area and the functional chip, and the first plastic packaging layer fills the through-hole.

As the further improvement of one embodiment of the utility model, the multi-core encapsulation module structure includes cladding institute It states the third insulating layer of third electroplated layer and base lower surface, the third electricity is connected by the hole of the third insulating layer The lower rewiring layer and the cladding third insulating layer and institute that the lower surface direction of coating and the past third insulating layer extends Lower the 4th insulating layer for rerouting layer is stated, the external pin connects the lower rewiring layer, and the 4th insulating layer exposing The external pin.

As the further improvement of one embodiment of the utility model, the gap of the filter chip and the chamber, The base lower surface and first lower surface are provided with the second plastic packaging layer, first upper surface and the upper surface of base plate It flushes.

Compared with prior art, the utility model has the beneficial effects that: one embodiment of the utility model utilizes encapsulation In same package substrate, the highly integrated of multi-chip may be implemented in two different chip packages by technology, improves package substrate Utilization rate, and then realize multi-core encapsulation module structure miniaturization；In addition, filter chip and functional chip are in upper and lower point Cloth, functional chip above package substrate and the space for being not take up package substrate, can be further improved package substrate Utilization rate, and the spacing between filter chip and functional chip becomes smaller, and is easy to implement between filter chip and functional chip Interconnection, simplify interconnection structure；It is set in chamber moreover, filter chip is embedded, so that multi-core encapsulation module structure is more Add frivolous.

Detailed description of the invention

Fig. 1 is the exemplary RF front-end module of the utility model one；

Fig. 2 is another exemplary RF front-end module of the utility model；

Fig. 3 is the cross-sectional view of the multi-core encapsulation module structure of one embodiment of the utility model；

Fig. 4 is the cofferdam cooperation through-hole of one embodiment of the utility model and the schematic diagram of first electrode；

The step of Fig. 5 is the production method of the multi-core encapsulation module structure of one embodiment of the utility model figure；

Fig. 6 a to Fig. 6 z-9 is the stream of the production method of the multi-core encapsulation module structure of one embodiment of the utility model Cheng Tu.

Specific embodiment

The utility model is described in detail below with reference to specific embodiment shown in the drawings.But these embodiment party Formula is not intended to limit the utility model, structure that those skilled in the art are made according to these embodiments, method or Transformation functionally is all contained in the protection scope of the utility model.

In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.

In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty Between relevant description language.

Join Fig. 1 and Fig. 2, one embodiment of the utility model provides a kind of general RF front-end module, radio-frequency front-end mould Block can be used in the mobile devices such as mobile phone, computer either other electronic equipments.

In conjunction with Fig. 1, in one example, RF front-end module includes (the Power Amplifier of power amplifier module 200 Module, PAM), power amplifier module 200 includes the first amplifier unit 201 being successively electrically connected, the first RF switch list Member 202 and the first RF filter cell 203, the first amplifier unit 201 are multi-mode-wide bandwidth Power Amplifier Unit.

In practical operation, the first amplifier unit 201 is used to receive the modulated signal of other component output, puts through overpower Greatly after the modulation, amplification of device module 200 and filtering operation, exported by filter cell 203.

In conjunction with Fig. 2, in another example, RF front-end module includes receiving 300 (Receive of diversity module Diversity Module, RDM), receiving diversity module 300 includes the low noise amplification multiplexer 301 being successively electrically connected (LNA Multiplexer Module, LMM), the 2nd RF filter cell 302 and RF duplexer unit 303, wherein low It includes the second amplifier unit 3011 and the 2nd RF switch unit 3012 being electrically connected that noise, which amplifies multiplexer 301, and second puts Big device unit 3011 is multi-mode-wide bandwidth low-noise amplifier unit, and the both ends of the 2nd RF switch unit 3012 connect respectively Connect the second amplifier unit 3011 and the 2nd RF filter cell 302.

In practical operation, signal divides by notch diplexer 304 to be believed here with high frequency for high-frequency signal and low frequency signal For number, high-frequency signal enters RF duplexer unit 303, then successively passes through the 2nd RF filter cell 302 and low noise It is exported after amplifying the filtering, modulation, amplifying operation of multiplexer 301 by the second amplifier unit 3011.

It should be understood that the electrical property between each units such as above-mentioned RF switch unit, filter cell, amplifier unit connects Connecing can be realized by packaging technology, i.e., RF switch chip, amplifier chip, filter chip etc. are packaged together and realize Various functions.

Present embodiment is with multi-core encapsulation module structure, the technique of RF switch chip, amplifier chip, filter chip For explain.

Join Fig. 3, is the multi-chip package mould with filter chip of the build-in cavities of one embodiment of the utility model The cross-sectional view of block structure 100.

Multi-core encapsulation module structure 100 include package substrate 10, filter chip 20, functional chip 30 and it is several mutually Link structure 50.

Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, and package substrate 10 has chamber Room 101.

Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin Circuit board is also possible to glass substrate or ceramic substrate etc..

Chamber 101 can be the through hole through package substrate 10, and but not limited to this.

Filter chip 20 is set in chamber 101, filter chip 20 have the first upper surface 21 for being oppositely arranged and First lower surface 22, the first upper surface 21 and upper surface of base plate 11 are located at ipsilateral, and the first upper surface 21 has several first electricity Pole 211.

First electrode 211 protrudes out the first upper surface 21 towards the direction far from the first lower surface 22, and but not limited to this.

Filter chip 20 can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or body Product acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the activity on 20 surface of filter chip Region (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs are being filtered The lower section of wave device chip 20 forms a cavity to protect the active region.

Functional chip 30 is set to the top of package substrate 10, and functional chip 30 has the second upper surface 31 being oppositely arranged And second lower surface 32, the second lower surface 32 are arranged face-to-face with upper surface of base plate 11, and the second upper surface 31 has several the Two electrodes 311.

Second electrode 311 protrudes out the second upper surface 31 towards the direction far from the second lower surface 32, and but not limited to this.

Functional chip 30 is amplifier chip or RF switch chip, and but not limited to this.

Several interconnection structures 50 are for being connected several first electrodes 211 and several second electrodes 311.

Here, " several interconnection structures 50 for several first electrodes 211 and several second electrodes 311 to be connected " refer to the It is electrically connected between one electrode 211 and second electrode 311, that is, realizes the interconnection of filter chip 20 and functional chip 30.

Present embodiment is encapsulated two different chips (filter chip 20 and functional chip 30) using encapsulation technology In same package substrate 10, the highly integrated of multi-chip may be implemented, improve the utilization rate of package substrate 10, and then realize multicore The miniaturization of piece encapsulation modular structure 100.

In addition, filter chip 20 and functional chip 30 are distributed in upper and lower, the functional chip above package substrate 10 30 and be not take up the space of package substrate 10, can be further improved the utilization rate of package substrate 10, and filter chip 20 and Spacing between functional chip 30 becomes smaller, the interconnection being easy to implement between filter chip 20 and functional chip 30, simplifies interconnection Structure.

It is set in chamber 101 moreover, filter chip 20 is embedded, so that multi-core encapsulation module structure 100 is more light It is thin.

It should be noted that the multi-core encapsulation module structure 100 of present embodiment is with a filter chip 20 and one A functional chip 30 is loaded into for package substrate 10, it is possible to understand that, in practice, referring to Figure 1 and Figure 2, it can wrap Containing multiple filter chips 20 and multiple functional chips 30, for example, around filter chip 20 (including up and down all around three Dimension direction) multiple functional chips 30 etc. can be electrically connected with.

In the present embodiment, functional chip 30 is located at the top of chamber 101, several first electrodes 211 and several second Electrode 311 is in face of back setting.

That is, filter chip 20 and about 30 functional chip are correspondingly arranged, first electrode 211 and second Electrode 311 is located at the opposite two sides of package substrate 10, in this way, the setting of filter chip 20 can't in the horizontal direction The excessive space for occupying 10 horizontal direction of package substrate, the size of package substrate 10 can be done small.

Here, the size of functional chip 30 is greater than the size of filter chip 20, and functional chip 30 and chamber 101 it Between to partly overlap.

That is, the outer profile of functional chip 30 is portion between the upright projection on package substrate 10 and chamber 101 Divide overlapping.

In the present embodiment, the side of package substrate 10 has several external pins 121, and interconnection structure 50 is for leading Logical first electrode 211, second electrode 311 and external pin 121.

External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., multi-chip package mould Block structure 100 can be electrically connected by external pin 121 with the realizations such as other chips or substrate, here, external pin 121 with For ball grid array 121, external pin 121 protrudes out the lower surface of multi-core encapsulation module structure 100.

In addition, but not limited to this, outside here by taking several external pins 121 are located at the side of base lower surface 12 as an example Portion's pin 121 may be alternatively located at other regions.

Package substrate 10 has several through-holes 13, and the 211, second electricity of first electrode is connected by through-hole 13 in interconnection structure 50 Pole 311 and external pin 121.

In the present embodiment, through-hole 13 and second electrode 311 are spaced apart from each other distribution.

Here, through-hole 13 is located at the outside of second electrode 311, and through-hole 13 is located at the outside of chamber 101, at this point, being located at The external pin 121 of 12 side of base lower surface can be towards shifting outside the two sides of functional chip 30, convenient for arranging other chips in advance The space of embedment, consequently facilitating realizing that the multi-chip 2.5D or 3D of high-performance and small size stack integration packaging and mould group.

In the present embodiment, interconnection structure 50 includes electroplated layer structure 53 and lead 51.

First electrode 211 is connected in electroplated layer structure 53, and electroplated layer structure 53 extends to package substrate 10 by through-hole 13 Lower section and external pin 121 is connected, lead 51 is for being connected second electrode 311 and electroplated layer structure 53.

Specifically, electroplated layer structure 53 includes the upper rewiring layer 531, intermediate wiring layer 532 and lower heavy cloth of mutual conduction Line layer 533.

Upper rewiring layer 531 is located at the top of package substrate 10 and first electrode 211 is connected.

Here, lead 51 connects second electrode 311 and upper rewiring layer 531.

Intermediate wiring layer 532 is including being connected positioned at the first electroplated layer 5321 of upper surface of base plate 11, in through-hole 13 Second electroplated layer 5322 of wall and third electroplated layer 5323 positioned at base lower surface 12.

Layer 531 is rerouted in the connection of first electroplated layer 5321.

The width that the first electroplated layer 5321 of rewiring layer 531 extends to upper surface of base plate 11 in connection is substantially equal to correspondence Third electroplated layer 5323 extend to the width of base lower surface 12.

Here, on the one hand, upper surface of base plate 11 and base lower surface 12 are provided with electroplated layer, can be improved electroplated layer with The strong degree that package substrate 10 combines；On the other hand, the first electroplated layer 5321 extends towards 211 direction of first electrode, convenient for upper It reroutes layer 531 and connects the first electroplated layer 5321, through-hole 13 can be towards shifting outside two sides, so that base lower surface 12 is outer Portion's pin 121 can move in addition.

Lower rewiring layer 533 is located at the lower section of package substrate 10 and external pin 121 is connected, and lower rewiring layer 533 connects Connect third electroplated layer 5323.

Here, multi-core encapsulation module structure 100 include positioned at upper surface of base plate 11, the top of the first upper surface 21 the One insulating layer 70, the upper rewiring that the first electroplated layer 5321 and first electrode 211 are connected by the hole of the first insulating layer 70 The second insulating layer 71 of layer 531 and the first insulating layer 70 of connection and the second lower surface 32, second insulating layer 71 have fluting 43, fluting 43, which exposes, to reroute layer 531 and connects for lead 51, and the other end of lead 51 connects second electrode 311.

Multi-core encapsulation module structure 100 includes the third insulating layer of cladding third electroplated layer 5323 and base lower surface 12 72, by the hole of third electroplated layer 5323 and toward third insulating layer 72 lower surface direction extend lower rewiring layer 533 with And cladding third insulating layer 72 and lower the 4th insulating layer 73 for rerouting layer 533, external pin 121 connect lower rewiring layer 533, And the 4th insulating layer 73 exposure external pin 121.

The lower setting for rerouting layer 533 can not only expand rewiring range, improve what subsequent external pin 121 was laid Freedom degree, the outer shifting of acceptable further accessory external pin 121.

Lead 51 is gold thread, and upper rewiring layer 531, intermediate wiring layer 532 and lower rewiring layer 533 are layers of copper.

Present embodiment realizes first electrode 211, second electrode 311 and outer using succinct rewiring (RDL) scheme Electric connection between portion's pin 121, process stabilizing and high reliablity.

The metal line materials of rewiring are that copper is (i.e. upper to reroute layer 531, intermediate wiring layer 532 and lower rewiring layer 533 For layers of copper), it reroutes and enhancing weight cloth can be set between copper and chip electrode (including first electrode 211 and second electrode 311) Line copper and chip electrode are attached to each other the metal or alloy film of power, which can be nickel, titanium, nickel chromium triangle, Titanium tungsten etc..

The first insulating layer 70, second is folded between package substrate 10, upper rewiring layer 531 and lower rewiring layer 533 absolutely Edge layer 71 and third insulating layer 72, to realize the electrical isolation between all parts.

It should be understood that the upper rewiring layer 531 in rewiring scheme is not limited with above-mentioned one layer, lower rewiring layer 533 are not also limited with above-mentioned one layer, can according to the actual situation depending on.

In addition, the advantage of present embodiment setting lead 51 is: structure is simple, reduces technology difficulty, improves production effect Rate.

In the present embodiment, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, cofferdam 40 and second Lower surface 32, the first upper surface 21 cooperate and enclose to set to form cavity S, the active region on 20 surface of cavity S respective filter chip Domain.

Present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from multi-core encapsulation module structure system During work or external substance enters inside cavity S and influences filter core in multi-core encapsulation module structure use process The normal use of piece 20, to improve the overall performance of multi-core encapsulation module structure 100.

In the present embodiment, cavity S is located at the inside of several first electrodes 211.

Cofferdam 40 includes positioned at the first cofferdam 41 of several 211 insides of first electrode and outside several first electrodes 211 Second cofferdam 42 of side, the first cofferdam 41 and the second lower surface 32 and the first upper surface 21 cooperate and enclose and set to form cavity S。

Here, the first cofferdam 41 is located at the inside of through-hole 13, and 42 part of the second cofferdam is located at 13 inside of through-hole, part position In 13 outside of through-hole.

Since cofferdam 40 has certain height, when the lower surface area when cofferdam 40 is too small, this may can not be supported There is collapsing phenomenon so as to cause cofferdam 40 in the cofferdam 40 of height, and the cofferdam 40 of present embodiment includes the first cofferdam 41 and the Two cofferdam 42, cofferdam 40 have sufficiently large lower surface, improve the stability in entire cofferdam 40；In addition, 40 lower surface of cofferdam It can combine with the 20 upper surface whole region of filter chip outside the 20 upper surface region cavity S of filter chip, further mention The forming stability of high cavity S.

In conjunction with Fig. 4, several through-holes 13 are in array distribution in upper surface of base plate 11, and have interval between adjacent through-holes 13, There is a space between two column through-holes 13, chamber 101 is located in the space, and has interval between chamber 101 and through-hole 13, The interior zone of the corresponding chamber 101 in first cofferdam 41, and 41 essence of the first cofferdam is to be located at the inside of first electrode 211, second Cofferdam 42 is extended by the interior zone of corresponding chamber 101 towards 13 direction of through-hole, and slots 43 positioned at the top in cofferdam 40, fluting 43 are located at the outside of functional chip 30.

In addition, the second cofferdam 42 extends up to lateral border and the encapsulation in the second cofferdam 42 towards the direction far from the first cofferdam 41 The lateral border of substrate 10 flushes, and the second cofferdam 42 exposes through-hole 13.

Certainly, since package substrate 10 is quadrilateral structure, lateral border further include package substrate 10 front side lateral margin and after Side lateral margin, the second cofferdam 42 can also extend to front side lateral margin and rear side lateral margin together, and but not limited to this, and package substrate 10 can also To be the structure of other shapes.

It should be noted that can be independent from each other between the first cofferdam 41 and the second cofferdam 42, such as the first cofferdam 41 be the first cyclic structure, and the first cyclic structure is located at the inside of several first electrodes 211, and the second cofferdam 42 is the second cyclic annular knot Structure, the second cyclic structure are located at the outside of several first electrodes 211.

Certainly, be also possible between the first cofferdam 41 and the second cofferdam 42 it is interconnected, at this point, the first cofferdam 41 and Interconnection is realized by third cofferdam 45 between two cofferdam 42, third cofferdam 45 is located at adjacent through-hole 13, adjacent first electrode Between 211 or other regions, that is to say, that cofferdam 40 at this time is covered on upper surface of base plate 11 and the first upper surface 21 Side removes other whole regions in cavity S and 13 region of through-hole.

In the present embodiment, the second lower surface 32 of functional chip 30 covers the upper surface in the first cofferdam 41, and second Lower surface 32 is Chong Die with the upper surface portion in the second cofferdam 42, and the first upper surface 21 and upper surface of base plate 11 cover first together The lower surface in the lower surface in cofferdam 41 and the second cofferdam 42.

Cofferdam 40 is made of the insulating materials of photaesthesia, and but not limited to this.

In the present embodiment, multi-core encapsulation module structure 100 further includes coating the second cofferdam 42 simultaneously to be exposed to outside Surface area and functional chip 30 the first plastic packaging layer 60, and the first plastic packaging layer 60 fills through-hole 13, and the first plastic packaging layer 60 cladding leads 51.

First plastic packaging layer 60 is located at side of the package substrate 10 far from base lower surface 12.

That is, the first plastic packaging layer 60 is located inside top and the through-hole 13 in the second cofferdam 42 at this time, the first plastic packaging layer All 13 interior zones of open area and through-hole around 60 cladding functional chips 30.

First plastic packaging layer 60 can be EMC (Epoxy Molding Compound) plastic packaging layer, due to present embodiment benefit External substance can be stopped to enter cavity S with cofferdam 40, without consider the first plastic packaging layer 60 whether can because of problem of materials shadow The protection zone in cavity S is rung, therefore, the range of choice of 60 material of the first plastic packaging layer expands significantly, and then can evade specific The selection of capsulation material is substantially widened plastic packaging making technology window and is effectively reduced cost.

In the present embodiment, the first upper surface 21 of filter chip 20 is flushed with upper surface of base plate 11, moreover, filtering Gap, base lower surface 12 and the first lower surface 22 of device chip 20 and chamber 101 are provided with the second plastic packaging layer 61.

That is, 5323 essence of third electroplated layer is to be located at the lower section of the second plastic packaging layer 61, and third insulating layer 72 is real For matter also in the lower section of the second plastic packaging layer 61, other explanations of the second plastic packaging layer 61 can saying with reference to the first plastic packaging layer 60 Bright, details are not described herein.

Here, pass through the setting of the second plastic packaging layer 61, on the one hand, can with compensating filter chip 20 and package substrate 10 it Between difference in thickness, to realize that the first upper surface 21 is flushed with upper surface of base plate 11, in order to subsequent first insulating layer 70, the The isostructural molding of three insulating layer 72；On the other hand, the second plastic packaging layer 61 can play protecting filter chip 20 and fix The effect of the relative position of filter chip 20 and chamber 101.

One embodiment of the utility model also provides a kind of production method of multi-core encapsulation module structure 100, in conjunction with preceding State the explanation and Fig. 5, Fig. 6 a to Fig. 6 z-9 of multi-core encapsulation module structure 100, production method comprising steps of

S1: ginseng Fig. 6 a provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；

S2: ginseng Fig. 6 b, in formation chamber 101 on package substrate 10；

S3: ginseng Fig. 6 c provides filter chip 20, and filter chip 20 has the first upper surface 21 being oppositely arranged and the A lower surface 22, the first upper surface 21 have several first electrodes 211；

S4: ginseng Fig. 6 d to Fig. 6 j loads filter chip 20 to chamber 101, the first upper surface 21 and upper surface of base plate 11 positioned at ipsilateral；

Step S4 is specific as follows:

Join Fig. 6 d, an interim jointing plate 90 is provided；

Join Fig. 6 e, the upper surface of base plate 11 of package substrate 10 is fitted in into interim jointing plate 90；

Join Fig. 6 f, filter chip 20 is loaded to chamber 101, the first upper surface 21 is located at same with upper surface of base plate 11 Side；

Here, the first upper surface 21 also fits in interim jointing plate 90, so, it can be achieved that the first upper surface 21 and substrate Upper surface 11 flushes.

Join Fig. 6 g, forms gap, base lower surface 12 and the first lower surface 22 of cladding filter chip 20 and chamber 101 The second plastic packaging layer 61；

Join Fig. 6 h, removes interim jointing plate 90；

Join Fig. 6 i, inverts package substrate 10.

Join Fig. 6 j, in forming several through-holes 13 on package substrate 10, through-hole 13 runs through the second plastic packaging layer 61.

S5: ginseng Fig. 6 k to Fig. 6 v, in forming the first interconnection structure on package substrate 10, the first interconnection structure conducting first is electric Pole 211；

Step S5 is specific as follows:

Join Fig. 6 k to Fig. 6 n, forms the first electroplated layer 5321 in upper surface of base plate 11,13 inner wall of Yu Tongkong forms the second electricity Coating 5322 forms third electroplated layer 5323 below the second plastic packaging layer 61；

It is specific as follows:

Join Fig. 6 k, is respectively formed beneath the first photoresist layer 81 in the top of upper surface of base plate 11 and the second plastic packaging layer 61 And second photoresist layer 82；

Join Fig. 6 l, forms the first aperture 811 in 81 exposure and imaging of the first photoresist layer, the first aperture 811 exposes logical Hole 13 and upper surface of base plate 11 form the second aperture 821, the second aperture 821 exposure in 82 exposure and imaging of the second photoresist layer Through-hole 13 and the second plastic packaging layer 61 out；

Join Fig. 6 m, forms the first electroplated layer 5321 in being exposed to outer upper surface of base plate 11, the through-hole 13 outside being exposed to Inner wall forms the second electroplated layer 5322, forms third electroplated layer 5323 in being exposed to the second outer plastic packaging layer 61；

Join Fig. 6 n, removes the first photoresist layer 81 and the second photoresist layer 82.

Join Fig. 6 o, lays the first insulating layer 70 in upper surface of base plate 11；

Join Fig. 6 p to Fig. 6 t, is formed in the top of the first insulating layer 70 by the hole conducting first on the first insulating layer 70 The upper rewiring layer 531 of electrode 211 and the first electroplated layer 5321；

It is specific as follows:

Join Fig. 6 p, forms the first hole 701 in 70 exposure and imaging of the first insulating layer, the first hole 701 exposes first Electrode 211, through-hole 13, the first electroplated layer 5321 and protection zone, protection zone are located at the first upper surface 21, and protection zone position In the inside of several first electrodes 211；

Join Fig. 6 q, forms third photoresist layer 83 in the top of the first insulating layer 70；

Join Fig. 6 r, forms third aperture 831 in 83 exposure and imaging of third photoresist layer, third aperture 831 exposes the One electrode 211, the first electroplated layer 5321 and the first insulating layer 70；

Join Fig. 6 s, reroutes layer 531 in being formed in third aperture 831；

Join Fig. 6 t, removes third photoresist layer 83.

Join Fig. 6 u and Fig. 6 v, in the first insulating layer 70, it is upper reroute layer 531 top lay second insulating layer 71, first Insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, and cofferdam 40 includes the first cofferdam 41 and the second cofferdam 42, and first encloses Weir 41 is located at the periphery of cavity S, and the lateral border in the second cofferdam 42 is flushed with the lateral border of package substrate 10, the exposure of the second cofferdam 42 Through-hole 13 out, cofferdam 40 have the fluting 43 for exposing and rerouting layer 531；

It is specific as follows:

Join Fig. 6 u, lays second insulating layer 71 in the first insulating layer 70, the upper top for rerouting layer 531 and protection zone；

Join Fig. 6 v, forms the second hole 711 in 71 exposure and imaging of second insulating layer, the second hole 711 exposes through-hole 13, upper rewiring layer 531 and protection zone, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, and cofferdam 40 is wrapped The first cofferdam 41 and the second cofferdam 42 are included, the first cofferdam 41 is located at the periphery of protection zone, the lateral border and envelope in the second cofferdam 42 The lateral border of dress substrate 10 flushes, and the second cofferdam 42 exposes through-hole 13, and cofferdam 40, which has to expose, reroutes layer 531 Fluting 43.

It should be noted that cofferdam 40 may include the third cofferdam 45 for connecting the first cofferdam 41 and the second cofferdam 42, That is removing the other surfaces region outside corresponding cavity S and 13 region of through-hole in upper surface of base plate 11 at this time is respectively formed cofferdam 40。

In addition, formed since independent package substrate 10 can be divided by the large substrates of wafer scale, when forming cofferdam 40, Can on large substrates the multiple cofferdam 40 of straight forming, then carry out the segmentation of large substrates again and obtain that there is single cofferdam 40 Single package substrate 10, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40 is also plastic on functional chip 30.

S6: ginseng Fig. 6 w, functional chip 30 is provided, functional chip 30 has the second upper surface 31 and second being oppositely arranged Lower surface 32, and the second upper surface 31 has several second electrodes 311；

S7: ginseng Fig. 6 x to Fig. 6 z-6 is loaded into functional chip 30 in the top of package substrate 10, the second lower surface 32 and base Plate upper surface 11 is arranged face-to-face, and forms the second interconnection structure of conducting second electrode 311 and the first interconnection structure；

S8: ginseng Fig. 6 z-7 to Fig. 6 z-9 forms the third interconnection structure of conducting external pin 121 and the first interconnection structure.

Step S7, S8 is specific as follows:

Join Fig. 6 x, functional chip 30 is loaded into the top of package substrate 10, the second lower surface 32 and upper surface of base plate 11 Setting face-to-face, the first cofferdam 41 cooperate with the second lower surface 32, the first upper surface 21 and enclose to set to form corresponding protection zone The cavity S in domain.

Join Fig. 6 y, connects the upper rewiring layer 531 in second electrode 311 and fluting 43 using gold thread 51；

Join Fig. 6 z, forms the first plastic packaging layer 60, the first plastic packaging layer far from the side of base lower surface 12 in package substrate 10 60 coat the second cofferdam 42 simultaneously is exposed to outer surface area and functional chip 30, and the first plastic packaging layer 60 fills through-hole 13；

Join Fig. 6 z-1, forms third insulating layer 72 in the lower section of third electroplated layer 5323 and the second plastic packaging layer 61；

Join Fig. 6 z-2 to Fig. 6 z-6, is formed in the lower section of third insulating layer 72 by the hole conducting on third insulating layer 72 The lower rewiring layer 533 of third electroplated layer 5323；

It is specific as follows:

Join Fig. 6 z-2, forms third hole 721 in 72 exposure and imaging of third insulating layer, third hole 721 exposes the Three electroplated layers 5323；

Join Fig. 6 z-3, forms the 5th photoresist layer 85 in the lower section of third insulating layer 72；

Join Fig. 6 z-4, forms the 5th aperture 851 in 85 exposure and imaging of the 5th photoresist layer, the 5th aperture 851 exposes Third hole 721 and third insulating layer 72；

Join Fig. 6 z-5, layer 533 is rerouted under being formed in the 5th aperture 851；

Join Fig. 6 z-6, removes the 5th photoresist layer 85.

Join Fig. 6 z-7 and Fig. 6 z-8, forms cladding third insulating layer 72 and lower the 4th insulating layer 73 for rerouting layer 533, the Four insulating layers 73 expose lower rewiring layer 533；

It is specific as follows:

Join Fig. 6 z-7, forms the 4th insulating layer 73 in the lower section of lower rewiring layer 533 and third insulating layer 72；

Join Fig. 6 z-8, the 4th hole 731 is formed in 73 exposure and imaging of the 4th insulating layer, under the 4th hole 731 exposes Reroute layer 533；

Join Fig. 6 z-9, forms ball grid array 121 in being exposed to outer lower rewiring layer 533, i.e., in shape in the 4th hole 731 At ball grid array 121.

Other explanations of the production method of the multi-core encapsulation module structure 100 of present embodiment can refer to above-mentioned multicore The explanation of piece encapsulation modular structure 100, details are not described herein.

The cofferdam 40 of the utility model is located at the inside and outside of first electrode 211, and the lateral border in the second cofferdam 42 with The lateral border of package substrate 10 flushes, and in other embodiments, cofferdam 40 may be alternatively located at the inside of first electrode 211, alternatively, The lateral border in the second cofferdam 42 is flushed with the lateral border of functional chip 30, or, the lateral border in the second cofferdam 42 is located at function Between the lateral border of chip 30 and the lateral border of package substrate 10 etc..

To sum up, present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from multi-core encapsulation module knot During structure is made or external substance enters inside cavity S and influences filtering in multi-core encapsulation module structure use process The normal use of device chip 20, to improve the overall performance of multi-core encapsulation module structure 100.

In addition, present embodiment utilizes encapsulation technology by two different chips (filter chip 20 and functional chip 30) It is packaged in same package substrate 10, the highly integrated of multi-chip may be implemented, improves the utilization rate of package substrate 10, Jin Ershi The miniaturization of existing multi-core encapsulation module structure 100.

It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book With the other embodiments of understanding.

Tool of the series of detailed descriptions listed above only for the feasible embodiment of the utility model Body explanation, they are all without departing from made by the utility model skill spirit not to limit the protection scope of the utility model Equivalent implementations or change should be included within the scope of protection of this utility model.

Claims

1. a kind of multi-core encapsulation module structure with filter chip of build-in cavities characterized by comprising

Filter chip is set in the chamber, and the filter chip has the first upper surface and first being oppositely arranged Lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first upper surface has several first electricity Pole；

Functional chip, is set to the top of the package substrate, the functional chip have the second upper surface being oppositely arranged and Second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second upper surface is with several Second electrode；

2. multi-core encapsulation module structure according to claim 1, which is characterized in that the side of the base lower surface has There are several external pins, the package substrate has several through-holes, and the interconnection structure is connected described the by the through-hole One electrode, the second electrode and the external pin.

3. multi-core encapsulation module structure according to claim 2, which is characterized in that the through-hole and the second electrode It is spaced apart from each other distribution.

4. multi-core encapsulation module structure according to claim 2, which is characterized in that the interconnection structure includes electroplated layer Structure and lead, the first electrode is connected in the electroplated layer structure, and the electroplated layer structure is extended to by the through-hole The lower section of the package substrate and the external pin is connected, the lead is for being connected the second electrode and the electroplated layer Structure.

5. multi-core encapsulation module structure according to claim 4, which is characterized in that the electroplated layer structure includes mutual The upper rewiring layer of conducting, intermediate wiring layer and lower rewiring layer, the upper top for rerouting layer and being located at the package substrate And the first electrode is connected, the lower rewiring layer is located at the lower section of the package substrate and the external pin is connected, institute State intermediate wiring layer include connected the first electroplated layer positioned at the upper surface of base plate, the inner wall positioned at the through-hole second Electroplated layer and third electroplated layer positioned at the base lower surface, wherein first electroplated layer connects the upper rewiring layer, The lead connects the second electrode and the upper rewiring layer, and the third electroplated layer connects the lower rewiring layer.

6. multi-core encapsulation module structure according to claim 5, which is characterized in that the multi-core encapsulation module structure Including being located at the first insulating layer above first upper surface of upper surface of base plate, leading by the hole of first insulating layer Lead under upper rewiring layer and connection first insulating layer and described second of first electroplated layer and the first electrode The second insulating layer on surface, the second insulating layer have a fluting, the fluting expose the upper rewiring layer and described in supplying Lead connection.

7. multi-core encapsulation module structure according to claim 6, which is characterized in that first insulating layer and described Two insulating layers cooperatively form cofferdam, and the cofferdam and second lower surface, the first upper surface cooperate and enclose to set to form cavity, institute Stating cofferdam includes being located at the first cofferdam on the inside of several first electrodes and the second cofferdam on the outside of several first electrodes, described First cofferdam and second lower surface, first upper surface cooperate and enclose to set to form cavity, the second cofferdam court The lateral border that direction far from first cofferdam extends up to second cofferdam is flushed with the lateral border of the package substrate, And second cofferdam exposes the through-hole.

8. multi-core encapsulation module structure according to claim 7, which is characterized in that the multi-core encapsulation module structure It further include the first plastic packaging layer positioned at side of the package substrate far from the base lower surface, the first plastic packaging layer is simultaneously It coats second cofferdam and is exposed to outer surface area and the functional chip, and the first plastic packaging layer filling is described logical Hole.

9. multi-core encapsulation module structure according to claim 5, which is characterized in that the multi-core encapsulation module structure Including coating the third insulating layer of the third electroplated layer and base lower surface, being connected by the hole of the third insulating layer The lower rewiring layer and the cladding third that the lower surface direction of the third electroplated layer and the past third insulating layer extends Insulating layer and lower the 4th insulating layer for rerouting layer, the external pin connect the lower rewiring layer, and the described 4th External pin described in insulating layer exposing.

10. multi-core encapsulation module structure according to claim 1, which is characterized in that the filter chip with it is described The gap of chamber, the base lower surface and first lower surface are provided with the second plastic packaging layer, first upper surface and institute Upper surface of base plate is stated to flush.