CN208507672U - Multi-chip integrating packaging module structure with chamber and filter chip - Google Patents

Abstract

The utility model discloses a kind of multi-chip integrating packaging module structure with chamber and filter chip, and encapsulation modular structure includes: package substrate, with several chambers；An at least filter chip and at least an amplifier chip, are respectively arranged in several chambers；RF switch chip is set to the top of package substrate；Several interconnection structures, for filter chip, amplifier chip and RF switch chip to be connected.The utility model utilizes encapsulation technology in same package substrate, the highly integrated of multi-chip to may be implemented, improve the utilization rate of package substrate multiple and different chip packages；In being distributed up and down, the RF switch chip above package substrate and the space for being not take up package substrate can be further improved the utilization rate of package substrate, simplify interconnection structure for filter chip, amplifier chip and RF switch chip；Filter chip and amplifier chip, which embed, to be set in several chambers, so that encapsulation modular structure is more frivolous.

Description

Multi-chip integrating packaging module structure with chamber and filter chip

Technical field

The utility model relates to field of semiconductor package more particularly to a kind of multi-chips with chamber and filter chip Integrating packaging module structure.

Background technique

To cater to the increasingly light and short development trend of electronic product, filter and radio-frequency transmissions component, receiving unit are needed It is highly integrateable in the encapsulating structure of limited areal, forms system in package (SystemInPackage, SIP) structure, with Reduce the size of hardware system.

For the filter and RF front-end module encapsulation integration technology in system-in-package structure, there are still suitable in the industry More technical problem urgent need to resolve, for example, connection structure, multiple chips between the protection structure of filter, multiple chips Layout etc..

Summary of the invention

The purpose of this utility model is to provide a kind of multi-chip integrating packaging module with chamber and filter chip Structure.

To realize that one of above-mentioned purpose of utility model, one embodiment of the utility model provide a kind of with chamber and filtering The multi-chip integrating packaging module structure of device chip, comprising:

Package substrate, with several chambers；

An at least filter chip and at least an amplifier chip, are respectively arranged in several chambers；

RF switch chip is set to the top of the package substrate；

Several interconnection structures, for filter chip, amplifier chip and RF switch chip to be connected.

As the further improvement of one embodiment of the utility model, the package substrate has on the substrate being oppositely arranged Surface and base lower surface, and the package substrate has first chamber, second chamber and the third chamber being spaced apart, it is described Multi-chip integrating packaging module structure includes positioned at the first filter chip of the first chamber, positioned at the second chamber Second filter chip and amplifier chip positioned at the third chamber, the first filter chip, which has, to be oppositely arranged First upper surface and the first lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and table on described first Face has several first electrodes, and the second filter chip has the second upper surface and the second lower surface being oppositely arranged, institute It states the second upper surface and the upper surface of base plate and is located at ipsilateral, and second upper surface has several second electrodes, described to put Big device chip has the third upper surface and third lower surface being oppositely arranged, the third upper surface and the upper surface of base plate position In ipsilateral, and the third upper surface has several third electrodes, and the RF switch chip has table on the 4th be oppositely arranged Face and the 4th lower surface, the 4th lower surface are arranged face-to-face with the upper surface of base plate, and the 4th lower surface has Several 4th electrodes, several interconnection structures are for being connected several first electrodes, several second electrodes, several third electrodes and several 4th electrode.

As the further improvement of one embodiment of the utility model, the side of the base lower surface has several outsides Pin, the package substrate have several through-holes, and several first electrodes, several are connected by the through-hole in the interconnection structure Second electrode, several third electrodes, several 4th electrodes and several external pins.

As the further improvement of one embodiment of the utility model, the interconnection structure includes metal column, scolding tin and electricity Coating structure, the metal column are connected to the lower section of the 4th electrode, and the first electrode, institute is connected in the electroplated layer structure Second electrode and the third electrode are stated, and the electroplated layer structure extends to the lower section of the package substrate by the through-hole And the external pin is connected, the scolding tin is for being connected the metal column and the electroplated layer structure.

As the further improvement of one embodiment of the utility model, the electroplated layer structure includes the upper heavy of mutual conduction Wiring layer, intermediate wiring layer and lower rewiring layer, the upper rewiring layer are located at described in top and the conducting of the package substrate First electrode, the second electrode, the third electrode and the scolding tin, the lower rewiring layer are located at the package substrate Simultaneously the external pin is connected in lower section, and the intermediate wiring layer includes connected the first electricity being located at the through-hole upper end opening Coating, the third electroplated layer positioned at the second electroplated layer of the through-hole wall and below the base lower surface, described One electroplated layer connects the upper rewiring layer, and the third electroplated layer connects the lower rewiring layer.

As the further improvement of one embodiment of the utility model, the multi-chip integrating packaging module structure includes the One insulating layer and second insulating layer, first insulating layer be located at the third electroplated layer and base lower surface, the first lower surface, Second lower surface, below third lower surface, and first insulating layer fills the through-hole, described in lower the rewirings layer process Hole on first insulating layer is connected the third electroplated layer and extends toward the lower surface direction of first insulating layer, described outer Portion's pin connects the lower rewiring layer, and the second insulating layer coats first insulating layer and the lower rewiring layer, and The second insulating layer exposure external pin.

As the further improvement of one embodiment of the utility model, the multi-chip integrating packaging module structure includes the Three insulating layers and the 4th insulating layer, the third insulating layer be located at the upper surface of base plate, the first upper surface, the second upper surface, The top of third upper surface, it is described it is upper reroute layer by the hole on the third insulating layer be connected first electroplated layer, The first electrode, the second electrode and the third electrode, the 4th insulating layer connect the third insulating layer and institute The 4th lower surface is stated, the 4th insulating layer, which has, exposes the upper fluting for rerouting layer and accommodating scolding tin.

As the further improvement of one embodiment of the utility model, the third insulating layer and the 4th insulating layer are matched Conjunction forms cofferdam, the cofferdam and the 4th lower surface and first upper surface cooperation and encloses to set to form the first cavity, and The cofferdam and the 4th lower surface and second upper surface cooperate and enclose and set to form the second cavity.

As the further improvement of one embodiment of the utility model, the cofferdam includes being located at several first electrodes If inside and forming the first cofferdam of the first cavity outer profile, the second cofferdam on the outside of several first electrodes, being located at On the inside of the dry second electrode and third cofferdam of formation the second cavity outer profile and the on the outside of several second electrodes the 4th Cofferdam, and the lateral border in the cofferdam is flushed with the substrate lateral border.

As the further improvement of one embodiment of the utility model, the multi-chip integrating packaging module structure further includes First plastic packaging layer of the side positioned at the package substrate far from the base lower surface, the first plastic packaging layer coat institute simultaneously It states cofferdam and is exposed to outer surface area and the RF switch chip.

As the further improvement of one embodiment of the utility model, the multi-chip integrating packaging module structure further includes Second plastic packaging layer, the second plastic packaging layer fill the gap of the first filter and the first chamber, second filtering Device and the gap of the second chamber and the gap of the amplifier chip and the third chamber, and the second plastic packaging layer covers Cover the base lower surface, first lower surface, second lower surface and the third lower surface, table on described first Face, second upper surface, the third upper surface and the upper surface of base plate flush.

Compared with prior art, the utility model has the beneficial effects that: one embodiment of the utility model utilizes encapsulation In same package substrate, the highly integrated of multi-chip may be implemented in multiple and different chip packages by technology, improves package substrate Utilization rate, and then realize multi-chip integrating packaging module structure miniaturization；In addition, filter chip, amplifier chip and RF switch chip is in distribution up and down, RF switch chip above package substrate and the space for being not take up package substrate, can be with The utilization rate of package substrate is further increased, and the spacing between RF switch chip and filter chip, amplifier chip becomes smaller, The interconnection being easy to implement between filter chip, amplifier chip and RF switch chip simplifies interconnection structure；Moreover, filter Chip and amplifier chip, which embed, to be set in several chambers, so that multi-chip integrating packaging module structure is more frivolous.

Detailed description of the invention

Fig. 1 is the exemplary RF front-end module of the utility model one；

Fig. 2 is another exemplary RF front-end module of the utility model；

Fig. 3 is the cross-sectional view of the multi-chip integrating packaging module structure of one embodiment of the utility model；

Fig. 4 be the cofferdam of the upper surface of base plate of one embodiment of the utility model, electrode, cavity, through-hole, between fluting Cooperate schematic top plan view；

The step of Fig. 5 is the production method of the multi-chip integrating packaging module structure of one embodiment of the utility model figure；

Fig. 6 a to Fig. 6 z-14 is the production method of the multi-chip integrating packaging module structure of one embodiment of the utility model Flow chart.

Specific embodiment

The utility model is described in detail below with reference to specific embodiment shown in the drawings.But these embodiment party Formula is not intended to limit the utility model, structure that those skilled in the art are made according to these embodiments, method or Transformation functionally is all contained in the protection scope of the utility model.

In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.

In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty Between relevant description language.

Join Fig. 1 and Fig. 2, one embodiment of the utility model provides a kind of general RF front-end module, radio-frequency front-end mould Block can be used in the mobile devices such as mobile phone, computer either other electronic equipments.

In conjunction with Fig. 1, in one example, RF front-end module includes (the Power Amplifier of power amplifier module 200 Module, PAM), power amplifier module 200 includes the first amplifier unit 201 being successively electrically connected, the first RF switch list Member 202 and the first RF filter cell 203, the first amplifier unit 201 are multi-mode-wide bandwidth Power Amplifier Unit.

In practical operation, the first amplifier unit 201 is used to receive the modulated signal of other component output, puts through overpower Greatly after the modulation, amplification of device module 200 and filtering operation, exported by filter cell 203.

In conjunction with Fig. 2, in another example, RF front-end module includes receiving 300 (Receive of diversity module Diversity Module, RDM), receiving diversity module 300 includes the low noise amplification multiplexer 301 being successively electrically connected (LNA Multiplexer Module, LMM), the 2nd RF filter cell 302 and RF duplexer unit 303, wherein low noise It includes the second amplifier unit 3011 and the 2nd RF switch unit 3012 being electrically connected, the second amplification that sound, which amplifies multiplexer 301, Device unit 3011 is multi-mode-wide bandwidth low-noise amplifier unit, and the both ends of the 2nd RF switch unit 3012 are separately connected Second amplifier unit 3011 and the 2nd RF filter cell 302.

In practical operation, signal divides by notch diplexer 304 to be believed here with high frequency for high-frequency signal and low frequency signal For number, high-frequency signal enters RF duplexer unit 303, then successively passes through the 2nd RF filter cell 302 and low noise It is exported after amplifying the filtering, modulation, amplifying operation of multiplexer 301 by the second amplifier unit 3011.

It should be understood that the electrical property between each units such as above-mentioned RF switch unit, filter cell, amplifier unit connects Connecing can be realized by packaging technology, i.e., RF switch chip, amplifier chip, filter chip etc. are packaged together and realize Various functions.

Present embodiment is said by taking RF switch chip, amplifier chip, the encapsulating structure of filter chip, technique as an example It is bright.

Join Fig. 3, is the multi-chip integration packaging mould with chamber and filter chip of one embodiment of the utility model The cross-sectional view of block structure 100.

Multi-chip integrating packaging module structure 100 includes package substrate 10, an at least filter chip (20,30), at least One amplifier chip 40, RF switch chip 50 and several interconnection structures 60.

Package substrate 10 has several chambers (101,102,103).

Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin Circuit board is also possible to glass substrate or ceramic substrate etc..

Chamber (101,102,103) can be the through hole through package substrate 10, and but not limited to this.

An at least filter chip (20,30) and at least an amplifier chip 40 be respectively arranged at several chambers (101, 102,103) in.

Here, filter chip (20,30) can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this.

RF switch chip 50 is set to the top of package substrate 10.

Several interconnection structures 60 are for being connected filter chip (20,30), amplifier chip 40 and RF switch chip 50.

Present embodiment utilizes encapsulation technology that multiple and different chip packages in same package substrate 10, may be implemented more Highly integrated, the utilization rate of raising package substrate 10 of chip, and then realize the small-sized of multi-chip integrating packaging module structure 100 Change.

In addition, filter chip (20,30), amplifier chip 40 and RF switch chip 50 are located at encapsulation in distribution up and down The RF switch chip 50 of 10 top of substrate and the space for being not take up package substrate 10, can be further improved the benefit of package substrate 10 With rate, and the spacing between RF switch chip 50 and filter chip (20,30), amplifier chip 40 becomes smaller, and is easy to implement filter Interconnection between wave device chip (20,30), amplifier chip 40 and RF switch chip 50 simplifies interconnection structure.

Moreover, filter chip (20,30) and amplifier chip 40 embed and are set to several chambers (101,102,103) In, so that multi-chip integrating packaging module structure 100 is more frivolous.

It should be noted that the multi-chip integrating packaging module structure 100 of present embodiment is with two filter chips (20,30), an amplifier chip 40 and a RF switch chip 50 are loaded into for package substrate 10, it is possible to understand that, In practice, referring to Figure 1 and Figure 2, it may include multiple filter chips (20,30), multiple amplifier chips 40 and multiple RF switch chip 50, (including up and down all around three-dimensional) can be electrically connected for example, around filter chip (20,30) There are multiple amplifier chips 40 etc..

In the present embodiment, package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, and Package substrate 10 has first chamber 101, second chamber 102 and the third chamber 103 being spaced apart.

Encapsulating structure 100 includes the first filter chip 20 positioned at first chamber 101, the positioned at second chamber 102 Two filter chips 30 and amplifier chip 40 positioned at third chamber 103.

Certainly, in other embodiments, the chamber quantity of package substrate 10 is not limited with above three, in a chamber Number of chips is not also limited with above three, moreover, the type of chip is not also amplified with above-mentioned two filter chip and one Device chip is limited, can according to the actual situation depending on.

First filter chip 20 has the first upper surface 21 and the first lower surface 22 being oppositely arranged, the first upper surface 21 With upper surface of base plate 11 be located at it is ipsilateral, and the first upper surface 21 have several first electrodes 211.

Here, first electrode 211 protrudes out the first upper surface 21 towards far from the direction of the first lower surface 22, but not as Limit.

Second filter chip 30 has the second upper surface 31 and the second lower surface 32 being oppositely arranged, the second upper surface 31 With upper surface of base plate 11 be located at it is ipsilateral, and the second upper surface 31 have several second electrodes 311.

Here, second electrode 311 protrudes out the second upper surface 31 towards far from the direction of the second lower surface 32, but not as Limit.

Amplifier chip 40 has the third upper surface 41 and third lower surface 42 being oppositely arranged, third upper surface 41 and base Plate upper surface 11 be located at it is ipsilateral, and third upper surface 41 have several third electrodes 411.

Here, third electrode 411 protrudes out third upper surface 41 towards far from the direction of third lower surface 42, but not as Limit.

RF switch chip 50 has the 4th upper surface 51 and the 4th lower surface 52 being oppositely arranged, the 4th lower surface 52 and base Plate upper surface 11 is arranged face-to-face, and the 4th lower surface 52 has several 4th electrodes 521.

Here, the 4th electrode 521 protrudes out the 4th lower surface 52 towards far from the direction of the 4th upper surface 51, but not as Limit.

Several interconnection structures 60 are for being connected several first electrodes 211, several second electrodes 311, several third electrodes 411 And several 4th electrodes 521.

Here, " several interconnection structures 60 are for being connected several first electrodes 211, several second electrodes 311, several thirds Electrode 411 and several 4th electrodes 521 ", which refer to can according to need, realizes first filter chip 20, second filter chip 30, the interconnection between amplifier chip 40 and RF switch chip 50, for example, can be according to RF front-end module in Fig. 1, Fig. 2 Specific structure is come the interconnected relationship that is laid out in multi-chip integrating packaging module structure 100.

In the present embodiment, RF switch chip 50 is located at first chamber 101, second chamber 102, third chamber 103 Top, several first electrodes 211, several second electrodes 311 and several third electrodes 411 are located at ipsilateral, several 4th electrodes 521 It is arranged face-to-face with several first electrodes 211, several second electrodes 311, several third electrodes 411.

RF switch chip 50 simultaneously with first filter chip 20, second filter chip 30, about 40 amplifier chip It is correspondingly arranged, in this way, RF switch chip 50 will not excessively occupy the sky of 10 horizontal direction of package substrate in the horizontal direction Between, the size of package substrate 10 can be done small.

Here, the size of RF switch chip 50 is greater than first filter chip 20, second filter chip 30, amplifier core The size of any one chip in piece 40, and RF switch chip 50 and first chamber 101, second chamber 102, third chamber 103 It partly overlaps.

That is, the outer profile of RF switch chip 50 is in the upright projection covering part first chamber on package substrate 10 101, second chamber 102, third chamber 103 are covered here with first chamber 101, second chamber 102 and part is completely covered For third chamber 103.

It should be noted that 50 size of RF switch chip is larger, RF switch chip 50 is set to the upper of package substrate 10 Side, on the one hand, it is not take up the space of package substrate 10 itself, on the other hand, such as corresponds to the product of Fig. 1, it can be real simultaneously Interconnection between existing first RF switch unit 202 and several first RF filter cells 203, the first amplifier unit 201, structure It is simple and compact.

In the present embodiment, the side of package substrate 10 has several external pins 121, and interconnection structure 60 is for being connected Several first electrodes 211, several second electrodes 311, several third electrodes 411, several 4th electrodes 521 and several external pins 121。

External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., the integrated envelope of multi-chip Die-filling block structure 100 can be electrically connected by external pin 121 with realizations such as other chips or substrates, here, external pin 121 by taking ball grid array 121 as an example, and external pin 121 protrudes out the lower surface of multi-chip integrating packaging module structure 100.

In addition, but not limited to this, outside here by taking several external pins 121 are located at the side of base lower surface 12 as an example Portion's pin 121 may be alternatively located at other regions.

Package substrate 10 have several through-holes 13, if interconnection structure 60 by through-hole 13 be connected several first electrodes 211, Dry second electrode 311, several third electrodes 411, several 4th electrodes 521 and several external pins 121.

In the present embodiment, through-hole 13 is between adjacent chamber, in this way, interconnection structure 60 and several first electrodes 211, several second electrodes 311, several third electrodes 411, the spacing between several 4th electrodes 521 can greatly reduce, thus Electrical transmission performance is improved, and can assist realizing the miniaturization of multi-chip integrating packaging module structure 100.

In the present embodiment, interconnection structure 60 includes metal column 61, scolding tin 62 and electroplated layer structure 63.

Metal column 61 is connected to the lower section of the 4th electrode 521, and first electrode 211, second electrode is connected in electroplated layer structure 63 311 and third electrode 411, and external pin is connected by the lower section that through-hole 13 extends to package substrate 10 in electroplated layer structure 63 121, scolding tin 62 is for being connected metal column 61 and electroplated layer structure 63.

Specifically, electroplated layer structure 63 includes the upper rewiring layer 631, intermediate wiring layer 632 and lower heavy cloth of mutual conduction Line layer 633.

Upper rewiring layer 631 is located at the top of package substrate 10 and first electrode 211, second electrode 311, third electricity is connected Pole 411 and scolding tin 62.

Lower rewiring layer 633 is located at the lower section of package substrate 10 and external pin 121 is connected.

Intermediate wiring layer 632 includes the first electroplated layer 6321 being located at 13 upper end opening of through-hole being connected, is located at through-hole Second electroplated layer 6322 of 13 inner walls and the third electroplated layer 6323 below base lower surface 12.

It should be noted that " the third electroplated layer 6323 positioned at 12 lower section of base lower surface " can refer to third electroplated layer 6323 directly contact base lower surface 12, and may also mean that between third electroplated layer 6323 and base lower surface 12 has other knots Structure.

Layer 631 is rerouted in the connection of first electroplated layer 6321, the connection of third electroplated layer 6323 is lower to reroute layer 633.

Here, 6321 essence of the first electroplated layer that layer 631 is rerouted in connection is to close the plane of 13 upper end opening of through-hole Electroplated layer, and the first electroplated layer 6321 protrudes out upper surface of base plate 11.

So, on the one hand, the first electroplated layer 6321 and the upper contact area rerouted between layer 631 can be increased, improved Electrical transmission performance between the two and combine strong degree；On the other hand, third electroplated layer 6323 prolongs along base lower surface 12 It stretches, cooperates lower rewiring layer 633, the layout freedom of the external pin 121 positioned at 12 side of base lower surface can be improved, into The outer shifting of one step accessory external pin 121, convenient for arranging other chip buried spaces in advance, consequently facilitating realize high-performance and The multi-chip 2.5D or 3D of small size stack integration packaging and mould group.

Here, multi-chip integrating packaging module structure 100 includes the first insulating layer 71 and second insulating layer 72.

First insulating layer 71 is located at third electroplated layer 6323 and base lower surface 12, the first lower surface 22, the second lower surface 32,42 lower section of third lower surface, and the first insulating layer 71 fills through-hole 13.

Here, the first insulating layer 71 is filled in the second side of the electroplated layer 6322 far from 13 inner wall of through-hole.

It should be noted that " the first insulating layer 71 is located at third electroplated layer 6323 and base lower surface 12, the first lower surface 22, the second lower surface 32, the lower section of third lower surface 42 " can refer to the first insulating layer 71 directly contact third electroplated layer 6323 and Base lower surface 12, the first lower surface 22, the second lower surface 32, third lower surface 42, alternatively, the first insulating layer 71 and third electricity Coating 6323 and base lower surface 12, the first lower surface 22, the second lower surface 32, there is also other knots between third lower surface 42 Structure.

The lower layer 633 that reroutes is by the hole conducting third electroplated layer 6323 on the first insulating layer 71 and past first insulating layer 71 lower surface direction extends, and the connection of external pin 121 is lower to reroute layer 633, and second insulating layer 72 coats the first insulating layer 71 And lower rewiring layer 633, and the exposure external pin 121 of second insulating layer 72.

Encapsulating structure further includes third insulating layer 73 and the 4th insulating layer 81.

Third insulating layer 73 is located at upper surface of base plate 11, the first upper surface 21, second upper surface 31, third upper surface 41 Top, the upper layer 631 that reroutes is by hole conducting the first electroplated layer 6321, first electrode 211, second on third insulating layer 73 Electrode 311 and third electrode 411, the 4th insulating layer 81 connect third insulating layer 73 and the 4th lower surface 52, the 4th insulating layer 81 With exposing upper rewiring layer 631 and accommodate the fluting 811 of scolding tin 62.

Wherein, metal column 61 is copper post, and upper rewiring layer 631, intermediate wiring layer 632 and lower rewiring layer 633 are copper Layer.

Present embodiment realizes first electrode 211, second electrode 311, third using succinct rewiring (RDL) scheme Electric connection between electrode 411, the 4th electrode 521 and external pin 121, process stabilizing and high reliablity.

The metal line materials of rewiring are that copper is (i.e. upper to reroute layer 631, intermediate wiring layer 632 and lower rewiring layer 633 For layers of copper), rerouting can set between copper and chip electrode (including first electrode 211, second electrode 311, third electrode 411) The metal or alloy film that enhancing reroutes copper and chip electrode is attached to each other power is set, which can be Nickel, titanium, nickel chromium triangle, titanium tungsten etc..

The first insulating layer 71, second is folded between package substrate 10, upper rewiring layer 631 and lower rewiring layer 633 absolutely Edge layer 72 and third insulating layer 73, to realize the electrical isolation between all parts.

It should be understood that the upper rewiring layer 631 in rewiring scheme is not limited with above-mentioned one layer, lower rewiring layer 633 are not also limited with above-mentioned one layer, can according to the actual situation depending on.

In addition, present embodiment setting copper post 61 and the advantage of scolding tin 62 are: (1) scolding tin 62 is in reflow soldering process Molten condition convenient for being combined with copper post 61, and combines effect preferable；(2) scolding tin 62 and the upper contact surface rerouted between layer 631 Product is big, and electrical transmission performance can be improved, and the strong degree that scolding tin 62 is combined with upper rewiring layer 631 also can be improved；(3) copper post 51 A part of space has been already taken up, the raw material usage amount of scolding tin 62 can be reduced when scolding tin 62 is set at this time, reduces scolding tin 62 Welding procedure difficulty, shorten weld interval, and then improve welding production capacity；(4) 61 appearance of copper post is significant, can be used as knowledge It is detected and possible defect recognition with improving recognition efficiency convenient for automatic aspect in other portion.

In the present embodiment, third insulating layer 73 and the 4th insulating layer 81 cooperatively form cofferdam 90, cofferdam 90 and the 4th Lower surface 52 and the first upper surface 21 cooperate and enclose to set to form the first cavity S1, and on cofferdam 90 and the 4th lower surface 52 and second Surface 31 cooperates and encloses and set to form the second cavity S2.

Here, first filter chip 20,30 surface of second filter chip active region (Active Zone) need It could be worked normally under the contact of no foreign object or coverage condition, that is to say, that need to filter in first filter chip 20, second The top of wave device chip 30 forms a cavity to protect the active region, at this point, first cavity S1, the second cavity S2 are right respectively Answer the active region of first filter chip 20,30 surface of second filter chip.

Present embodiment forms the first cavity S1, the second cavity S2 by setting cofferdam 90, it is possible to prevente effectively from encapsulating During structure fabrication or in encapsulating structure use process external substance enter inside the first cavity S1, the second cavity S2 and The normal use for influencing first filter chip 20, second filter chip 30, to improve multi-chip integrating packaging module knot The overall performance of structure 100.

Cofferdam 90 include positioned at 211 inside of several first electrodes and formed the first cavity S1 outer profile the first cofferdam 91, Positioned at second cofferdam 92 in several 211 outsides of first electrode, outside several 311 insides of second electrodes and the second cavity S2 of formation The third cofferdam 93 of profile and the 4th cofferdam 94 on the outside of several second electrodes 311, and the lateral border in cofferdam 90 and encapsulation 10 lateral border of substrate flushes.

Here, it since cofferdam 90 has certain height, when the lower surface area when cofferdam 90 is too small, may can not prop up Support the cofferdam 90 of the height, collapsing phenomenon occur so as to cause cofferdam 90, the cofferdam 90 of present embodiment have it is sufficiently large under Surface improves the stability in entire cofferdam 90；In addition, 90 lower surface of cofferdam can be filtered with first filter chip 20, second 30 upper surface of wave device chip removes the first cavity S1, the second cavity S2, first electrode 211, table on other outside second electrode 311 Face whole region combines, and further improves the forming stability of the first cavity S1, the second cavity S2.

It is cofferdam, the electrode, cavity, through-hole, fluting of the upper surface of base plate of one embodiment of the utility model in conjunction with Fig. 4 Between cooperation schematic top plan view have been left out part-structure (such as RF switch chip 50, plastic packaging layer etc. for ease of description Deng.

There are first chamber 101, second chamber 102 and third chamber 103, several first electrodes 211 on package substrate 10 In array distribution in the first upper surface 21 of the first filter chip 20 for being located at first chamber 101, and adjacent first electrode 211 Between there is interval, the first cofferdam 91 is located at the inside of first electrode 211, and around the setting of the periphery of the first cavity S1, second Cofferdam 92 is located at the outside of first electrode 211, and several second electrodes 311 are in array distribution in positioned at the second of second chamber 102 Second upper surface 31 of filter chip 30, and there is interval between adjacent second electrode 311, third cofferdam 93 is located at the second electricity The inside of pole 311, and be arranged around the periphery of the second cavity S2, the 4th cofferdam 94 is located at the outside of second electrode 311.

Here, the intermediate region adjacent in the first cavity S1 and the second cavity S2,92 essence of the second cofferdam and the 4th cofferdam 94 are connected, that is to say, that substantive not bounded between the first cofferdam 91, the second cofferdam 92, third cofferdam 93 and the 4th cofferdam 94 Limit, but continuous structure.

In addition, the lateral border in cofferdam 90 is flushed with the lateral border of package substrate 10.

Certainly, since package substrate 10 is quadrilateral structure, lateral border further include package substrate 10 front side lateral margin and after Side lateral margin, cofferdam 90 can also extend to front side lateral margin and rear side lateral margin together, and but not limited to this, and package substrate 10 is also possible to The structure of other shapes.

It should be noted that by taking the first cofferdam 91 and the second cofferdam 92 as an example, between the first cofferdam 91 and the second cofferdam 92 It can be independent from each other, such as the first cofferdam 91 is the first cyclic structure, the first cyclic structure is located at several first electrodes 211 Inside, the second cofferdam 92 is the second cyclic structure, and the second cyclic structure is located at the outside of several first electrodes 211.

Certainly, be also possible between the first cofferdam 91 and the second cofferdam 92 it is interconnected, at this point, the first cofferdam 91 and Between two cofferdam 92 by the 5th cofferdam 95 realize interconnection, the 5th cofferdam 95 between adjacent first electrode 211 either Other regions.

That is, cofferdam 90 at this time is covered with upper surface of base plate 11, the first upper surface 21, the second upper surface 31, third First electrode 211, second electrode 311, third electrode 411, the first cavity S1, the second cavity S2 are removed above upper surface 41 and are led to Other whole regions in 13 region of hole.

Cofferdam 90 is made of the insulating materials of photaesthesia, and but not limited to this.

In the present embodiment, multi-chip integrating packaging module structure 100 further includes being located at package substrate 10 far from substrate First plastic packaging layer 96 of the side of lower surface 12, the first plastic packaging layer 96 coat simultaneously cofferdam 90 be exposed to outer surface area and RF switch chip 50.

That is, the first plastic packaging layer 96 coats open area all around RF switch chip 50 at this time.

First plastic packaging layer 96 can be EMC (Epoxy Molding Compound) plastic packaging layer, due to present embodiment benefit External substance can be stopped to enter the first cavity S1, the second cavity S2 with cofferdam 90, without considering that the first plastic packaging layer 96 whether can The protection zone in the first cavity S1, the second cavity S2 is influenced because of problem of materials, the choosing of 96 material of the first plastic packaging layer It selects range to expand significantly, and then the selection of specific capsulation material can be evaded, plastic packaging making technology window is substantially widened and have Effect reduces cost.

In the present embodiment, multi-chip integrating packaging module structure 100 further includes the second plastic packaging layer 97, the second plastic packaging layer The gap of 97 filling first filters 20 and first chamber S1, the gap of second filter 30 and second chamber S2 and amplifier core The gap of piece 40 and third chamber S3, and the second plastic packaging layer 97 covers base lower surface 12, the first lower surface 22, the second lower surface 32 and third lower surface 42, the first upper surface 21, the second upper surface 31, third upper surface 41 and upper surface of base plate 11 flush.

That is, 6323 essence of third electroplated layer is to be located at the lower section of the second plastic packaging layer 97, and the first insulating layer 71 is real For matter also in the lower section of the second plastic packaging layer 97, other explanations of the second plastic packaging layer 97 can saying with reference to the first plastic packaging layer 96 Bright, details are not described herein.

Here, pass through the setting of the second plastic packaging layer 97, on the one hand, the filtering of first filter chip 20, second can be compensated Difference in thickness between device chip 30, amplifier chip 40 and package substrate 10, to realize table on the first upper surface 21, second Face 31, third upper surface 41 and upper surface of base plate 11 flush, in order to structures such as subsequent first insulating layer 71, third insulating layers 73 Molding；On the other hand, the second plastic packaging layer 97 can play protection first filter chip 20, second filter chip 30, put The effect of big device chip 40 and the relative position between fixed each chip and corresponding chamber.

One embodiment of the utility model also provides a kind of production method of multi-chip integrating packaging module structure 100, knot Close aforementioned multi-chip integrating packaging module structure 100 explanation and Fig. 5, Fig. 6 a to Fig. 6 z-14, production method comprising steps of

S1: ginseng Fig. 6 a provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；

S2: ginseng Fig. 6 b, in forming several chambers (101,102,103) on package substrate 10；

S3: ginseng Fig. 6 c to Fig. 6 i, an at least filter chip (20,30) and an at least amplifier chip 40 are provided, and will Filter chip (20,30) and amplifier chip 40 are loaded respectively to several chambers (101,102,103)；

Step S2, S3 is specifically included:

Join Fig. 6 b, in forming the first chamber 101, second chamber 102 and third chamber being spaced apart on package substrate 10 103；

Join Fig. 6 c, first filter chip 20 is provided, first filter chip 20 has the first upper surface being oppositely arranged 21 and first lower surface 22, the first upper surface 21 there are several first electrodes 211；

Join Fig. 6 d, second filter chip 30 is provided, second filter chip 30 has the second upper surface being oppositely arranged 31 and second lower surface 32, the second upper surface 31 there are several second electrodes 311；

Join Fig. 6 e, amplifier chip 40 is provided, amplifier chip 40 has the third upper surface 41 being oppositely arranged and third Lower surface 42, third upper surface 41 have several third electrodes 411；

Join Fig. 6 f, an interim jointing plate 98 is provided, the upper surface of base plate 11 of package substrate 10 is fitted in into interim jointing plate 98；

Join Fig. 6 g, first filter chip 20, second filter chip 30 and amplifier chip 40 are loaded into the respectively One chamber 101, second chamber 102 and third chamber 103, the first upper surface 21, the second upper surface 31 and third upper surface 41 are pasted Invest interim jointing plate 98；

Join Fig. 6 h, formed cladding first filter chip 20 and the gap of first chamber 101, second filter chip 30 with The gap of second chamber 102, the gap of amplifier chip 40 and third chamber 103, base lower surface 12, the first lower surface 22, Second plastic packaging layer 97 of the second lower surface 32 and third lower surface 42；

Join Fig. 6 i, removes interim jointing plate 98.

S4: ginseng Fig. 6 j to Fig. 6 z-14 provides RF switch chip 50, RF switch chip 50 is loaded into package substrate 10 Top, and form the interconnection structure 60 of conducting filter chip (20,30), amplifier chip 40 and RF switch chip 50.

Step S4 is specifically included:

Join Fig. 6 j, is formed above upper surface of base plate 11, the first upper surface 21, the second upper surface 31, third upper surface 41 Third insulating layer 73；

Join Fig. 6 k to Fig. 6 o, is formed in the top of third insulating layer 73 by the hole conducting first on third insulating layer 73 The upper rewiring layer 631 of electrode 211, second electrode 311 and third electrode 411.

It is specific as follows:

Join Fig. 6 k, forms third hole 731 in 73 exposure and imaging of third insulating layer, third hole 731 exposes first Electrode 211, second electrode 311, third electrode 411 and the region for corresponding to the first cavity S1, the second cavity S2；

Join Fig. 6 l, forms the second photoresist layer 82 in the top of third insulating layer 73；

Join Fig. 6 m, forms the second aperture 821 in 82 exposure and imaging of the second photoresist layer, the second aperture 821 exposes the One electrode 211, second electrode 311, third electrode 411 and third insulating layer 73；

Join Fig. 6 n, reroutes layer 631 in being formed in the second aperture 821；

Join Fig. 6 o, removes the second photoresist layer 82.

Join Fig. 6 p to Fig. 6 q, forms covering third insulating layer 73 and upper the 4th insulating layer 81 for rerouting layer 631, the 4th absolutely Edge layer 81 has the fluting 811 for exposing and rerouting layer 631, and third insulating layer 73 and the 4th insulating layer 81 cooperatively form cofferdam 90, if cofferdam 90 includes on the inside of several first electrodes 211 and forming the first cofferdam 91 of the first cavity S1 outer profile, being located at Second cofferdam 92 in dry 211 outside of first electrode positioned at several 311 insides of second electrodes and forms the second cavity S2 outer profile Third cofferdam 93 and positioned at the 4th cofferdam 94 in 311 outside of several second electrodes, the first cavity S1 be located at the first upper surface 21 and Positioned at the inside of several first electrodes 211, the second cavity S2 is located at the second upper surface 31 and is located at the interior of several second electrodes 311 Side；

It is specific as follows:

Join Fig. 6 p, forms the 4th insulating layer 81 in third insulating layer 73 and the upper top for rerouting layer 631；

Join Fig. 6 q, forms the first aperture 812 in 81 exposure development of the 4th insulating layer, the first aperture 812 exposes the first chamber Room S1, second chamber S2 and fluting 811, fluting 811, which exposes, reroutes layer 631.

It should be noted that cofferdam 90 may include the first cofferdam of connection by taking the first cofferdam 91 and the second cofferdam 92 as an example 91 and second cofferdam 92 the 5th cofferdam 95, that is to say, that cofferdam 90 at this time is covered with upper surface of base plate 11, the first upper surface 21, the second upper surface 31, first electrode 211, second electrode 311, third electrode 411, first are removed above third upper surface 41 Cavity S1, the second region cavity S2 other whole regions.

In addition, formed since independent package substrate 10 can be divided by the large substrates of wafer scale, it, can when forming cofferdam 90 With the multiple cofferdam 90 of straight forming on large substrates, the segmentation of large substrates is then carried out again and obtains the list with single cofferdam 90 A package substrate 10, in this way, being greatly improved packaging efficiency, certainly, cofferdam 90 is also plastic on RF switch chip 50.

Join Fig. 6 r, RF switch chip 50 is provided, RF switch chip 50 includes the 4th upper surface 51 and the 4th being oppositely arranged Lower surface 52, the 4th lower surface 52 have several 4th electrodes 521；

Join Fig. 6 s to Fig. 6 w, sequentially forms UBM layer 64 and metal column 61 in the lower section of the 4th electrode 521；

It is specific as follows:

Join Fig. 6 s, forms UBM layer 64 in the 4th lower surface 52；

Join Fig. 6 t, forms third photoresist layer 83 below UBM layer 64；

Join Fig. 6 u, forms third aperture 831 in 83 exposure and imaging of third photoresist layer；

Join Fig. 6 v, in formation metal column 61 in third aperture 831；

Join Fig. 6 w, remove third photoresist layer 83 and is exposed to outer UBM layer 64.

Join Fig. 6 x, in setting scolding tin 62 in fluting 811；

Join Fig. 6 y, RF switch chip 50 is loaded into the top of package substrate 10, the 4th lower surface 52 and upper surface of base plate 11 settings face-to-face, the first cofferdam 91 and the 4th lower surface 52, the first upper surface 21 cooperate and enclose and set to form the first cavity S1, third cofferdam 93 and the 4th lower surface 52, the second upper surface 31 cooperate and enclose to set to form the second cavity S2, metal column 61 Alignment fluting 811, scolding tin 62 and 61 mutual conduction of metal column；

Join Fig. 6 z, forms the first plastic packaging layer 96, the first plastic packaging layer far from the side of base lower surface 12 in package substrate 10 96 coat cofferdam 90 simultaneously is exposed to outer surface area and RF switch chip 50；

Join Fig. 6 z-1, in forming through-hole 13 on encapsulation base 10, through-hole 13 is through the second plastic packaging layer 96, package substrate 10 and the One insulating layer 71, and through-hole 13 exposes and reroutes layer 631；

Join Fig. 6 z-2 to Fig. 6 z-5, form intermediate wiring layer 632, intermediate wiring layer 632 is located at through-hole 13 including what is be connected The first electroplated layer 6321 at upper end opening, positioned at 13 inner wall of through-hole the second electroplated layer 6322 and be located under the second plastic packaging layer 97 The third electroplated layer 6323 of side, the first electroplated layer 6321 are connected and reroute layer 631；

It is specific as follows:

Join Fig. 6 z-2, forms the 4th photoresist layer 84 in the lower section of the second plastic packaging layer 97；

Join Fig. 6 z-3, forms the 4th aperture 841 in 84 exposure and imaging of the 4th photoresist layer, the 4th aperture 841 exposes Through-hole 13 and the second plastic packaging layer 97；

Join Fig. 6 z-4, the wiring layer 632 among being formed in the 4th aperture 841；

Join Fig. 6 z-5, removes the 4th photoresist layer 84.

Join Fig. 6 z-6, forms the first insulating layer 71, the first insulation in the lower section of intermediate wiring layer 632 and the second plastic packaging layer 97 Layer 71 fills through-hole 13；

Join Fig. 6 z-7 to Fig. 6 z-11, is formed in the lower section of the first insulating layer 71 and led by the hole on the first insulating layer 71 Logical third electroplated layer 6323 and the lower rewiring layer 633 extended toward the lower surface direction of the first insulating layer 71；

It is specific as follows:

Join Fig. 6 z-7, forms the first hole 711 in 71 exposure and imaging of the first insulating layer, the first hole 711 exposes the Three electroplated layers 6323；

Join Fig. 6 z-8, forms the 5th photoresist layer 85 in the lower section of the first insulating layer 71；

Join Fig. 6 z-9, forms the 5th aperture 851 in 85 exposure and imaging of the 5th photoresist layer, the 5th aperture 851 exposes First insulating layer 71 and the first hole 711；

Join Fig. 6 z-10, layer 633 is rerouted under being formed in the 5th aperture 851；

Join Fig. 6 z-11, removes the 5th photoresist layer 85.

Join Fig. 6 z-12 and Fig. 6 z-13, form the first insulating layer 71 of cladding and the lower second insulating layer 72 for rerouting layer 633, Second insulating layer 72 exposes lower rewiring layer 633；

It is specific as follows:

Join Fig. 6 z-12, forms second insulating layer 72 in the first insulating layer 71 and the lower lower section for rerouting layer 633；

Join Fig. 6 z-13, the second hole 721 is formed in 72 exposure and imaging of second insulating layer, under the second hole 721 exposes Reroute layer 633.

Join Fig. 6 z-14, forms ball grid array 121 in being exposed to outer lower rewiring layer 633.

Other explanations of the production method of the multi-chip integrating packaging module structure 100 of present embodiment can refer to above-mentioned The explanation of multi-chip integrating packaging module structure 100, details are not described herein.

The cofferdam 90 of the utility model is located at the inside and outside of first electrode 211, and in second electrode 311 Side and outside, and the lateral border in cofferdam 90 is flushed with the lateral border of package substrate 10, in other embodiments, cofferdam 90 can also Positioned at the inside of first electrode 211 and the inside of second electrode 311, alternatively, the lateral border in cofferdam 90 and RF switch chip 50 Lateral border flushes, or, the lateral border in cofferdam 90 is located at the lateral border of RF switch chip 50 and the lateral border of package substrate 10 Between etc..

To sum up, present embodiment forms the first cavity S1, the second cavity S2 by setting cofferdam 90, it is possible to prevente effectively from In encapsulating structure manufacturing process or external substance enters in the first cavity S1, the second cavity S2 in encapsulating structure use process Portion and the normal use for influencing first filter chip 20, second filter chip 30, to improve multi-chip integration packaging mould The overall performance of block structure 100.

In addition, present embodiment using encapsulation technology by multiple and different chip packages in same package substrate 10, can be with It realizes the highly integrated of multi-chip, improves the utilization rate of package substrate 10, and then realize multi-chip integrating packaging module structure 100 Miniaturization.

It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book With the other embodiments of understanding.

Tool of the series of detailed descriptions listed above only for the feasible embodiment of the utility model Body explanation, they are all without departing from made by the utility model skill spirit not to limit the protection scope of the utility model Equivalent implementations or change should be included within the scope of protection of this utility model.

Claims (11)

1. a kind of multi-chip integrating packaging module structure with chamber and filter chip characterized by comprising

Package substrate, with several chambers；

An at least filter chip and at least an amplifier chip, are respectively arranged in several chambers；

RF switch chip is set to the top of the package substrate；

Several interconnection structures, for filter chip, amplifier chip and RF switch chip to be connected.

2. multi-chip integrating packaging module structure according to claim 1, which is characterized in that the package substrate has phase To the upper surface of base plate and base lower surface of setting, and the package substrate has first chamber, the second chamber being spaced apart And third chamber, the multi-chip integrating packaging module structure include the first filter chip for being located at the first chamber, position Second filter chip in the second chamber and the amplifier chip positioned at the third chamber, the first filter core Piece has the first upper surface and the first lower surface being oppositely arranged, and first upper surface and the upper surface of base plate are located at same Side, and first upper surface has several first electrodes, the second filter chip has table on second be oppositely arranged Face and the second lower surface, second upper surface and the upper surface of base plate be located at it is ipsilateral, and if second upper surface have Dry second electrode, the amplifier chip have the third upper surface and third lower surface being oppositely arranged, the third upper surface It is located at the upper surface of base plate ipsilateral, and the third upper surface has several third electrodes, and the RF switch chip has The 4th upper surface being oppositely arranged and the 4th lower surface, the 4th lower surface are arranged face-to-face with the upper surface of base plate, and 4th lower surface have several 4th electrodes, several interconnection structures for be connected several first electrodes, several second electrodes, Several third electrodes and several 4th electrodes.

3. multi-chip integrating packaging module structure according to claim 2, which is characterized in that the one of the base lower surface Side has several external pins, and the package substrate has several through-holes, if the interconnection structure is connected by the through-hole Dry first electrode, several second electrodes, several third electrodes, several 4th electrodes and several external pins.

4. multi-chip integrating packaging module structure according to claim 3, which is characterized in that the interconnection structure includes gold Belong to column, scolding tin and electroplated layer structure, the metal column is connected to the lower section of the 4th electrode, and institute is connected in the electroplated layer structure State first electrode, the second electrode and the third electrode, and the electroplated layer structure extended to by the through-hole it is described The lower section of package substrate and the external pin is connected, the scolding tin is for being connected the metal column and the electroplated layer structure.

5. multi-chip integrating packaging module structure according to claim 4, which is characterized in that the electroplated layer structure includes The upper rewiring layer of mutual conduction, intermediate wiring layer and lower rewiring layer, the upper rewiring layer are located at the package substrate Simultaneously the first electrode, the second electrode, the third electrode and the scolding tin is connected in top, and the lower rewiring layer is located at Simultaneously the external pin is connected in the lower section of the package substrate, and the intermediate wiring layer includes connected positioned at the through-hole upper end First electroplated layer of opening, the second electroplated layer positioned at the through-hole wall and the third below the base lower surface Electroplated layer, first electroplated layer connect the upper rewiring layer, and the third electroplated layer connects the lower rewiring layer.

6. multi-chip integrating packaging module structure according to claim 5, which is characterized in that the multi-chip integration packaging Modular structure includes the first insulating layer and second insulating layer, and first insulating layer is located at the third electroplated layer and substrate following table Face, the first lower surface, the second lower surface, third lower surface lower section, and first insulating layer fills the through-hole, it is described lower heavy The lower surface of the third electroplated layer and past first insulating layer is connected by the hole on first insulating layer for wiring layer Direction extends, and the external pin connects the lower rewiring layer, and the second insulating layer coats first insulating layer and institute State lower rewiring layer, and the second insulating layer exposure external pin.

7. multi-chip integrating packaging module structure according to claim 5, which is characterized in that the multi-chip integration packaging Modular structure includes third insulating layer and the 4th insulating layer, and the third insulating layer is located at the upper surface of base plate, table on first Face, the second upper surface, third upper surface top, it is described upper to reroute layer institute is connected by the hole on the third insulating layer State the first electroplated layer, the first electrode, the second electrode and the third electrode, the 4th insulating layer connection described the Three insulating layers and the 4th lower surface, the 4th insulating layer, which has, to be exposed the upper rewiring layer and accommodates opening for scolding tin Slot.

8. multi-chip integrating packaging module structure according to claim 7, which is characterized in that the third insulating layer and institute The 4th insulating layer is stated to cooperatively form cofferdam, the cofferdam and the 4th lower surface and first upper surface cooperation and enclose and set shape At the first cavity, and the cofferdam and the 4th lower surface and second upper surface cooperate and enclose and set to form the second cavity.

9. multi-chip integrating packaging module structure according to claim 8, which is characterized in that the cofferdam includes being located at institute State on the inside of several first electrodes and formed the first cofferdam of the first cavity outer profile, the on the outside of several first electrodes Two cofferdam on the inside of several second electrodes and form the third cofferdam of the second cavity outer profile and are located at several second electricity The 4th cofferdam on the outside of pole, and the lateral border in the cofferdam is flushed with the substrate lateral border.

10. multi-chip integrating packaging module structure according to claim 9, which is characterized in that the integrated envelope of the multi-chip Die-filling block structure further includes the first plastic packaging layer positioned at side of the package substrate far from the base lower surface, and described first Plastic packaging layer coats the cofferdam simultaneously and is exposed to outer surface area and the RF switch chip.

11. multi-chip integrating packaging module structure according to claim 10, which is characterized in that the integrated envelope of the multi-chip Die-filling block structure further includes the second plastic packaging layer, and the second plastic packaging layer is filled between the first filter and the first chamber Gap, the second filter and the gap of the second chamber and the gap of the amplifier chip and the third chamber, and The second plastic packaging layer covers the base lower surface, first lower surface, second lower surface and the third following table Face, first upper surface, second upper surface, the third upper surface and the upper surface of base plate flush.