CN108807350A - The multi-chamber encapsulating structure and preparation method thereof of amplifier chip electrode peripheral hardware - Google Patents
The multi-chamber encapsulating structure and preparation method thereof of amplifier chip electrode peripheral hardware Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Present invention is disclosed a kind of multi-chamber encapsulating structures of amplifier chip electrode peripheral hardware and preparation method thereof, and encapsulating structure includes：Package substrate has the first, second, third chamber being spaced apart；First filter chip is located at first chamber and has first electrode；Second filter chip is located at second chamber and has second electrode；Amplifier chip is located at third chamber and has third electrode；RF switch chips are set to the top of package substrate and have the 4th electrode；First, second, third electrode is located at homonymy, and interconnection structure is for conducting first, second, third and the 4th electrode.Multiple chip packages in same package substrate, are realized the highly integrated of multi-chip by the present invention；Filter, amplifier and RF switch chips are simultaneously not take up substrate space in distribution, RF switch chips up and down, and substrate utilization can be improved, and simplify interconnection structure；Filter chip and amplifier chip are embedded in chamber so that encapsulating structure is more frivolous.
Description
Technical field
The present invention relates to a kind of encapsulation of the multi-chamber of field of semiconductor package more particularly to amplifier chip electrode peripheral hardware to tie
Structure and preparation method thereof.
Background technology
To cater to the increasingly light and short development trend of electronic product, filter is needed with radio-frequency transmissions component, receiving unit
It is highly integrateable in the encapsulating structure of limited areal, forms system in package (SystemInPackage, SIP) structure, with
Reduce the size of hardware system.
Integration technology is encapsulated with RF front-end module for the filter in system-in-package structure, there are still suitable in the industry
More technical problem urgent need to resolve, for example, connection structure, multiple chips between the protection structure of filter, multiple chips
Layout etc..
Invention content
The purpose of the present invention is to provide a kind of multi-chamber encapsulating structure of amplifier chip electrode peripheral hardware and its making sides
Method.
One of for achieving the above object, an embodiment of the present invention provides a kind of the more of amplifier chip electrode peripheral hardware
Chamber encapsulating structure, including：
Package substrate has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has interval
First chamber, second chamber and the third chamber of distribution；
First filter chip, is located at the first chamber, and the first filter chip has first be oppositely arranged
Upper surface and the first lower surface, first upper surface are located at homonymy, and the first upper table mask with the upper surface of base plate
There are several first electrodes；
Second filter chip, is located at the second chamber, and the second filter chip has second be oppositely arranged
Upper surface and the second lower surface, second upper surface are located at homonymy, and the second upper table mask with the upper surface of base plate
There are several second electrodes；
Amplifier chip, is located at the third chamber, the amplifier chip have the third upper surface that is oppositely arranged and
Third lower surface, the third upper surface and the upper surface of base plate are located at homonymy, and the third lower surface is with several the
Three electrodes；
RF switch chips, are set to the top of the package substrate, and the RF switch chips have the 4th be oppositely arranged
Upper surface and the 4th lower surface, the 4th lower surface are arranged face-to-face with the upper surface of base plate, and the 4th lower surface
With several 4th electrodes；
Several interconnection structures, for several first electrodes, several second electrodes, several third electrodes and the several 4th to be connected
Electrode.
As being further improved for an embodiment of the present invention, there are several outsides to draw for the side of the base lower surface
There are several through-holes, the interconnection structure several first electrodes, Ruo Gan is connected by the through-hole for foot, the package substrate
Two electrodes, several third electrodes, several 4th electrodes and several external pins.
As being further improved for an embodiment of the present invention, the interconnection structure includes the first metal column, the second metal
Column, scolding tin and electroplated layer structure, first metal column are connected to the lower section of the 4th electrode, the second metal column connection
In the lower section of the third electrode, the first electrode, the second electrode, and the electroplated layer is connected in the electroplated layer structure
Structure extends to the lower section of the package substrate by the through-hole by second metal column and the external pin is connected, institute
Scolding tin is stated for first metal column and the electroplated layer structure to be connected.
As being further improved for an embodiment of the present invention, the electroplated layer structure includes the intermediate wiring of mutual conduction
Layer and lower rewiring layer, the lower rewiring layer is located at the lower section of the package substrate and the external pin is connected, in described
Between wiring layer include connected the first electroplated layer positioned at the upper surface of base plate, the second electroplated layer positioned at the through-hole wall
And the first electrode, described second is connected in the third electroplated layer below the base lower surface, first electroplated layer
Electrode and the scolding tin, the third electroplated layer connect second metal column and the lower rewiring layer.
As being further improved for an embodiment of the present invention, the encapsulating structure includes the first insulating layer and the second insulation
Layer, first insulating layer are located under the third electroplated layer and base lower surface, the first lower surface, the second lower surface, third
Lower face, and first insulating layer fills the through-hole, the lower layer that reroutes is by the hole on first insulating layer
Hole is connected the third electroplated layer and extends toward the lower surface direction of first insulating layer, and described in external pin connection
Lower rewiring layer, the second insulating layer coat first insulating layer and the lower rewiring layer, and the second insulating layer
The exposure external pin.
As being further improved for an embodiment of the present invention, the encapsulating structure includes third insulating layer and the 4th insulation
Layer, the third insulating layer be located at the upper surface of base plate, the first upper surface, the second upper surface, third upper surface top, institute
It states the first electroplated layer and is connected the first electrode and the second electrode by the hole on the third insulating layer, the described 4th
Insulating layer connects the third insulating layer and the 4th lower surface, and the 4th insulating layer, which has, exposes first plating
Layer and the fluting for accommodating scolding tin.
As being further improved for an embodiment of the present invention, the third insulating layer and the 4th insulating layer coordinate shape
At cofferdam, the encapsulating structure includes the 5th insulating layer positioned at the 4th lower surface, and the cofferdam is insulated with the described 5th
The lower surface and first upper surface of layer coordinate and enclose to set to form the first cavity, and the cofferdam and the 5th insulating layer
Lower surface and second upper surface coordinate and enclose and set to form the second cavity.
As being further improved for an embodiment of the present invention, the cofferdam includes being located on the inside of several first electrodes
And it forms the first cofferdam of the first cavity outer profile, the second cofferdam on the outside of several first electrodes, be located at several the
On the inside of the two electrodes and third cofferdam for forming the second cavity outer profile and the 4th cofferdam on the outside of several second electrodes,
And the lateral border in the cofferdam is flushed with the substrate lateral border.
As being further improved for an embodiment of the present invention, the 5th insulating layer extends under the 4th electrode
Surface, and partly overlap between the 5th insulating layer and first metal column.
As being further improved for an embodiment of the present invention, the encapsulating structure further includes remote positioned at the package substrate
First plastic packaging layer of the side from the base lower surface, the first plastic packaging layer coat simultaneously the cofferdam be exposed to it is outer upper
Surface region and the RF switch chips.
As being further improved for an embodiment of the present invention, the encapsulating structure further includes the second plastic packaging layer, and described
Two plastic packaging layers fill the gap of the first filter and the first chamber, the second filter and the second chamber
Gap and the gap of the amplifier chip and the third chamber, and the second plastic packaging layer covering base lower surface,
First lower surface, second lower surface and the third lower surface, first upper surface, second upper surface,
The third upper surface and the upper surface of base plate flush, and the second plastic packaging layer exposes second metal column.
One of for achieving the above object, an embodiment of the present invention provides a kind of the more of amplifier chip electrode peripheral hardware
The production method of chamber encapsulating structure, including step：
S1：Package substrate is provided, there is the upper surface of base plate and base lower surface being oppositely arranged；
S2：In forming the first chamber being spaced apart, second chamber and third chamber on the package substrate；
S3：First filter chip, second filter chip and amplifier chip, the first filter chip tool are provided
There are the first upper surface and the first lower surface being oppositely arranged, and first upper surface has several first electrodes, described second
Filter chip has the second upper surface and the second lower surface being oppositely arranged, and second upper surface has several second electricity
Pole, the amplifier chip have the third upper surface that is oppositely arranged and third lower surface, and if the third lower surface have
Dry third electrode；
S4：The first filter chip is loaded to the first chamber, first upper surface on the substrate
Surface is located at homonymy, and the second filter chip is loaded to the second chamber, second upper surface on the substrate
Surface is located at homonymy, and the amplifier chip chip is loaded to the third chamber, the third upper surface on the substrate
Surface is located at homonymy；
S5：RF switch chips are provided, the RF switch chips are loaded into the top of the package substrate, the RF switches
Chip has the 4th upper surface and the 4th lower surface being oppositely arranged, and the 4th lower surface and the upper surface of base plate are face-to-face
Setting, and the 4th lower surface has several 4th electrodes, and if formed several first electrodes of conducting, several second electrodes,
The interconnection structure of dry third electrode and several 4th electrodes.
As being further improved for an embodiment of the present invention, step S4 is specifically included：
The second metal column is formed in the lower section of the third electrode；
One interim jointing plate is provided；
The upper surface of base plate of package substrate is fitted in into interim jointing plate；
The first filter chip, second filter chip and amplifier chip are loaded into first chamber respectively
Room, the second chamber and the third chamber, first upper surface, second upper surface and the third upper table face paste
Invest the interim jointing plate；
Form gap, the second filter chip and the institute for coating the first filter chip and the first chamber
It states under the gap of second chamber, the gap of the amplifier chip and the third chamber, the base lower surface, described first
The second plastic packaging layer on surface, second lower surface and the third lower surface, the second plastic packaging layer coat second gold medal
Belong to column；
Remove the interim jointing plate；
The second plastic packaging layer is ground to expose second metal column；
Step S5 is specifically included：
Third insulating layer is formed above the upper surface of base plate, the first upper surface, the second upper surface, third upper surface,
And form several through-holes in the package substrate；
Intermediate wiring layer is formed, the intermediate wiring layer includes that first connected be located above the third insulating layer is electric
Coating, the second electroplated layer positioned at the through-hole wall and the third electroplated layer positioned at the base lower surface, first electricity
The first electrode and the second electrode is connected by the hole on the third insulating layer in coating；
Form the first insulating layer for coating the third electroplated layer and the second plastic packaging layer lower surface, and first insulating layer
Fill the through-hole；
The 4th insulating layer for covering the third insulating layer and first electroplated layer is formed, the 4th insulating layer has
The fluting of first electroplated layer is exposed, the third insulating layer and the 4th insulating layer cooperatively form cofferdam, described to enclose
Weir includes the first cofferdam for being located on the inside of several first electrodes and being formed the first cavity outer profile, is located at several first electrodes
Second cofferdam in outside on the inside of several second electrodes and forms the third cofferdam of the second cavity outer profile and positioned at several the
The 4th cofferdam on the outside of two electrodes, first cavity are located at first upper surface and the inside positioned at several first electrodes,
Second cavity is located at second upper surface and the inside positioned at several second electrodes；
RF switch chips are provided, the RF switch chips include the 4th upper surface and the 4th lower surface being oppositely arranged, institute
Stating the 4th lower surface has several 4th electrodes；
The 5th insulating layer is formed in the lower section of the 4th lower surface, the 5th insulating layer covers several 4th electrodes
Intermediate region, and the 5th insulating layer extends to the lower surface of the 4th electrode, the 5th insulating layer and the described 4th
It partly overlaps between electrode；
The first metal column is formed in the lower section of the 4th electrode, between the 5th insulating layer and first metal column
It partly overlaps；
In scolding tin is arranged in fluting；
The RF switch chips are loaded into the top of the package substrate, the 4th lower surface and the substrate upper table
Face is arranged face-to-face, and lower surface, first upper surface of first cofferdam and the 5th insulating layer cooperate and enclose
If forming first cavity, lower surface of the third cofferdam with the 5th insulating layer, the second upper surface phase interworking
It closes and encloses to set to form second cavity, first metal column is directed at the fluting, the scolding tin and first metal column
Mutual conduction；
The first plastic packaging layer is formed in side of the package substrate far from the base lower surface, the first plastic packaging layer is same
When coat the cofferdam and be exposed to outer surface area and the RF switch chips；
It is formed in the lower section of first insulating layer and the third plating is connected by the hole on first insulating layer
Layer and the lower rewiring layer extended toward the lower surface direction of first insulating layer；
It is formed and coats first insulating layer and the lower second insulating layer for rerouting layer, the second insulating layer exposure
Go out the lower rewiring layer；
It is formed and coats first insulating layer and the lower second insulating layer for rerouting layer, the second insulating layer exposure
Go out the lower rewiring layer；
Ball grid array is formed in being exposed to outer lower rewiring layer.
Compared with prior art, the beneficial effects of the present invention are：An embodiment of the present invention will be more using encapsulation technology
The highly integrated of multi-chip may be implemented in same package substrate in a different chip package, improves the utilization rate of package substrate,
And then realize the miniaturization of encapsulating structure；In addition, filter chip, amplifier chip and RF switch chips are in distribution up and down, position
RF switch chips above package substrate and the space for being not take up package substrate, can further increase the utilization of package substrate
Rate, and the spacing between RF switch chips and filter chip, amplifier chip becomes smaller, and is easy to implement filter chip, amplification
Interconnection between device chip and RF switch chips simplifies interconnection structure；Moreover, filter chip and the embedded setting of amplifier chip
In several chambers so that encapsulating structure is more frivolous.
Description of the drawings
Fig. 1 is an exemplary RF front-end module of the invention；
Fig. 2 is another exemplary RF front-end module of the present invention；
Fig. 3 is the sectional view of the encapsulating structure of an embodiment of the present invention；
Fig. 4 is the cooperation between the cofferdam of the upper surface of base plate of an embodiment of the present invention, electrode, cavity, through-hole, fluting
Schematic top plan view；
The step of Fig. 5 is the production method of the encapsulating structure of an embodiment of the present invention is schemed；
Fig. 6 a to Fig. 6 z-10 are the flow charts of the production method of the encapsulating structure of an embodiment of the present invention.
Specific implementation mode
Below with reference to specific implementation mode shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally
Transformation is included within the scope of protection of the present invention.
In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots
Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.
In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is
A unit as shown in the drawings or feature are described relative to another unit or feature for the purpose convenient for explanation
Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not
Same orientation.For example, if the equipment in figure overturn, it is described as being located at other units or feature " below " or " under "
Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both
Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty
Between relevant description.
Join Fig. 1 and Fig. 2, an embodiment of the present invention provides a kind of general RF front-end module, and RF front-end module can
For in the mobile devices such as mobile phone, computer either other electronic equipments.
In conjunction with Fig. 1, in one example, RF front-end module includes (the Power Amplifier of power amplifier module 200
Module, PAM), power amplifier module 200 includes the first amplifier unit 201 being electrically connected successively, the first RF switch lists
Member 202 and the first RF filter cells 203, the first amplifier unit 201 are the Power Amplifier Unit of multi-mode-wide bandwidth.
In practical operation, the first amplifier unit 201 is used to receive the modulated signal of other component output, is put through overpower
Greatly after the modulation, amplification of device module 200 and filtering operation, exported by filter cell 203.
In conjunction with Fig. 2, in another example, RF front-end module includes receiving 300 (Receive of diversity module
Diversity Module, RDM), it includes the low noise amplification multiplexer 301 being electrically connected successively to receive diversity module 300
(LNA Multiplexer Module, LMM), the 2nd RF filter cells 302 and RF duplexers unit 303, wherein low noise
It includes the second amplifier unit 3011 and the 2nd RF switch units 3012 being electrically connected, the second amplification that sound, which amplifies multiplexer 301,
Device unit 3011 is the low-noise amplifier unit of multi-mode-wide bandwidth, and the both ends of the 2nd RF switch units 3012 are separately connected
Second amplifier unit 3011 and the 2nd RF filter cells 302.
In practical operation, signal divides by notch diplexer 304 to be believed with high frequency here for high-frequency signal and low frequency signal
For number, high-frequency signal enters RF duplexers unit 303, then passes through the 2nd RF filter cells 302 and low noise successively
It is exported by the second amplifier unit 3011 after amplifying the filtering, modulation, amplifieroperation of multiplexer 301.
It should be understood that electrically connecting between each units such as above-mentioned RF switch units, filter cell, amplifier unit
Connecing can be realized by packaging technology, i.e., RF switch chips, amplifier chip, filter chip etc. are packaged together and realize
Various functions.
Present embodiment is said by taking RF switch chips, amplifier chip, the encapsulating structure of filter chip, technique as an example
It is bright.
Join Fig. 3, is the section view of the multi-chamber encapsulating structure 100 of the amplifier chip electrode peripheral hardware of an embodiment of the present invention
Figure.
Encapsulating structure 100 includes package substrate 10, first filter chip 20, second filter chip 30, amplifier core
Piece 40, RF switch chips 50 and several interconnection structures 60.
Between package substrate 10 has the upper surface of base plate 11 being oppositely arranged and base lower surface 12, and package substrate 10 has
Every the first chamber 101, second chamber 102 and third chamber 103 of distribution.
Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin
Circuit board can also be glass substrate or ceramic substrate etc..
First chamber 101, second chamber 102 and third chamber 103 can be through the through hole of package substrate 10, but not
As limit.
First filter chip 20 is located at first chamber 101, and first filter chip 20 has first be oppositely arranged
Upper surface 21 and the first lower surface 22, the first upper surface 21 is located at homonymy with upper surface of base plate 11, and the first upper surface 21 has
Several first electrodes 211.
Here, first electrode 211 protrudes out the first upper surface 21 towards the direction far from the first lower surface 22, but not as
Limit.
Second filter chip 30 is located at second chamber 102, and second filter chip 30 has second be oppositely arranged
Upper surface 31 and the second lower surface 32, the second upper surface 31 is located at homonymy with upper surface of base plate 11, and the second upper surface 31 has
Several second electrodes 311.
Here, second electrode 311 protrudes out the second upper surface 31 towards the direction far from the second lower surface 32, but not as
Limit.
First filter chip 20, second filter chip 30 can be surface acoustic wave filter chip (Surface
Acoustic Wave, SAW) or bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this.
Amplifier chip 40 is located at third chamber 103, amplifier chip 40 have the third upper surface 41 being oppositely arranged and
Third lower surface 42, third upper surface 41 is located at homonymy with upper surface of base plate 11, and third lower surface 42 has several thirds electricity
Pole 421.
Here, third electrode 421 protrudes out third lower surface 42 towards the direction far from third upper surface 41, but not as
Limit.
RF switch chips 50 are set to the top of package substrate 10, and RF switch chips 50 have the 4th upper table being oppositely arranged
Face 51 and the 4th lower surface 52, the 4th lower surface 52 are arranged face-to-face with upper surface of base plate 11, and if the 4th lower surface 52 have
Dry 4th electrode 521.
Here, the 4th electrode 521 protrudes out the 4th lower surface 52 towards the direction far from the 4th upper surface 51, but not as
Limit.
Several interconnection structures 60 are for being connected several first electrodes 211, several second electrodes 311, several third electrodes 421
And several 4th electrodes 521.
Here, " several interconnection structures 60 are for being connected several first electrodes 211, several second electrodes 311, several thirds
Electrode 421 and several 4th electrodes 521 " refer to that can realize first filter chip 20, second filter chip as needed
30, the interconnection between amplifier chip 40 and RF switch chips 50, for example, can be according to RF front-end module in Fig. 1, Fig. 2
Concrete structure is come the interconnected relationship that is laid out in encapsulating structure 100.
Present embodiment utilizes encapsulation technology that multiple and different chip packages in same package substrate 10, may be implemented more
Highly integrated, the utilization rate of raising package substrate 10 of chip, and then realize the miniaturization of encapsulating structure 100.
In addition, first filter chip 20, second filter chip 30, amplifier chip 40 and RF switch chips 50 are presented
Lower distribution, RF switch chips 50 above package substrate 10 and the space for being not take up package substrate 10, can further carry
The utilization rate of high package substrate 10, and RF switch chips 50 and first filter chip 20, second filter chip 30, amplifier
Spacing between chip 40 becomes smaller, be easy to implement first filter chip 20, second filter chip 30, amplifier chip 40 and
Interconnection between RF switch chips 50 simplifies interconnection structure.
Moreover, first filter chip 20, second filter chip 30 and amplifier chip 40 are embedded to be set to the first chamber
In room 101, second chamber 102, third chamber 103 so that encapsulating structure 100 is more frivolous.
It should be noted that the encapsulating structure 100 of present embodiment is with two filter chip (first filter chips
20, second filter chip 30), an amplifier chip 40 and a RF switch chip 50 be loaded into for package substrate 10,
Can include multiple filter chips (20,30), multiple amplifiers with reference to figure 1 and Fig. 2 it should be understood that in practice
Chip 40 and multiple RF switch chips 50, for example, around filter chip (20,30) (including all around three-dimensional side up and down
To) multiple amplifier chips 40 etc. can be electrically connected with.
Certainly, in other embodiments, the chamber quantity of package substrate 10 is not limited with above three, in a chamber
Number of chips is not also limited with above three, moreover, the type of chip is not also amplified with above-mentioned two filter chip and one
Device chip is limited, can be depending on actual conditions.
In the present embodiment, RF switch chips 50 are located at the top of chamber 101, several first electrodes 211, several second
Electrode 311 is located at homonymy, and third electrode 421 is located at the opposite side of first electrode 211, several 4th electrodes 521 and several first
Electrode 211, several second electrodes 311 are arranged face-to-face.
RF switch chips 50 simultaneously with first filter chip 20, second filter chip 30, about 40 amplifier chip
It is correspondingly arranged, in this way, in the horizontal direction, RF switch chips 50 will not excessively occupy the sky of 10 horizontal direction of package substrate
Between, the size of package substrate 10 can be done small.
Here, the size of RF switch chips 50 is more than first filter chip 20, second filter chip 30, amplifier core
The size of any one chip in piece 40, and RF switch chips 50 and first chamber 101, second chamber 102, third chamber 103
It partly overlaps.
That is, the outer profile of RF switch chips 50 is in the upright projection covering part first chamber on package substrate 10
101, second chamber 102, third chamber 103 are covered so that first chamber 101, second chamber 102 and part is completely covered here
For third chamber 103.
It should be noted that 50 size of RF switch chips is larger, RF switch chips 50 are set to the upper of package substrate 10
Side, on the one hand, it is not take up the space of of package substrate 10 itself, on the other hand, such as corresponds to the product of Fig. 1, it can be real simultaneously
Existing interconnection between first RF switch units 202 and several first RF filter cells 203, the first amplifier unit 201, structure
It is simple and compact.
In the present embodiment, the side of package substrate 10 has several external pins 121, and interconnection structure 60 is for being connected
Several first electrodes 211, several second electrodes 311, several third electrodes 421, several 4th electrodes 521 and several external pins
121。
External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., and encapsulating structure 100 is logical
Crossing external pin 121 can be electrically connected with realizations such as other chips or substrates, and here, external pin 121 is with ball grid array 121
For, external pin 121 protrudes out the lower surface of encapsulating structure 100.
In addition, here by taking several external pins 121 are located at the side of base lower surface 12 as an example, but not limited to this, outside
Portion's pin 121 may be alternatively located at other regions.
Package substrate 10 have several through-holes 13, if interconnection structure 60 by through-hole 13 be connected several first electrodes 211,
Dry second electrode 311, several third electrodes 421, several 4th electrodes 521 and several external pins 121.
In the present embodiment, through-hole 13 is between adjacent chamber, in this way, interconnection structure 60 and several first electrodes
211, the spacing between several second electrodes 311, several third electrodes 421, several 4th electrodes 521 can greatly reduce, to
Electrical transmission performance is improved, and can assist realizing the miniaturization of encapsulating structure 100.
In the present embodiment, interconnection structure 60 includes the first metal column 611, the second metal column 612, scolding tin 62 and plating
Layer structure 63.
First metal column 611 is connected to the lower section of the 4th electrode 521, and the second metal column 612 is connected to third electrode 421
Lower section, first electrode 211, second electrode 311 is connected in electroplated layer structure 63, and electroplated layer structure 63 extends to envelope by through-hole 13
It fills the lower section of substrate 10 and the second metal column 612 and external pin 121 is connected, scolding tin 62 is for being connected the first metal column 61 and electricity
Coating structure 63.
Specifically, electroplated layer structure 63 includes the intermediate wiring layer 632 and lower rewiring layer 633 of mutual conduction.
Lower rewiring layer 633 is located at the lower section of package substrate 10 and external pin 121 is connected.
Intermediate wiring layer 632 is including being connected positioned at the first electroplated layer 6321 of upper surface of base plate 11, in through-hole 13
Second electroplated layer 6322 of wall and the third electroplated layer 6323 below base lower surface 12.
It should be noted that " the third electroplated layer 6323 for being located at 12 lower section of base lower surface " can refer to third electroplated layer
6323 are in direct contact base lower surface 12, may also mean that there are other knots between third electroplated layer 6323 and base lower surface 12
Structure.
First electrode 211, second electrode 311 and scolding tin 62 is connected in first electroplated layer 6321, and third electroplated layer 6323 connects
Second metal column 612 and lower rewiring layer 633.
That is, the first electroplated layer 6321 extends towards upper surface of base plate 11 and first electrode 211 and the is connected at this time
Two electrodes 311, third electroplated layer 6323 extend towards base lower surface 12 and the second metal column 612 are connected.
Here, on the one hand, upper surface of base plate 11 and base lower surface 12 are both provided with electroplated layer, can improve electroplated layer with
The strong degree that package substrate 10 combines；On the other hand, the first electroplated layer 6321 is towards the side of first electrode 211, second electrode 311
Realize the conducting of first electrode 211, second electrode 311 to extension, third electroplated layer 6323 is towards 612 direction of the second metal column
Extend and realize the conducting of third electrode 411, simple in structure, electrical transmission performance is reliable, and third electroplated layer 6323 is along base
Plate lower surface 12 extends, and coordinates lower rewiring layer 633, can improve the external pin 121 positioned at 12 side of base lower surface
Layout freedom, the outer shifting of further accessory external pin 121, convenient for arranging other chip buried spaces in advance, to just
In multi-chip 2.5D or 3D the stacking integration packaging and module of realizing high-performance and small size.
Here, encapsulating structure 100 includes the first insulating layer 73 and second insulating layer 71.
First insulating layer 73 is located at third electroplated layer 6323 and base lower surface 12, the first lower surface 22, the second lower surface
32,42 lower section of third lower surface, and the first insulating layer 73 fills through-hole 13, lower rewiring layer 633 is by the first insulating layer 73
Hole conducting third electroplated layer 6323 and extend toward the lower surface direction of the first insulating layer 73, the lower weight of the connection of external pin 121
Wiring layer 633, second insulating layer 71 coats the first insulating layer 73 and lower rewiring layer 633, and second insulating layer 71 exposes outside
Pin 121.
It should be noted that " the first insulating layer 73 is located at third electroplated layer 6323 and base lower surface 12, the first lower surface
22, the second lower surface 32, the lower section of third lower surface 42 " can refer to the first insulating layer 73 be in direct contact third electroplated layer 6323 and
Base lower surface 12, the first lower surface 22, the second lower surface 32, third lower surface 42, alternatively, the first insulating layer 73 and third electricity
There is also other knots between coating 6323 and base lower surface 12, the first lower surface 22, the second lower surface 32, third lower surface 42
Structure.
Encapsulating structure 100 further includes third insulating layer 72 and the 4th insulating layer 81.
Third insulating layer 72 is located at upper surface of base plate 11, the first upper surface 21, second upper surface 31, third upper surface 41
Top, the first electroplated layer 6321 is by the hole conducting first electrode 211 and second electrode 311 on third insulating layer 72, and the 4th
Insulating layer 81 connects third insulating layer 72 and the 4th lower surface 52, and the 4th insulating layer 81, which has, exposes the first electroplated layer 6321 simultaneously
Accommodate the fluting 811 of scolding tin 62.
Wherein, the first metal column 611, the second metal column 612 are copper post, and intermediate wiring layer 632 and lower rewiring layer 633 are equal
For layers of copper.
Present embodiment realizes first electrode 211, second electrode 311, third using succinct rewiring (RDL) scheme
Electric connection between electrode 421, the 4th electrode 521 and external pin 121, process stabilizing and reliability are high.
The metal line materials of rewiring are copper (wiring layer 632 and lower rewiring layer 633 are layers of copper among i.e.), are rerouted
Enhancing can be set between copper and chip electrode (including first electrode 211, second electrode 311, third electrode 421) and reroute copper
The metal or alloy film of power is attached to each other with chip electrode, which can be nickel, titanium, nickel chromium triangle, titanium tungsten
Deng.
It is exhausted it to be folded with second insulating layer 71, third between package substrate 10, intermediate wiring layer 632 and lower rewiring layer 633
Edge layer 72 and the first insulating layer 73, to realize the electrical isolation between all parts.
It should be understood that the lower rewiring layer 633 in rewiring scheme is not limited with above-mentioned one layer, it can be according to reality
Depending on situation.
In addition, present embodiment setting copper post 61 and the advantage of scolding tin 62 are：(1) scolding tin 62 is in reflow soldering process
Molten condition convenient for being combined with copper post 61, and combines effect preferable；(2) scolding tin 62 and the upper contact surface rerouted between layer 631
Product is big, can improve electrical transmission performance, and the strong degree that scolding tin 62 is combined with upper rewiring layer 631 also can be improved；(3) copper post 51
A part of space has been already taken up, the raw material usage amount of scolding tin 62 can be reduced when scolding tin 62 is set at this time, reduces scolding tin 62
Welding procedure difficulty, shorten weld interval, and then improve welding production capacity；(4) 61 appearance of copper post is notable, can be used as and know
It is detected and possible defect recognition convenient for automatic aspect with improving recognition efficiency in other portion.
In the present embodiment, third insulating layer 72 and the 4th insulating layer 81 cooperatively form cofferdam 90, and encapsulating structure 100 wraps
The 5th insulating layer 82 positioned at the 4th lower surface 52 is included, cofferdam 90 is matched with the lower surface of the 5th insulating layer 82 and the first upper surface 21
It closes and encloses to set to form the first cavity S1, and cofferdam 90 coordinates with the lower surface of the 5th insulating layer 82 and the second upper surface 31 and encloses and set
Form the second cavity S2.
Here, first filter chip 20,30 surface of second filter chip active region (Active Zone) need
It could be worked normally under the contact of no foreign object or coverage condition, that is to say, that need to filter in first filter chip 20, second
The top of wave device chip 30 forms a cavity to protect the active region, at this point, first cavity S1, the second cavity S2 are right respectively
Answer first filter chip 20,30 surface of second filter chip active region.
Present embodiment forms the first cavity S1, the second cavity S2 by the way that cofferdam 90 is arranged, it is possible to prevente effectively from encapsulating
During structure fabrication or during encapsulating structure use external substance into inside the first cavity S1, the second cavity S2 and
The normal use for influencing first filter chip 20, second filter chip 30, to improve the globality of encapsulating structure 100
Energy.
Cofferdam 90 include be located at the inside of several first electrodes 211 and formed the first cavity S1 outer profiles the first cofferdam 91,
Positioned at second cofferdam 92 in 211 outside of several first electrodes, outside 311 inside of several second electrodes and the second cavity S2 of formation
The third cofferdam 93 of profile and the 4th cofferdam 94 on the outside of several second electrodes 311, and the lateral border in cofferdam 90 and encapsulation
10 lateral border of substrate flushes.
Here, since there is certain height may can not be propped up when the lower surface area in cofferdam 90 is too small in cofferdam 90
There is phenomenon of caving in so as to cause cofferdam 90 in the cofferdam 90 for supportting the height, the cofferdam 90 of present embodiment have it is sufficiently large under
Surface improves the stability in entire cofferdam 90；In addition, 90 lower surface of cofferdam can be filtered with first filter chip 20, second
30 upper surface of wave device chip removes the first cavity S1, the second cavity S2, first electrode 211, other upper tables outside second electrode 311
Face whole region combines, and further improves the forming stability of the first cavity S1, the second cavity S2.
In conjunction with Fig. 4, between the cofferdam of the upper surface of base plate of an embodiment of the present invention, electrode, cavity, through-hole, fluting
Cooperation schematic top plan view have been left out part-structure (such as RF switch chips 50, plastic packaging layer etc. for convenience of description.
There are first chamber 101, second chamber 102 and third chamber 103, several first electrodes 211 on package substrate 10
In array distribution in the first upper surface 21 of the first filter chip 20 positioned at first chamber 101, and adjacent first electrode 211
Between there is interval, the first cofferdam 91 to be located at the inside of first electrode 211, and around the setting of the periphery of the first cavity S1, second
Cofferdam 92 is located at the outside of first electrode 211, and several second electrodes 311 are in array distribution in positioned at the second of second chamber 102
Second upper surface 31 of filter chip 30, and there is interval between adjacent second electrode 311, third cofferdam 93 is located at the second electricity
The inside of pole 311, and be arranged around the periphery of the second cavity S2, the 4th cofferdam 94 is located at the outside of second electrode 311.
Here, the intermediate region adjacent in the first cavity S1 and the second cavity S2,92 essence of the second cofferdam and the 4th cofferdam
94 are connected, that is to say, that substantive not bounded between the first cofferdam 91, the second cofferdam 92, third cofferdam 93 and the 4th cofferdam 94
Limit, but continuous structure.
In addition, the lateral border in cofferdam 90 is flushed with the lateral border of package substrate 10.
Certainly, since package substrate 10 is quadrilateral structure, lateral border further include package substrate 10 front side lateral margin and after
Side lateral margin, cofferdam 90 can also extend to front side lateral margin and rear side lateral margin together, and but not limited to this, and package substrate 10 can also be
The structure of other shapes.
It should be noted that by taking the first cofferdam 91 and the second cofferdam 92 as an example, between the first cofferdam 91 and the second cofferdam 92
It can be independent from each other, such as the first cofferdam 91 is the first cyclic structure, the first cyclic structure is located at several first electrodes 211
Inside, the second cofferdam 92 is the second cyclic structure, and the second cyclic structure is located at the outside of several first electrodes 211.
Certainly, can also be interconnected between the first cofferdam 91 and the second cofferdam 92, at this point, the first cofferdam 91 and
Between two cofferdam 92 by the 5th cofferdam 95 realize interconnect, the 5th cofferdam 95 between adjacent first electrode 211 either
Other regions.
That is, cofferdam 90 at this time is covered with upper surface of base plate 11, the first upper surface 21, the second upper surface 31, third
The top of upper surface 41 remove first electrode 211, second electrode 311,13 region the first cavity S1, the second cavity S2 and through-hole its
His whole region.
Cofferdam 90 is made of the insulating materials of photaesthesia, and but not limited to this.
In the present embodiment, the 5th insulating layer 82 extends to the lower surface of the 4th electrode 521, and the 5th insulating layer 82 with
It partly overlaps between first metal column 611.
That is, the 5th insulating layer 82 covers the inside region of several 4th electrodes 521 and the part of the 4th electrode 521
Lower surface area is partly incorporated into the 5th insulating layer at this point, 611 part of the first metal column is incorporated into the lower section of the 4th electrode 521
The longitudinal section of 82 lower section, the first metal column 611 is substantially boot last.
So designing is advantageous in that：(1) the 5th insulating layer 82 realizes isolation as dielectric layer, avoids signal interference；(2)
The adhesive force of the first metal column 611 can be improved, and then improves electrical transmission performance.
In the present embodiment, encapsulating structure 100 further includes being located at side of the package substrate 10 far from base lower surface 12
The first plastic packaging layer 96, the first plastic packaging layer 96 coats cofferdam 90 and is exposed to outer surface area and RF switch chips 50 simultaneously.
Here, due to having the 5th insulating layer 82 between the 4th insulating layer 81 of part and the 4th lower surface 52, the
The lateral area of four electrodes 521 has gap, the first plastic packaging layer between the 4th lower surface 52 and the upper surface of the 4th insulating layer 81
96 fill the gap.
That is, the first plastic packaging layer 96 coats open area all around RF switch chips 50 at this time.
It should be understood that since the 5th insulating layer 82 at this time partly overlaps with the first metal column 611, it is not present between the two
Gap it is possible to prevente effectively from the first plastic packaging layer 96 enters the first cavity S1, the second cavity S2, and then further increases the first cavity
The leakproofness of S1, the second cavity S2.
First plastic packaging layer 96 can be EMC (Epoxy Molding Compound) plastic packaging layer, due to present embodiment profit
It can stop that external substance enters the first cavity S1, the second cavity S2 with cofferdam 90, without considering that the first plastic packaging layer 96 whether can
The protection zone in the first cavity S1, the second cavity S2 is influenced because of problem of materials, therefore, the choosing of 96 material of the first plastic packaging layer
It selects range significantly to expand, and then the selection of specific capsulation material can be evaded, plastic packaging making technology window is substantially widened and have
Effect reduces cost.
In the present embodiment, encapsulating structure 100 further includes the second plastic packaging layer 97, the first filtering of the second plastic packaging layer 97 filling
The gap of device 20 and first chamber S1, the gap of second filter 30 and second chamber S2 and amplifier chip 40 and third chamber
The gap of S3, and the second plastic packaging layer 97 covering base lower surface 12, the first lower surface 22, the second lower surface 32 and third lower surface
42, the first upper surface 21, the second upper surface 31, third upper surface 41 and upper surface of base plate 11 flush, and the second plastic packaging layer 97 is sudden and violent
Expose the second metal column 612.
That is, 6323 essence of third electroplated layer is positioned at the lower section of the second plastic packaging layer 97, and the first insulating layer 73 is real
For matter also in the lower section of the second plastic packaging layer 97, other explanations of the second plastic packaging layer 97 can saying with reference to the first plastic packaging layer 96
Bright, details are not described herein.
Here, pass through the setting of the second plastic packaging layer 97, on the one hand, the filtering of first filter chip 20, second can be compensated
Difference in thickness between device chip 30, amplifier chip 40 and package substrate 10, to realize the first upper surface 21, the second upper table
Face 31, third upper surface 41 and upper surface of base plate 11 flush, in order to structures such as follow-up first insulating layer 73, third insulating layers 72
Molding；On the other hand, the second plastic packaging layer 97 can play protection first filter chip 20, second filter chip 30, put
The effect of big device chip 40 and the relative position between fixed each chip and corresponding chamber.
The production method that an embodiment of the present invention also provides a kind of encapsulating structure 100, in conjunction with aforementioned encapsulation structure 100
Illustrate and Fig. 5, Fig. 6 a to Fig. 6 z-10, production method include step：
S1：Join Fig. 6 a, package substrate 10 is provided, there is the upper surface of base plate 11 being oppositely arranged and base lower surface 12；
S2：Join Fig. 6 b, in forming the first chamber 101, second chamber 102 and third chamber being spaced apart on package substrate 10
Room 103；
S3：Join Fig. 6 c to Fig. 6 e, first filter chip 20, second filter chip 30 and amplifier chip 40 be provided,
First filter chip 20 has the first upper surface 21 and the first lower surface 22 that are oppositely arranged, and if the first upper surface 21 have
Dry first electrode 211, second filter chip 30 have the second upper surface 31 and the second lower surface 32 being oppositely arranged, and second
There are several second electrodes 311, amplifier chip 40 to have the third upper surface 41 being oppositely arranged and third following table for upper surface 31
Face 42, and third lower surface 42 has several third electrodes 421；
S4：Join Fig. 6 f to Fig. 6 k, first filter chip 20 is loaded to first chamber 101, the first upper surface 21 and base
Plate upper surface 11 is located at homonymy, and second filter chip 30 is loaded to second chamber 102, the second upper surface 31 and upper surface of base plate
11 are located at homonymy, and amplifier chip 40 is loaded to third chamber 103, and third upper surface 41 is located at homonymy with upper surface of base plate 11；
Step S4 is specifically included：
Join Fig. 6 f, the second metal column 612 is formed in the lower section of third electrode 421；
Join Fig. 6 g, an interim jointing plate 98 is provided, the upper surface of base plate 11 of package substrate 10 is fitted in into interim jointing plate
98；
Join Fig. 6 h, first filter chip 20, second filter chip 30 and amplifier chip 40 are loaded into the respectively
One chamber 101, second chamber 102 and third chamber 103, the first upper surface 21, the second upper surface 31 and third upper surface 41 are pasted
Invest interim jointing plate 98；
Join Fig. 6 i, formed the gap of cladding first filter chip 20 and first chamber 101, second filter chip 30 with
The gap of second chamber 102, the gap of amplifier chip 40 and third chamber 103, base lower surface 12, the first lower surface 22,
Second plastic packaging layer 97 of the second lower surface 32 and third lower surface 42, the second plastic packaging layer 97 coat the second metal column 612；
Join Fig. 6 j, removes interim jointing plate 98；
Join Fig. 6 k, the second plastic packaging layer 97 of grinding is to expose the second metal column 612.
S5：Join Fig. 6 l to Fig. 6 z-10, RF switch chips 50 are provided, RF switch chips 50 are loaded into package substrate 10
Top, RF switch chips 50 have the 4th upper surface 51 and the 4th lower surface 52 being oppositely arranged, the 4th lower surface 52 and substrate
Upper surface 11 is arranged face-to-face, and the 4th lower surface 52 has several 4th electrodes 521, and forms several first electrodes of conducting
211, several second electrodes 311, several third electrodes 421 and several 4th electrodes 521 interconnection structure 60.
Step S5 is specifically included：
Join Fig. 6 l to Fig. 6 n, on upper surface of base plate 11, the first upper surface 21, the second upper surface 31, third upper surface 41
It is rectangular to form several through-holes 13 at third insulating layer 72, and in package substrate 10；
It is specific as follows：
Join Fig. 6 l, is formed above upper surface of base plate 11, the first upper surface 21, the second upper surface 31, third upper surface 41
Third insulating layer 72；
Join Fig. 6 m, in the second hole 721 of exposed and developed formation of third insulating layer 72, third hole 721 exposes first
The region of electrode 211, second electrode 311 and corresponding first cavity S1, the second cavity S2；
Join Fig. 6 n, forms several through-holes 13 in package substrate 10, through-hole 13 runs through third insulating layer 72 and the second plastic packaging layer
97；
Join Fig. 6 o to Fig. 6 r, form intermediate wiring layer 632, intermediate wiring layer 632 is located at third insulating layer including what is be connected
72 top the first electroplated layer 6321, positioned at the second electroplated layer 6322 of 13 inner wall of through-hole and positioned at the third of base lower surface 12
Electroplated layer 6323, the first electroplated layer 6321 is by the hole conducting first electrode 211 and second electrode on third insulating layer 72
311。
It is specific as follows：
Join Fig. 6 o, third photoresist layer 83 is respectively formed beneath in the top of third insulating layer 72 and the second plastic packaging layer 97
And the 4th photoresist layer 84；
Join Fig. 6 p, in the 83 exposed and developed formation third trepanning 831 of third photoresist layer, third trepanning 831 exposes the
One electrode 211, second electrode 311, third insulating layer 72 and through-hole 13, in the 84 exposed and developed formation the 4th of the 4th photoresist layer
Trepanning 841, the 4th trepanning 841 expose the second plastic packaging layer 97, the second metal column 612 and through-hole 13；
Join Fig. 6 q, forms the first electroplated layer 6321 in being exposed to outer third insulating layer 72, the through-hole 13 outside being exposed to
Inner wall forms the second electroplated layer 6322, and third electroplated layer 6323 is formed in being exposed to the second outer plastic packaging layer 97；
Join Fig. 6 r, removes third photoresist layer 83 and the 4th photoresist layer 84.
First insulating layer 73 of ginseng Fig. 6 s, formation cladding third electroplated layer 6323 and 97 lower surface of the second plastic packaging layer, and the
One insulating layer 73 fills through-hole 13；
4th insulating layer 81 of ginseng Fig. 6 t and Fig. 6 u, formation covering third insulating layer 72 and the first electroplated layer 6321, the 4th
Insulating layer 81 has the fluting 811 for exposing the first electroplated layer 6321, and third insulating layer 72 and the 4th insulating layer 81 cooperatively form
Cofferdam 90, cofferdam 90 include the first cofferdam 91, the position for being located at 211 inside of several first electrodes and forming the first cavity S1 outer profiles
In second cofferdam 92 in 211 outside of several first electrodes, positioned at 311 inside of several second electrodes and the second cavity S2 foreign steamers of formation
Wide third cofferdam 93 and the 4th cofferdam 94 positioned at 311 outside of several second electrodes, the first cavity S1 are located at the first upper surface
21 and positioned at the inside of several first electrodes 211, the second cavity S2 is located at the second upper surface 31 and positioned at several second electrode 311
Inside；
It is specific as follows：
Join Fig. 6 t, the 4th insulating layer 81 is formed in the top of third insulating layer 72 and the first electroplated layer 6321；
Join Fig. 6 u, forms the first trepanning 812 in 81 exposure imaging of the 4th insulating layer, the first trepanning 812 exposes the first chamber
Room S1, second chamber S2 and fluting 811, fluting expose the first electroplated layer 6321.
It should be noted that by taking the first cofferdam 91 and the second cofferdam 92 as an example, cofferdam 90 may include the first cofferdam of connection
91 and second cofferdam 92 the 5th cofferdam 95, that is to say, that cofferdam 90 at this time is covered with upper surface of base plate 11, the first upper surface
21, the second upper surface 31,41 top of third upper surface remove first electrode 211, second electrode 311, the first cavity S1, the second sky
Other whole regions in 13 region chamber S2 and through-hole.
In addition, formed since independent package substrate 10 can be divided by the large substrates of wafer scale, it, can when being molded cofferdam 90
With the multiple cofferdam 90 of straight forming on large substrates, the segmentation of large substrates is then carried out again and obtains the list with single cofferdam 90
A package substrate 10, in this way, being greatly improved packaging efficiency, certainly, cofferdam 90 is also plastic on RF switch chips 50.
Join Fig. 6 v, RF switch chips 50 are provided, RF switch chips 50 include the 4th upper surface 51 and the 4th being oppositely arranged
Lower surface 52, the 4th lower surface 52 have several 4th electrodes 521；
Join Fig. 6 w and Fig. 6 y, the 5th insulating layer 82 is formed in the lower section of the 4th lower surface 52, if the 5th insulating layer 82 covers
The intermediate region of dry 4th electrode 521, and the 5th insulating layer 82 extends to the lower surface of the 4th electrode 521, the 5th insulating layer 82
It partly overlaps between the 4th electrode 521；
It is specific as follows：
Join Fig. 6 w, the 5th insulating layer 82 is formed in the lower section of the 4th lower surface 52；
Join Fig. 6 x, in 82 the second trepanning 821 of exposed and developed formation of the 5th insulating layer, the second trepanning 821 exposes the 4th
The portion lower surface region of electrode 521 and its outwardly extending 4th lower surface, 52 region.
Join Fig. 6 y, the first metal column 611, the 5th insulating layer 82 and the first metal column are formed in the lower section of the 4th electrode 521
It partly overlaps between 611.
Join Fig. 6 z, in setting scolding tin 62 in fluting 811；
Join Fig. 6 z-1, RF switch chips 50 are loaded into the top of package substrate 10, the 4th lower surface 52 and substrate upper table
Face 11 is arranged face-to-face, and lower surface, the first upper surface 21 of the first cofferdam 91 and the 5th insulating layer 82 cooperate and enclose and set shape
At the first cavity S1, lower surface, the second upper surface 31 of third cofferdam 93 and the 5th insulating layer 82 cooperate and enclose to set to be formed
Second cavity S2, the first metal column 611 alignment fluting 811,611 mutual conduction of scolding tin 62 and the first metal column.
Join Fig. 6 z-2, the first plastic packaging layer 96, the first plastic packaging are formed in side of the package substrate 10 far from base lower surface 12
Layer 96 coats cofferdam 90 and is exposed to outer surface area and RF switch chips 50 simultaneously；
Join Fig. 6 z-3 to Fig. 6 z-7, is formed by the hole conducting on the first insulating layer 73 in the lower section of the first insulating layer 73
Third electroplated layer 6323 and the lower rewiring layer 633 extended toward the lower surface direction of the first insulating layer 73；
It is specific as follows：
Join Fig. 6 z-3, in 73 exposed and developed formation third hole 731 of the first insulating layer, third hole 731 exposes the
Three electroplated layers 6323；
Join Fig. 6 z-4, the 5th photoresist layer 85 is formed in the lower section of the first insulating layer 73；
Join Fig. 6 z-5, in 85 the 5th trepanning 851 of exposed and developed formation of the 5th photoresist layer, the 5th trepanning 851 exposes
First insulating layer 73 and third hole 731；
Join Fig. 6 z-6, layer 633 is rerouted under being formed in the 5th trepanning 851；
Join Fig. 6 z-7, removes the 5th photoresist layer 85.
Join Fig. 6 z-8 and Fig. 6 z-9, forms the first insulating layer 73 of cladding and the lower second insulating layer 71 for rerouting layer 633, the
Two insulating layers 71 expose lower rewiring layer 633；
It is specific as follows：
Join Fig. 6 z-8, second insulating layer 71 is formed in the first insulating layer 73 and the lower lower section for rerouting layer 633；
Join Fig. 6 z-9, in the first hole 711 of exposed and developed formation of second insulating layer 71, under the first hole 711 exposes
Reroute layer 633.
Join Fig. 6 z-10, ball grid array 121 is formed in being exposed to outer lower rewiring layer 633.
Other explanations of the production method of the encapsulating structure 100 of present embodiment can refer to above-mentioned encapsulating structure 100
Illustrate, details are not described herein.
The cofferdam 90 of the present invention is located at the inside and outside of first electrode 211, and positioned at the inside of second electrode 311 and
Outside, and the lateral border in cofferdam 90 is flushed with the lateral border of package substrate 10, in other embodiments, cofferdam 90 may be alternatively located at
The inside of first electrode 211 and the inside of second electrode 311, alternatively, the outside of the lateral border in cofferdam 90 and RF switch chips 50
Edge flushes, or, the lateral border in cofferdam 90 is located between the lateral border of RF switch chips 50 and the lateral border of package substrate 10
Etc..
To sum up, present embodiment forms the first cavity S1, the second cavity S2 by the way that cofferdam 90 is arranged, it is possible to prevente effectively from
In encapsulating structure manufacturing process or external substance enters in the first cavity S1, the second cavity S2 during encapsulating structure use
Portion and the normal use for influencing first filter chip 20, second filter chip 30, to improve the entirety of encapsulating structure 100
Performance.
In addition, present embodiment using encapsulation technology by multiple and different chip packages in same package substrate 10, can be with
It realizes the highly integrated of multi-chip, improves the utilization rate of package substrate 10, and then realize the miniaturization of encapsulating structure 100.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiment of understanding.
The series of detailed descriptions listed above only for the present invention feasible embodiment specifically
Bright, they are all without departing from equivalent implementations made by technical spirit of the present invention not to limit the scope of the invention
Or change should all be included in the protection scope of the present invention.
Claims (13)
1. a kind of multi-chamber encapsulating structure of amplifier chip electrode peripheral hardware, which is characterized in that including:
Package substrate, has the upper surface of base plate and base lower surface that are oppositely arranged, and the package substrate has and is spaced apart
First chamber, second chamber and third chamber；
First filter chip, is located at the first chamber, and the first filter chip has the first upper table being oppositely arranged
Face and the first lower surface, first upper surface and the upper surface of base plate are located at homonymy, and if first upper surface with
Dry first electrode；
Second filter chip, is located at the second chamber, and the second filter chip has the second upper table being oppositely arranged
Face and the second lower surface, second upper surface and the upper surface of base plate are located at homonymy, and if second upper surface with
Dry second electrode；
Amplifier chip, is located at the third chamber, and the amplifier chip has the third upper surface being oppositely arranged and third
Lower surface, the third upper surface is located at homonymy with the upper surface of base plate, and the third lower surface has several thirds electricity
Pole；
RF switch chips, are set to the top of the package substrate, and the RF switch chips have the 4th upper table being oppositely arranged
Face and the 4th lower surface, the 4th lower surface are arranged face-to-face with the upper surface of base plate, and the 4th lower surface has
Several 4th electrodes；
Several interconnection structures, for several first electrodes, several second electrodes, several third electrodes and several 4th electricity to be connected
Pole.
2. encapsulating structure according to claim 1, which is characterized in that the side of the base lower surface has several outsides
There are several through-holes, the interconnection structure several first electrodes, several are connected by the through-hole for pin, the package substrate
Second electrode, several third electrodes, several 4th electrodes and several external pins.
3. encapsulating structure according to claim 2, which is characterized in that the interconnection structure includes the first metal column, second
Metal column, scolding tin and electroplated layer structure, first metal column are connected to the lower section of the 4th electrode, second metal column
It is connected to the lower section of the third electrode, the first electrode, the second electrode, and the electricity is connected in the electroplated layer structure
Second metal column is connected and the outside is drawn by the way that the through-hole extends to the lower section of the package substrate in coating structure
Foot, the scolding tin is for being connected first metal column and the electroplated layer structure.
4. encapsulating structure according to claim 3, which is characterized in that the electroplated layer structure includes the centre of mutual conduction
Wiring layer and lower rewiring layer, the lower rewiring layer are located at the lower section of the package substrate and the external pin are connected, institute
State the first electroplated layer positioned at the upper surface of base plate that intermediate wiring layer includes connected, the second electricity positioned at the through-hole wall
The first electrode, described is connected in coating and the third electroplated layer below the base lower surface, first electroplated layer
Second electrode and the scolding tin, the third electroplated layer connect second metal column and the lower rewiring layer.
5. encapsulating structure according to claim 4, which is characterized in that the encapsulating structure includes the first insulating layer and second
Insulating layer, first insulating layer are located at the third electroplated layer and base lower surface, the first lower surface, the second lower surface,
Below three lower surfaces, and first insulating layer fills the through-hole, and the lower rewiring layer is by first insulating layer
Hole be connected the third electroplated layer and toward first insulating layer lower surface direction extend, and the external pin connect
The lower rewiring layer, the second insulating layer coats first insulating layer and the lower rewiring layer, and described second is exhausted
Edge layer exposes the external pin.
6. encapsulating structure according to claim 4, which is characterized in that the encapsulating structure includes third insulating layer and the 4th
Insulating layer, the third insulating layer be located at the upper surface of base plate, the first upper surface, the second upper surface, third upper surface it is upper
The first electrode and the second electrode, institute is connected by the hole on the third insulating layer in side, first electroplated layer
It states the 4th insulating layer and connects the third insulating layer and the 4th lower surface, the 4th insulating layer, which has, exposes described the
One electroplated layer and the fluting for accommodating scolding tin.
7. encapsulating structure according to claim 6, which is characterized in that the third insulating layer and the 4th insulating layer are matched
Conjunction forms cofferdam, and the encapsulating structure includes the 5th insulating layer positioned at the 4th lower surface, the cofferdam and the described 5th
The lower surface of insulating layer and first upper surface coordinate and enclose to set to form the first cavity, and the cofferdam is insulated with the described 5th
The lower surface and second upper surface of layer coordinate and enclose and set to form the second cavity.
8. encapsulating structure according to claim 7, which is characterized in that the cofferdam includes being located at several first electrodes
If inside and forming the first cofferdam of the first cavity outer profile, the second cofferdam on the outside of several first electrodes, being located at
On the inside of the dry second electrode and third cofferdam of formation the second cavity outer profile and the on the outside of several second electrodes the 4th
Cofferdam, and the lateral border in the cofferdam is flushed with the substrate lateral border.
9. encapsulating structure according to claim 7, which is characterized in that the 5th insulating layer extends to the 4th electrode
Lower surface, and partly overlap between the 5th insulating layer and first metal column.
10. encapsulating structure according to claim 9, which is characterized in that the encapsulating structure further includes being located at the encapsulation
First plastic packaging layer of side of the substrate far from the base lower surface, the first plastic packaging layer coat the cofferdam simultaneously and are exposed to
Outer surface area and the RF switch chips.
11. encapsulating structure according to claim 10, which is characterized in that the encapsulating structure further includes the second plastic packaging layer,
The second plastic packaging layer fills the gap of the first filter and the first chamber, the second filter and described second
The gap of chamber and the gap of the amplifier chip and the third chamber, and the second plastic packaging layer covers under the substrate
Surface, first lower surface, second lower surface and the third lower surface, first upper surface, on described second
Surface, the third upper surface and the upper surface of base plate flush, and the second plastic packaging layer exposes second metal column.
12. a kind of production method of the multi-chamber encapsulating structure of amplifier chip electrode peripheral hardware, which is characterized in that including step：
S1：Package substrate is provided, there is the upper surface of base plate and base lower surface being oppositely arranged；
S2：In forming the first chamber being spaced apart, second chamber and third chamber on the package substrate；
S3：First filter chip, second filter chip and amplifier chip are provided, the first filter chip has phase
To the first upper surface and the first lower surface of setting, and first upper surface has several first electrodes, second filtering
Device chip has the second upper surface and the second lower surface being oppositely arranged, and second upper surface has several second electrodes,
The amplifier chip has the third upper surface that is oppositely arranged and a third lower surface, and the third lower surface has several the
Three electrodes；
S4：The first filter chip is loaded to the first chamber, first upper surface and the upper surface of base plate
Positioned at homonymy, the second filter chip is loaded to the second chamber, second upper surface and the upper surface of base plate
Positioned at homonymy, the amplifier chip chip is loaded to the third chamber, the third upper surface and the upper surface of base plate
Positioned at homonymy；
S5：RF switch chips are provided, the RF switch chips are loaded into the top of the package substrate, the RF switch chips
With the 4th upper surface being oppositely arranged and the 4th lower surface, the 4th lower surface is set face-to-face with the upper surface of base plate
It sets, and the 4th lower surface has several 4th electrodes, and forms several first electrodes of conducting, several second electrodes, several
The interconnection structure of third electrode and several 4th electrodes.
13. the production method of encapsulating structure according to claim 12, which is characterized in that step S4 is specifically included：
The second metal column is formed in the lower section of the third electrode；
One interim jointing plate is provided；
The upper surface of base plate of package substrate is fitted in into interim jointing plate；
The first filter chip, second filter chip and amplifier chip are loaded into the first chamber, institute respectively
Second chamber and the third chamber are stated, first upper surface, second upper surface and the third upper surface are attached at
The interim jointing plate；
Form the gap for coating the first filter chip and the first chamber, the second filter chip and described the
The gap of two chambers, the amplifier chip and the gap of the third chamber, the base lower surface, first following table
The second plastic packaging layer in face, second lower surface and the third lower surface, the second plastic packaging layer coat second metal
Column；
Remove the interim jointing plate；
The second plastic packaging layer is ground to expose second metal column；
Step S5 is specifically included：
The formation third insulating layer above the upper surface of base plate, the first upper surface, the second upper surface, third upper surface, and in
The package substrate forms several through-holes；
Intermediate wiring layer is formed, the intermediate wiring layer includes that first connected be located above the third insulating layer is electroplated
Layer, the second electroplated layer positioned at the through-hole wall and the third electroplated layer positioned at the base lower surface, first plating
The first electrode and the second electrode is connected by the hole on the third insulating layer in layer；
The first insulating layer for coating the third electroplated layer and the second plastic packaging layer lower surface is formed, and first insulating layer is filled
The through-hole；
The 4th insulating layer for covering the third insulating layer and first electroplated layer is formed, the 4th insulating layer has exposure
Go out the fluting of first electroplated layer, the third insulating layer and the 4th insulating layer cooperatively form cofferdam, the cofferdam packet
It includes on the inside of several first electrodes and is formed the first cofferdam of the first cavity outer profile, be located on the outside of several first electrodes
The second cofferdam, on the inside of several second electrodes and form the third cofferdam of the second cavity outer profile and positioned at several second electricity
The 4th cofferdam on the outside of pole, first cavity is located at first upper surface and the inside positioned at several first electrodes, described
Second cavity is located at second upper surface and the inside positioned at several second electrodes；
RF switch chips are provided, the RF switch chips include the 4th upper surface and the 4th lower surface being oppositely arranged, and described the
Four lower surfaces have several 4th electrodes；
The 5th insulating layer is formed in the lower section of the 4th lower surface, the 5th insulating layer covers the centre of several 4th electrodes
Region, and the 5th insulating layer extends to the lower surface of the 4th electrode, the 5th insulating layer and the 4th electrode
Between partly overlap；
The first metal column, part between the 5th insulating layer and first metal column are formed in the lower section of the 4th electrode
Overlapping；
In scolding tin is arranged in fluting；
The RF switch chips are loaded into the top of the package substrate, the 4th lower surface and the upper surface of base plate face
It is provided opposite to, lower surface, first upper surface of first cofferdam and the 5th insulating layer cooperate and enclose and set shape
At first cavity, lower surface, second upper surface of the third cofferdam and the 5th insulating layer cooperate and
It encloses and sets to form second cavity, first metal column is directed at the fluting, and the scolding tin and first metal column are mutual
Conducting；
The first plastic packaging layer is formed in side of the package substrate far from the base lower surface, the first plastic packaging layer wraps simultaneously
It covers the cofferdam and is exposed to outer surface area and the RF switch chips；
It is formed in the lower section of first insulating layer and the third electroplated layer is connected simultaneously by the hole on first insulating layer
The lower rewiring layer extended toward the lower surface direction of first insulating layer；
The second insulating layer for coating first insulating layer and the lower rewiring layer is formed, the second insulating layer exposes institute
State lower rewiring layer；
Ball grid array is formed in being exposed to outer lower rewiring layer.
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| CN201810909245.4A CN108807350A (en) | 2018-08-10 | 2018-08-10 | The multi-chamber encapsulating structure and preparation method thereof of amplifier chip electrode peripheral hardware |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109802302A (en) * | 2019-01-15 | 2019-05-24 | 南京理工大学 | Three electrode switch chip of closed plane based on LTCC technique |
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