CN208507673U - The multi-chip stacking encapsulation modular structure of flush type filter chip - Google Patents
The multi-chip stacking encapsulation modular structure of flush type filter chip Download PDFInfo
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- CN208507673U CN208507673U CN201821289576.4U CN201821289576U CN208507673U CN 208507673 U CN208507673 U CN 208507673U CN 201821289576 U CN201821289576 U CN 201821289576U CN 208507673 U CN208507673 U CN 208507673U
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
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- 238000000576 coating method Methods 0.000 claims description 6
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
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- 238000010897 surface acoustic wave method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Connection Of Batteries Or Terminals (AREA)
Abstract
The utility model discloses a kind of multi-chip stacking encapsulation modular structure of flush type filter chip, and encapsulating structure includes: package substrate, with chamber；Filter chip is set in chamber, and the first upper surface and upper surface of base plate are located at ipsilateral, and the first upper surface has several first electrodes；Functional chip is set to the top of package substrate, and the second lower surface is arranged face-to-face with upper surface of base plate, and the second lower surface has several second electrodes；Several interconnection structures, for several first electrodes and several second electrodes to be connected.The utility model utilizes encapsulation technology that in same package substrate, the highly integrated of multi-chip is may be implemented in two different chip packages；In being distributed up and down, the functional chip above package substrate and the space for being not take up package substrate can be further improved the utilization rate of package substrate, simplify interconnection structure for filter chip and functional chip；Filter chip is embedded to be set in chamber, so that encapsulating structure is more frivolous.
Description
Technical field
The utility model relates to field of semiconductor package more particularly to a kind of multi-chip stackings of flush type filter chip
Formula encapsulation modular structure.
Background technique
To cater to the increasingly light and short development trend of electronic product, filter and radio-frequency transmissions component, receiving unit are needed
It is highly integrateable in the encapsulating structure of limited areal, forms system in package (SystemInPackage, SIP) structure, with
Reduce the size of hardware system.
For the filter and RF front-end module encapsulation integration technology in system-in-package structure, there are still suitable in the industry
More technical problem urgent need to resolve, for example, connection structure, multiple chips between the protection structure of filter, multiple chips
Layout etc..
Summary of the invention
The purpose of this utility model is to provide a kind of multi-chip stacking Encapsulation Moulds agllutinations of flush type filter chip
Structure.
To realize one of above-mentioned purpose of utility model, one embodiment of the utility model provides a kind of flush type filter core
The multi-chip stacking encapsulation modular structure of piece, comprising:
Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber；
Filter chip is set in the chamber, the filter chip have the first upper surface for being oppositely arranged and
First lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first upper surface has several the
One electrode；
Functional chip, is set to the top of the package substrate, and the functional chip has table on second be oppositely arranged
Face and the second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second lower surface has
Several second electrodes；
Several interconnection structures, for several first electrodes and several second electrodes to be connected.
As the further improvement of one embodiment of the utility model, the functional chip is located at the top of the chamber,
Several first electrodes are arranged face-to-face with several second electrodes.
As the further improvement of one embodiment of the utility model, the side of the base lower surface has several outsides
Pin, the package substrate have several through-holes, and the first electrode, described is connected by the through-hole in the interconnection structure
Second electrode and the external pin.
As the further improvement of one embodiment of the utility model, the through-hole and the second electrode are spaced apart from each other point
Cloth.
As the further improvement of one embodiment of the utility model, the interconnection structure includes metal column, scolding tin and electricity
Coating structure, the metal column are connected to the lower section of the second electrode, and the first electrode is connected in the electroplated layer structure, and
The external pin, the scolding tin is connected by the lower section that the through-hole extends to the package substrate in the electroplated layer structure
For the metal column and the electroplated layer structure to be connected.
As the further improvement of one embodiment of the utility model, the electroplated layer structure includes mutual electrically conducting
Upper rewiring layer, intermediate wiring layer and lower rewiring layer, upper top and the conducting for rerouting layer and being located at the package substrate
The first electrode, the lower rewiring layer are located at the lower section of the package substrate and the external pin are connected, the centre
Wiring layer include connected the first electroplated layer positioned at the upper surface of base plate, the second electroplated layer positioned at the through-hole wall and
Positioned at the third electroplated layer of the base lower surface, first electroplated layer connects the upper rewiring layer, the third plating
Layer connects the lower rewiring layer.
As the further improvement of one embodiment of the utility model, the encapsulation modular structure includes being located at the substrate
First electricity is connected by the hole on first insulating layer for the first insulating layer above upper surface, the first upper surface
The upper rewiring layer of coating and the first electrode and connect the second of first insulating layer and second lower surface absolutely
Edge layer, the second insulating layer, which has, exposes the upper fluting for rerouting layer and accommodating scolding tin.
As the further improvement of one embodiment of the utility model, first insulating layer and the second insulating layer are matched
Conjunction forms cofferdam, and the cofferdam and second lower surface, the first upper surface cooperate and enclose and set to form cavity.
As the further improvement of one embodiment of the utility model, the cofferdam includes being located on the inside of several first electrodes
The first cofferdam and the second cofferdam on the outside of several first electrodes, it is first cofferdam and second lower surface, described
First upper surface cooperates and encloses and set to form cavity.
As the further improvement of one embodiment of the utility model, second cofferdam is towards far from first cofferdam
The lateral border that direction extends up to second cofferdam is flushed with the lateral border of the package substrate, and second cofferdam exposure
The through-hole out.
As the further improvement of one embodiment of the utility model, the encapsulation modular structure further includes being located at the envelope
The first plastic packaging layer of side of the substrate far from the base lower surface is filled, the first plastic packaging layer coats second cofferdam simultaneously
It is exposed to outer surface area and the functional chip, and the first plastic packaging layer fills the through-hole.
As the further improvement of one embodiment of the utility model, the encapsulation modular structure includes coating the third
The third electroplated layer is connected by the hole on the third insulating layer in the third insulating layer of electroplated layer and base lower surface
And the lower rewiring layer and the cladding third insulating layer that extend toward the lower surface direction of the third insulating layer and it is described under
The 4th insulating layer of layer is rerouted, the external pin connects the lower rewiring layer, and described in the 4th insulating layer exposing
External pin.
As the further improvement of one embodiment of the utility model, the gap of the filter chip and the chamber,
The base lower surface and first lower surface are provided with the second plastic packaging layer, first upper surface and the upper surface of base plate
It flushes.
Compared with prior art, the utility model has the beneficial effects that: one embodiment of the utility model utilizes encapsulation
In same package substrate, the highly integrated of multi-chip may be implemented in two different chip packages by technology, improves package substrate
Utilization rate, and then realize encapsulation modular structure miniaturization；In addition, filter chip and functional chip are in distribution up and down, position
Functional chip above package substrate and the space for being not take up package substrate, can be further improved the utilization of package substrate
Rate, and the spacing between filter chip and functional chip becomes smaller, and is easy to implement mutual between filter chip and functional chip
Even, simplify interconnection structure；It is set in chamber moreover, filter chip is embedded, so that encapsulation modular structure is more frivolous.
Detailed description of the invention
Fig. 1 is the exemplary RF front-end module of the utility model one；
Fig. 2 is another exemplary RF front-end module of the utility model；
Fig. 3 is the cross-sectional view of the encapsulation modular structure of one embodiment of the utility model；
Fig. 4 is the cofferdam cooperation through-hole of one embodiment of the utility model and the schematic diagram of first electrode；
The step of Fig. 5 is the production method of the encapsulation modular structure of one embodiment of the utility model figure；
Fig. 6 a to Fig. 6 z-13 is the flow chart of the production method of the encapsulation modular structure of one embodiment of the utility model.
Specific embodiment
The utility model is described in detail below with reference to specific embodiment shown in the drawings.But these embodiment party
Formula is not intended to limit the utility model, structure that those skilled in the art are made according to these embodiments, method or
Transformation functionally is all contained in the protection scope of the utility model.
In each diagram of the application, for the ease of illustration, structure or partial certain sizes can be relative to other knots
Structure or part are exaggerated, and therefore, are only used for the basic structure of the theme of diagram the application.
In addition, the term of the representation space relative position used herein such as "upper", " top ", "lower", " lower section " is
A unit as shown in the drawings or feature are described for the purpose convenient for explanation relative to another unit or feature
Relationship.The term of relative space position can be intended to include equipment in use or work other than orientation as shown in the figure not
Same orientation.For example, being described as being located at other units or feature " below " or " under " if the equipment in figure overturn
Unit will be located at other units or feature " top ".Therefore, exemplary term " lower section " can include above and below both
Orientation.Equipment can otherwise be directed (be rotated by 90 ° or other directions), and be interpreted accordingly it is used herein with it is empty
Between relevant description language.
Join Fig. 1 and Fig. 2, one embodiment of the utility model provides a kind of general RF front-end module, radio-frequency front-end mould
Block can be used in the mobile devices such as mobile phone, computer either other electronic equipments.
In conjunction with Fig. 1, in one example, RF front-end module includes (the Power Amplifier of power amplifier module 200
Module, PAM), power amplifier module 200 includes the first amplifier unit 201 being successively electrically connected, the first RF switch list
Member 202 and the first RF filter cell 203, the first amplifier unit 201 are multi-mode-wide bandwidth Power Amplifier Unit.
In practical operation, the first amplifier unit 201 is used to receive the modulated signal of other component output, puts through overpower
Greatly after the modulation, amplification of device module 200 and filtering operation, exported by filter cell 203.
In conjunction with Fig. 2, in another example, RF front-end module includes receiving 300 (Receive of diversity module
Diversity Module, RDM), receiving diversity module 300 includes the low noise amplification multiplexer 301 being successively electrically connected
(LNA Multiplexer Module, LMM), the 2nd RF filter cell 302 and RF duplexer unit 303, wherein low noise
It includes the second amplifier unit 3011 and the 2nd RF switch unit 3012 being electrically connected, the second amplification that sound, which amplifies multiplexer 301,
Device unit 3011 is multi-mode-wide bandwidth low-noise amplifier unit, and the both ends of the 2nd RF switch unit 3012 are separately connected
Second amplifier unit 3011 and the 2nd RF filter cell 302.
In practical operation, signal divides by notch diplexer 304 to be believed here with high frequency for high-frequency signal and low frequency signal
For number, high-frequency signal enters RF duplexer unit 303, then successively passes through the 2nd RF filter cell 302 and low noise
It is exported after amplifying the filtering, modulation, amplifying operation of multiplexer 301 by the second amplifier unit 3011.
It should be understood that the electrical property between each units such as above-mentioned RF switch unit, filter cell, amplifier unit connects
Connecing can be realized by packaging technology, i.e., RF switch chip, amplifier chip, filter chip etc. are packaged together and realize
Various functions.
Present embodiment is said by taking RF switch chip, amplifier chip, the encapsulating structure of filter chip, technique as an example
It is bright.
Join Fig. 3, is the multi-chip stacking package module of the flush type filter chip of one embodiment of the utility model
The cross-sectional view of structure 100.
Encapsulation modular structure 100 includes package substrate 10, filter chip 20, functional chip 30 and several interconnection structures
50。
Package substrate 10 has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged, and package substrate 10 has chamber
101。
Here, package substrate 10 is the loading plate for carrying chip, and package substrate 10 can be printing made of organic resin
Circuit board is also possible to glass substrate or ceramic substrate etc..
Chamber 101 can be the through hole through package substrate 10, and but not limited to this.
Filter chip 20 is set in chamber 101, filter chip 20 have the first upper surface 21 for being oppositely arranged and
First lower surface 22, the first upper surface 21 and upper surface of base plate 11 are located at ipsilateral, and the first upper surface 21 has several first electricity
Pole 211.
First electrode 211 protrudes out the first upper surface 21 towards the direction far from the first lower surface 22, and but not limited to this.
Filter chip 20 can be surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or volume
Acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited to this, the active region on 20 surface of filter chip
Domain (Active Zone) needs to work normally under the contact of no foreign object or coverage condition, that is to say, that needs are filtering
The lower section of device chip 20 forms a cavity to protect the active region.
Functional chip 30 is set to the top of package substrate 10, and functional chip 30 has the second upper surface 31 being oppositely arranged
And second lower surface 32, the second lower surface 32 are arranged face-to-face with upper surface of base plate 11, and the second lower surface 32 has several the
Two electrodes 321.
Second electrode 321 protrudes out the second lower surface 32 towards the direction far from second surface 31, and but not limited to this.
Functional chip 30 is amplifier chip or RF switch chip, and but not limited to this.
Several interconnection structures 50 are for being connected several first electrodes 211 and several second electrodes 321.
Here, " several interconnection structures 50 are for being connected several first electrodes 211 and several second electrodes 321 " refers to first
It is electrically connected between electrode 211 and second electrode 321, that is, realizes the interconnection of filter chip 20 and functional chip 30.
Present embodiment is encapsulated two different chips (filter chip 20 and functional chip 30) using encapsulation technology
In same package substrate 10, the highly integrated of multi-chip may be implemented, improve the utilization rate of package substrate 10, and then realize encapsulation
The miniaturization of modular structure 100.
In addition, filter chip 20 and functional chip 30 are distributed in upper and lower, the functional chip above package substrate 10
30 and be not take up the space of package substrate 10, can be further improved the utilization rate of package substrate 10, and filter chip 20 and
Spacing between functional chip 30 becomes smaller, the interconnection being easy to implement between filter chip 20 and functional chip 30, simplifies interconnection
Structure.
It is set in chamber 101 moreover, filter chip 20 is embedded, so that encapsulation modular structure 100 is more frivolous.
It should be noted that the encapsulation modular structure 100 of present embodiment is with a filter chip 20 and a function
Chip 30 is loaded into for package substrate 10, it is possible to understand that, in practice, referring to Figure 1 and Figure 2, it may include multiple
Filter chip 20 and multiple functional chips 30, for example, around filter chip 20 (including all around three-dimensional side up and down
To) multiple functional chips 30 etc. can be electrically connected with.
In the present embodiment, functional chip 30 is located at the top of chamber 101, several first electrodes 211 and several second
Electrode 321 is arranged face-to-face.
That is, filter chip 20 and about 30 functional chip are correspondingly arranged, first electrode 211 and the second electricity
Pole 321 is also to be arranged face-to-face, in this way, the setting of filter chip 20 can't excessively occupy envelope in the horizontal direction
The space of 10 horizontal direction of substrate is filled, the size of package substrate 10 can be done small.
Here, the size of functional chip 30 is greater than the size of filter chip 20, and functional chip 30 covers chamber 101
Upper area.
That is, chamber 101 is completely covered in the upright projection on package substrate 10 in the outer profile of functional chip 30.
In the present embodiment, the side of package substrate 10 has several external pins 121, and interconnection structure 50 is for being connected
First electrode 211, second electrode 321 and external pin 121.
External pin 121 can be ball grid array (Ball Grid Array, BGA), pad etc., encapsulation modular structure
100 can be electrically connected by external pin 121 with realizations such as other chips or substrates, and here, external pin 121 is with ball bar battle array
For column 121, external pin 121 protrudes out the lower surface of encapsulation modular structure 100.
In addition, but not limited to this, outside here by taking several external pins 121 are located at the side of base lower surface 12 as an example
Portion's pin 121 may be alternatively located at other regions.
Package substrate 10 has several through-holes 13, and the 211, second electricity of first electrode is connected by through-hole 13 in interconnection structure 50
Pole 321 and external pin 121.
In the present embodiment, through-hole 13 and second electrode 321 are spaced apart from each other distribution.
Here, through-hole 13 is located at the outside of second electrode 321, and through-hole 13 is located at the outside of chamber 101, at this point, being located at
The external pin 121 of 12 side of base lower surface can be towards shifting outside the two sides of functional chip 30, convenient for arranging other chips in advance
The space of embedment, consequently facilitating realizing that the multi-chip 2.5D or 3D of high-performance and small size stack integration packaging and mould group.
In the present embodiment, interconnection structure 50 includes metal column 51, scolding tin 52 and electroplated layer structure 53.
Metal column 51 is connected to the lower section of second electrode 321, and first electrode 211, and electroplated layer is connected in electroplated layer structure 53
External pin 121 is connected by the lower section that through-hole 13 extends to package substrate 10 in structure 53, and scolding tin 52 is for being connected metal column
51 and electroplated layer structure 53.
Specifically, electroplated layer structure 53 includes the upper rewiring layer 531, intermediate wiring layer 532 and lower heavy cloth of mutual conduction
Line layer 533.
Upper rewiring layer 531 is located at the top of package substrate 10 and first electrode 211 is connected.
Intermediate wiring layer 532 is including being connected positioned at the first electroplated layer 5321 of upper surface of base plate 11, in through-hole 13
Second electroplated layer 5322 of wall and third electroplated layer 5323 positioned at base lower surface 12.
Layer 531 is rerouted in the connection of first electroplated layer 5321.
The width that the first electroplated layer 5321 of rewiring layer 531 extends to upper surface of base plate 11 in connection is substantially equal to correspondence
Third electroplated layer 5323 extend to the width of base lower surface 12.
Here, on the one hand, upper surface of base plate 11 and base lower surface 12 are provided with electroplated layer, can be improved electroplated layer with
The strong degree that package substrate 10 combines；On the other hand, the first electroplated layer 5321 extends towards 211 direction of first electrode, convenient for upper
It reroutes layer 531 and connects the first electroplated layer 5321, and since scolding tin 52 at this time does not enter through-hole 13, through-hole 13 can be towards outside two sides
It moves, so that the external pin 121 of base lower surface 12 can move in addition.
Lower rewiring layer 533 is located at the lower section of package substrate 10 and external pin 121 is connected, and lower rewiring layer 533 connects
Connect third electroplated layer 5323.
Here, encapsulation modular structure 100 includes the first insulating layer positioned at upper surface of base plate 11,21 top of the first upper surface
70, be connected by the hole on the first insulating layer 70 the upper rewiring layer 531 of first electroplated layer 5321 and first electrode 211 with
And the second insulating layer 71 of the first insulating layer 70 and the second lower surface 32 is connected, second insulating layer 71, which has, exposes rewiring
Layer 531 and the fluting 43 for accommodating scolding tin 52, the corresponding second electrode 321 of fluting 43 are arranged.
Encapsulation modular structure 100 includes the third insulating layer 72 of cladding third electroplated layer 5323 and base lower surface 12, warp
Under the hole conducting third electroplated layer 5323 crossed on third insulating layer 72 simultaneously extends toward the lower surface direction of third insulating layer 72
It reroutes layer 533 and coats third insulating layer 72 and lower the 4th insulating layer 73 for rerouting layer 533, the connection of external pin 121
Lower rewiring layer 533, and the 4th insulating layer 73 exposure external pin 121.
The lower setting for rerouting layer 533 can not only expand rewiring range, improve the laying of subsequent external pin 121 oneself
By spending, the outer shifting of acceptable further accessory external pin 121.
Metal column 51 is copper post, and upper rewiring layer 531, intermediate wiring layer 532 and lower rewiring layer 533 are layers of copper.
Present embodiment realizes first electrode 211, second electrode 321 and outer using succinct rewiring (RDL) scheme
Electric connection between portion's pin 121, process stabilizing and high reliablity.
The metal line materials of rewiring are that copper is (i.e. upper to reroute layer 531, intermediate wiring layer 532 and lower rewiring layer 533
For layers of copper), it reroutes and enhancing weight cloth can be set between copper and chip electrode (including first electrode 211 and second electrode 321)
Line copper and chip electrode are attached to each other the metal or alloy film of power, which can be nickel, titanium, nickel chromium triangle,
Titanium tungsten etc..
The first insulating layer 70, second is folded between package substrate 10, upper rewiring layer 531 and lower rewiring layer 533 absolutely
Edge layer 71 and third insulating layer 72, to realize the electrical isolation between all parts.
It should be understood that the upper rewiring layer 531 in rewiring scheme is not limited with above-mentioned one layer, lower rewiring layer
533 are not also limited with above-mentioned one layer, can according to the actual situation depending on.
In addition, the advantage of present embodiment setting metal column 51 and scolding tin 52 is: (1) scolding tin 52 is in reflow soldering process
For molten condition, convenient for being combined with metal column 51, and combine effect preferable；(2) connecing between scolding tin 52 and upper rewiring layer 531
Contacting surface product is big, and electrical transmission performance can be improved, and the strong degree that scolding tin 52 is combined with upper rewiring layer 531 also can be improved；(3) golden
Belong to column 51 and already taken up a part of space, the raw material usage amount of scolding tin 52 can be reduced when scolding tin 52 is set at this time, is reduced
The welding procedure difficulty of scolding tin 52, shortens weld interval, and then improves welding production capacity；(4) 51 appearance of metal column is significant, can
To improve recognition efficiency as identification part, and then convenient for the detection of automatic aspect and possible defect recognition.
In the present embodiment, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, cofferdam 40 and second
Lower surface 32, the first upper surface 21 cooperate and enclose to set to form cavity S, the active region on 20 surface of cavity S respective filter chip
Domain.
Present embodiment by setting cofferdam 40 formed cavity S, it is possible to prevente effectively from encapsulating structure manufacturing process or
It is that external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process, thus
Improve the overall performance of encapsulation modular structure 100.
In the present embodiment, cavity S is located at the inside of several first electrodes 211.
Cofferdam 40 includes positioned at the first cofferdam 41 of several 211 insides of first electrode and outside several first electrodes 211
Second cofferdam 42 of side, the first cofferdam 41 and the second lower surface 32 and the first upper surface 21 cooperate and enclose and set to form cavity S.
Here, the first cofferdam 41 is located at the inside of through-hole 13, and 42 part of the second cofferdam is located at 13 inside of through-hole, is partially located at
13 outside of through-hole.
Since cofferdam 40 has certain height, when the lower surface area when cofferdam 40 is too small, this may can not be supported
There is collapsing phenomenon so as to cause cofferdam 40 in the cofferdam 40 of height, and the cofferdam 40 of present embodiment includes the first cofferdam 41 and the
Two cofferdam 42, cofferdam 40 have sufficiently large lower surface, improve the stability in entire cofferdam 40；In addition, 40 lower surface of cofferdam
It can combine with the 20 upper surface whole region of filter chip outside the 20 upper surface region cavity S of filter chip, further mention
The forming stability of high cavity S.
In conjunction with Fig. 4, several through-holes 13 are in array distribution in upper surface of base plate 11, and have interval between adjacent through-holes 13,
There is a space between two column through-holes 13, chamber 101 is located in the space, and has interval between chamber 101 and through-hole 13, the
The interior zone of the corresponding chamber 101 in one cofferdam 41, and 41 essence of the first cofferdam is positioned at the inside of first electrode 211, second encloses
Weir 42 is extended by the interior zone of corresponding chamber 101 towards 13 direction of through-hole, and fluting 43 is located at the top in cofferdam 40.
In addition, the second cofferdam 42 extends up to lateral border and the encapsulation in the second cofferdam 42 towards the direction far from the first cofferdam 41
The lateral border of substrate 10 flushes, and the second cofferdam 42 exposes through-hole 13.
Certainly, since package substrate 10 is quadrilateral structure, lateral border further include package substrate 10 front side lateral margin and after
Side lateral margin, the second cofferdam 42 can also extend to front side lateral margin and rear side lateral margin together, and but not limited to this, and package substrate 10 can also
To be the structure of other shapes.
It should be noted that can be independent from each other between the first cofferdam 41 and the second cofferdam 42, such as the first cofferdam
41 be the first cyclic structure, and the first cyclic structure is located at the inside of several first electrodes 211, and the second cofferdam 42 is the second cyclic annular knot
Structure, the second cyclic structure are located at the outside of several first electrodes 211.
Certainly, be also possible between the first cofferdam 41 and the second cofferdam 42 it is interconnected, at this point, the first cofferdam 41 and
Interconnection is realized by third cofferdam 45 between two cofferdam 42, third cofferdam 45 is located at adjacent through-hole 13, adjacent first electrode
211, between adjacent second electrode 321 or other regions, that is to say, that cofferdam 40 at this time is covered with upper surface of base plate 11
And first remove cavity S and 13 region of through-hole above upper surface 21 other whole regions.
In the present embodiment, the second lower surface 32 of functional chip 30 covers the upper surface in the first cofferdam 41, and second
Lower surface 32 is Chong Die with the upper surface portion in the second cofferdam 42, and the first upper surface 21 and upper surface of base plate 11 cover first together and enclose
The lower surface in the lower surface on weir 41 and the second cofferdam 42.
Cofferdam 40 is made of the insulating materials of photaesthesia, and but not limited to this.
In the present embodiment, encapsulation modular structure 100 further includes coating the second cofferdam 42 simultaneously to be exposed to outer upper table
First plastic packaging layer 60 of face region and functional chip 30, and the first plastic packaging layer 60 fills through-hole 13.
First plastic packaging layer 60 is located at side of the package substrate 10 far from base lower surface 12.
That is, the first plastic packaging layer 60 is located inside top and the through-hole 13 in the second cofferdam 42 at this time, the first plastic packaging layer
All 13 interior zones of open area and through-hole around 60 cladding functional chips 30.
First plastic packaging layer 60 can be EMC (Epoxy Molding Compound) plastic packaging layer, due to present embodiment benefit
External substance can be stopped to enter cavity S with cofferdam 40, without consider the first plastic packaging layer 60 whether can because of problem of materials shadow
The protection zone in cavity S is rung, therefore, the range of choice of 60 material of the first plastic packaging layer expands significantly, and then can evade specific
The selection of capsulation material is substantially widened plastic packaging making technology window and is effectively reduced cost.
In the present embodiment, the first upper surface 21 of filter chip 20 is flushed with upper surface of base plate 11, moreover, filtering
Gap, base lower surface 12 and the first lower surface 22 of device chip 20 and chamber 101 are provided with the second plastic packaging layer 61.
That is, 5323 essence of third electroplated layer is to be located at the lower section of the second plastic packaging layer 61, and third insulating layer 72 is real
For matter also in the lower section of the second plastic packaging layer 61, other explanations of the second plastic packaging layer 61 can saying with reference to the first plastic packaging layer 60
Bright, details are not described herein.
Here, pass through the setting of the second plastic packaging layer 61, on the one hand, can with compensating filter chip 20 and package substrate 10 it
Between difference in thickness, to realize that the first upper surface 21 is flushed with upper surface of base plate 11, in order to subsequent first insulating layer 70, the
The isostructural molding of three insulating layer 72；On the other hand, the second plastic packaging layer 61 can play protecting filter chip 20 and fix
The effect of the relative position of filter chip 20 and chamber 101.
One embodiment of the utility model also provides a kind of production method of encapsulation modular structure 100, in conjunction with aforementioned encapsulation
The explanation and Fig. 5, Fig. 6 a to Fig. 6 z-13 of modular structure 100, production method comprising steps of
S1: ginseng Fig. 6 a provides package substrate 10, has the upper surface of base plate 11 and base lower surface 12 being oppositely arranged；
S2: ginseng Fig. 6 b, in formation chamber 101 on package substrate 10；
S3: ginseng Fig. 6 c provides filter chip 20, and filter chip 20 has the first upper surface 21 being oppositely arranged and the
A lower surface 22, the first upper surface 21 have several first electrodes 211；
S4: ginseng Fig. 6 d to Fig. 6 j loads filter chip 20 to chamber 101, the first upper surface 21 and upper surface of base plate
11 positioned at ipsilateral；
Step S4 is specific as follows:
Join Fig. 6 d, an interim jointing plate 90 is provided；
Join Fig. 6 e, the upper surface of base plate 11 of package substrate 10 is fitted in into interim jointing plate 90；
Join Fig. 6 f, filter chip 20 is loaded to chamber 101, the first upper surface 21 is located at same with upper surface of base plate 11
Side；
Here, the first upper surface 21 also fits in interim jointing plate 90, so, it can be achieved that on the first upper surface 21 and substrate
Surface 11 flushes.
Join Fig. 6 g, forms gap, base lower surface 12 and the first lower surface 22 of cladding filter chip 20 and chamber 101
The second plastic packaging layer 61；
Join Fig. 6 h, removes interim jointing plate 90；
Join Fig. 6 i, inverts package substrate 10.
Join Fig. 6 j, in forming several through-holes 13 on package substrate 10, through-hole 13 runs through the second plastic packaging layer 61.
S5: ginseng Fig. 6 k to Fig. 6 v, in forming the first interconnection structure on package substrate 10, the first interconnection structure conducting first is electric
Pole 211；
Step S5 is specific as follows:
Join Fig. 6 k to Fig. 6 n, form the first electroplated layer 5321 in upper surface of base plate 11, forms the second electricity in 13 inner wall of through-hole
Coating 5322 forms third electroplated layer 5323 below the second plastic packaging layer 61；
It is specific as follows:
Join Fig. 6 k, is respectively formed beneath the first photoresist layer 81 in the top of upper surface of base plate 11 and the second plastic packaging layer 61
And second photoresist layer 82；
Join Fig. 6 l, forms the first aperture 811 in 81 exposure and imaging of the first photoresist layer, the first aperture 811 exposes logical
Hole 13 and upper surface of base plate 11 form the second aperture 821, the second aperture 821 exposure in 82 exposure and imaging of the second photoresist layer
Through-hole 13 and the second plastic packaging layer 61 out；
Join Fig. 6 m, forms the first electroplated layer 5321 in being exposed to outer upper surface of base plate 11, the through-hole 13 outside being exposed to
Inner wall forms the second electroplated layer 5322, forms third electroplated layer 5323 in being exposed to the second outer plastic packaging layer 61；
Join Fig. 6 n, removes the first photoresist layer 81 and the second photoresist layer 82.
Join Fig. 6 o, lays the first insulating layer 70 in upper surface of base plate 11；
Join Fig. 6 p to Fig. 6 t, is formed in the top of the first insulating layer 70 by the hole conducting first on the first insulating layer 70
The upper rewiring layer 531 of electrode 211 and the first electroplated layer 5321；
It is specific as follows:
Join Fig. 6 p, forms the first hole 701 in 70 exposure and imaging of the first insulating layer, the first hole 701 exposes first
Electrode 211, through-hole 13, the first electroplated layer 5321 and protection zone, protection zone are located at the first upper surface 21, and protection zone position
In the inside of several first electrodes 211；
Join Fig. 6 q, forms third photoresist layer 83 in the top of the first insulating layer 70；
Join Fig. 6 r, forms third aperture 831 in 83 exposure and imaging of third photoresist layer, third aperture 831 exposes the
One electrode 211, the first electroplated layer 5321 and the first insulating layer 70；
Join Fig. 6 s, reroutes layer 531 in being formed in third aperture 831；
Join Fig. 6 t, removes third photoresist layer 83.
Join Fig. 6 u to Fig. 6 v, in the first insulating layer 70, it is upper reroute layer 531 top lay second insulating layer 71, first
Insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, and cofferdam 40 includes the first cofferdam 41 and the second cofferdam 42, and first encloses
Weir 41 is located at the periphery of cavity S, and the lateral border in the second cofferdam 42 is flushed with the lateral border of package substrate 10, the exposure of the second cofferdam 42
Through-hole 13 out, cofferdam 40 have the fluting 43 for exposing and rerouting layer 531；
It is specific as follows:
Join Fig. 6 u, lays second insulating layer 71 in the first insulating layer 70, the upper top for rerouting layer 531 and protection zone；
Join Fig. 6 v, forms the second hole 711 in 71 exposure and imaging of second insulating layer, the second hole 711 exposes through-hole
13, upper rewiring layer 531 and protection zone, the first insulating layer 70 and second insulating layer 71 cooperatively form cofferdam 40, and cofferdam 40 is wrapped
The first cofferdam 41 and the second cofferdam 42 are included, the first cofferdam 41 is located at the periphery of protection zone, the lateral border in the second cofferdam and encapsulation
The lateral border of substrate 10 flushes, and the second cofferdam 42 exposes through-hole 13, and cofferdam 40 has the fluting for exposing and rerouting layer 531
43。
It should be noted that cofferdam 40 may include the third cofferdam 45 for connecting the first cofferdam 41 and the second cofferdam 42,
That is removing the other surfaces region outside corresponding cavity S and 13 region of through-hole in upper surface of base plate 11 at this time is respectively formed cofferdam
40。
In addition, formed since independent package substrate 10 can be divided by the large substrates of wafer scale, it, can when forming cofferdam 40
With the multiple cofferdam 40 of straight forming on large substrates, the segmentation of large substrates is then carried out again and obtains the list with single cofferdam 40
A package substrate 10, in this way, being greatly improved packaging efficiency, certainly, cofferdam 40 is also plastic on functional chip 30.
S6: ginseng Fig. 6 w, functional chip 30 is provided, functional chip 30 has under the second upper surface 31 and second being oppositely arranged
Surface 32, and the second lower surface 32 has several second electrodes 321；
S7: ginseng Fig. 6 x to Fig. 6 z-10 is loaded into functional chip 30 top of package substrate 10, the second lower surface 32 with
Upper surface of base plate 11 is arranged face-to-face, and forms the second interconnection structure of conducting second electrode 321 and the first interconnection structure；
S8: ginseng Fig. 6 z-11 to Fig. 6 z-13, the third for forming conducting external pin 121 and the first interconnection structure mutually link
Structure.
Step S7, S8 is specific as follows:
Join Fig. 6 x to Fig. 6 z-1, forms metal column 51 in the lower surface of second electrode 321；
It is specific as follows:
Join Fig. 6 x, forms the 4th photoresist layer 84 in the second lower surface 32；
Join Fig. 6 y, forms the 4th aperture 841 in 84 exposure and imaging of the 4th photoresist layer, the 4th aperture 841 exposes the
Two electrodes 321；
Join Fig. 6 z, in formation metal column 51 in the 4th aperture 841；
Join Fig. 6 z-1, removes the 4th photoresist layer 84.
Join Fig. 6 z-2, in setting scolding tin 52 in fluting 43；
Join Fig. 6 z-3, functional chip 30 is loaded into the top of package substrate 10, the second lower surface 32 and upper surface of base plate
11 settings face-to-face, the first cofferdam 41 and the second lower surface 32, the first upper surface 21 cooperate and enclose to set to form cavity S, and
The alignment of metal column 51 fluting 43, scolding tin 52 and 51 mutual conduction of metal column.
Join Fig. 6 z-4, forms the first plastic packaging layer 60, the first plastic packaging far from the side of base lower surface 12 in package substrate 10
Layer 60 coats the second cofferdam 42 simultaneously and is exposed to outer surface area and functional chip 30, and the first plastic packaging layer 60 fills through-hole
13；
Join Fig. 6 z-5, forms third insulating layer 72 in the lower section of third electroplated layer 5323 and the second plastic packaging layer 61；
Join Fig. 6 z-6 to Fig. 6 z-10, is formed in the lower section of third insulating layer 72 and led by the hole on third insulating layer 72
The lower rewiring layer 533 of logical third electroplated layer 5323；
It is specific as follows:
Join Fig. 6 z-6, forms third hole 721 in 72 exposure and imaging of third insulating layer, third hole 721 exposes the
Three electroplated layers 5323；
Join Fig. 6 z-7, forms the 5th photoresist layer 85 in the lower section of third insulating layer 72；
Join Fig. 6 z-8, forms the 5th aperture 851 in 85 exposure and imaging of the 5th photoresist layer, the 5th aperture 851 exposes
Third hole 721 and third insulating layer 72；
Join Fig. 6 z-9, layer 533 is rerouted under being formed in the 5th aperture 851；
Join Fig. 6 z-10, removes the 5th photoresist layer 85.
Join Fig. 6 z-11 and Fig. 6 z-12, form cladding third insulating layer 72 and lower the 4th insulating layer 73 for rerouting layer 533,
4th insulating layer 73 exposes lower rewiring layer 533；
It is specific as follows:
Join Fig. 6 z-11, forms the 4th insulating layer 73 in the lower section of lower rewiring layer 533 and third insulating layer 72；
Join Fig. 6 z-12, the 4th hole 731 is formed in 73 exposure and imaging of the 4th insulating layer, under the 4th hole 731 exposes
Reroute layer 533.
Join Fig. 6 z-13, forms ball grid array 121 in being exposed to outer lower rewiring layer 533, i.e., in the 4th hole 731
Form ball grid array 121.
Other explanations of the production method of the encapsulation modular structure 100 of present embodiment can refer to above-mentioned Encapsulation Moulds agllutination
The explanation of structure 100, details are not described herein.
The cofferdam 40 of the utility model is located at the inside and outside of first electrode 211, and the lateral border in the second cofferdam 42 with
The lateral border of package substrate 10 flushes, and in other embodiments, cofferdam 40 may be alternatively located at the inside of first electrode 211, alternatively,
The lateral border in the second cofferdam 42 is flushed with the lateral border of functional chip 30, or, the lateral border in the second cofferdam 42 is located at function
Between the lateral border of chip 30 and the lateral border of package substrate 10 etc..
To sum up, present embodiment forms cavity S by setting cofferdam 40, it is possible to prevente effectively from encapsulating structure manufacturing process
In or external substance enters the normal use for inside cavity S and influencing filter chip 20 in encapsulating structure use process,
To improve the overall performance of encapsulation modular structure 100.
In addition, present embodiment utilizes encapsulation technology by two different chips (filter chip 20 and functional chip 30)
It is packaged in same package substrate 10, the highly integrated of multi-chip may be implemented, improves the utilization rate of package substrate 10, and then realize
The miniaturization of encapsulation modular structure 100.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiments of understanding.
Tool of the series of detailed descriptions listed above only for the feasible embodiment of the utility model
Body explanation, they are all without departing from made by the utility model skill spirit not to limit the protection scope of the utility model
Equivalent implementations or change should be included within the scope of protection of this utility model.
Claims (13)
1. a kind of multi-chip stacking encapsulation modular structure of flush type filter chip characterized by comprising
Package substrate, has the upper surface of base plate and base lower surface being oppositely arranged, and the package substrate has chamber；
Filter chip is set in the chamber, and the filter chip has the first upper surface and first being oppositely arranged
Lower surface, first upper surface and the upper surface of base plate are located at ipsilateral, and first upper surface has several first electricity
Pole；
Functional chip, is set to the top of the package substrate, the functional chip have the second upper surface being oppositely arranged and
Second lower surface, second lower surface are arranged face-to-face with the upper surface of base plate, and second lower surface is with several
Second electrode；
Several interconnection structures, for several first electrodes and several second electrodes to be connected.
2. encapsulation modular structure according to claim 1, which is characterized in that the functional chip is located at the upper of the chamber
Side, several first electrodes are arranged face-to-face with several second electrodes.
3. encapsulation modular structure according to claim 1, which is characterized in that the side of the base lower surface has several
External pin, the package substrate have several through-holes, the interconnection structure by the through-hole be connected the first electrode,
The second electrode and the external pin.
4. encapsulation modular structure according to claim 3, which is characterized in that the through-hole and the second electrode are mutual
Every distribution.
5. encapsulation modular structure according to claim 3, which is characterized in that the interconnection structure includes metal column, scolding tin
And electroplated layer structure, the metal column are connected to the lower section of the second electrode, electroplated layer structure conducting first electricity
Pole, and the external pin, institute is connected by the lower section that the through-hole extends to the package substrate in the electroplated layer structure
Scolding tin is stated for the metal column and the electroplated layer structure to be connected.
6. encapsulation modular structure according to claim 5, which is characterized in that the electroplated layer structure includes mutually electrically leading
Logical upper rewiring layer, intermediate wiring layer and lower rewiring layer, the upper rewiring layer are located at the top of the package substrate simultaneously
The first electrode is connected, the lower rewiring layer is located at the lower section of the package substrate and the external pin is connected, described
Intermediate wiring layer includes connected the first electroplated layer positioned at the upper surface of base plate, the second plating positioned at the through-hole wall
Layer and third electroplated layer positioned at the base lower surface, first electroplated layer connect the upper rewiring layer, the third
Electroplated layer connects the lower rewiring layer.
7. encapsulation modular structure according to claim 6, which is characterized in that the encapsulating structure includes being located at the substrate
First electricity is connected by the hole on first insulating layer for the first insulating layer above upper surface, the first upper surface
The upper rewiring layer of coating and the first electrode and connect the second of first insulating layer and second lower surface absolutely
Edge layer, the second insulating layer, which has, exposes the upper fluting for rerouting layer and accommodating scolding tin.
8. encapsulation modular structure according to claim 7, which is characterized in that first insulating layer and second insulation
Layer cooperatively forms cofferdam, and the cofferdam and second lower surface, the first upper surface cooperate and enclose and set to form cavity.
9. encapsulation modular structure according to claim 8, which is characterized in that the cofferdam includes being located at several first electrodes
First cofferdam of inside and the second cofferdam on the outside of several first electrodes, first cofferdam and second lower surface,
First upper surface cooperates and encloses and set to form cavity.
10. encapsulation modular structure according to claim 9, which is characterized in that second cofferdam is towards far from described first
The lateral border that the direction in cofferdam extends up to second cofferdam is flushed with the lateral border of the package substrate, and described second encloses
Weir exposes the through-hole.
11. encapsulation modular structure according to claim 9, which is characterized in that the encapsulation modular structure further includes being located at
First plastic packaging layer of side of the package substrate far from the base lower surface, the first plastic packaging layer coat described simultaneously
Two cofferdam are exposed to outer surface area and the functional chip, and the first plastic packaging layer fills the through-hole.
12. encapsulation modular structure according to claim 6, which is characterized in that the encapsulation modular structure includes cladding institute
It states the third insulating layer of third electroplated layer and base lower surface, the third is connected by the hole on the third insulating layer
Electroplated layer and the lower rewiring layer extended toward the lower surface direction of the third insulating layer and the cladding third insulating layer and
Lower the 4th insulating layer for rerouting layer, the external pin connects the lower rewiring layer, and the 4th insulating layer is sudden and violent
Reveal the external pin.
13. encapsulation modular structure according to claim 1, which is characterized in that the filter chip and the chamber
Gap, the base lower surface and first lower surface are provided with the second plastic packaging layer, first upper surface and the substrate
Upper surface flushes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821289576.4U CN208507673U (en) | 2018-08-10 | 2018-08-10 | The multi-chip stacking encapsulation modular structure of flush type filter chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821289576.4U CN208507673U (en) | 2018-08-10 | 2018-08-10 | The multi-chip stacking encapsulation modular structure of flush type filter chip |
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|---|---|
| CN208507673U true CN208507673U (en) | 2019-02-15 |
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ID=65300308
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108711569A (en) * | 2018-08-10 | 2018-10-26 | 付伟 | With the multichip packaging structure and preparation method thereof for accommodating filter chip chamber |
| CN113421876A (en) * | 2021-06-21 | 2021-09-21 | 广东省科学院半导体研究所 | Filter radio frequency module packaging structure and manufacturing method thereof |
-
2018
- 2018-08-10 CN CN201821289576.4U patent/CN208507673U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108711569A (en) * | 2018-08-10 | 2018-10-26 | 付伟 | With the multichip packaging structure and preparation method thereof for accommodating filter chip chamber |
| CN113421876A (en) * | 2021-06-21 | 2021-09-21 | 广东省科学院半导体研究所 | Filter radio frequency module packaging structure and manufacturing method thereof |
| CN113421876B (en) * | 2021-06-21 | 2023-01-17 | 广东省科学院半导体研究所 | Filter radio frequency module packaging structure and manufacturing method thereof |
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Effective date of registration: 20200618 Address after: 313200 No. 926 Changhong East Street, Fuxi Street, Deqing County, Huzhou City, Zhejiang Province (Mogan Mountain National High-tech Zone) Patentee after: Zhejiang Rongcheng Semiconductor Co., Ltd Address before: 215123 Jiangsu city Suzhou Industrial Park 99 Jinji Hu Road 99 Suzhou Nancheng NW-05 building 301 Patentee before: Fu Wei |
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