CN111952284A - Stack packaging structure and manufacturing method thereof - Google Patents

Stack packaging structure and manufacturing method thereof Download PDF

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Publication number
CN111952284A
CN111952284A CN202010625796.5A CN202010625796A CN111952284A CN 111952284 A CN111952284 A CN 111952284A CN 202010625796 A CN202010625796 A CN 202010625796A CN 111952284 A CN111952284 A CN 111952284A
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CN
China
Prior art keywords
chip
package
substrate
conductive circuit
interconnection
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Pending
Application number
CN202010625796.5A
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Chinese (zh)
Inventor
周海锋
沈锦新
赵华
张江华
周青云
吴昊平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN202010625796.5A priority Critical patent/CN111952284A/en
Publication of CN111952284A publication Critical patent/CN111952284A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to a stacked package structure and a manufacturing method thereof, wherein the package structure comprises a first package body (1) and a second package body (3), the first package body (1) at least comprises an interconnection chip (12) which is laterally and vertically mounted, and the first package body (1) and the second package body (3) are electrically connected through the interconnection chip (12). The whole packaging thickness of the invention is obviously reduced, and the requirement of high density and fine pitch can be met.

Description

Stack packaging structure and manufacturing method thereof
Technical Field
The invention relates to a stacked packaging structure and a manufacturing method thereof, belonging to the technical field of semiconductor packaging.
Background
Nowadays, electronic products are developing towards the trend of being short, small, light, thin and multifunctional, such as 5G smart phones, tablet computers, communication base stations, and the like, and the design of POP stacked packages with smaller volume, thinner thickness and high density has been widely applied to practical production based on the requirement of functions of portable electronic devices, but the traditional POP stacked packages generally achieve interconnection between packages through metal pillar conduction, and the package structure thereof has the following defects:
1. the number, height and diameter dimensions of the metal posts in the high-density package cannot meet the fine-pitch design due to the limitation of the electroplating process;
2. the line spacing in the high-density packaging body is reduced, but the design of the line is limited by the influence of the metal column process and cannot be flexible and changeable;
3. the excessive number of metal posts can increase the production cost, increase the process difficulty and reduce the packaging yield.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a stacked package structure and a manufacturing method thereof in view of the above prior art, so as to solve the problems of the prior art that the metal pillar process difficulty is increased, the package yield is low, and the production cost is high due to the fine pitch.
The technical scheme adopted by the invention for solving the problems is as follows: a stacked package structure comprises a first package body and a second package body, wherein the first package body at least comprises an interconnection chip which is laterally and vertically mounted, and the first package body is electrically connected with the second package body through the interconnection chip.
Optionally, the interconnection chip includes a Si substrate and at least one conductive circuit, the bottom of the conductive circuit is electrically connected to the first package body, and the top of the conductive circuit is electrically connected to the second package body.
Optionally, the interconnection chip is of a single-layer circuit structure, the upper surface of the Si substrate is provided with at least one conductive circuit, and the conductive circuits are spaced apart by the Si substrate.
Optionally, the conductive line of the interconnection chip is a straight line or a zigzag line.
Optionally, the interconnection chip is of a multilayer circuit structure, and at least one insulating layer and a plurality of conductive circuits are arranged above the conductive circuits.
Optionally, the interconnection chip is of a multilayer circuit structure, and the lower surface of the Si substrate is provided with at least one conductive circuit.
Optionally, the first package further includes a first functional chip and a second substrate, the first functional chip is mounted on the upper surface of the second substrate in a planar manner, the peripheries of the first functional chip and the interconnection chip are encapsulated with a first molding compound, and the back surface of the second substrate is provided with a second metal ball.
Optionally, the second package body includes a second functional chip and a first substrate, the second functional chip is attached to the first substrate, and a molding compound is encapsulated on the periphery of the second functional chip and the upper surface of the first substrate.
Optionally, the substrate includes a redistribution layer, and an insulating layer is coated on the periphery of the redistribution layer.
A method of manufacturing a package on package structure, the method comprising the steps of:
step one, taking a wafer;
step two, forming a conductive circuit on the surface of the wafer;
step three, cutting the wafer to form single interconnected chips;
step four, taking a carrier plate, and mounting a first functional chip and at least one interconnection chip on the carrier plate, wherein the first functional chip is mounted on a plane, and the interconnection chip is mounted on a side direction;
step five, encapsulating the first functional chip and the interconnection chip by using a first plastic packaging material;
step six, thinning the upper surface of the plastic packaging material until a conductive circuit on the side surface of the interconnected chip is exposed;
forming a first substrate on the upper surface of the plastic packaging material and above the conductive circuit;
step eight, mounting a second functional chip on the first substrate;
step nine, encapsulating the second functional chip by using a second plastic packaging material;
step ten, removing the carrier plate;
step eleven, forming a second substrate on the lower surface of the first plastic packaging material and below the conductive circuit;
and step twelve, performing ball planting on the back of the second substrate to obtain the stacked packaging structure.
Optionally, in the second step, the conductive lines extend to the edge of the chip, and after the chip is cut into single interconnected chips, the conductive lines are exposed from the side surface.
Optionally, in the second step, the conductive circuit is not exposed out of the edge of the chip, and the conductive circuit is exposed through a later-stage thinning process.
Optionally, the conductive traces in step two are single-layer conductive traces or multi-layer conductive traces.
Compared with the prior art, the invention has the advantages that:
1. according to the invention, the conductive circuit is manufactured through a chip manufacturing process, the lower-layer packaging body is electrically connected with the upper-layer packaging body through the conductive circuit on the interconnection chip in a lateral vertical mounting mode, and a redistribution circuit layer is formed through a rewiring process, so that the overall packaging thickness is obviously reduced, the conductive circuit design of the interconnection chip is flexible, and different point interconnection and multidimensional interconnection can be realized through different circuit designs;
2. the interconnection chip prepared by the invention is a conventional non-functional chip, the preparation process is mature, the whole stacking and packaging process is simple, the integral packaging yield can be improved, and the cost is lower;
3. according to the invention, the interconnection of the upper and lower packaging bodies can be realized by stacking and packaging the interconnection chips in a lateral vertical surface mounting manner, the Si chips are vertically interconnected, the occupied volume is small, the current transmission path is shorter, better electrical performance can be realized, and the requirement of high density and fine spacing can be realized.
Drawings
Fig. 1 is a schematic diagram of an SIP stack package structure according to the present invention.
Fig. 2A-2E are schematic diagrams of various embodiments of an interconnect die.
Fig. 3 to 12 are schematic diagrams illustrating steps of a manufacturing method of an SIP stack package structure according to the present invention.
Wherein:
first package 1
First functional chip 11
Interconnect chip 12
Si substrate 12.1
Conductive circuit one 12.2
First plastic package material 13
First substrate 2
First rewiring 21
First insulating layer 22
Second package 3
Second functional chip 31
First metal ball 32
Second molding compound 33
Second substrate 4
Second rewiring 41
Second insulating layer 42
Second metal ball 5
Conducting circuit two 6
Insulating layer 7
Conducting circuit three 8
Conductive trace four 9.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
As shown in fig. 1, the package on package structure according to the present invention includes a first package 1 and a second package 3, wherein the first package 1 includes at least one interconnection chip 12 mounted vertically and laterally, and the first package 1 and the second package 3 are electrically connected through the interconnection chip 12.
The interconnection chip 12 comprises a Si substrate 12.1 and a first conductive trace 12.2, wherein the bottom of the first conductive trace 12.2 is electrically connected with the first package body 1, and the top of the first conductive trace 12.2 is electrically connected with the second package body 3.
The first package body 1 further comprises a first functional chip 11 and a second substrate 4, the first functional chip 11 is mounted on the upper surface of the second substrate 4 in a planar mode, a first plastic package material 13 is packaged on the peripheries of the first functional chip 11 and the interconnection chip 12, and a second metal ball 5 is arranged on the back surface of the second substrate 4.
The second substrate 4 includes a second redistribution line 41, the periphery of the second redistribution line 41 is covered with a second insulating layer 42, and the first functional chip 11 and the interconnection chip 12 are electrically connected to the second redistribution line 41 respectively.
The second package 3 includes a second functional chip 31 and the first substrate 2, the second functional chip 31 is attached to the first substrate 2 through a first metal ball 32, and a second molding compound 33 is encapsulated around the second functional chip 31 and the first metal ball 32.
The first substrate 2 includes a first redistribution line 21, the periphery of the first redistribution line 21 is coated with a first insulating layer 22, and the interconnection chip 12 and the first metal ball 32 are electrically connected to the first redistribution line 21 respectively.
The first and second rewirings 21 and 41 include a plurality of layers of rewirings.
As shown in fig. 2A, the interconnect chip 12 has a single-layer circuit structure, the surface of the Si substrate 12.1 is provided with at least one conductive circuit one 12.2, and the conductive circuits one 12.2 are spaced apart from each other by the Si substrate 12.1.
As shown in fig. 2B and 2C, in order to better implement reasonable design and distribution of the circuit layout and implement the interconnection of the different points of the conductive traces and the interconnection and intercommunication of the multi-dimensional chip, the conductive trace one 12.2 on the surface of the interconnected chip may be designed as an inclined straight line or a zigzag line.
As shown in fig. 2D, the interconnection chip has a multilayer circuit structure, and an insulating layer 7 and a conductive circuit three 8 are further disposed above the conductive circuit one 12.2.
As shown in fig. 2E, the interconnection chip has a multilayer circuit structure, and the lower surface of the Si substrate 12.1 is provided with a four conductive circuit line 9.
Referring to fig. 3 to 12, the manufacturing method of the stacked package structure according to the present invention includes the following steps:
step one, taking a complete wafer;
forming a first conductive circuit on the surface of the wafer through processes of sputtering, electroplating, photoetching development, etching, photoresist removal and the like, wherein the first conductive circuit extends to the edge of a single chip and can be of a single-layer structure or a multi-layer structure;
cutting the wafer to form a single interconnection chip, and cutting the side surface of the interconnection chip to expose the conductive circuit;
step four, referring to fig. 3 and fig. 4, a carrier plate is taken, and a first functional chip and at least one interconnection chip are mounted on the carrier plate, wherein the first functional chip is mounted on a plane, and the interconnection chip is mounted vertically in a lateral direction;
step five, referring to fig. 5, the first functional chip and the interconnection chip are encapsulated by a plastic package material;
step six, referring to fig. 6, grinding and thinning the upper surface of the plastic packaging material until the conductive circuit on the side surface of the interconnected chip is exposed;
seventhly, referring to fig. 7, forming a first substrate on the upper surface of the plastic package material through a rewiring process, wherein the first substrate is electrically connected with the conductive circuit;
step eight, referring to fig. 8, mounting a second functional chip on the first substrate;
step nine, referring to fig. 9, encapsulating the second functional chip;
step ten, referring to fig. 10, removing the carrier plate at the bottom;
step eleven, referring to fig. 11, forming a second substrate on the lower surface of the plastic package material through a rewiring process, wherein the second substrate is electrically connected with the conductive circuit;
step twelve, referring to fig. 12, ball mounting is performed on the back surface of the second substrate to form solder balls, so as to obtain a stacked package structure.
In the embodiment, the lateral conduction connection of the interconnected chips is realized through thinning and rewiring processes, the overall thickness of the stacked package is reduced, and the stacked package has better electrical property;
furthermore, in the high-density chip stack package, in order to ensure that the dense-pitch line width and the line pitch do not cause short circuit, the first conducting circuit is not exposed at the edge of the chip when the interconnected chip is processed, then the conducting circuit is exposed on the surface of the package body in the thinning process, and the functional chip and the interconnected chip are connected and conducted through the RDL redistribution line layer.
In addition, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the protection scope of the claims of the present invention.

Claims (6)

1. A package on package structure, comprising: a stacked package structure comprises a first package body and a second package body, wherein the first package body at least comprises an interconnection chip which is laterally and vertically mounted, and the first package body is electrically connected with the second package body through the interconnection chip.
2. The package on package structure of claim 1, wherein: the interconnection chip comprises a Si substrate and at least one conductive circuit, the bottom of the conductive circuit is electrically connected with the first packaging body, and the top of the conductive circuit is electrically connected with the second packaging body.
3. The package on package structure of claim 2, wherein: the interconnection chip is of a single-layer circuit structure, at least one conductive circuit is arranged on the upper surface of the Si substrate, and the conductive circuits are spaced by the Si substrate.
4. The package on package structure of claim 2, wherein: the interconnection chip is of a multilayer circuit structure, and at least one insulating layer and one conductive circuit are arranged above the conductive circuit.
5. The package on package structure of claim 2, wherein: the interconnection chip is of a multilayer circuit structure, and the lower surface of the Si substrate is provided with at least one conductive circuit.
6. A method for manufacturing a package on package structure, the method comprising the steps of:
step one, taking a wafer;
step two, forming a conductive circuit on the surface of the wafer;
cutting the wafer to form a single interconnection chip, and cutting the side surface of the interconnection chip to expose the conductive circuit;
step four, taking a carrier plate, and mounting a first functional chip and at least one interconnection chip on the carrier plate, wherein the first functional chip is mounted on a plane, and the interconnection chip is mounted on a side direction;
step five, encapsulating the first functional chip and the interconnection chip by using a first plastic packaging material;
step six, thinning the upper surface of the plastic packaging material until a conductive circuit on the side surface of the interconnected chip is exposed;
forming a first substrate on the upper surface of the plastic packaging material and above the conductive circuit;
step eight, mounting a second functional chip on the first substrate;
step nine, encapsulating the second functional chip by using a second plastic packaging material;
step ten, removing the carrier plate;
step eleven, forming a second substrate on the lower surface of the first plastic packaging material and below the conductive circuit;
and step twelve, performing ball planting on the back of the second substrate to obtain the stacked packaging structure.
CN202010625796.5A 2020-07-01 2020-07-01 Stack packaging structure and manufacturing method thereof Pending CN111952284A (en)

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Application Number Priority Date Filing Date Title
CN202010625796.5A CN111952284A (en) 2020-07-01 2020-07-01 Stack packaging structure and manufacturing method thereof

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Application Number Priority Date Filing Date Title
CN202010625796.5A CN111952284A (en) 2020-07-01 2020-07-01 Stack packaging structure and manufacturing method thereof

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CN111952284A true CN111952284A (en) 2020-11-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117498825A (en) * 2023-12-29 2024-02-02 合肥矽迈微电子科技有限公司 Semiconductor packaging structure and packaging method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106653703A (en) * 2015-11-04 2017-05-10 美光科技公司 Package-on-package structure
CN109427759A (en) * 2017-08-29 2019-03-05 华为技术有限公司 A kind of chip-packaging structure and preparation method thereof, electronic equipment
CN208655635U (en) * 2018-09-20 2019-03-26 蔡亲佳 Stack embedded packaging structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106653703A (en) * 2015-11-04 2017-05-10 美光科技公司 Package-on-package structure
CN109427759A (en) * 2017-08-29 2019-03-05 华为技术有限公司 A kind of chip-packaging structure and preparation method thereof, electronic equipment
CN208655635U (en) * 2018-09-20 2019-03-26 蔡亲佳 Stack embedded packaging structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117498825A (en) * 2023-12-29 2024-02-02 合肥矽迈微电子科技有限公司 Semiconductor packaging structure and packaging method

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Application publication date: 20201117

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