CN115101519A - Three-dimensional stacked fan-out type packaging structure and preparation method thereof - Google Patents
Three-dimensional stacked fan-out type packaging structure and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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Abstract
The invention provides a three-dimensional stacked fan-out type packaging structure and a preparation method thereof. The transmission chip is arranged on the lower surface of the silicon switching layer, and the chip stacking body comprising a plurality of chips is arranged on the upper surface of the silicon switching layer, so that the integration level of the whole structure is improved, the packaging volume is reduced, the substrate area is saved, and a large number of chips can be accommodated on a small-area substrate; the stacked design is adopted to generate overlapping among the chips, which is also beneficial to heat transfer, thereby improving the heat dissipation effect. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a three-dimensional stacked fan-out type packaging structure and a preparation method thereof.
Background
Packaging has developed rapidly in recent years, and flip chip electronic packaging has occupied 60-70% of the IC package market as the mainstream packaging form. For high-end flip chip packages, such as CPUs for servers, AI, and HPC, multi-chip integration is required, which requires multiple chips to be placed on one substrate. The flip-chip fan-out package structure includes various chip types including a core chip (core die), an IO chip (IO die), a cache/SRAM chip, a structural chip, and the like. As the number of cores and functional complexity of such high performance chips increases, more and more chips need to be integrated onto a single substrate. As shown in fig. 1 and 2, in the prior art, the transmitting chip 122 and the first chip 201 are formed on the substrate 302, and the transmitting chip 122 and the first chip 201 are sequentially laid on the surface of the substrate 302, so as to accommodate a larger number of chips, it is necessary to increase the area of the substrate, which also urges the substrate size to be from 50 × 50mm 2 Rapidly increased to 100 x 100mm 2 . However, as the size of the substrate increases, the cost and the defective rate increase, which hinders the application of the large-sized substrate.
Therefore, a package structure is needed to accommodate a larger number of chips under the condition of the existing small-sized substrate.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a three-dimensional stacked fan-out package structure, comprising:
the lower surface of the silicon switching layer is bonded with a transmission chip;
the coating layer coats the side wall of the transmission chip, and a first conductive column penetrating through the coating layer is arranged in the coating layer;
a chip stacked body bonded to an upper surface of the silicon via layer, the chip stacked body including 2 or more chips stacked in a vertical direction, signal transmission being performed between adjacent chip stacked bodies through the transmission chip;
a substrate disposed below the cladding layer;
and a rewiring layer or a metal welding ball electrically connected with the first conductive column is further arranged between the coating layer and the substrate, so that the substrate is electrically connected with the silicon switching layer.
Preferably, the redistribution layer includes a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer.
Preferably, the rewiring layer is bonded to the substrate through a bonding glue layer; and a second conductive column is arranged in the bonding adhesive layer, and the substrate is electrically connected with the silicon switching layer sequentially through the second conductive column, the metal wiring layer and the first conductive column.
Preferably, the transmission chip is electrically connected to the substrate through the redistribution layer and the second conductive pillar.
Preferably, when the coating layer is connected with the substrate through a metal solder ball, the coating layer also coats the lower surface of the transmission chip, and the substrate is electrically connected with the silicon switching layer through the metal solder ball and the first conductive column in sequence.
The invention also provides a preparation method of the three-dimensional stacked fan-out type packaging structure, which comprises the following steps:
s1: providing a silicon switching layer, wherein a transmission chip is bonded on the lower surface of the silicon switching layer;
s2: forming a coating layer on the lower surface of the silicon switching layer, wherein the coating layer coats the side wall of the transmission chip and is internally provided with a first conductive post penetrating through the coating layer;
s3: bonding a chip stacked body on the upper surface of the silicon switching layer, wherein the chip stacked body comprises more than 2 chips stacked along the vertical direction, and signal transmission is carried out between the adjacent chip stacked bodies through the transmission chip;
s4: connecting a substrate below the coating layer;
and a rewiring layer or a metal solder ball electrically connected with the first conductive column is further formed between the coating layer and the substrate, so that the substrate is electrically connected with the silicon transfer layer.
Preferably, after step S3, the redistribution layer is formed on the lower surface of the cladding layer, and the redistribution layer includes a routing dielectric layer and a metal routing layer located in the routing dielectric layer.
Preferably, after the rewiring layer is formed, the rewiring layer is bonded to the substrate through a bonding glue layer; and a second conductive column is arranged in the bonding adhesive layer, and the substrate is electrically connected with the silicon switching layer sequentially through the second conductive column, the metal wiring layer and the first conductive column.
Preferably, the transmission chip is electrically connected to the substrate through the redistribution layer and the second conductive pillar.
Preferably, in step S2, the coating layer further coats the lower surface of the transmission chip; the coating layer is connected with the substrate through a metal solder ball, and the substrate is electrically connected with the silicon switching layer through the metal solder ball and the first conductive column in sequence.
As described above, the present invention provides a three-dimensional stacked fan-out package structure and a method for manufacturing the same, wherein the fan-out package structure sequentially includes a chip stacked body, a silicon via layer, a transmission chip, a cladding layer, and a substrate from top to bottom, and a rewiring layer or a metal solder ball is disposed to electrically connect the silicon via layer and the substrate for signal transmission. The transmission chip is arranged on the lower surface of the silicon switching layer, and the chip stacking body containing a plurality of chips is arranged on the upper surface of the silicon switching layer, so that the integration level of the whole structure is improved, the packaging volume is reduced, the substrate area is saved, and a large number of chips can be accommodated on a small-area substrate; the stacked design is adopted to enable the chips to be overlapped, so that heat transfer is facilitated, and the heat dissipation effect is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
Drawings
Fig. 1 is a schematic top view of a chip arrangement in the prior art.
Fig. 2 is a schematic diagram of a side view of a chip arrangement in the prior art.
FIG. 3 is a schematic diagram of a silicon interposer.
FIG. 4 is a schematic diagram showing the structure of the clad layer.
Fig. 5 is a schematic view of a structure in which a first chip is bonded to a wafer.
Fig. 6 shows a schematic diagram of a chip stack structure formed by dicing a wafer.
Fig. 7 is a schematic diagram showing a structure of forming a rewiring layer.
Fig. 8 shows a schematic diagram of the structure after cutting.
Fig. 9 is a schematic view of a structure bonded to a substrate.
Fig. 10 is a schematic view showing the arrangement of the metal solder balls.
FIG. 11 is a schematic top view of a fan-out package structure according to the present invention.
Description of the element reference numerals: 101 a silicon transition layer; 102 a coating layer; 121 a first conductive pillar; 122 a transmission chip; 302 a substrate; 201 a first chip; 202 a second chip; 103 rewiring layer; 311 a metal solder ball; 131 a metal wiring layer; 132 a wiring dielectric layer; 301 bonding the adhesive layer; 312 second conductive pillars; 2021 wafer.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
The embodiment provides a preparation method of a three-dimensional stacked fan-out package structure, which comprises the following steps:
s1: providing a silicon transfer layer 101, wherein a transmission chip 122 is bonded to the lower surface of the silicon transfer layer 101, as shown in fig. 3;
s2: forming a cladding layer 102 on the lower surface of the silicon interposer 101, wherein the cladding layer 102 covers the sidewall of the transmission chip 122, and a first conductive pillar 121 penetrating through the cladding layer 102 is disposed in the cladding layer 102, as shown in fig. 4;
s3: bonding a chip stacked body on the upper surface of the silicon transit layer 101, wherein the chip stacked body comprises more than 2 chips stacked along the vertical direction, and signal transmission is performed between adjacent chip stacked bodies through the transmission chip 122, as shown in fig. 7;
s4: a substrate 302 is disposed below the cladding layer 102, as shown in fig. 9 and 10.
A redistribution layer 103 or a metal solder ball 311 electrically connected to the first conductive pillar 121 is further formed between the cladding layer 102 and the substrate 302, so that the substrate 302 and the silicon interposer 101 are electrically connected.
Specifically, the silicon interposer 101 is a silicon interposer, which has TSV through holes inside a silicon layer as conductive paths for an upper chip stack and a lower device, and the transmission chip 122 may be an IO chip for transmission of IO signals between upper adjacent chip stacks. The chip stack in this embodiment includes a first chip 201 and a second chip 202, the first chip 201 may be a core processing chip (core die), and the second chip 202 may be a cache die (cache die), and it should be understood that the types of the first chip 201 and the second chip 202 are not limited thereto, and the chips in the chip stack are not limited to 2 layers, and may also be 3 layers, 4 layers … …. There are electrical connections between the individual chips in the chip stack for signal transmission, such as between the first chip 201 and the second chip 202. As shown in fig. 11, the transmitting chip 122 may be used for signal transmission between 2 adjacent chip stacks, or may be used for signal transmission between 4 or more adjacent chip stacks, which is not limited herein. The substrate 302 may be a glass substrate, a ceramic substrate, a metal substrate, an organic polymer substrate, or the like. In addition, after step S3, a cutting process (i.e., Singulation) may be further included to separate the unwanted parts by cutting, as shown in fig. 8.
The transmission chip 122 is arranged on the lower surface of the silicon switching layer 101, and the chip stacked body comprising a plurality of chips is arranged on the upper surface of the silicon switching layer 101, so that the integration level of the whole structure is improved, and a larger number of chips can be accommodated on a small-area substrate. In addition, the stacked design is adopted, so that the chips are overlapped, and the heat transfer is facilitated, thereby improving the heat dissipation effect.
Specifically, as shown in fig. 5 to 6, the first chip 201 is bonded to the wafer 2021, and then the wafer 2021 is cut (i.e., Singulation) to separate unnecessary portions, thereby finally forming the chip stack.
Optionally, in step S4, in addition to the electrical connection through the first conductive pillars 121, the substrate 302 and the silicon interposer 101 are also connected through a redistribution layer 103 or a metal solder ball 311, as shown in fig. 9-10.
Optionally, as shown in fig. 7, after step S3, the redistribution layer 103 is formed on the lower surface of the cladding layer 102, where the redistribution layer 103 includes a routing dielectric layer 132 and a metal routing layer 131 located in the routing dielectric layer 132. The wiring dielectric layer 132 is made of one or a combination of more than two of the group consisting of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer 131 includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium. The materials, the number of layers and the distribution morphology of the wiring dielectric layer 132 and the metal wiring layer 131 can be set according to the specific situation of the semiconductor chip, and are not limited herein.
Further, as shown in fig. 9, after the redistribution layer 103 is formed, the redistribution layer 103 is bonded to the substrate 302 through a bonding glue layer 301. A second conductive pillar 312 is disposed in the bonding adhesive layer 301, and the substrate 302 is electrically connected to the silicon interposer layer 101 sequentially through the second conductive pillar 312, the metal wiring layer 131, and the first conductive pillar 121. Optionally, the transmission chip 122 may also be electrically connected to the substrate 302 through the redistribution layer 103 and the second conductive pillar 312. The first conductive pillars 121 and the second conductive pillars 312 may be made of one or more of copper, aluminum, nickel, gold, silver, tin, and titanium, and the cladding layer 102 and the bonding glue layer 301 may be made of one or a combination of polyimide, silica gel, and epoxy resin.
Optionally, in step S2, the cover layer 102 further covers the lower surface of the transmission chip 122 to form a protection, that is, the thickness of the cover layer 102 is greater than that of the transmission chip 122. As shown in fig. 10, after step S3, the cladding layer 102 and the substrate 302 are connected by a metal solder ball 311, and the substrate 302 is electrically connected to the silicon interposer 101 by the metal solder ball 311, the first conductive pillar 121, and the like in sequence. Besides the metal solder balls 311 for realizing electrical connection, a certain gap can be ensured between the cladding layer 102 and the substrate 302. The material of the metal solder ball 311 may be one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more of the above materials.
Based on the above manufacturing method, this embodiment further provides a fan-out package structure stacked in three dimensions, as shown in fig. 9 to 10, where the fan-out package structure includes:
a silicon transfer layer 101, wherein a transmission chip 122 is bonded on the lower surface of the silicon transfer layer 101;
the cladding layer 102, the cladding layer 102 cladding the sidewall of the transmission chip 122, and a first conductive pillar 121 penetrating through the cladding layer 102 is disposed in the cladding layer 102;
a chip stacked body bonded to the upper surface of the silicon interposer layer 101, the chip stacked body including 2 or more chips stacked in a vertical direction, and signal transmission between adjacent chip stacked bodies is performed through the transmission chip 122;
a substrate 302, the substrate 302 disposed below the cladding layer 102;
and a rewiring layer or a metal welding ball electrically connected with the first conductive column is further arranged between the coating layer and the substrate, so that the substrate is electrically connected with the silicon switching layer.
Specifically, the silicon interposer 101 is a silicon interposer, which is provided with TSV inside a silicon layer as a conductive channel between an upper chip stack and a lower device, and the transmission chip 122 may be an IO chip for transmission of IO signals between upper adjacent chip stacks. The chip stack in this embodiment includes a first chip 201 and a second chip 202, the first chip 201 may be a core processing chip (core die), and the second chip 202 may be a cache chip (cache die), and it should be understood that the types of the first chip 201 and the second chip 202 are not limited thereto, and the chips in the chip stack are not limited to 2 layers, and may also be 3 layers, 4 layers … …. There are electrical connections between the individual chips in the chip stack for signal transmission, such as between the first chip 201 and the second chip 202. As shown in fig. 11, the transmitting chip 122 may be used for signal transmission between 2 adjacent chip stacks, or may be used for signal transmission between 4 or more adjacent chip stacks, which is not limited herein. The substrate 302 may be a glass substrate, a ceramic substrate, a metal substrate, an organic polymer substrate, or the like.
The transmission chip 122 is arranged on the lower surface of the silicon switching layer 101, and the chip stacked body comprising a plurality of chips is arranged on the upper surface of the silicon switching layer 101, so that the integration level of the whole structure is improved, and a larger number of chips can be accommodated on a small-area substrate. In addition, the stacked design is adopted, so that the chips are overlapped, and the heat transfer is facilitated, thereby improving the heat dissipation effect.
Optionally, the substrate 302 and the silicon interposer 101 are electrically connected through the first conductive pillars 121, and are also connected through a redistribution layer 103 or a metal solder ball 311.
Optionally, as shown in fig. 9, a redistribution layer 103 is formed on the lower surface of the cladding layer 102, where the redistribution layer 103 includes a routing dielectric layer 132 and a metal routing layer 131 located in the routing dielectric layer 132. The wiring dielectric layer 132 is made of one or a combination of more than two of the group consisting of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the material of the metal wiring layer 131 includes one or a combination of two or more of the group consisting of copper, aluminum, nickel, gold, silver, and titanium. The materials, the number of layers and the distribution morphology of the wiring dielectric layer 132 and the metal wiring layer 131 can be set according to the specific situation of the semiconductor chip, and are not limited herein.
Further, the redistribution layer 103 is bonded to the substrate 302 through a bonding glue layer 301. A second conductive pillar 312 is disposed in the bonding adhesive layer 301, and the substrate 302 is electrically connected to the silicon interposer layer 101 sequentially through the second conductive pillar 312, the metal wiring layer 131, and the first conductive pillar 121. Optionally, the transmission chip 122 may also be electrically connected to the substrate 302 through the redistribution layer 103 and the second conductive pillar 312. The first conductive pillars 121 and the second conductive pillars 312 may be made of one or more of copper, aluminum, nickel, gold, silver, tin, and titanium, and the cladding layer 102 and the bonding glue layer 301 may be made of one or a combination of polyimide, silica gel, and epoxy resin.
Optionally, as shown in fig. 10, the cladding layer 102 further covers the lower surface of the transmission chip 122 to form protection, that is, the thickness of the cladding layer 102 is greater than that of the transmission chip 122. The cladding layer 102 and the substrate 302 are connected through a metal solder ball 311, and the substrate 302 is electrically connected with the silicon transition layer 101 through the metal solder ball 311, the first conductive pillar 121 in sequence. Besides being used for realizing electrical connection, the metal solder balls 311 can also ensure a certain gap between the cladding layer 102 and the substrate 302. The material of the metal solder ball 311 may be one of copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more of the above materials.
In summary, the invention provides a three-dimensional stacked fan-out package structure and a method for manufacturing the same, the fan-out package structure sequentially includes a chip stacked body, a silicon via layer, a transmission chip, a cladding layer and a substrate from top to bottom, and the electrical connection between the silicon via layer and the substrate is realized by arranging a rewiring layer or a metal solder ball, so as to perform signal transmission. The transmission chip is arranged on the lower surface of the silicon switching layer, and the chip stacking body containing a plurality of chips is arranged on the upper surface of the silicon switching layer, so that the integration level of the whole structure is improved, the packaging volume is reduced, the substrate area is saved, and a large number of chips can be accommodated on a small-area substrate; the stacked design is adopted to enable the chips to be overlapped, so that heat transfer is facilitated, and the heat dissipation effect is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A three-dimensional stacked fan-out package structure, the fan-out package structure comprising:
the lower surface of the silicon switching layer is bonded with a transmission chip;
the coating layer coats the side wall of the transmission chip, and a first conductive column penetrating through the coating layer is arranged in the coating layer;
a chip stacked body bonded to an upper surface of the silicon via layer, the chip stacked body including 2 or more chips stacked in a vertical direction, signal transmission being performed between adjacent chip stacked bodies through the transmission chip;
a substrate disposed below the cladding layer;
a rewiring layer or a metal solder ball electrically connected with the first conductive column is further arranged between the coating layer and the substrate, so that the substrate is electrically connected with the silicon switching layer.
2. The fan-out package structure of claim 1, wherein the re-routing layer comprises a routing dielectric layer and a metal routing layer within the routing dielectric layer.
3. The fan-out package structure of claim 2, wherein the redistribution layer is bonded to the substrate with a layer of bonding glue; and a second conductive column is arranged in the bonding adhesive layer, and the substrate is electrically connected with the silicon switching layer sequentially through the second conductive column, the metal wiring layer and the first conductive column.
4. The fan-out package structure of claim 3, wherein the transmission chip is electrically connected to the substrate through the redistribution layer and the second conductive pillar.
5. The fan-out package structure of claim 1, wherein when the cladding layer is connected to the substrate through a metal solder ball, the cladding layer further wraps a lower surface of the transmission chip, and the substrate is electrically connected to the silicon interposer layer sequentially through the metal solder ball and the first conductive pillar.
6. A preparation method of a three-dimensional stacked fan-out type packaging structure is characterized by comprising the following steps:
s1: providing a silicon switching layer, wherein a transmission chip is bonded on the lower surface of the silicon switching layer;
s2: forming a coating layer on the lower surface of the silicon switching layer, wherein the coating layer coats the side wall of the transmission chip and is internally provided with a first conductive post penetrating through the coating layer;
s3: bonding a chip stacked body on the upper surface of the silicon switching layer, wherein the chip stacked body comprises more than 2 chips stacked along the vertical direction, and signal transmission is carried out between the adjacent chip stacked bodies through the transmission chip;
s4: connecting a substrate below the coating layer;
and a rewiring layer or a metal solder ball electrically connected with the first conductive column is further formed between the coating layer and the substrate, so that the substrate is electrically connected with the silicon transfer layer.
7. The method according to claim 6, wherein after step S3, the redistribution layer is formed on the lower surface of the encapsulation layer, and the redistribution layer comprises a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer.
8. The manufacturing method according to claim 7, wherein after the rewiring layer is formed, the rewiring layer is bonded to the substrate through a bonding paste layer; and a second conductive column is arranged in the bonding adhesive layer, and the substrate is electrically connected with the silicon switching layer sequentially through the second conductive column, the metal wiring layer and the first conductive column.
9. The method according to claim 8, wherein the transmission chip is electrically connected to the substrate through the redistribution layer and the second conductive pillar.
10. The manufacturing method according to claim 6, wherein in step S2, the clad layer further covers a lower surface of the transmission chip; the coating layer is connected with the substrate through a metal welding ball, and the substrate is electrically connected with the silicon switching layer through the metal welding ball, the first conductive column and the silicon switching layer in sequence.
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| CN202211037844.4A CN115101519A (en) | 2022-08-29 | 2022-08-29 | Three-dimensional stacked fan-out type packaging structure and preparation method thereof |
| PCT/CN2023/099289 WO2024045758A1 (en) | 2022-08-29 | 2023-06-09 | Three-dimensional stacked fan-out package structure and preparation method therefor |
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| CN202211037844.4A CN115101519A (en) | 2022-08-29 | 2022-08-29 | Three-dimensional stacked fan-out type packaging structure and preparation method thereof |
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| WO (1) | WO2024045758A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2024045758A1 (en) * | 2022-08-29 | 2024-03-07 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional stacked fan-out package structure and preparation method therefor |
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| KR102663810B1 (en) * | 2016-12-30 | 2024-05-07 | 삼성전자주식회사 | electronic device package |
| CN114171469A (en) * | 2021-12-30 | 2022-03-11 | 长电集成电路(绍兴)有限公司 | Wafer-level fan-out multi-chip packaging structure and preparation method thereof |
| CN115101519A (en) * | 2022-08-29 | 2022-09-23 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional stacked fan-out type packaging structure and preparation method thereof |
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| US20190229104A1 (en) * | 2004-06-30 | 2019-07-25 | Renesas Electronics Corporation | Semiconductor device |
| CN105518860A (en) * | 2014-12-19 | 2016-04-20 | 英特尔Ip公司 | Stack type semiconductor device package with improved interconnection bandwidth |
| CN107564825A (en) * | 2017-08-29 | 2018-01-09 | 睿力集成电路有限公司 | A kind of chip double-side encapsulating structure and its manufacture method |
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| WO2024045758A1 (en) * | 2022-08-29 | 2024-03-07 | 盛合晶微半导体(江阴)有限公司 | Three-dimensional stacked fan-out package structure and preparation method therefor |
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