CN117316907A - Wafer-level non-TSV 3D stacked packaging structure and method - Google Patents

Wafer-level non-TSV 3D stacked packaging structure and method Download PDF

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Publication number
CN117316907A
CN117316907A CN202311613617.6A CN202311613617A CN117316907A CN 117316907 A CN117316907 A CN 117316907A CN 202311613617 A CN202311613617 A CN 202311613617A CN 117316907 A CN117316907 A CN 117316907A
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China
Prior art keywords
chip unit
layer
chip
tsv
copper column
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CN202311613617.6A
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Inventor
张黎
张宇锋
龚嘉明
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Zhejiang Hexin Integrated Circuit Co ltd
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Zhejiang Hexin Integrated Circuit Co ltd
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Priority to CN202311613617.6A priority Critical patent/CN117316907A/en
Publication of CN117316907A publication Critical patent/CN117316907A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view

Abstract

The invention discloses a wafer-level non-TSV 3D stacking packaging structure and a method, wherein the wafer-level non-TSV 3D stacking packaging structure comprises a substrate and a plurality of chip unit layers which are stacked, all the chip unit layers are mutually stacked and are arranged on the substrate; the chip unit layer comprises at least one inverted chip unit, a plastic sealing layer is arranged on the outer side of the chip unit, a rewiring layer is arranged between adjacent chip unit layers, and the front side of each chip unit is communicated with the side copper column through the rewiring layer. According to the invention, the wafer-level packaging of the non-TSV is adopted, a substrate is not required to be arranged between adjacent chip units, and interconnection is realized by using a PI/RDL process, so that the thickness of the chip is thinner and the electrical performance loss is smaller; the copper columns on the back and the side of the chip are thinned synchronously, so that an ultrathin structure is realized, the minimum thickness of the chip can reach 20um level, and the overall packaging thickness can be controlled.

Description

Wafer-level non-TSV 3D stacked packaging structure and method
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a wafer-level non-TSV 3D stacking packaging structure and method.
Background
Conventional through silicon via-free 3D (non-TSV 3D ) stack packaging technology is a technology that stacks multiple chips or components in a vertical direction. This technique enables the transmission of signals and power by using electrical and mechanical connections between the chips while maintaining a compact package size.
The traditional non-TSV 3D stacking package is stacked by a substrate in a metal wire bonding or flip-chip technology or a combination of the metal wire bonding and the flip-chip technology, and large grid array package (LGA)/ball grid array package (BGA) substrate operation is carried out singly, so that the operation efficiency is not high. Meanwhile, since a plurality of chips need to be stacked in a vertical direction by means of a substrate, the packaged chips have a large thickness, substantially above 80um, which may result in a long signal transmission distance, thereby increasing signal transmission delay and power consumption.
Meanwhile, the manufacturing cost of the conventional non-TSV 3D stack packaging technology is high. Since a plurality of chips or components need to be stacked together in a vertical direction, a high-precision assembly process and an expensive packaging material need to be used. In addition, it is necessary to make a connector such as a pin or a terminal to make an electrical connection, which also increases the cost of the package.
Disclosure of Invention
In order to solve the above problems, the invention provides a wafer-level non-TSV 3D stacked package structure and a method thereof, which have low cost and high operation efficiency, and can reduce the thickness of a chip and reduce the electrical property loss.
For this purpose, the technical scheme of the invention is as follows: a wafer level non-TSV 3D stacked package structure comprises a substrate and a plurality of chip unit layers which are stacked, wherein all the chip unit layers are stacked together and are arranged on the substrate; the chip unit layer comprises at least one inverted chip unit, a plastic sealing layer is arranged on the outer side of the chip unit, a rewiring layer is arranged between adjacent chip unit layers, and the front side of each chip unit is communicated with the side copper column through the rewiring layer.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: the chip unit comprises a chip body, wherein the front surface of the chip body is provided with solder bumps, and the solder bumps are electrically connected with the side copper columns through the rewiring layer.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: a first rewiring layer is arranged below the first chip unit layer, and a first copper column is arranged on the first rewiring layer; the first chip unit layer comprises at least one first chip unit, the first chip unit is inverted on the first rewiring layer, the first plastic sealing layer covers the first chip unit and the first copper column, and the first plastic sealing layer, the back surface of the first chip unit and the first copper column are thinned synchronously.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: a second redistribution layer is arranged below the second chip unit layer, and a second copper column is arranged on the second redistribution layer; the second chip unit layer comprises at least one second chip unit which is inverted on the second redistribution layer; and a second plastic sealing layer is arranged on the outer side of the second chip unit, covers the second chip unit and the second copper column, and is thinned synchronously with the back of the second chip unit and the second copper column.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: the top chip unit layer is provided with a third wiring layer, the third wiring layer is provided with welding spots, and the welding spots are formed by ball implantation or electroplating.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: a plurality of second redistribution layers are arranged between the adjacent chip unit layers, and a dielectric layer is arranged between the adjacent second redistribution layers.
The other technical scheme of the invention is as follows: the wafer-level non-TSV 3D stacking packaging method comprises the following steps:
1) Preparing a plurality of chip units: finishing wafer level packaging on the front surface of the silicon wafer, manufacturing solder bumps, and grinding and scribing the silicon wafer to obtain a chip unit;
2) Preparing a substrate: manufacturing a first rewiring layer and a first copper column on the front surface of the substrate;
3) Inverting at least one first chip unit on a first rewiring layer of the substrate, wherein the front surface of the first chip unit is communicated with the first copper column through the first rewiring layer;
4) Carrying out plastic package on the first chip unit, wherein the plastic package covers the first chip unit and the first copper column;
5) Grinding the front surface of the substrate to expose the first copper column and the back surface of the first chip unit to form a first chip unit layer;
6) Disposing a second redistribution layer and a second copper pillar over the first chip unit layer;
7) Inverting at least one second chip unit on the second redistribution layer, wherein the front surface of the second chip unit is communicated with the second copper column through the second redistribution layer;
8) Repeating the steps 4) to 6) to form a second chip unit layer;
9) Repeating the steps 7) to 8), and stacking a plurality of chip unit layers;
10 After the stacking quantity reaches the requirement, performing ball implantation or electroplating process above the topmost chip unit layer;
11 And (3) carrying out post-treatment on the packaging body obtained in the step 10) to obtain the qualified product chip.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: in the step 1), all the chip units may be the same type of chip or different types of chips.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: and 5) grinding, and thinning the chip unit to 20-25 mu m.
The above-mentioned scheme is based on and is a preferable scheme of the above-mentioned scheme: in the step 6), if the back surface of the chip unit is provided with an electrode, the electrode may be led out through the second redistribution layer.
Compared with the prior art, the invention has the beneficial effects that:
by adopting the wafer level packaging of the non-TSV, a substrate is not required to be arranged between adjacent chip units, and interconnection is realized by using a PI/RDL process, so that the thickness of the chip is thinner and the electrical performance loss is smaller;
after the chip unit is inverted, a wafer-level bottom filling process is adopted to realize complete filling of the back surface of the chip unit; the back of the chip unit can be directly covered with a wiring insulating material without an epoxy resin type EMC material; meanwhile, the back of the chip unit can be conducted, and if the back of the chip unit is an electrode, the electrode can be conducted out through RDL;
the thickness of the chip is adopted for flip-chip mounting by adopting a standard process, copper columns on the back surface and the side edges of the chip are thinned synchronously, so that an ultrathin structure is realized, the minimum thickness of the chip can reach 20um, the thickness of the whole package can be controlled, or more chip units can be stacked under the same thickness, and more functions are realized;
the multi-layer chip units can be stacked based on the product requirement, the same layer of chip unit layers can be tiled with a plurality of chip units, the chip units can be the same chip, different types of chips can be selected, diversified functional design is realized, more use requirements are met, and the universality is strong.
Drawings
Further details are provided below in connection with the drawings and the embodiments of the invention.
Fig. 1 is a schematic diagram of a package structure of an embodiment 1;
fig. 2 is a structural side view (a) and a plan view (b) of the first chip unit of embodiment 1;
fig. 3 is a structural side view (a) and a plan view (b) of the second chip unit of embodiment 1;
fig. 4 to 12 are views illustrating steps of the packaging process in embodiment 1: side view (a) and top view (b);
fig. 13 is a schematic diagram of a package structure of embodiment 2;
fig. 14 is a side view (a) and a top view (b) of the structure of the first chip unit layer of embodiment 3;
fig. 15 is a schematic diagram of a package structure of embodiment 3.
Marked in the figure as: the chip comprises a substrate 1, a first chip unit 2, a first PI layer 21, solder bumps 22, a second chip unit 3, a first rewiring layer 4, a first copper column 5, a first plastic sealing layer 6, a second PI layer 7, a second rewiring layer 8, a second copper column 9, a second plastic sealing layer 10, a third PI layer 11, a third rewiring layer 12, a spherical protrusion 13, a third chip unit 14, a third copper column 15, a third plastic sealing layer 16, a fourth PI layer 17 and a fourth rewiring layer 18.
Detailed Description
In the description of the present invention, it should be noted that, for the azimuth words such as the terms "center", "transverse (X)", "longitudinal (Y)", "vertical (Z)", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., the azimuth and positional relationships are based on the azimuth or positional relationships shown in the drawings, only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and should not be construed as limiting the specific protection scope of the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features. Thus, the definition of "a first", "a second" feature may explicitly or implicitly include one or more of such feature, and in the description of the present invention, the meaning of "a number", "a number" is two or more, unless otherwise specifically defined.
Example 1
As shown in fig. 1, the wafer-level non-TSV 3D stacked package structure according to this embodiment includes a substrate 1 and two stacked chip units, namely a first chip unit 2 and a second chip unit 3. The chip unit comprises a chip body, and the front surface of the chip body is provided with a PI layer 21 and solder bumps 22.
The front surface of the substrate 1 is provided with a first redistribution layer 4 and a first copper pillar 5, the first chip unit 2 is inverted on the first redistribution layer 4, and the solder bump 22 of the first chip unit 2 is electrically connected with the first redistribution layer 4. Performing a plastic packaging process on the back surface of the first chip unit 2 to form a first plastic packaging layer 6, wherein the first plastic packaging layer 6 covers the first chip unit 2 and the first copper column 5; and then grinding, thinning the first plastic sealing layer, and synchronously thinning the back surface of the first chip unit 2 and the first copper column 5 when the first plastic sealing layer is thinned to form a first chip unit layer.
After thinning, a second PI layer 7 and a second redistribution layer 8 are laid above the first chip unit 2, a dielectric layer can be arranged between adjacent second redistribution layers 8, the specific PI layer and a wiring layer (Metal) are determined according to the actual wiring of the chip, and if the back surface of the first chip unit is an electrode, the back surface of the first chip unit can also be led out through the second redistribution layer.
The second redistribution layer on the outermost side of the back surface of the first chip unit 2 is provided with a second copper pillar 9, the second chip unit 3 is inverted on the second redistribution layer 8 of the first chip unit 2, and the solder bump on the second chip unit 3 is electrically connected with the second redistribution layer 8. And the back surface of the second chip unit 3 is subjected to a plastic packaging process to form a second plastic packaging layer 10, the second plastic packaging layer 10 covers the second chip unit 3 and the second copper column 9, and when the second plastic packaging layer is thinned, the back surface of the second chip unit and the second copper column are thinned synchronously to form a second chip unit layer.
After thinning, a third PI layer 11 and a third redistribution layer 12 are laid over the second chip unit 3, where the PI layer and a signal line (Metal) layer are determined by actually routing the chip, and if the back surface of the second chip unit is an electrode, the back surface of the second chip unit can also be led out through the third redistribution layer.
UBM pads are disposed on the third redistribution layer 12 on the back side of the second chip unit 3, the UBM pads are used for disposing spherical bumps 13, the spherical bumps 13 can be implemented through ball-plating or electroplating processes, and the bump shapes can meet the packaging appearance requirements of BGA or LGA based on product requirements. UBM is the bump bottom metallization.
All chip units may be of the same type of chip or of different types of chips. As shown in fig. 2 and 3, the present embodiment stacks the first chip unit 2 and the second chip unit 3 of different types.
The packaging process of this embodiment is as follows:
1) Preparing a plurality of chip units: manufacturing a PI layer 21 and a solder bump 22 on the front surface of the silicon wafer by completing the bump manufacturing of the wafer level package; then grinding and scribing the silicon wafer to obtain a chip unit meeting the requirements; wafer level packaging (Wafer Level Packaging, abbreviated WLP) is an advanced packaging technology, which has the advantages of small size, excellent electrical performance, good heat dissipation, low cost, etc., and has been rapidly developed in recent years. Unlike conventional packaging processes, wafer level packaging encapsulates the chip while it is still on the wafer, and a protective layer may be attached to the top or bottom of the wafer, then the circuit is connected, and then the wafer is diced into individual chips.
2) Preparing a substrate: a first redistribution layer 4 (RDL layer) and a first copper pillar 5 are fabricated on the front side of the substrate 1, as shown in fig. 4;
3) Inverting the first chip unit 2 on the first rewiring layer 4 of the substrate 1, i.e. making the first chip unit electrically connected to the substrate, as shown in fig. 5;
4) The plastic packaging process is carried out on the first chip unit 2, so that the first plastic packaging layer 6 covers the outer sides of the first chip unit 2 and the first copper column 5, and the first chip unit and the first copper column are protected, as shown in fig. 6;
5) Grinding the front surface of the substrate 1, and simultaneously thinning the first plastic sealing layer 6, the first copper column 5 and the back surface of the first chip unit 2 to expose the back surfaces of the first copper column and the first chip unit, wherein the minimum of the first chip unit can be thinned to 20, as shown in fig. 7;
6) Manufacturing a Wafer bump (Wafer bumping) on the back surface of the exposed first chip unit 2 and adding a second copper pillar 9, wherein the PI layer II 7 and the second redistribution layer 8 on the Wafer bump are determined according to the actual wiring of the chip, and if the back surface of the first chip unit is an electrode, the Wafer bump can be exported by arranging the second redistribution layer, as shown in fig. 8 and 9;
7) Inverting the second chip unit 3 on the second redistribution layer 8 of the first chip unit 2, so that the two chip units are electrically connected;
8) The second chip unit 3 is subjected to a plastic packaging process, so that the second chip unit 3 and the outer sides of the second copper columns 9 are covered with a second plastic packaging layer 10, and the second chip unit and the second copper columns are protected;
9) Grinding the front surface of the substrate 1, and simultaneously thinning the second plastic sealing layer 10, the second copper column 9 and the back surface of the second chip unit 3 to expose the back surfaces of the second copper column and the second chip unit, as shown in fig. 10;
10 Wafer bumping and Bump (Bump) are manufactured on the back of the exposed second chip unit, wherein the number of the specific PI layer three 11 and the number of the third wiring layer 12 are determined according to the actual wiring of the chip, the spherical Bump 13 can be realized through ball-planting or electroplating technology, and the shape of the Bump can realize the packaging appearance requirement of the BGA or LGA based on the product requirement, as shown in fig. 11;
11 Grinding, printing, back-gluing and scribing the back of the substrate, and then testing to obtain qualified chips, namely grinding the back of the substrate of the chip, printing or drawing circuits and other necessary information of the chips on the surface of the chip, coating glue or adhesive on the back of the chip for fixing the chips and protecting the internal circuits of the chips, cutting a wafer into single chips, and carrying out functional and reliability tests on each chip, and classifying the chips into qualified products or unqualified products according to the test results, as shown in fig. 12.
Example 2
As shown in fig. 13, the package structure in this embodiment includes a substrate 1 and three stacked chip units, namely a first chip unit 2, a second chip unit 3, and a third chip unit 14. The remaining structure is similar to embodiment 1, except that:
after the PI layer three 11 and the third redistribution layer 12 are laid above the second chip unit 3, a third copper pillar 15 is disposed on the third redistribution layer on the outermost side of the back surface of the second chip unit, the third chip unit 14 is inverted on the third redistribution layer 12 of the second chip unit 3, and the solder bump on the third chip unit is electrically connected with the third redistribution layer. And the back surface of the third chip unit 14 is subjected to a plastic packaging process to form a third plastic packaging layer 16, the third plastic packaging layer 16 covers the third chip unit 14 and the third copper column 15, and when the third plastic packaging layer is thinned, the back surface of the third chip unit and the third copper column are thinned synchronously.
After thinning, a fourth PI layer 17 and a fourth re-wiring layer 18 are laid over the third chip unit 14, and UBM pads are disposed on the fourth re-wiring layer, so that Bump can be implemented through ball-mounting or electroplating technology, and Bump can be used for implementing the packaging appearance requirements of BGA or LGA based on product requirements.
By analogy, the packaging structure in this embodiment may further stack the fourth chip unit, the fifth chip unit, and the like, so as to realize diversification of the packaged chips.
Example 3
In embodiment 1 and embodiment 2, only one chip unit is provided for each chip unit layer, but the difference in this embodiment is that: some or all of the die unit layers may be provided with more than 2 die units. As shown in fig. 14, two chip units are tiled on the chip unit layer, the two chip units do not interfere with each other, and the front sides of the chip units are conducted with the side copper columns through the rewiring layer.
As shown in fig. 15, the first chip unit layer and the second chip unit layer are provided with more than one chip unit, and the number of the chip units on each chip unit layer may be identical or different, and the types of the chip units on the same layer may be identical or different, so long as the actual requirements of customers are met.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be within the scope of the present invention.

Claims (10)

1. The utility model provides a wafer level non-TSV 3D stacks packaging structure which characterized in that: the chip unit layers are mutually stacked and are arranged on the substrate; the chip unit layer comprises at least one inverted chip unit, a plastic sealing layer is arranged on the outer side of the chip unit, a rewiring layer is arranged between adjacent chip unit layers, and the front side of each chip unit is communicated with the side copper column through the rewiring layer.
2. The wafer level non-TSV 3D stacked package structure according to claim 1, wherein: the chip unit comprises a chip body, wherein the front surface of the chip body is provided with solder bumps, and the solder bumps are electrically connected with the side copper columns through the rewiring layer.
3. The wafer level non-TSV 3D stacked package structure according to claim 1, wherein: a first rewiring layer is arranged below the first chip unit layer, and a first copper column is arranged on the first rewiring layer; the first chip unit layer comprises at least one first chip unit, the first chip unit is inverted on the first rewiring layer, the first plastic sealing layer covers the first chip unit and the first copper column, and the first plastic sealing layer, the back surface of the first chip unit and the first copper column are thinned synchronously.
4. The wafer level non-TSV 3D stacked package structure according to claim 3, wherein: a second redistribution layer is arranged below the second chip unit layer, and a second copper column is arranged on the second redistribution layer; the second chip unit layer comprises at least one second chip unit which is inverted on the second redistribution layer; and a second plastic sealing layer is arranged on the outer side of the second chip unit, covers the second chip unit and the second copper column, and is thinned synchronously with the back of the second chip unit and the second copper column.
5. The wafer level non-TSV 3D stacked package structure according to claim 1, wherein: the top chip unit layer is provided with a third wiring layer, the third wiring layer is provided with welding spots, and the welding spots are formed by ball implantation or electroplating.
6. The wafer level non-TSV 3D stacked package structure according to claim 1, wherein: a plurality of second redistribution layers are arranged between the adjacent chip unit layers, and a dielectric layer is arranged between the adjacent second redistribution layers.
7. The wafer-level non-TSV 3D stacking packaging method is characterized by comprising the following steps of: the method comprises the following steps:
1) Preparing a plurality of chip units: finishing wafer level packaging on the front surface of the silicon wafer, manufacturing solder bumps, and grinding and scribing the silicon wafer to obtain a chip unit;
2) Preparing a substrate: manufacturing a first rewiring layer and a first copper column on the front surface of the substrate;
3) Inverting at least one first chip unit on a first rewiring layer of the substrate, wherein the front surface of the first chip unit is communicated with the first copper column through the first rewiring layer;
4) Carrying out plastic package on the first chip unit, wherein the plastic package covers the first chip unit and the first copper column;
5) Grinding the front surface of the substrate to expose the first copper column and the back surface of the first chip unit to form a first chip unit layer;
6) Disposing a second redistribution layer and a second copper pillar over the first chip unit layer;
7) Inverting at least one second chip unit on the second redistribution layer, wherein the front surface of the second chip unit is communicated with the second copper column through the second redistribution layer;
8) Repeating the steps 4) to 6) to form a second chip unit layer;
9) Repeating the steps 7) to 8), and stacking a plurality of chip unit layers;
10 After the stacking quantity reaches the requirement, performing ball implantation or electroplating process above the topmost chip unit layer;
11 And (3) carrying out post-treatment on the packaging body obtained in the step 10) to obtain the qualified product chip.
8. The wafer level non-TSV 3D stacked package method according to claim 7, wherein: in the step 1), all the chip units may be the same type of chip or different types of chips.
9. The wafer level non-TSV 3D stacked package method according to claim 7, wherein: and 5) grinding, and thinning the chip unit to 20-25 mu m.
10. The wafer level non-TSV 3D stacked package method according to claim 7, wherein: in the step 6), if the back surface of the chip unit is provided with an electrode, the electrode may be led out through the second redistribution layer.
CN202311613617.6A 2023-11-29 2023-11-29 Wafer-level non-TSV 3D stacked packaging structure and method Pending CN117316907A (en)

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US20130105973A1 (en) * 2011-11-02 2013-05-02 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3d and package-on-package applications, and method of manufacture
CN103730434A (en) * 2012-10-11 2014-04-16 台湾积体电路制造股份有限公司 Pop structures and methods of forming the same
CN208460760U (en) * 2018-05-04 2019-02-01 袁鹰 Three-dimensional system level packaging structure
CN115206948A (en) * 2022-05-30 2022-10-18 盛合晶微半导体(江阴)有限公司 Three-dimensional fan-out type packaging structure of ultrahigh-density connection system and preparation method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130105973A1 (en) * 2011-11-02 2013-05-02 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3d and package-on-package applications, and method of manufacture
CN103730434A (en) * 2012-10-11 2014-04-16 台湾积体电路制造股份有限公司 Pop structures and methods of forming the same
CN208460760U (en) * 2018-05-04 2019-02-01 袁鹰 Three-dimensional system level packaging structure
CN115206948A (en) * 2022-05-30 2022-10-18 盛合晶微半导体(江阴)有限公司 Three-dimensional fan-out type packaging structure of ultrahigh-density connection system and preparation method thereof

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