CN217468336U - Electronic packaging structure - Google Patents

Electronic packaging structure Download PDF

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Publication number
CN217468336U
CN217468336U CN202221088283.6U CN202221088283U CN217468336U CN 217468336 U CN217468336 U CN 217468336U CN 202221088283 U CN202221088283 U CN 202221088283U CN 217468336 U CN217468336 U CN 217468336U
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China
Prior art keywords
chip
silicon
adhesive film
layer
filling layer
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Application number
CN202221088283.6U
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Chinese (zh)
Inventor
瞿宏宇
潘远杰
周祖源
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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Priority to CN202221088283.6U priority Critical patent/CN217468336U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The utility model provides an electronic packaging structure, electronic packaging structure includes at least: a silicon interconnect structure; at least one chip soldered on the silicon connector structure; an adhesive film deposited on the side wall of the chip; and the filling layer is formed on the surface of the silicon connecting body structure and wraps the chip and the adhesive film. The method of forming the structure includes at least: firstly, preparing a silicon connector structure; then, soldering at least one chip to the silicon connector structure; then, depositing an adhesive film on the side wall of the chip; and finally, forming a filling layer wrapping the chip and the adhesive film on the surface of the silicon connecting body structure. The utility model discloses the chip with increased the adhesion membrane on the contact interface of filling layer, can provide stronger cohesion between filling layer and chip, improve the stability of filling layer, prevent to peel off.

Description

Electronic packaging structure
Technical Field
The utility model relates to a semiconductor package technical field especially relates to an electronic packaging structure.
Background
Lower cost, more reliable, faster, and higher density circuits are sought after goals for integrated circuit packaging. In the future, integrated circuit packages will increase the integration density of various electronic components by continually reducing the minimum feature size. Currently, advanced packaging methods include: wafer Level Chip Scale Packaging (WLCSP), Fan-Out Wafer Level Packaging (Fan Out Wafer Level Package, FOWLP), flip Chip (FliChip), stack Package (Package on Package, POP), and the like.
With the increase of the interconnection density of the package and the further decrease of the thickness of the package, techniques such as Through Silicon Vias (TSV), 2.5D connectors (interposer), 3DIC, etc. have been introduced. The packaging structure is characterized in that a plurality of chips (die) are assembled on a silicon connector (interposer) by utilizing the silicon connector (interposer), and filling layers (underfills) are filled around the chips and between the silicon connector and the chips. However, it is found that a serious delamination occurs between the filling layer and the chip, and the filling layer may even peel off after a long time, which may not protect the chip and the metal connection structure between the chip and the silicon connector.
Therefore, it is an object of the present invention to provide an electronic package structure capable of improving the adhesion between a filling layer and a chip.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an electronic package structure for solving the problem of delamination between the filling layer and the chip in the prior art.
To achieve the above and other related objects, the present invention also provides an electronic package structure, which at least includes:
a silicon interconnect structure;
at least one chip soldered on the silicon connector structure;
an adhesive film deposited on the side wall of the chip;
and the filling layer is formed on the surface of the silicon connecting body structure and wraps the chip and the adhesive film.
Optionally, the silicon interconnect structure comprises:
a silicon substrate;
a through hole formed in the silicon substrate;
the metal column is filled in the through hole;
and the rewiring layers are formed on the front surface and the back surface of the silicon substrate and are connected with the metal columns, wherein the rewiring layer on the back surface is connected to the glass substrate, and the rewiring layer on the front surface is welded with the chip.
Optionally, the bonding surface of the chip has a dielectric layer, a first bump electrically connected to the chip is formed on the surface of the dielectric layer, a redistribution layer on the front side of the silicon substrate includes a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer and connected to the metal post, a second bump electrically connected to the metal wiring layer is formed on the surface of the wiring dielectric layer, and the redistribution layer on the front side is welded to the chip through the second bump and the first bump.
Optionally, the adhesive film is also deposited on the surface of the chip.
Optionally, the material of the adhesion film comprises TEOS.
Optionally, the adhesive film has a thickness between 0.5um and 1.5 um.
Optionally, the material of the filling layer includes one or more of polyimide, silicone, and epoxy.
As described above, the electronic packaging structure of the present invention at least includes: a silicon interconnect structure; at least one chip soldered on the silicon connector structure; an adhesive film deposited on the side wall of the chip; and the filling layer is formed on the surface of the silicon connecting body structure and wraps the chip and the adhesive film. The method of forming the structure includes at least: firstly, preparing a silicon connector structure; then, soldering at least one chip to the silicon connector structure; then, depositing an adhesive film on the side wall of the chip; and finally, forming a filling layer wrapping the chip and the adhesive film on the surface of the silicon connecting body structure. The utility model discloses the chip with increased the adhesion membrane on the contact interface of filling layer, can provide stronger cohesion between filling layer and chip, improve the stability of filling layer, prevent to peel off.
Drawings
Fig. 1 to fig. 4 are schematic structural diagrams of steps of the method for manufacturing an electronic package structure according to the present invention. Fig. 4 is a schematic view of the electronic package structure of the present invention.
Description of the element reference numerals
1 silicon interconnect structure
101 silicon substrate
102 through hole
103 metal column
104. 105 wiring dielectric layer
2 glass substrate
3 first projection welding point
4 chip
5 dielectric layer
6 second projection welding point
7 adhesive film
8 filling layer
Detailed Description
The following description of the embodiments of the present invention is provided for illustrative purposes, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The present invention can also be implemented or applied through other different specific embodiments, and various details in the present specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
Please refer to the attached drawings. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the invention in a schematic manner, and only the components related to the invention are shown in the drawings rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, quantity and proportion of the components in actual implementation may be changed at will, and the layout of the components may be more complicated.
The utility model provides an electron packaging structure, as shown in FIG. 4, electron packaging structure includes at least: a silicon interconnect structure 1, at least one chip 4, an adhesive film 7, and a fill layer 8. The chip 4 is welded on the silicon connector structure 1; the adhesive film 7 is deposited on the side wall of the chip 4; the filling layer 8 is formed on the surface of the silicon connector structure 1 and wraps the chip 4 and the adhesive film 7.
As an example, the silicon interconnect structure 1 comprises: a silicon substrate 101, a via 102, a metal pillar 103, and a re-wiring layer. The through hole 102 is formed in the silicon substrate 101; the metal pillar 103 is filled in the through hole 102; the rewiring layers are formed on the front surface and the back surface of the silicon substrate 101 and connected with the metal posts 103, wherein the rewiring layer on the back surface is connected to the glass substrate 2, and the rewiring layer on the front surface is welded with the chip 4.
The metal posts 103 may be one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. Methods of filling the metal pillar 103 include, but are not limited to, deposition methods, electroplating methods, and the like. In the present embodiment, the metal pillar 103 is electroplated copper.
The rewiring layer on the back side can be connected to the glass substrate 2 and the rewiring layer on the front side can be soldered to the chip 4 using reflow and thermocompression processes.
The chip 4 may be any conventional semiconductor chip suitable for packaging, and may be a plurality of chips of the same type or a plurality of different types, for example, a System On Chip (SOC) device, or a memory chip, such as an HBM, and the like, without limitation. In addition, a plurality of the chips 4 are generally packaged, and three chips 4 are shown in fig. 4, based on the requirements of packaging efficiency, package size and the like.
As an example, the bonding surface of the chip 4 has a dielectric layer 5, a first bump 3(bump) electrically connected to the chip 4 is formed on the surface of the dielectric layer 5, the redistribution layer on the front surface of the silicon substrate 101 includes a wiring dielectric layer 104 and a metal wiring layer (not shown) located in the wiring dielectric layer 104 and connected to the metal pillar 103, a second bump 6(bump) electrically connected to the metal wiring layer is formed on the surface of the wiring dielectric layer 104, and the redistribution layer on the front surface is bonded to the chip 4 through the second bump 6 and the first bump 3, so that the chip 4 and the silicon connector structure 1 are welded and fixed.
The chip 4 is flip-chip mounted on the silicon interconnect structure 1, i.e. the bonding surface of the chip 4 is bonded to the second bump bond 6 on the front surface of the silicon interconnect structure 1.
By way of example, the adhesive film 7 may be deposited on the sidewalls of the chip 4 by a Chemical Vapor Deposition (CVD) process, although in other embodiments, the adhesive film 7 may be deposited by other suitable film forming processes. The material of the adhesion film 7 includes, but is not limited to, TEOS (tetraethyl orthosilicate). In this embodiment, the TEOS adhesive film 7 is prepared by using a chemical vapor deposition method, and the obtained TEOS adhesive film 7 has good coverage and low-temperature deposition characteristics. Because the bonding force between the TEOS adhesion film 7 and the chip 4 is greater than the bonding force between the TEOS adhesion film 7 and the filling layer 8, and the bonding force between the TEOS adhesion film 7 and the filling layer 8 is greater than the bonding force between the filling layer 8 and the chip 4, the adhesion between the filling layer 8 and the chip 4 can be greatly improved by depositing the adhesion film 7 on the side wall surface of the chip 4 before the filling layer 8 is prepared, the risk of layered peeling of the filling layer 8 is reduced, and the packaging reliability is improved.
As an example, the thickness of the adhesive film 7 is between 0.5um and 1.5 um. Preferably, the adhesive film 7 has a thickness of 0.8um to 1.5 um. In a specific embodiment, the adhesive film 7 has a thickness of 1 um. In another specific embodiment, the adhesive film 7 has a thickness of 1.2 um.
As an example, the adhesive film 7 is also deposited on the surface of the chip 4. In particular, the face of the chip 4 facing upwards after flip-chip mounting is also deposited with an adhesive film 7. The adhesive film 7 on the surface can protect the chip 4 from contamination.
The filling layer 8 wraps the dielectric layer 5, the first bump pads 3 and the second bump pads 6 in addition to wrapping the chip 4 and the adhesive film 7. The filling layer 8 can be used to increase the bonding strength between the silicon connector structure 1 and the chip 4 and to protect the first bump 3, the second bump 6 and the chip 4 from contamination. The material of the filling layer 8 includes, but is not limited to, one or more of polyimide, silicone, and epoxy, and the method for forming the filling layer 8 includes, but is not limited to, one or more of inkjet, dispensing, compression molding, transfer molding, liquid sealing, vacuum lamination, and spin coating.
The electronic packaging structure can be prepared by the following preparation method, and the preparation method at least comprises the following steps:
step 1) is first performed, preparing a silicon interconnect structure 1.
As an example, as shown in fig. 1 for a prepared silicon interconnect structure, the step of preparing the silicon interconnect structure 1 may comprise: firstly, providing a silicon substrate 101, forming a through hole 102 in the silicon substrate 101, and filling a metal material into the through hole 102 to form a metal column 103; and forming rewiring layers connected with the metal posts 103 on the front surface and the back surface of the silicon substrate 101, wherein the rewiring layer on the back surface is connected to the glass substrate 2, and the rewiring layer on the front surface is welded with the chip 4.
The metal posts 103 may be one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium. Methods of filling the metal pillar 103 include, but are not limited to, deposition methods, electroplating methods, and the like. In the present embodiment, the metal pillar 103 is electroplated copper.
The rewiring layer on the back side can be connected to the glass substrate 2 and the rewiring layer on the front side can be soldered to the chip 4 using reflow and thermocompression processes.
Then step 2) is performed, as shown in fig. 2, at least one chip 4 is soldered onto said silicon interconnect structure 1.
The chip 4 may be any conventional semiconductor chip suitable for packaging, and may be a plurality of chips of the same type or a plurality of different types, for example, a System On Chip (SOC) device, or a memory chip, such as an HBM, and the like, without limitation. In addition, a plurality of the chips 4 are generally packaged, and three chips 4 are shown in the drawing, based on the requirements of packaging efficiency, packaging size and the like.
As an example, the bonding surface of the chip 4 has a dielectric layer 5, a first bump 3(bump) electrically connected to the chip 4 is formed on the surface of the dielectric layer 5, the redistribution layer on the front surface of the silicon substrate 101 includes a wiring dielectric layer 104 and a metal wiring layer (not shown) located in the wiring dielectric layer 104 and connected to the metal pillar 103, a second bump 6(bump) electrically connected to the metal wiring layer is formed on the surface of the wiring dielectric layer 104, and the redistribution layer on the front surface is bonded to the chip 4 through the second bump 6 and the first bump 3, so that the chip 4 and the silicon connector structure 1 are welded and fixed.
The chip 4 is flip-chip mounted on the silicon connector structure 1, i.e. the bonding surface of the chip 4 is facing down and bonded to the second bump bond 6 on the front surface of the silicon substrate 101.
Step 3) is then carried out, as shown in fig. 3, depositing an adhesive film 7 on the side walls of the chip 4.
By way of example, the adhesive film 7 may be deposited on the sidewalls of the chip 4 by a Chemical Vapor Deposition (CVD) process, although in other embodiments, the adhesive film 7 may be deposited by other suitable film forming processes. The material of the adhesion film 7 includes, but is not limited to, TEOS (tetraethyl orthosilicate). In this embodiment, the TEOS adhesive film 7 is prepared by using a chemical vapor deposition method, and the obtained TEOS adhesive film 7 has good coverage and low-temperature deposition characteristics. Because the bonding force between the TEOS adhesion film 7 and the chip 4 is greater than the bonding force between the TEOS adhesion film 7 and the filling layer 8, and the bonding force between the TEOS adhesion film 7 and the filling layer 8 is greater than the bonding force between the filling layer 8 and the chip 4, the adhesion between the filling layer 8 and the chip 4 can be greatly improved by depositing the adhesion film 7 on the side wall surface of the chip 4 before the filling layer 8 is prepared, the risk of layered peeling of the filling layer 8 is reduced, and the packaging reliability is improved.
As an example, the thickness of the adhesive film 7 is between 0.5um and 1.5 um. Preferably, the adhesive film 7 has a thickness of 0.8um to 1.5 um. In a specific embodiment, the adhesive film 7 has a thickness of 1 um. In another specific embodiment, the adhesive film 7 has a thickness of 1.2 um.
As an example, the adhesive film 7 is also deposited on the surface of the chip 4. In particular, the face of the chip 4 facing upwards after flip-chip mounting is also deposited with an adhesive film 7. The adhesive film 7 on the surface can protect the chip 4 from contamination.
Then step 4) is carried out, as shown in fig. 4, a filling layer 8 is formed on the surface of the silicon connector structure 1 to wrap the chip 4 and the adhesive film 7.
In addition, the filling layer 8 also covers the dielectric layer 5, the first bump points 3 and the second bump points 6. The filling layer 8 can improve the bonding strength between the silicon connector structure 1 and the chip 4 and protect the first bump 3, the second bump 6 and the chip 4 from contamination. The material of the filling layer 8 includes, but is not limited to, one or more of polyimide, silicone, and epoxy, and the method for forming the filling layer 8 includes, but is not limited to, one or more of inkjet, dispensing, compression molding, transfer molding, liquid sealing, vacuum lamination, and spin coating.
To sum up, the utility model provides an electronic packaging structure, electronic packaging structure includes at least: a silicon interconnect structure 1; at least one chip 2 soldered on said silicon connector structure 1; an adhesive film 7 deposited on the side wall of the chip 4; and the filling layer 8 is formed on the surface of the silicon connecting body structure 1 and wraps the chip 4 and the adhesive film 7. The method of forming the structure includes at least: first, a silicon interconnect structure 1 is prepared; then, at least one chip 4 is soldered onto the silicon interconnect structure 1; then, depositing an adhesive film 7 on the side wall of the chip 4; finally, a filling layer 8 wrapping the chip 4 and the adhesive film 7 is formed on the surface of the silicon connector structure 1. The utility model discloses chip 4 with increased adhesion film 7 on the contact interface of filling layer 8, can provide stronger cohesion between filling layer 8 and chip 4, improve filling layer 8's stability, prevent to peel off.
Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles and effects of the present invention, and are not to be construed as limiting the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (7)

1. An electronic package, comprising:
a silicon interconnect structure;
at least one chip soldered on the silicon connector structure;
an adhesive film deposited on the side wall of the chip;
and the filling layer is formed on the surface of the silicon connecting body structure and wraps the chip and the adhesive film.
2. The electronic package structure of claim 1, wherein said silicon connector structure comprises:
a silicon substrate;
a through hole formed in the silicon substrate;
the metal column is filled in the through hole;
and the rewiring layers are formed on the front surface and the back surface of the silicon substrate and are connected with the metal columns, wherein the rewiring layer on the back surface is connected to the glass substrate, and the rewiring layer on the front surface is welded with the chip.
3. The electronic package structure of claim 2, wherein: the welding surface of the chip is provided with a dielectric layer, a first projection welding point electrically connected with the chip is formed on the surface of the dielectric layer, a rewiring layer on the front surface of the silicon substrate comprises a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer and connected with the metal column, a second projection welding point electrically connected with the metal wiring layer is formed on the surface of the wiring dielectric layer, and the rewiring layer on the front surface of the silicon substrate is welded with the chip through the second projection welding point and the first projection welding point.
4. The electronic package structure of claim 1, wherein: the adhesive film is also deposited on the surface of the chip.
5. The electronic package structure of claim 1, wherein: the material of the adhesion film comprises TEOS.
6. The electronic package structure of claim 1, wherein: the thickness of the adhesive film is between 0.5um and 1.5 um.
7. The electronic package structure of claim 1, wherein: the material of the filling layer comprises one or more of polyimide, silica gel and epoxy resin.
CN202221088283.6U 2022-05-07 2022-05-07 Electronic packaging structure Active CN217468336U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202221088283.6U CN217468336U (en) 2022-05-07 2022-05-07 Electronic packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202221088283.6U CN217468336U (en) 2022-05-07 2022-05-07 Electronic packaging structure

Publications (1)

Publication Number Publication Date
CN217468336U true CN217468336U (en) 2022-09-20

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
CN (1) CN217468336U (en)

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