CN114171506A - Multilayer stacked memory packaging structure and packaging method - Google Patents

Multilayer stacked memory packaging structure and packaging method Download PDF

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Publication number
CN114171506A
CN114171506A CN202111496915.2A CN202111496915A CN114171506A CN 114171506 A CN114171506 A CN 114171506A CN 202111496915 A CN202111496915 A CN 202111496915A CN 114171506 A CN114171506 A CN 114171506A
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memory
memory chip
substrate
layer
memory chips
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杜茂华
吴明敏
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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Priority to CN202111496915.2A priority Critical patent/CN114171506A/en
Publication of CN114171506A publication Critical patent/CN114171506A/en
Priority to PCT/CN2022/137244 priority patent/WO2023104093A1/en
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    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]

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Abstract

The invention provides a multilayer stacked memory packaging structure and a packaging method, wherein the packaging structure comprises a first memory chip, a plurality of second memory chips, a substrate and a plastic packaging layer; a plurality of first conductive through holes are formed in the second memory chip, and a plurality of second conductive through holes electrically connected with the plurality of first conductive through holes are formed in the substrate; the plurality of second memory chips are sequentially stacked on the substrate, the plurality of second memory chips are in hybrid bonding connection, and the substrate is in thermocompression bonding connection with the second memory chips; the first memory chips are arranged on one sides of the plurality of second memory chips, which are far away from the substrate, and the first memory chips and the second memory chips are in hybrid bonding connection; the plastic packaging layer wraps the first memory chip, the plurality of second memory chips and the substrate. The packaging structure of the invention realizes the superfine pitch interconnection, increases the number of vertical interconnections of the memory chip, improves the data throughput and increases the capacity.

Description

Multilayer stacked memory packaging structure and packaging method
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a multilayer stacked memory packaging structure and a packaging method.
Background
With the development of cloud computing and mobile interconnection, the demand of servers such as data centers is increasing dramatically. High-end servers require high capacity, large bandwidth, and low power consumption for memory devices. To meet this demand, companies have successively introduced multi-layer stacked storage packaging products based on three-dimensional stacking technology. As shown in fig. 1, the stacked structure of the multi-layer stacked memory package uses through-silicon vias 2 to interconnect a plurality of memory chips 1 vertically, the memory chips 1 are welded together by bumps 3, the memory chips 1 are stacked on a substrate 4, a non-conductive adhesive 5 is present between the chips, the whole memory chip structure is protected by a molding layer 6, and finally the package is connected with the outside by solder balls 7. Since the through silicon vias 2 have the advantages of high density and short vertical interconnection distance, the data transmission speed is greatly improved.
Currently, a Thermal Compression Bond (TCB) process is used for a multi-chip multi-stack of a multi-layer stacked memory to connect the bump 3 with the chip back pad 8 and the chip back pad 8 with the through-silicon via 2 of the chip by rapid heating. At present, the bump mainly has a copper-tin structure, and the bonding pad on the back of the chip mainly has a nickel-gold structure. The final stacked structure is protected by a molding layer 6.
In the case of using copper-tin bumps, the pitch between the bumps 3 and the height of the tin need to be strictly controlled in order to prevent short-circuiting between the bumps due to the deformability of the tin at the time of reflow.
At present, the distance is more than 40um, and when the distance is reduced to be less than 25um, the tin is excessively small, so that the tin is comprehensively converted into intermetallic compounds under the condition of hot load, and the reliability is failed.
In order to increase the memory capacity and data throughput speed, the number of chip stacks and the number of pins need to be increased, but in the current micro-bump mechanism, the space for continuous improvement is limited due to the limitation of bump height and space.
In view of the above problems, there is a need for a multi-layer stacked memory package and a method thereof that are reasonable in design and can effectively solve the above problems.
Disclosure of Invention
The present invention is directed to at least one of the problems of the prior art, and provides a method and a structure for packaging a multi-layer stacked memory.
One aspect of the present invention provides a multi-layer stacked memory package structure, the package structure including a substrate, a first memory chip, a plurality of second memory chips, and a molding layer;
a plurality of first conductive through holes are formed in the second memory chip, and a plurality of second conductive through holes electrically connected with the plurality of first conductive through holes are formed in the substrate;
the plurality of second memory chips are sequentially stacked on the substrate, the plurality of second memory chips are in hybrid bonding connection, and the substrate is in thermocompression bonding connection with the second memory chips;
the first memory chips are arranged on one sides of the second memory chips, which face away from the substrate, and the first memory chips are in hybrid bonding connection with the second memory chips;
the plastic packaging layer wraps the first memory chip, the plurality of second memory chips and the substrate.
Optionally, a first passivation layer and a first metal pad are disposed on a surface of the second memory chip facing the first memory chip, and a second passivation layer and a second metal pad are disposed on a surface of the second memory chip facing away from the first memory chip;
the first passivation layer and the second passivation layer in every two adjacent layers of the second memory chip are in hybrid bonding connection;
and the first metal pad and the second metal pad in every two adjacent layers of the second memory chip are in hybrid bonding connection.
Optionally, a third passivation layer and a third metal pad are disposed on a surface of the first memory chip facing the second memory chip;
the third passivation layer is in hybrid bonding connection with the first passivation layer on the side, facing the first memory chip, of the second memory chip;
the third metal pad is in hybrid bonding connection with the first metal pad on the side, facing the first memory chip, of the second memory chip.
Optionally, a fourth metal pad is disposed on a surface of the substrate facing the second memory chip, and a bump is disposed on a side of the second memory chip close to the substrate, the side facing the substrate;
and the fourth metal pad is connected with the salient point in a hot-pressing bonding mode.
Optionally, the package structure further includes a non-conductive adhesive film, and the bump is wrapped by the non-conductive adhesive film.
Optionally, the package structure further includes a dielectric layer and a redistribution layer, where the dielectric layer and the redistribution layer are sequentially disposed on the second passivation layer of the second memory chip close to the substrate, and the redistribution layer is electrically connected to the bump.
Optionally, the package structure further includes a solder ball disposed on a surface of the substrate facing away from the second memory chip, where the solder ball corresponds to and is electrically connected to the second conductive via.
Optionally, the first conductive through hole and the second conductive through hole are all silicon through holes.
Optionally, the molding compound layer comprises a first molding compound layer and a second molding compound layer,
the first plastic packaging layer is arranged on the first memory chips and sleeved outside the plurality of second memory chips;
the second plastic package layer is arranged on the substrate and sleeved on the first plastic package layer and the outer side of the first memory chip.
Another aspect of the present invention provides a method for packaging a multi-layer stacked memory, the multi-layer stacked memory package structure is the package structure described above, the method includes:
forming a plurality of cutting marks at preset positions in the first memory chip;
sequentially mixing, bonding and stacking a plurality of second memory chips with first conductive through holes on the first memory chip between two adjacent cutting marks;
plastically packaging the first memory chip and the plurality of second memory chips to form a first plastic packaging layer;
adhering the first memory chip subjected to plastic packaging to a film, and cutting the first plastic packaging layer at positions corresponding to the plurality of cutting marks to form a plurality of independent second memory chip groups;
cutting the first memory chip along the plurality of cutting marks to form a plurality of independent memory stacking modules;
carrying out thermocompression bonding on the plurality of memory stacking modules and a substrate, wherein the substrate is provided with a second conductive through hole;
carrying out plastic package on the substrate and the memory stacking module to form a second plastic package layer;
and cutting the second plastic packaging layer and the substrate to form an independent memory packaging structure.
The invention relates to a multilayer stack memory packaging structure and a packaging method, wherein a plurality of second memory chips are sequentially stacked on a substrate in the packaging structure, the second memory chips are in hybrid bonding connection, and the substrate is in hot-press bonding connection with the second memory chips; the first memory chips are arranged on one sides of the plurality of second memory chips, which are far away from the substrate, and the first memory chips and the second memory chips are in hybrid bonding connection; the plastic packaging layer wraps the substrate, the first memory chip and the plurality of second memory chips. The multilayer stacked memory packaging structure can realize the interconnection of superfine intervals, increase the number of vertical interconnection of memory chips and further increase the number of data channels, thereby improving the data throughput; because the plurality of second memory chips and the second memory chip and the first memory chip are connected in a hybrid bonding manner, the substrate and the second memory chips are connected in a hot-pressing bonding manner, so that the bonding height can be reduced, the number of layers of the memory chips can be increased, and the capacity of the packaging structure can be increased.
Drawings
FIG. 1 is a diagram of a multi-level stacked memory package in the prior art;
FIG. 2 is a schematic structural diagram of a multi-layer stacked memory package structure according to another embodiment of the present invention;
FIG. 3 is a flow chart illustrating a method for packaging a multi-level stack memory according to another embodiment of the present invention;
fig. 4-16 are schematic views illustrating a packaging process of a multi-layer stacked memory packaging method according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 2, an aspect of the present invention provides a multi-layer stacked memory package structure 100, where the package structure 100 includes a first memory chip 110, a plurality of second memory chips 120, a substrate 130, and a molding layer. It should be noted that, in this embodiment, the first memory chip 110 and the plurality of second memory chips 120 are both dynamic random access memory chips, and may also be other memory chips, and this embodiment is not particularly limited.
The second memory chip 120 is provided with a plurality of first conductive vias 121, and the substrate 130 is provided with a plurality of second conductive vias 131 electrically connected to the plurality of first conductive vias 121. In the present embodiment, the cross-sectional size of the second conductive via 131 is larger than the cross-sectional size of the first conductive via 121. The first conductive through hole 121 and the second conductive through hole 131 can be silicon through holes, and the silicon through holes have the advantages of high density and short vertical interconnection distance, so that the vertical electrical interconnection of the silicon through holes is realized by adopting a silicon through hole technology, the packaging height is reduced, and the data transmission speed is increased.
The plurality of second memory chips 120 are sequentially stacked and arranged on the substrate 130, the plurality of second memory chips 120 are in hybrid bonding connection, and the substrate 130 is in thermocompression bonding connection with the second memory chips 120.
The first memory chip 110 is disposed on a side of the plurality of second memory chips 120 facing away from the substrate 130, and the first memory chip 110 and the second memory chips 120 are hybrid-bonded.
The molding compound wraps the first memory chip 110, the plurality of second memory chips 120, and the substrate 130. The plastic package layer includes a first plastic package layer 140 and a second plastic package layer 220, the first plastic package layer 140 is disposed on the first memory chip 110 and is sleeved outside the plurality of second memory chips 120, that is, the first plastic package layer 140 only wraps two side portions of the plurality of second memory chips 120 that are stacked. The second molding compound layer 220 is disposed on the substrate 130 and covers the first molding compound layer 140 and the first memory chip 110. It should be noted that the first molding compound layer 140 and the second molding compound layer 220 may be made of epoxy resin, and the like, and can protect the package structure 100.
The multilayer stacked memory packaging structure can realize the interconnection of superfine space, increase the number of vertical interconnection, and increase the number of data channels to improve the data throughput; because the plurality of second memory chips and the second memory chip and the first memory chip are connected in a hybrid bonding manner, the substrate and the second memory chips are connected in a hot-pressing bonding manner, so that the bonding height can be reduced, the number of layers of the memory chips can be increased, and the capacity of the packaging structure can be increased.
Illustratively, as shown in fig. 2, a surface of the second memory chip 120 facing the first memory chip 110 is provided with a first passivation layer 122 and a first metal pad 123, a surface of the second memory chip 120 facing away from the first memory chip 110 is provided with a second passivation layer 124 and a second metal pad 125, the first passivation layer 122 and the second passivation layer 124 in each two adjacent layers of the second memory chip 120 are in hybrid bonding connection, and the first metal pad 123 and the second metal pad 125 in each two adjacent layers of the second memory chip 120 are in hybrid bonding connection. The hybrid bonding between the second memory chips 120 can reduce the bonding height of the package structure, thereby increasing the number of chip layers and the capacity of the package structure.
It should be noted that in this embodiment, the first passivation layer 122 and the second passivation layer 124 may be made of silicon dioxide, the first metal pad 123 and the second metal pad 125 may be made of metal copper, and the materials of the first passivation layer 122 and the second passivation layer 124 and the first metal pad 123 and the second metal pad 125 are not specifically limited in this embodiment and may be selected as needed.
Illustratively, as shown in fig. 2, a surface of the first memory chip 110 facing the second memory chip 120 is provided with a third passivation layer 112 and a third metal pad 113, a side of the second memory chip 120 facing the first memory chip 110 is provided with a first passivation layer 122 and a first metal pad 123, the third passivation layer 112 is in hybrid bonding connection with the first passivation layer 122 of the second memory chip 120 facing the first memory chip 110, and the third metal pad 113 is in hybrid bonding connection with the first metal pad 123 of the second memory chip 120 facing the first memory chip 110. The first memory chip 110 and the second memory chip 120 are connected by hybrid bonding, so that a smaller pitch (less than 10 um) can be realized, the number of vertical interconnects can be increased, and the number of data channels can be increased, thereby improving data throughput.
It should be noted that the material of the third passivation layer 112 may be a silicon dioxide material, and the material of the third metal pad 113 may be a metal copper material, which is not specifically limited in this embodiment and may be selected as needed.
Illustratively, as shown in fig. 2, the fourth metal pad 132 is disposed on a surface of the substrate 130 facing the second memory chip 120, and a bump 190 is disposed on a side of the second memory chip 120 facing the substrate 130, that is, only the second memory chip 120 near the substrate 130 is disposed with the bump 190 on the side facing the substrate 130, and the other second memory chips 120 are not disposed with the bump structure, wherein the fourth metal pad 132 is thermally compression bonded to the bump 190.
It should be noted that, in this embodiment, the positions of the fourth metal pads 132 correspond to the positions of the bumps 190 and have the same number, if the substrate 130 is not a dedicated substrate adapted to the second memory chip 120 and the first memory chip 110, but the substrate in the chip package manufacturing process may be a general-purpose substrate, the number of the fourth metal pads 132 on the substrate 130 may be greater than the number of the bumps 190 on the second memory chip 120, as long as it is ensured that the bumps 190 on the second memory chip 120 all have the corresponding fourth metal pads 132 connected in a matching manner therewith, and that an adequate information transmission channel between the second memory chip 120 and the substrate 130 is ensured, the number of the bumps 190 is determined according to the number of the information transmission channels between the second memory chip 120 and the substrate 130, and it is intended to ensure that an adequate information transmission channel is provided between the second memory chip 120 and the substrate 130, the operation efficiency of the second memory chip 120 is ensured. In this embodiment, the material of the fourth metal pad 132 may be a metal copper material, and the material of the bump 190 may be a copper-tin material, which is not specifically limited in this embodiment.
For example, as shown in fig. 2, the package structure 100 further includes a non-conductive adhesive film 200, and the non-conductive adhesive film 200 wraps the bumps 190 to protect the bumps 190, in this embodiment, the non-conductive adhesive film 200 may also adopt other underfill materials, which may be selected according to actual needs, and this embodiment is not limited in particular.
Illustratively, it is further preferable that the package structure 100 further includes a dielectric layer 170 and a redistribution layer 180, the dielectric layer 170 and the redistribution layer 180 are sequentially disposed on the second passivation layer 124 of the second memory chip 120 near the substrate 130, wherein the redistribution layer 180 is electrically connected to the bump 190. In this embodiment, the material of the dielectric layer 170 may be Polyimide (PI), Polybenzoxazole (PBO), or the like. The material of the redistribution layer 180 is typically titanium and copper. The dielectric layer 170 and the redistribution layer 180 are disposed on the second passivation layer 124 of the second memory chip 120 close to the substrate 130, so that the high-density interconnection requirement of the package structure can be well met, and the yield can be improved.
Illustratively, as shown in fig. 2, the package structure 100 further includes solder balls 133, where the solder balls 133 are disposed on a surface of the substrate 130 facing away from the second memory chip 120, and the solder balls 133 correspond to and are electrically connected to the second conductive vias 131. The solder balls 133 correspond to the second conductive vias 131 one to one, and the package structure 100 performs signal transmission with the outside through the solder balls 133.
As shown in fig. 3, an aspect of the present invention provides a method S100 for packaging a multi-layer stacked memory, where the method S100 includes:
s110, forming a plurality of cutting marks at predetermined positions in the first memory chip.
Specifically, as shown in fig. 4, in the present embodiment, a plurality of scribe lines 111 are formed in predetermined positions of the first memory chip 110 by a laser stealth dicing method. The scribe line 111 is also a laser damage layer in the first memory chip 110. As shown in fig. 4 and 5, in the present embodiment, laser stealth dicing is performed on the surface of the first memory chip 110 facing away from the second memory chip 120. Adopt the stealthy cutting method of laser can avoid the piece that produces when the blade cutting on the one hand, on the other hand, when using stealthy cutting, the tool mark width is almost zero, can reduce the width of cutting way, further reduces the interval between the first memory chip.
And S120, sequentially mixing, bonding and stacking a plurality of second memory chips with first conductive through holes on the first memory chip between two adjacent cutting marks.
Specifically, as shown in fig. 4 and 5, between two adjacent dicing cuts 111, a plurality of second memory chips 120 having first conductive vias 121 are sequentially hybrid-bonded and stacked on the first memory chip 110.
Illustratively, as shown in fig. 5, the second memory chip 120 is provided with a plurality of first conductive vias 121, and the first conductive vias 121 may be further optimized as through-silicon vias, and vertical electrical interconnection of the through-silicon vias is achieved by using a through-silicon via technology, so that the package height is reduced.
As shown in fig. 5, a surface of the second memory chip 120 facing the first memory chip 110 is provided with a first passivation layer 122 and a first metal pad 123, a surface of the second memory chip 120 facing away from the first memory chip 110 is provided with a second passivation layer 124 and a second metal pad 125, and a surface of the first memory chip 110 facing the second memory chip 120 is provided with a third passivation layer 112 and a third metal pad 113.
In this embodiment, the first passivation layer 122, the second passivation layer 124, and the third passivation layer 112 may be made of silicon dioxide, and the first metal pad 123, the second metal pad 125, and the third metal pad 113 may be made of metal copper.
The sequentially hybrid bonding and stacking a plurality of second memory chips having conductive vias on the first memory chip comprises:
first, as shown in fig. 5, between two adjacent scribe lines 111, that is, along two sides of the two adjacent scribe lines 111, the first passivation layer 122 of the bottom second memory chip is bonded to the third passivation layer 112 of the first memory chip 110, and then baking is performed at a temperature of 200 ℃ or higher, so that the first metal pad 123 on the bottom second memory chip 120 is bonded to the third metal pad 113 on the first memory chip 110, that is, the first copper pad on the bottom second memory chip 120 and the third copper pad on the first memory chip 110 are thermally expanded by copper to form a bond.
Next, as shown in fig. 6, the remaining layers of second memory chips 120 are sequentially mixed, bonded and stacked on the bottom layer of second memory chips 120, wherein the first passivation layer 122 and the second passivation layer 124 in every two adjacent layers of second memory chips 120 are bonded; and, the first metal pads 123 and the second metal pads 125 in every two adjacent layers of the second memory chips 120 are bonded.
That is, as shown in fig. 6, on both sides of the plurality of cutting traces 111, the bottom layer second memory chip 120 is hybrid-bonded to the first memory chip 110, the second layer second memory chip 120 is disposed on the bottom layer second memory chip 120 and hybrid-bonded to the bottom layer second memory chip 120, the third layer second memory chip 120 is disposed on the second layer second memory chip 120 and hybrid-bonded to the second layer second memory chip 120, and so on, the remaining layers of second memory chips 120 are sequentially hybrid-bonded and stacked on the bottom layer second memory chip 120.
S130, carrying out plastic package on the first memory chip and the plurality of second memory chips to form a first plastic package layer.
Specifically, as shown in fig. 7, the first memory chip 110 and the plurality of second memory chips 120 stacked on the first memory chip 110 are molded to form a first molding layer 140. The first molding layer 140 wraps the first memory chip 110 and the plurality of second memory chips 120 stacked on the first memory chip 110. Then, the surface of the first molding layer 140 is polished to expose the second passivation layer 124 and the second metal pad 125 of the surface of the second memory chip 120 facing away from the first memory chip 110. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
S140, the first memory chip after plastic packaging is attached to a film, and the first plastic packaging layer is cut at the position corresponding to the cutting marks to form a plurality of independent second memory chip groups.
For example, before the first memory chip subjected to plastic molding is attached to a die attach film, in this embodiment, the method further includes:
and forming salient points on the surfaces of the second memory chip on the top layer and the first plastic packaging layer, which are deviated from the first memory chip, wherein the salient points are electrically connected with the second conductive through holes.
Further preferably, before the first bump is formed, a dielectric layer is first formed on the surface of the second memory chip and the first molding layer on the top layer, which face away from the first memory chip.
Specifically, as shown in fig. 8, a dielectric layer 170 is coated on the top surfaces of the second memory chip and the first molding layer 140, which are away from the first memory chip 110, the material of the dielectric layer 170 may be Polyimide (PI), Polybenzoxazole (PBO), or the like, the coating method is usually wafer spin coating, and the embodiment is not limited in particular.
Next, a rewiring layer is formed on the dielectric layer. Specifically, as shown in fig. 8, the dielectric layer 170 is patterned by a photolithography process to form a plurality of first openings (not shown), and a redistribution layer 180 is deposited at the plurality of first openings, the deposition method is sputtering, electroplating, and the like, the material of the redistribution layer 180 is usually titanium and copper, and the deposition method and the metal material are not particularly limited in this embodiment. The redistribution layer 180 is formed on the dielectric layer 170, so that high-density interconnection requirements can be well met, and the yield is improved.
And forming a bump on the rewiring layer. Specifically, as shown in fig. 8, the redistribution layer 180 is patterned by using a photolithography process, a plurality of second openings (not labeled) are formed on the redistribution layer 180, and a plurality of bumps 190 are formed at the plurality of second openings. The plurality of bumps 190 are electrically connected to the plurality of second conductive vias 131 on the substrate 130.
In this embodiment, since the first memory chip 110 is thick, after the bumps 190 are formed, as shown in fig. 9, the side of the first memory chip 110 away from the second memory chip 120 needs to be thinned.
And finally, forming a non-conductive adhesive film on the salient points. Specifically, as shown in fig. 10, after thinning the side of the first memory chip 110 away from the second memory chip 120, a non-conductive adhesive film 200 is formed on the plurality of bumps 190, and the non-conductive adhesive film 200 wraps the plurality of bumps 190 to protect the plurality of bumps 190. The non-conductive adhesive film 200 may also be filled with other underfill, which may be selected according to actual needs, and the embodiment is not limited in particular.
It should be noted that, in step S140, it is optional to sequentially form the dielectric layer 170 and the redistribution layer 180 on the surfaces of the top second memory chip and the first plastic package layer 140 away from the first memory chip 110, and a plurality of bumps 190 may also be directly formed on the surfaces of the top second memory chip and the first plastic package layer 140 away from the first memory chip 110.
After the above steps are completed, as shown in fig. 11, the first memory chip 110 after plastic encapsulation is attached to the die attach film 150, and the first plastic encapsulation layer 140 is cut at the position corresponding to the plurality of cutting traces 111 to form a cutting street 161, so that the plurality of second memory chips 120 stacked in sequence form a plurality of independent second memory chip sets 160. When the first molding compound layer 140 is cut, the cutting path 161 is stopped from the surface of the first memory chip 110 facing the second memory chip 120.
S150, cutting the first memory chip along the plurality of cutting marks to form a plurality of independent memory stacking modules.
Illustratively, as shown in fig. 12, the patch film 150 is stretched under a predetermined low temperature condition, so that the plurality of cutting traces 111 (i.e., laser damage layers) in the first memory chip 110 are enlarged under the stretching force, and finally the separation of the first memory chip 110 is achieved, thereby forming a plurality of independent memory stack modules 210 as shown in fig. 13, wherein each independent memory stack module 210 includes the first memory chip 110 and a plurality of second memory chips 120.
And S160, carrying out hot-press bonding on the plurality of memory stacking modules and a substrate, wherein the substrate is provided with a second conductive through hole.
Illustratively, as shown in fig. 14, the substrate 130 is provided with a plurality of second conductive vias 131, and a surface of the substrate 130 facing the memory stack module 210 is provided with fourth metal pads 132. The plurality of memory stack modules 210 are thermocompression bonded to the substrate 130, specifically, the bump 190 is thermocompression bonded to the fourth metal pad 132. That is, the plurality of memory stack modules 210 are attached to the substrate 130 through a thermocompression bonding process. The plurality of bumps 190 are electrically connected to the plurality of second conductive vias 131 through the plurality of fourth metal pads 132 on the substrate 130, so as to realize signal propagation between the memory stack module 210 and the substrate 130.
When the plurality of memory stack modules 210 and the fourth metal pads 132 are bonded by hot pressing, a pre-soldering process may be performed to pre-position the memory stack modules 210 relative to each other on the substrate 130 for a subsequent packaging process. The bumps 190 or the fourth metal pads 132 may be coated with solder, and the relative position of the memory stack module 210 on the substrate 130 may be fixed in advance by hot pressing of a hot pressing process, but the pre-soldering process may also be performed by melting the solder on the bumps 190 and the fourth metal pads 132 with a soldering pen to fix the relative position of the memory stack module 210 on the substrate 130 in advance.
It should be further noted that the solder may be a copper-zinc alloy material, a silver-copper alloy material, a tin-lead alloy material, or the like, and is capable of melting in a protective gas atmosphere at a preset temperature, and the solder that is convenient for the bump 190 or the fourth metal pad 132 to dip can be the solder described in this embodiment, which is not limited herein.
It should be noted that, in this embodiment, the positions of the fourth metal pads 132 correspond to the positions of the bumps 190 and have the same number, if the substrate 130 is not a dedicated substrate adapted to the second memory chip 120 and the first memory chip 110, but the substrate in the chip package manufacturing process may be a general-purpose substrate, the number of the fourth metal pads 132 on the substrate 130 may be greater than the number of the bumps 190 on the second memory chip 120, as long as it is ensured that the bumps 190 on the second memory chip 120 all have the corresponding fourth metal pads 132 to be connected in a matching manner, so as to ensure sufficient information transmission channels between the second memory chip 120 and the substrate 130, the number of the bumps 190 is determined according to the number of the information transmission channels between the second memory chip 120 and the substrate 130, and is intended to ensure sufficient information transmission channels between the second memory chip 120 and the substrate 130, the operation efficiency of the second memory chip 120 is ensured. In this embodiment, the material of the fourth metal pad 132 may be a metal copper material, and the material of the bump 190 may be a copper-tin material, which is not specifically limited in this embodiment.
S170, carrying out plastic package on the substrate and the memory stacking module to form a second plastic package layer.
Specifically, as shown in fig. 14, the substrate 130 and the memory stack module 210 are molded to form a second molding compound layer 220, and the second molding compound layer 220 wraps the substrate 130 and the memory stack module 210. The plastic packaging method may be vacuum lamination of the film layer or a conventional plastic packaging process, and this embodiment is not particularly limited.
And S180, cutting the second plastic packaging layer and the substrate to form an independent memory packaging structure.
Illustratively, before the dicing the second molding compound layer and the substrate, the method further comprises:
as shown in fig. 15, a solder ball 133 is formed on a surface of the substrate 130 facing away from the memory stack module 210, and the solder ball 133 corresponds to the second conductive via 131. In this embodiment, the solder balls 133 may be made of a copper-tin material.
After the solder balls 133 are formed, the second molding compound layer 220 and the substrate 130 are cut to form a separate multi-layer stacked memory package structure as shown in fig. 16.
According to the multilayer stacked memory packaging method, the second memory chips with the first conductive through holes are sequentially mixed, bonded and stacked on the first memory chip, and the memory stacked modules and the substrate are subjected to hot-press bonding, so that ultrafine-pitch interconnection can be realized, the number of vertical interconnections is increased, the number of data channels is increased, the data throughput can be improved, and meanwhile, due to the fact that the second memory chips and the first memory chip and the second memory chip are mixed and bonded, the bonding height is reduced, the number of layers of the memory chips can be increased, and the capacity is increased.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. A multilayer stacked memory package structure is characterized in that the package structure comprises a first memory chip, a plurality of second memory chips, a substrate and a plastic package layer;
a plurality of first conductive through holes are formed in the second memory chip, and a plurality of second conductive through holes electrically connected with the plurality of first conductive through holes are formed in the substrate;
the plurality of second memory chips are sequentially stacked on the substrate, the plurality of second memory chips are in hybrid bonding connection, and the substrate is in thermocompression bonding connection with the second memory chips;
the first memory chips are arranged on one sides of the second memory chips, which face away from the substrate, and the first memory chips are in hybrid bonding connection with the second memory chips;
the plastic package layer wraps the first memory chip, the plurality of second memory chips and the substrate.
2. The package structure of claim 1, wherein a surface of the second memory chip facing the first memory chip is provided with a first passivation layer and a first metal pad, and a surface of the second memory chip facing away from the first memory chip is provided with a second passivation layer and a second metal pad;
the first passivation layer and the second passivation layer in every two adjacent layers of the second memory chip are in hybrid bonding connection;
and the first metal pad and the second metal pad in every two adjacent layers of the second memory chip are in hybrid bonding connection.
3. The package structure of claim 2, wherein a surface of the first memory chip facing the second memory chip is provided with a third passivation layer and a third metal pad;
the third passivation layer is in hybrid bonding connection with the first passivation layer on the side, facing the first memory chip, of the second memory chip;
the third metal pad is in hybrid bonding connection with the first metal pad on the side, facing the first memory chip, of the second memory chip.
4. The package structure according to claim 1, wherein a surface of the substrate facing the second memory chip is provided with a fourth metal pad, and a side of the second memory chip close to the substrate facing the substrate is provided with a bump;
and the fourth metal pad is connected with the salient point in a hot-pressing bonding mode.
5. The package structure of claim 4, further comprising a non-conductive adhesive film, wherein the non-conductive adhesive film wraps the bump.
6. The package structure of claim 5, further comprising a dielectric layer and a redistribution layer disposed in sequence over the second passivation layer of the second memory chip proximate to the substrate, wherein the redistribution layer is electrically connected to the bump.
7. The package structure according to any one of claims 1 to 6, further comprising a solder ball disposed on a surface of the substrate facing away from the second memory chip, wherein the solder ball corresponds to and is electrically connected to the second conductive via.
8. The package structure according to any one of claims 1 to 6, wherein the first conductive via and the second conductive via are both through silicon vias.
9. The package structure of any one of claims 1 to 6, wherein the molding layer comprises a first molding layer and a second molding layer,
the first plastic packaging layer is arranged on the first memory chips and sleeved outside the plurality of second memory chips;
the second plastic package layer is arranged on the substrate and sleeved on the first plastic package layer and the outer side of the first memory chip.
10. A method of packaging a multi-level stacked memory, wherein the multi-level stacked memory package structure is the package structure of any one of claims 1 to 9, the method comprising:
forming a plurality of cutting marks at preset positions in the first memory chip;
sequentially mixing, bonding and stacking a plurality of second memory chips with first conductive through holes on the first memory chip between two adjacent cutting marks;
plastically packaging the first memory chip and the plurality of second memory chips to form a first plastic packaging layer;
adhering the first memory chip subjected to plastic packaging to a film, and cutting the first plastic packaging layer at positions corresponding to the plurality of cutting marks to form a plurality of independent second memory chip groups;
cutting the first memory chip along the plurality of cutting marks to form a plurality of independent memory stacking modules;
carrying out thermocompression bonding on the plurality of memory stacking modules and a substrate, wherein the substrate is provided with a second conductive through hole;
carrying out plastic package on the substrate and the memory stacking module to form a second plastic package layer;
and cutting the second plastic packaging layer and the substrate to form an independent memory packaging structure.
CN202111496915.2A 2021-12-08 2021-12-08 Multilayer stacked memory packaging structure and packaging method Pending CN114171506A (en)

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PCT/CN2022/137244 WO2023104093A1 (en) 2021-12-08 2022-12-07 Packaging method and packaging structure of multi-layer stacked high-bandwidth memory

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104093A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Packaging method and packaging structure of multi-layer stacked high-bandwidth memory
WO2024022116A1 (en) * 2022-07-27 2024-02-01 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor
WO2024125547A1 (en) * 2022-12-16 2024-06-20 维沃移动通信有限公司 Packaging structure, electronic device and packaging method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023104093A1 (en) * 2021-12-08 2023-06-15 Tongfu Microelectronics Co., Ltd. Packaging method and packaging structure of multi-layer stacked high-bandwidth memory
WO2024022116A1 (en) * 2022-07-27 2024-02-01 长鑫存储技术有限公司 Semiconductor structure and manufacturing method therefor
WO2024125547A1 (en) * 2022-12-16 2024-06-20 维沃移动通信有限公司 Packaging structure, electronic device and packaging method

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