CN101656248A - Chip-stacked package structure of substrate with groove and packaging method thereof - Google Patents
Chip-stacked package structure of substrate with groove and packaging method thereof Download PDFInfo
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- CN101656248A CN101656248A CN200810213650A CN200810213650A CN101656248A CN 101656248 A CN101656248 A CN 101656248A CN 200810213650 A CN200810213650 A CN 200810213650A CN 200810213650 A CN200810213650 A CN 200810213650A CN 101656248 A CN101656248 A CN 101656248A
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- active surface
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- 239000000758 substrate Substances 0.000 title claims abstract description 95
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 abstract description 4
- 238000000576 coating method Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 238000012856 packing Methods 0.000 description 3
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Wire Bonding (AREA)
Abstract
The invention discloses a chip stacking structure, which comprises a substrate, a conducting layer, a first chip, a plurality of first leads, a second adhesion layer, a second chip, a plurality of second leads, a packaging body and a plurality of conducting elements, wherein the substrate is provided with a front and a back, the front of the substrate is provided with a groove, and two sides of the substrate are provided with a plurality of through holes; the conducting layer is arranged in the plurality of through holes to form a plurality of conducting posts; the first chip is provided withan active surface and a back, the active surface is upwards, and the back of the first chip is fixedly connected to the surface of the groove of the substrate through a first adhesion layer; the plurality of first leads are used for electrically connecting the first chip and the surface of the groove of the substrate; the second adhesion layer coats partial first leads and the first chip; the second chip is provided with an active surface and a back, the active surface is upwards, and the second chip is connected with the second adhesion layer through the back; the second adhesion layer coatspartial first leads; the plurality of second leads are used for electrically connecting the second chip and the surface of the groove of the substrate; the packaging body is used for coating the firstchip, the second chip, the plurality of first leads, the plurality of second leads and partial front of the substrate; and the plurality of conducting elements are arranged on the surfaces of the plurality of conducing posts exposed on the front of the substrate.
Description
Technical field
Relevant a kind of encapsulating structure of the present invention and method thereof, particularly relevant a kind of with a plurality of chip-stacked encapsulating structure and method for packing thereof in the substrate of groove.
Background technology
In various application, in a single integrated circuit structure the worth a kind of encapsulating structure that need consider with a plurality of Chip Packaging.This kind encapsulating structure can the integrality of limiting element on two chips.The chip-stacked restriction of this kind is that whether can be packaged into a single encapsulating structure by electronic component caused.In addition, the chip-stacked restriction of this kind also can cause electronic component and encapsulating structure incompatibility to improve.For example, the element on the chip of two different size sizes may produce the demand of different voltages.
In addition, two identical Chip Packaging of size are connected with extraneous by the setting of sharing at an encapsulating structure and two chips.In general, the upper surface of chip comprises a plurality of connection end points in order to electrically connect with outer member.When a plurality of Chip Packaging became an encapsulating structure, each chip can only touch the one side of chip, was a very important problem in an encapsulating structure with a plurality of Chip Packaging therefore.
Summary of the invention
In view of above problem, main purpose of the present invention is to utilize the substrate with groove to carry out piling up so as to dwindling package dimensions of multicore sheet.
Another object of the present invention is to utilize the interior conductive pole of substrate as electrically connecting element, in order to electrically connect most encapsulating structures, to form a multiple stacked structure.
According to above-mentioned purpose, the present invention discloses a kind of semiconductor stack stack structure, comprising: a substrate has a front and a back side and has the positive interior both sides that reach a plurality of through holes at substrate that a groove is arranged on substrate; One conductive layer is arranged in a plurality of through holes to form a plurality of conductive poles; One first chip has an active surface and a back side, and active surface up and by first adhesion layer back side of first chip is fixed on the surface of groove of substrate; Many first leads are in order to the surface of the groove that electrically connects first chip and substrate; One second adhesion layer coats partly first lead and first chip; Second chip has an active surface and a back side, and active surface is connected with first chip up and by second adhesion layer, and second adhesion layer coating part, first lead; Many second leads are in order to the surface of the groove that electrically connects second chip and substrate; One packaging body is in order to coat the partial front of first chip, second chip, many first leads, many second leads and substrate; And a plurality of conducting elements, be arranged on the surface of a plurality of conductive poles in the front that is exposed to substrate.
According to above-mentioned semiconductor stack stack structure, the present invention also discloses a kind of method that forms the semiconductor stack stack structure, and it comprises: a substrate is provided, has a positive and back side and in having a groove on the front and have a plurality of through holes in the both sides of substrate; Form a conductive layer in a plurality of through holes to form a plurality of conductive poles; Attach one first chip in the groove of substrate, be up, and be fixed in by first adhesion layer on the part surface of groove the active surface of first chip; Form many first leads, electrically connect the surface of the groove of the active surface of first chip and substrate; Attaching one second chip, is that wherein second adhesion layer is in order to coat the active surface of part first lead and first chip with the active surface of second chip up and affixed by second adhesion layer and first chip; Form many second leads, electrically connect the surface of the groove of the active surface of second chip and substrate; Form a packaging body, in order to coat the partial front of first chip, second chip, many first leads, many second leads and substrate; And form a plurality of conducting elements on a surface of a plurality of conductive poles that exposed to the open air in the front of substrate.
The present invention discloses in addition a kind of multiple stacked structure, and it comprises: a substrate has a positive and back side and in having on the front in a groove and the both sides of a plurality of through hole at substrate; One conductive layer is arranged in a plurality of through holes to form a plurality of conductive poles; One first chip has an active surface and a back side, and active surface up and by first adhesion layer back side of first chip is fixed on the surface of groove of substrate; Many first leads are in order to the surface of the groove that electrically connects first chip and substrate; One second adhesion layer coats partly first lead and first chip; Second chip has an active surface and a back side, and active surface is connected with first chip up and by second adhesion layer, and second adhesion layer coating part, first lead; Many second leads are in order to the surface of this groove of electrically connecting second chip and substrate; One packaging body is in order to coat the partial front of first chip, second chip, many first leads, many second leads and substrate; A plurality of conducting elements, go up to form one first semiconductor package on a surface that is arranged on a plurality of conductive poles in the front that is exposed to substrate; And a stacked structure, be to be electrically connected on the conduction end points of a plurality of conductive poles of first chip stack structure with a plurality of conducting elements that first chip stack structure has one second chip stack structure of mutually same structure.
According to above-mentioned multiple stacked structure, the present invention discloses a kind of method that forms multiple stacked structure in addition, and it comprises: a substrate is provided, has a positive and back side, and have a groove and have a plurality of through holes in the both sides of substrate on the front; Form a conductive layer in a plurality of through holes to form a plurality of conductive poles; Attaching one first chip in the groove of substrate, is with an active surface of first chip up and be fixed in by one first adhesion layer on the part surface of groove; Form many first leads, electrically connect the surface of the groove of the active surface of first chip and substrate; Attaching one second chip, is that wherein second adhesion layer is in order to coat the active surface of many first leads of part and first chip with an active surface of second chip up and affixed by one second adhesion layer and first chip; Form many second leads, electrically connect the surface of the groove of the active surface of second chip and substrate; Form a packaging body, in order to coat the partial front of first chip, second chip, many first leads, many second leads and substrate; Form a plurality of conducting elements on a surface of a plurality of conductive poles that exposed to the open air in the front of substrate, to form one first chip stack structure; And pile up one second chip stack structure that has same structure with first encapsulating structure, be on the conduction end points of a plurality of conducting elements with second chip stack structure a plurality of conductive poles of being electrically connected to first chip stack structure.
Description of drawings
For can clearer understanding purpose of the present invention, structure, feature and function thereof, below conjunction with figs. is elaborated to preferred embodiment of the present invention, wherein:
Fig. 1 to Fig. 7 is disclosed technology according to the present invention, and expression forms each step schematic diagram of chip-stacked encapsulating structure; And
Fig. 8 is disclosed technology according to the present invention, and expression forms the schematic diagram of multiple stacked structure.
Embodiment
The present invention is a kind of encapsulating structure and method for packing thereof in this direction of inquiring into, and a groove that a plurality of chips is formed on substrate is to reduce package dimensions size, the method that encapsulates then.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention do not limit Chip Packaging mode be specific details that those skilled in the art were familiar with.On the other hand, the detailed step of back segment operations such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet,, can be described in detail as follows for preferred embodiment of the present invention, yet except these are described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention do not limited, and it is as the criterion with appended claim institute restricted portion.
Fig. 1 to Fig. 7 is disclosed technology according to the present invention, and expression forms each step schematic diagram of chip-stacked encapsulating structure.At first, please refer to Fig. 1, it provides the substrate 10 with a groove 12, and the formation method of its further groove 12 is to utilize general semiconductor technology, and it comprises: the substrate 10 that provides and have a front (expression in the drawings) and a back side (expression in the drawings) earlier; Then, form the photoresist layer (not expression in the drawings) of a patterning; Then, carry out one and develop and etching step, remove partly substrate 10, make that the central part that is adjacent at substrate 10 forms a groove 12.At this, the material of substrate 10 can be PCB circuit board or the metal substrate (metal foil) that has configured configuration.
Then, again the photoresist layer of another patterning (expression in the drawings) is formed on the substrate 10 with groove 12; Develop then and etching, make to form a plurality of through holes 102, as shown in Figure 2 in the both sides with groove 12 of substrate 10; And then, after the photoresist layer of strip patternization, in each through hole 102, select suitable electric conducting material to form conductive pole 20, the method that its conductive pole 20 forms comprises electric conducting material, be packed in a plurality of through holes 102 in the mode of electroplating (plating), and the upper and lower surface exposure that makes each conductive pole 20 is in the two ends on the upper and lower surface of packaging body, form the first conduction end points 202 and the second conduction end points 204 respectively, as shown in Figure 3.
Then please refer to Fig. 4, being expression is formed on schematic diagram on the groove of substrate with one first chip.In Fig. 4, provide one first chip 40, it has an active surface and a back side, and a plurality of weld pads 402 are arranged on active surface; Then, with the active surface of first chip 40 up and groove 12 lip-deep first adhesion layers 30, the back side of first chip 30 is anchored on the surface of groove 12 of substrate 10 by being formed on substrate 10.In another embodiment, first adhesion layer 30 can be formed on the back side of first chip 40 earlier, and then is pasted on the surface of groove 12 of substrate 10, and the chip 40 of winning is anchored on the substrate 10 by first adhesion layer 30.In this embodiment, the material of first adhesion layer 30 is two-stage hot-setting adhesive (B-stage).Then, utilize routing to engage the mode of (bonding wire), one end of many first leads 50 is formed on a plurality of weld pads 402 of active surface of first chip 40, the other end of its many first leads 50 is formed on the surface of groove 12 of substrate 10, in order to electrically connect the substrate 10 and first chip 40.
And then, please refer to Fig. 5, it is that expression is with the second chip-stacked schematic diagram on first chip.In Fig. 5, be that one second chip 42 is provided earlier, it has an active surface and a back side, and has a plurality of weld pads 422 on active surface; Then, the active surface of second chip 42 up, and be attached on first chip 40 by one second adhesion layer 32, to form a chip stack structure, envelope many first leads 50 of part that electrically connect with first chip 40 and the active surface that covers first chip 40 simultaneously at this second adhesion layer 32.At this, the material of second adhesion layer 32 can be
Bao Mo Fu Cover Soldering Line (film over wireFOW).Continue equally with reference to figure 5, it is the mode of utilizing routing to engage, one end of many second leads 52 is formed on a plurality of weld pads 422 of active surface of second chip 42 and the other end is formed on the surface with groove 12 of substrate 10, and electrically separates with groove 12 lip-deep many first leads 40 that are formed on substrate 10.In this embodiment, its first chip 40 and second chip 42 can be the chips with same size and function, or have the chip of different size and function.
And then, with reference to figure 6, it is that expression forms the schematic diagram of a packaging body with the coating chip stacked structure.In Fig. 6, be that a macromolecular material (not expression in the drawings) is injected in the groove 12 of substrate 10.Then, macromolecular material is carried out a baking program (bake process), macromolecular material is solidified forming a packaging body 60 enveloping first adhesion layer 30, first chip 40, second adhesion layer 32, second chip 42, many first leads 50 and many second leads 52, and cover on the front of substrate 10 partly.In this embodiment, macromolecular material can be silica gel, epoxy resin, acrylic acid (acrylic), reach benzocyclobutene materials such as (BCB).
Then, with reference to figure 7, it is that expression is formed on the end points of conductive pole a plurality of conducting elements to finish the schematic diagram of an encapsulating structure.First end points 202 at the upper surface of a plurality of conductive poles 20 that expose to the open air forms a plurality of conducting elements 70 in the arrayed mode, and for example metal coupling (metal bump) or tin ball (solder ball) are promptly finished chip-stacked encapsulating structure.
In addition, in another embodiment, a plurality of chip-stacked encapsulating structures can be piled up each other, as shown in Figure 8.In Fig. 8, be to pile up with second chip stack structure that first chip stack structure has a same structure, make the second conduction end points 204 of conductive pole 20 of a plurality of conducting elements 70 of second chip stack structure and first chip stack structure electrically connect, at this, between a plurality of conducting elements 70 of second conduction end points 204 and second chip stack structure of conductive pole 20, also comprise a plurality of weld pads 80, can form a multiple stacked structure whereby.
Though the present invention discloses as above with aforesaid preferred embodiment; yet it is not in order to limit the present invention; anyly be familiar with those skilled in the art; without departing from the spirit and scope of the present invention; when can making all changes that is equal to or replacement, therefore scope of patent protection of the present invention must be looked being as the criterion that the appended the application's claim scope of this specification defined.
Claims (10)
1. semiconductor stack stack structure comprises:
One substrate has a positive and back side and has a groove and is arranged in this front of this substrate and reaches the both sides of a plurality of through holes at this substrate;
One electric conducting material is arranged in these through holes to form a plurality of conductive poles;
One first chip has an active surface and a back side, and this active surface up and by one first adhesion layer this back side of this first chip is fixed on the surface of this groove of this substrate;
Many first leads are on this surface in order to this groove of electrically connecting this first chip and this substrate;
One second adhesion layer coats partly these first leads and this first chip;
One second chip has an active surface and a back side, and this active surface reaches this back side up and be connected with this second adhesion layer, and this second adhesion layer coats partly these first leads;
Many second leads are on this surface in order to this groove of electrically connecting this second chip and this substrate;
One packaging body should the front in order to the part that coats this first chip, this second chip, these first leads, these second leads and this substrate; And
A plurality of conducting elements, it is arranged on the surface of these conductive poles in this front that is exposed to this substrate.
2. semiconductor stack stack structure according to claim 1 is characterized in that this first chip is identical with the size of this second chip.
3. semiconductor stack stack structure according to claim 1 is characterized in that this first chip is different with the size of this second chip.
4. method that forms the semiconductor stack stack structure comprises:
One substrate is provided, has a positive and back side and in having a groove on this front and in the both sides of this substrate, having a plurality of through holes;
Form a conductive layer in these through holes to form a plurality of conductive poles;
Attaching one first chip in this groove of this substrate, is with an active surface of this first chip up and be fixed in by one first adhesion layer on the part surface of this groove;
Form many first leads, electrically connect this surface of this groove of this active surface of this first chip and this substrate;
Attaching one second chip, is that a active surface with this second chip reaches this back side up and one second adhesion layer is affixed, and wherein this second adhesion layer is in order to coat partly this active surface of these first leads and this first chip;
Form many second leads, electrically connect this surface of this groove of this active surface of this second chip and this substrate;
Form a packaging body, should the front in order to the part that coats this first chip, this second chip, these first leads, these second leads and this substrate; And
Form a plurality of conducting elements on a surface of these conductive poles that exposed to the open air in this front of this substrate.
5. method according to claim 4 is characterized in that the method that forms this groove comprises:
The photoresist layer that forms a patterning is on this substrate;
Be etched with and remove partly this substrate; And
Remove the photoresist layer of this patterning, to form this groove on this front of this substrate.
6. method according to claim 4 is characterized in that the size of this first chip and this second chip is identical.
7. method according to claim 4 is characterized in that the size difference of this first chip and this second chip.
8. multiple stacked structure comprises:
One substrate has a positive and back side and in having on this front in a groove and the both sides of a plurality of through hole at this substrate;
One conductive layer is arranged in these through holes to form a plurality of conductive poles;
One first chip has an active surface and a back side, and with this active surface up and by one first adhesion layer this back side of this first chip is fixed on the surface of this groove of this substrate;
Many first leads are in order to this surface of this groove of electrically connecting this first chip and this substrate;
One second adhesion layer coats partly these first leads and this first chip;
One second chip has an active surface and a back side, and with this active surface up and this back side and one second adhesion layer affixed, and this second adhesion layer coats partly these first leads;
Many second leads are on this surface in order to this groove of electrically connecting this second chip and this substrate;
One packaging body should the front in order to the part that coats this first chip, this second chip, these first leads, these second leads and this substrate;
A plurality of conducting elements, go up to form one first chip stack structure on a surface that is arranged on these conductive poles in this front that is exposed to this substrate; And
One multiple stacked structure is to be electrically connected on the conduction end points of these conductive poles of this first chip stack structure with a plurality of conducting elements that this first chip stack structure has one second chip stack structure of mutually same structure.
9. multiple stacked structure according to claim 8 is characterized in that also comprising a plurality of connection weld pads between these conducting elements of these conduction end points on this first chip and this second chip.
10. method that forms multiple stacked structure comprises:
One substrate is provided, has a front and a back side and have a plurality of through holes in having on this front in a groove and the both sides at this substrate;
Form a conductive layer in these through holes to form a plurality of conductive poles;
Attaching one first chip in this groove of this substrate, is with an active surface of this first chip up and be fixed in by one first adhesion layer on the part surface of this groove;
Form many first leads, electrically connect this surface of this groove of this active surface of this first chip and this substrate;
Attaching one second chip, is that a active surface with this second chip reaches this back side up and this one second adhesion layer is affixed, and wherein this second adhesion layer is in order to coat partly this active surface of these first leads and this first chip;
Form many second leads, electrically connect this surface of this groove of this active surface of this second chip and this substrate;
Form a packaging body, should the front in order to the part that coats this first chip, this second chip, these first leads, these second leads and this substrate;
Form a plurality of conducting elements on a surface of these conductive poles that exposed to the open air in this front of this substrate, to form one first chip stack structure; And
Pile up one second chip stack structure that has same structure with this first chip stack structure, be on the conduction end points of a plurality of conducting elements with this second chip stack structure these conductive poles of being electrically connected to this first chip stack structure, to form this multiple stacked structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810213650A CN101656248A (en) | 2008-08-19 | 2008-08-19 | Chip-stacked package structure of substrate with groove and packaging method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810213650A CN101656248A (en) | 2008-08-19 | 2008-08-19 | Chip-stacked package structure of substrate with groove and packaging method thereof |
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| CN101656248A true CN101656248A (en) | 2010-02-24 |
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| CN200810213650A Pending CN101656248A (en) | 2008-08-19 | 2008-08-19 | Chip-stacked package structure of substrate with groove and packaging method thereof |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315196A (en) * | 2010-07-08 | 2012-01-11 | 南茂科技股份有限公司 | Multigrain stack encapsulation structure |
| CN103219324A (en) * | 2012-01-18 | 2013-07-24 | 刘胜 | Stackable semiconductor chip packaging structure and process thereof |
| CN103325799A (en) * | 2012-03-20 | 2013-09-25 | 南茂科技股份有限公司 | Chip stacking structure and manufacturing method thereof |
| CN104425429A (en) * | 2013-08-29 | 2015-03-18 | 英飞凌科技股份有限公司 | Semiconductor package with multi-level die block |
| CN104979297A (en) * | 2014-04-13 | 2015-10-14 | 英飞凌科技股份有限公司 | Baseplate for an electronic module and method of manufacturing the same |
| CN106067457A (en) * | 2016-08-11 | 2016-11-02 | 苏州日月新半导体有限公司 | Integrated circuit package body and manufacture method thereof and the base plate for packaging used |
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| CN110085525A (en) * | 2014-06-08 | 2019-08-02 | 联测总部私人有限公司 | The method of semiconductor packages and encapsulation semiconductor device |
| CN110690208A (en) * | 2019-10-08 | 2020-01-14 | 中国电子科技集团公司第二十四研究所 | Power hybrid integrated circuit packaging structure |
| WO2021073133A1 (en) * | 2019-10-16 | 2021-04-22 | 长鑫存储技术有限公司 | Semiconductor packaging method, semiconductor package structure, and package body |
| CN114980499A (en) * | 2022-05-19 | 2022-08-30 | 维沃移动通信有限公司 | Packaging structure, packaging method of packaging structure and electronic equipment |
| CN117542794A (en) * | 2024-01-10 | 2024-02-09 | 浙江集迈科微电子有限公司 | Three-dimensional stacked packaging structure based on adapter plate and manufacturing method thereof |
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2008
- 2008-08-19 CN CN200810213650A patent/CN101656248A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315196B (en) * | 2010-07-08 | 2014-08-06 | 南茂科技股份有限公司 | Multigrain stack encapsulation structure |
| CN102315196A (en) * | 2010-07-08 | 2012-01-11 | 南茂科技股份有限公司 | Multigrain stack encapsulation structure |
| CN103219324A (en) * | 2012-01-18 | 2013-07-24 | 刘胜 | Stackable semiconductor chip packaging structure and process thereof |
| CN103325799B (en) * | 2012-03-20 | 2016-12-28 | 南茂科技股份有限公司 | Chip stacking structure and manufacturing method thereof |
| CN103325799A (en) * | 2012-03-20 | 2013-09-25 | 南茂科技股份有限公司 | Chip stacking structure and manufacturing method thereof |
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