CN114980499A

CN114980499A - Packaging structure, packaging method of packaging structure and electronic equipment

Info

Publication number: CN114980499A
Application number: CN202210548324.3A
Authority: CN
Inventors: 蒙凯
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2022-05-19
Filing date: 2022-05-19
Publication date: 2022-08-30

Abstract

The embodiment of the application discloses a packaging structure, a packaging method of the packaging structure and electronic equipment; the packaging structure comprises a first circuit board, a second circuit board, a first functional chip and a second functional chip; the first circuit board is provided with a cavity and a conductive through hole; the first functional chip is arranged in the cavity; the second circuit board is arranged on at least one side of the first functional chip and covers the cavity, the first functional chip is electrically connected with the second circuit board, and the second circuit board is electrically conducted with the first circuit board through the conductive through hole; the second functional chip is disposed on at least one of the first circuit board and the second circuit board.

Description

Packaging structure, packaging method of packaging structure and electronic equipment

Technical Field

The application belongs to the technical field of circuit board production and manufacturing, and particularly relates to a packaging structure, a packaging method of the packaging structure and electronic equipment.

Background

The main board device is one of the core components in the electronic equipment, and along with the gradual increase of the functions of the electronic equipment, the integration level of the main board device is higher and higher. In the related art, the motherboard device mostly uses a Package on Package (PoP) manner to save area.

Taking a System On Chip (SOC) and a Memory (Memory) in a smart phone as examples, a stack structure formed by the SOC is as follows: the device comprises a Memory Package (Memory Package) and an SOC Package (SOC Package), wherein the SOC Package is generally composed of an upper layer Substrate and a lower layer Substrate, the upper layer Substrate (Top Substrate) is used for being connected with a Dynamic Random Access Memory (DRAM), the lower layer Substrate (Bottom Substrate) is used for being connected with a main board in the device, the upper layer Substrate and the lower layer Substrate are generally electrically connected through an intermediate layer (Embedded layer), a common structure comprises Solder balls such as copper balls (Cu Core balls) or Solder balls (Solder balls), and plastic sealing glue (Mold Resin) is used for filling and supporting.

However, since the pad size between the upper and lower substrates is small, the soldering tends to be deviated. Moreover, the SOC package has an upper Substrate and a lower Substrate, and the Memory package also has a Substrate (Memory Substrate), and when the two are stacked and connected to the main board, the total thickness is too high, which is not favorable for the thin design of the electronic product.

Disclosure of Invention

An object of the embodiments of the present application is to provide a package structure, a packaging method of the package structure, and an electronic device, so as to solve the problem that the total thickness of the conventional multi-chip stacked package structure is too high.

In a first aspect, an embodiment of the present application provides a package structure, where the package structure includes:

the first circuit board is provided with a cavity and a conductive through hole;

the first functional chip is arranged in the cavity;

the second circuit board is arranged on at least one side of the first functional chip and covers the cavity, the first functional chip is electrically connected with the second circuit board, and the second circuit board is electrically conducted with the first circuit board through the conductive through hole; and

a second functional chip disposed on at least one of the first circuit board and the second circuit board.

In a second aspect, an embodiment of the present application provides a packaging method of the packaging structure, where the packaging method includes:

arranging a cavity on the first circuit board;

packaging a first functional chip in the cavity, and forming a conductive through hole on the first circuit board;

arranging a second circuit board on at least one side of the first functional chip, enabling the second circuit board to cover the cavity, electrically conducting the first functional chip and the second circuit board, and electrically conducting the first circuit board and the second circuit board through a conductive through hole;

disposing a second functional chip on at least one of the first circuit board and the second circuit board.

In a third aspect, an embodiment of the present application provides an electronic device, which includes the package structure described above.

In the embodiment of the application, a circuit board is used for accommodating a part of functional chips, the stacking height of the packaging structure can be obviously reduced, the circuit board is provided with the conductive through hole, the circuit board can be electrically conducted with another circuit board (the circuit board can be a rewiring layer formed on the functional chips) through the conductive through hole, the original copper Ball (Cu Core Ball) or Solder Ball (Solder Ball) is replaced by the conductive through hole technology between the two layers of circuit boards, the electrical connection between the upper layer circuit board and the lower layer circuit board is realized, and the purpose of reducing the height of products can be finally achieved.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of a package structure provided in an embodiment of the present application;

fig. 2 is a second schematic structural diagram of a package structure according to an embodiment of the present disclosure;

fig. 3 is a third schematic structural diagram of a package structure according to an embodiment of the present application;

fig. 4 is a schematic flowchart of a packaging method of a package structure according to an embodiment of the present disclosure;

FIG. 5 is one of the flow diagrams of a packaging method of the package structure shown in FIG. 1;

FIG. 6 is a second flowchart of the packaging method of the package structure shown in FIG. 1;

FIG. 7 is one of the flow diagrams of a packaging method of the package structure shown in FIG. 2;

FIG. 8 is a second flowchart of a packaging method of the package structure shown in FIG. 2;

FIG. 9 is one of the flow diagrams of a packaging method of the package structure shown in FIG. 3;

FIG. 10 is a second flowchart of a packaging method of the package structure shown in FIG. 3;

fig. 11 is a third flowchart illustrating a packaging method of the package structure shown in fig. 3.

Reference numerals:

100. a first circuit board; 110. a cavity; 120. a conductive via; 130. a substrate circuit layer; 200. a second circuit board; 300. a first functional chip; 400. a second functional chip; 500. pasting a film; 600. a colloid; 700. a plastic packaging layer; 800. welding the part; 900. and (4) gold wires.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The features of the terms first and second in the description and in the claims of the present application may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specified. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.

In the description of the present application, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The package structure, the package method of the package structure, and the electronic device provided in the embodiments of the present application are respectively described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.

The packaging structure provided by the embodiment of the application can be applied to various types of electronic equipment, has the characteristics of small height and size and convenience in welding, and is favorable for realizing the light and thin development of the electronic equipment.

According to an embodiment of the present application, there is provided a package structure, referring to fig. 1 to 3, including a first circuit board 100, a second circuit board 200, a first functional chip 300, and a second functional chip 400; a cavity 110 is provided on the first circuit board 100, and a conductive through hole 120 penetrating in a thickness direction is further provided on the first circuit board 100; the first functional chip 300 is disposed in the cavity 110; the second circuit board 200 is disposed on at least one side of the first functional chip 300 and covers the cavity 110, the first functional chip 300 is electrically connected to the second circuit board 200, and the second circuit board 200 is electrically connected to the first circuit board 100 through the conductive via 120; the second functional chip 400 is disposed on at least one of the first circuit board 100 and the second circuit board 200.

In the embodiment of the present application, no intermediate layer (the intermediate layer includes, for example, a copper ball or a solder ball and a layer filled with a glue) is disposed between the first circuit board 100 and the second circuit board 200 for electrically connecting the two circuit boards, but the first circuit board 100 is directly provided with the conductive via 120, and the two circuit boards are electrically connected by the conductive via 120, so that the electrical connection is more stable, and the dimension in the thickness direction can be reduced, thereby being beneficial to reducing the height of the package structure.

That is, in the embodiment of the present application, one or more conductive vias 120 may be directly formed on the first circuit board 100, and may be used for electrical connection with other devices such as circuit boards.

In an embodiment of the present application, a conductive metal material may be plated inside the conductive via 120.

For example, the wall of the conductive via 120 is plated with a conductive metal material.

For another example, the conductive via 120 may be filled with a conductive metal material.

When the conductive through hole 120 is formed, one skilled in the art may choose to plate only the wall of the conductive through hole 120, or may fill the entire conductive through hole 120 with a conductive metal material.

It should be noted that, if only the hole wall of the conductive through hole 120 is selected to be plated, the conductivity of the conductive through hole 120 is actually realized by the hole wall, and the whole conductive through hole 120 is hollow, so that a large amount of air is left therein, which may cause expansion in the later processing; or else some residue may remain in the holes, which is detrimental to the processing of the product. Therefore, other hole filling materials can be selectively filled in the conductive via 120. The pore-filling material may be, for example, a non-conductive material (insulating material). The weight is light, the integral weight of the product is not increased, and the conductivity of the conductive through hole 120 is not influenced.

In the embodiment of the present application, the first circuit board 100 having the cavity structure in the thickness direction is designed, and a part of the functional chip, such as the first functional chip 300 described above, is accommodated by using the space of the first circuit board 100 in the thickness direction. That is, by using the first circuit board 100 as a carrier, a part of the functional chips can be embedded in the first circuit board 100, and compared with the design of direct stacking (stacking), the size of the entire package structure in the thickness direction can be effectively reduced, and the height of the package structure can be further reduced.

In the embodiment of the present application, the first functional chip 300 is embedded in the first circuit board 100, a Layer of the second circuit board 200 may be formed on at least one surface of the first circuit board, and the second circuit board 200 may be used as a Redistribution Layer (RDL) to distribute the circuits on the first functional chip 300 to a desired place. Thus, the second circuit board 200 can be directly electrically connected to the first circuit board 100 through the conductive via 120.

In the embodiment of the application, a circuit board is used for accommodating a part of functional chips, so that the stacking height of the packaging structure can be obviously reduced, the circuit board is provided with the conductive through hole 120, and the circuit board can be electrically conducted with another circuit board (such as a rewiring layer formed on the functional chips) through the conductive through hole 120, so that the two layers of circuit boards adopt a conductive through hole technology to replace the original copper Ball (Cu Core Ball) or Solder Ball (Solder Ball), the electrical connection between the upper layer circuit board and the lower layer circuit board is realized, and the purpose of reducing the height of the product can be finally achieved.

It should be noted that, in the embodiment of the present application, the first circuit board 100 is designed to have a structure with a cavity, that is, a cavity 110 is formed on the first circuit board 100 and can be used for receiving a part of the functional chip. Meanwhile, the first circuit board 100 is further provided with a conductive through hole 120 penetrating through the thickness direction of the circuit board, and the conductive through hole 120 is disposed to avoid the cavity 110, that is, the conductive through hole 120 is disposed at a position on the first circuit board 100 other than the cavity.

The first circuit board 100 is not limited to be provided with only one cavity 110 for accommodating the first functional chips 300, and the number of the cavities 110 can be flexibly adjusted according to the specific number of the first functional chips 300.

In addition, the number of the second functional chips 400 is not limited, and can be flexibly selected according to specific needs. The second functional chip 400 may be, for example, directly disposed (e.g., mounted) on one of the first circuit board 100 and the second circuit board 200.

It should be noted that when there are a plurality of second functional chips 400, the plurality of second functional chips 400 may be stacked (stacked) to reduce the area of the whole package structure, for example, and those skilled in the art can flexibly adjust the size as required.

In the embodiment of the present application, the specific types of the first functional chip 300 and the second functional chip 400 may be flexibly selected according to needs, which is not limited in the embodiment of the present application.

In some examples of the present application, referring to fig. 1 to 3, the first functional chip 300 may be attached to at least one of the first circuit board 100 and the second circuit board 200 by an adhesive film 500.

In the embodiment of the present application, referring to fig. 1 to 3, the first functional chip 300 is embedded in the cavity 110 of the first circuit board 100, and after the second circuit board 200 (i.e., RDL) is formed on one side of the first functional chip 300, the second circuit board 200 may also cover the cavity 110, so that the cavity 110 forms a closed accommodating space.

Meanwhile, the second circuit board 200 is formed as a re-wiring layer on at least one side of the first functional chip 300, which is electrically connected to the first functional chip 300, for distributing the circuits on the first functional chip 300 to a desired place. On this basis, the second circuit board 200 can be electrically connected to the first circuit board 100 through the conductive via 120.

For example, referring to fig. 1 and fig. 2, a cavity 110 is formed on one side of the first circuit board 100, the first functional chip 300 is located in the cavity 110, and the back side of the first functional chip 300 may be adhered to the bottom wall of the cavity 110 through a Die Attach Film (DAF), for example, that is, fixedly connected to the first circuit board 100. At this time, the second circuit board 200 may be formed on the side of the cavity 110 that is open, that is, on the side of the first functional chip 300 that faces away from the first circuit board 100, so as to distribute the circuits on the first functional chip 300 to the required places. Thus, the second circuit board 200 (i.e., a rewiring layer) is formed on one surface of the first functional chip 300, and the circuit can be electrically connected to the first circuit board 100 through the conductive via 120.

For another example, referring to fig. 3, a cavity 110 is formed at one side of the first circuit board 100, the first functional chip 300 is located in the cavity 110, and a back side of the first functional chip 300 may be adhered to a bottom wall of the cavity 110 through a Die Attach Film (DAF), that is, fixedly connected to the first circuit board 100, at this time, a layer of the second circuit board 200 may be covered on an open side of the cavity 110, that is, on a side of the first functional chip 300 away from the first circuit board 100, so as to distribute circuits on the first functional chip 300 to a desired place; meanwhile, the thickness of the first circuit board 100 may be reduced by grinding one side of the first circuit board 100, and the back side of the first functional chip 300 is exposed, at this time, a second circuit board 200 (i.e., a rewiring layer) may also be formed on the back side of the first functional chip 300, and the back side of the first functional chip 300 and the second circuit board 200 may be bonded and fixed by, for example, a Die Attach Film (DAF), and at this time, the second circuit board 200 formed on one surface of the first functional chip 300 may be electrically connected to the second circuit board 200 formed on the back side of the second functional chip 400 through the conductive through hole 120.

Referring to fig. 3, a fan-shaped region may be formed on the back side of the first functional chip 300, a second circuit board 200 (i.e., a rewiring layer) may be formed in the fan-shaped region, the circuits of the first functional chip 300 may be distributed to a desired place, and another second circuit board 200 formed on the surface of the first functional chip 300 may be electrically connected to the second circuit board 200 on the back side of the first functional chip 300 through the conductive via 120.

Referring to fig. 3, in this manner as described above, it is necessary to reduce the thickness dimension of the first circuit board 100 to expose a portion of the first functional chip 300, wherein the second circuit board 200 having a smaller thickness dimension is designed to be used as a rewiring layer, which makes it possible to make the height dimension of the entire package structure lower.

In some examples of the present application, referring to fig. 1 to 3, the cavity 110 is filled with a glue 600 covering the first functional chip 300.

In the embodiment of the present application, the first functional chip 300 is embedded in the cavity 110 of the first circuit board 100, and the second circuit board 200 is matched with the first circuit board 100 to seal the cavity 110 on the first circuit board 100.

However, the first functional chip 300 does not fill the entire cavity 110, i.e., there is a certain empty space in the cavity 110. The empty space can be filled with the colloid 600, and the design can well protect the first functional chip 300 in the cavity 110 and prevent the first functional chip 300 from being damaged after the packaging structure is accidentally dropped or impacted. Meanwhile, the fixing of the first functional chip 300 can be more stable.

In some examples of the present application, the number of the first functional chips 300 is at least one;

when the number of the first functional chips 300 is plural, the plural first functional chips 300 are commonly disposed in one of the cavities 110, or the first circuit board 100 includes plural cavities 110 with different depths, and the plural first functional chips 300 are respectively disposed in the plural cavities 110 with different depths.

In the embodiment of the present application, the first functional chip 300 may be, for example, an IC chip, and the number of the first functional chips may be one, or may be multiple, and a person skilled in the art may flexibly select the first functional chip according to actual needs, which is not limited in the embodiment of the present application.

In the embodiment of the present application, the cavity 110 formed on the first circuit board 100 may be one, or may be a plurality of cavities with different sizes and different depths, so that functional chips with different sizes and structures may be placed therein to adapt to more packaging structure designs.

In some examples of the present application, the number of the second functional chips 400 is at least one; when the number of the second functional chips 400 is plural, the plural second functional chips 400 may be stacked in sequence, and two adjacent second functional chips 400 are bonded by the adhesive film 500.

In the embodiment of the present application, a part of the functional chips may be embedded in the cavity 110 formed on the first circuit board 100, and a part of the functional chips may be stacked on one side of the first circuit board 100 or the second circuit board 200. That is, when the number of functional chips is large, the functional chips can be arranged in a stacked manner, and the area of the whole packaging structure can be reduced.

The second functional chip 400 is, for example, an IC chip, and the number thereof may be two, and referring to fig. 1 to 3, the two IC chips may be bonded to each other by, for example, a Die Attach Film (DAF), and may be bonded to one side of the first circuit board 100 or the second circuit board 200 by a Die Attach Film (DAF).

In the embodiment of the present application, the second functional chip 400 may be mounted and stacked as needed, and may be electrically connected to the first circuit board 100 or the second circuit board 200 by using a gold wire 900, or may be electrically connected to the first circuit board 100 or the second circuit board 200 by using a flip chip method, which is not limited in the embodiment of the present application.

For example, referring to fig. 1, a plurality of second functional chips 400 may be adhesively fixed by a Die Attach Film (DAF) on a side of the first circuit board 100 facing away from the second circuit board 200 in a stacked manner.

For another example, referring to fig. 2 and 3, a plurality of second functional chips 400 are bonded and fixed on a side of the second circuit board 200 facing away from the first circuit board 100 by a Die Attach Film (DAF) in a stacked manner.

In some examples of the present application, referring to fig. 1 to 3, the second functional chip 400 is covered with a molding layer 700.

In the embodiment of the present application, after the second functional chip 400 is mounted on one of the first circuit board 100 and the second circuit board 200, a plastic package (Compound) may be used to mold the second functional chip 400, so as to form a protection structure on the second functional chip 400, so as to better protect the second functional chip 400 of the stacked design. The plastic package layer 700 is dustproof and waterproof, and can also appropriately resist impact, which is helpful for prolonging the service life of the whole package structure.

In some examples of the present application, referring to fig. 1 to 3, a soldering part 800 is provided on a side of the first circuit board 100 and the second circuit board 200 facing the outside.

The soldering portion 800 may be used to solder the package structure of the embodiment of the present application to a motherboard or other components in an electronic device.

The soldering portions 800 may be solder balls, such as copper balls or solder balls, for example, and may be flexibly disposed at suitable positions on the first circuit board 100 or the second circuit board 200 according to requirements, and the number of the solder balls may also be flexibly adjusted according to the area of the package structure, which is not limited in the embodiment of the present application.

The embodiment of the present application further provides a packaging method of a package structure, which can be used for manufacturing the package structure, and the packaging method is described in detail below with reference to fig. 4 to 11.

According to the packaging method of the packaging structure provided by the embodiment of the application, as shown in fig. 4, the packaging method includes:

step 410, forming a cavity 110 on the first circuit board 100.

This step 410 may include the steps of:

step 411, providing a PCB substrate;

the PCB substrate may have no circuit layer, and then a predetermined substrate circuit layer 130 is selectively formed on one side of the PCB substrate as required, as shown in fig. 5. Of course, the circuit layer may not be fabricated, and those skilled in the art may flexibly select the circuit layer according to needs, and the embodiment of the present application does not specifically limit this.

Step 412, after step 411, a cavity structure is fabricated on one side of the PCB substrate to form the cavity 110 on the first circuit board 100.

For example, when the substrate circuit layer 130 is formed on one side of a PCB substrate, a cavity structure may be selectively formed on a non-circuit layer side of the PCB substrate to form the cavity 110.

The size of the cavity 110 formed on the first circuit board 100 may be flexibly manufactured according to specific requirements, which is not limited in the embodiments of the present application.

For example, for the first circuit board 100, the cavity 110 formed thereon may be a plurality of cavity structures with different sizes and different depths, so that the first functional chip 300 with different sizes and shapes can be placed therein, which is suitable for more packaging structure designs.

Step 420, packaging the first functional chip 300 in the cavity 110, and forming a conductive via 120 on the first circuit board 100.

In the embodiment of the present application, a cavity 110 is formed at one side of the first circuit board 100, and the cavity 110 can be used for receiving the first functional chip 300. On this basis, a conductive via 120 may be formed on the first circuit board 100 at a position avoiding the cavity 110. That is, the conductive vias 120 are disposed in the non-cavity region of the first circuit board 100, and are mainly used for electrical connection with other circuit layers.

The number and the positions of the conductive through holes 120 can be flexibly set according to the requirement.

The conductive through hole 120 may be plated with a conductive metal material.

For another example, the conductive via 120 is filled with a conductive metal material.

It should be noted that, one skilled in the art may choose to plate only the walls of the conductive vias 120, or may fill the entire conductive vias 120 with a conductive metal material.

Step 430, arranging a second circuit board 200 on at least one side of the first functional chip 300, so that the second circuit board 200 covers the cavity 110, the first functional chip 300 is electrically connected with the second circuit board 200, and the first circuit board 100 is electrically connected with the second circuit board 200 through the conductive through hole 120.

In the embodiment of the present application, the second circuit board 200 may be a rewiring layer, which is electrically connected to the first circuit board 100 through the conductive via 120. An electrical connection layer which is usually a copper ball or a solder ball can be omitted from being arranged between the two layers of circuit boards, so that the height of the packaging structure can be reduced.

For example, the back side of the first functional chip 300 may be bonded and fixed on the first circuit board 100, and then a fan-shaped region is formed on the surface of the first functional chip 300 facing away from the first circuit board 100; a Redistribution Layer (RDL) is formed on the sector area, i.e., the second pcb 200, which can distribute the circuits of the first functional chip 300 to a desired location as much as possible.

Since a Redistribution Layer (RDL) is formed on a surface of the first functional chip 300, the circuit can be electrically connected to the circuit Layer formed in the first circuit board 100 through the conductive via 120.

The cavity 110 is a closed accommodating space surrounded by the first circuit board 100 and the second circuit board 200. When the first functional chip 300 is packaged in the cavity 110, the back side of the first functional chip 300 may be adhesively fixed on one side of the first circuit board 100 by, for example, a Die Attach Film (DAF). Of course, the first functional chip 300 may be adhesively fixed on the second circuit board 200 by, for example, a Die Attach Film (DAF).

Step 440, disposing a second functional chip on at least one of the first circuit board and the second circuit board.

The second functional chip 400 may be mounted and stacked as needed, and may be electrically connected to the first circuit board 100 or the second circuit board 200 by using a gold wire 900, or may be electrically connected to the first circuit board 100 or the second circuit board 200 by using a flip chip, which is not limited in this embodiment.

In the embodiment of the present application, a part of the functional chips is stacked on one side of the first circuit board 100 or the second circuit board 200. When the number of functional chips is large, a stacking mode can be adopted, and the area of the packaging structure can be reduced.

It should be noted that after the cavity 110 is formed on the first circuit board 100, the conductive via 120 may be directly opened. After the first functional chip 300 is packaged, the first circuit board 100 may be provided with the conductive through-hole 120. The sequence of steps can be adjusted as required in the production process as long as the influence between the cavity 110 and the conductive via 120 is not affected, and this is not particularly limited by the embodiment of the present application.

The following describes in detail the packaging method of the package structure provided in the embodiments of the present application with three specific embodiments.

Example 1

The packaging method of the packaging structure provided by the embodiment of the application can comprise the following steps:

step 510, forming a cavity 110 on the first circuit board 100.

Referring to fig. 5, this step 510 may include the steps of:

step 511, providing a PCB substrate, wherein the PCB substrate may have no circuit layer;

step 512, manufacturing a set PCB substrate circuit layer 130 on one side of the PCB substrate;

step 513, after step 512, a cavity structure is fabricated on one side of the non-circuit layer of the PCB substrate to form the cavity 110 on the first circuit board 100.

The size of the cavity 110 formed on the first circuit board 100 may be flexibly manufactured according to specific requirements, which is not limited in the embodiment of the present application.

Step 520, please refer to fig. 5, the first functional chip 300 is disposed in the cavity 110 and attached to the first circuit board 100, and the first circuit board 100 is provided with a conductive through hole 120 penetrating through the thickness direction.

In this step 520, the first functional chip 300 may be placed in the cavity 110 formed on the first circuit board 100, and the first functional chip 300 may be attached to the first circuit board 100 through, for example, a Die Attach Film (DAF). Thereby realizing the fixed packaging of the first functional chip 300 in the cavity 110.

In step 520, a certain number of conductive vias 120 may be formed on the first circuit board 100 at positions avoiding the cavity 110. That is, the conductive vias 120 are disposed in the non-cavity region of the first circuit board 100, and are mainly used for electrical connection with other circuit layers.

The conductive through hole 120 may be plated with a conductive metal material.

For example, the walls of the conductive vias 120 are plated with a conductive metal material.

In addition, the cavity 110 may be further filled with an adhesive 600, and the adhesive 600 may cover the first functional chip 300, and may be used to protect and further fix the first functional chip 300.

Step 530, referring to fig. 6, the second circuit board 200 is disposed on a side of the first functional chip 300 away from the first circuit board 100, so that the second circuit board 200 covers the cavity 110, the first functional chip 300 is electrically connected to the second circuit board 200, and the first circuit board 100 is electrically connected to the second circuit board 200 through the conductive through hole 120.

After the first functional chip 300 is attached to the first circuit board 100 in step 520, the second circuit board 200 may be continuously formed on the surface of the first functional chip 300 away from the first circuit board 100, that is, the redistribution layer is formed, at this time, the cavity 110 may be sealed by the second circuit board 200, and the first functional chip 300 is packaged in the cavity 110. And, the second circuit board 200 formed on the surface of the first functional chip 300 may be electrically connected to the first circuit board 100 through the conductive via 120.

Step 540, please continue to refer to fig. 6, the first circuit board 100 is turned over, and the second functional chip 400 is disposed on a side of the first circuit board 100 away from the second circuit board 200.

In step 540, the first circuit board 100 may be turned over by 180 °, for example, and then other functional chips, such as the second functional chip 400, are disposed on the side of the first circuit board 100 where the circuit layer is formed (the chips may be mounted and stacked as needed, and the chips may be gold bonding wires 900 chips or flip chips, and fig. 6 only shows a schematic diagram of the gold bonding wires 900 chips).

And, a molding layer 700 made of a molding compound covers the second functional chip 400.

In step 550, please refer to fig. 6, a soldering portion 800 is disposed on an outward side of the second circuit board 200, or a soldering portion 800 is disposed on a side of the second circuit board 20 away from the first circuit board 100.

For example, a plurality of solder balls may be disposed on the surface of the second circuit board 200 facing the outside, which may be used for soldering the package structure of the embodiment of the present application to a main board of an electronic device.

Compared with the traditional stacking mode, the scheme provided by the embodiment 1 adopts a technology that the functional chips are embedded into the circuit board, the second circuit board 200 is introduced to replace the middle sealing adhesive layer and the upper and lower layers of substrates, and the conductive through holes 120 formed in the first circuit board 100 replace copper balls or solder balls, so that the supporting is more stable, and the overall height of the formed packaging structure can be effectively reduced.

Example 2

Referring to fig. 7 and 8, a method for packaging a package structure provided in an embodiment of the present application may include the following steps:

step 710, forming a cavity 110 on the first circuit board 100.

Referring to fig. 7, this step 710 may include the steps of:

step 711, providing a PCB substrate, wherein the PCB substrate may have no circuit layer;

step 712, manufacturing a set PCB substrate circuit layer on one side of the PCB substrate;

step 713, after step 712, a cavity structure is formed on one side of the non-circuit layer of the PCB substrate to form the cavity 110 on the first circuit board 100.

Step 720, please continue to refer to fig. 7, the first functional chip 300 is disposed in the cavity 110 and attached to the first circuit board 100, and the first circuit board 100 is provided with a conductive through hole 120 penetrating in the thickness direction.

In this step 720, the first functional chip 300 may be placed in the cavity 110 formed on the first circuit board 100, and the first functional chip 300 may be attached to the first circuit board 100 by, for example, a Die Attach Film (DAF). Thereby realizing the fixed packaging of the first functional chip 300 in the cavity 110.

In step 720, a certain number of conductive vias 120 may be formed on the first circuit board 100 at positions avoiding the cavity 110. That is, the conductive vias 120 are disposed in the non-cavity region of the first circuit board 100, and are mainly used for electrical connection with the circuit layers of other layers.

The conductive through hole 120 may be plated with a conductive metal material.

Step 730, referring to fig. 8, forming the second circuit board 200 on a side of the first functional chip 300 away from the first circuit board 100, so that the second circuit board 200 covers the cavity 110, the first functional chip 300 is electrically connected to the second circuit board 200, and the first circuit board 100 is electrically connected to the second circuit board 200 through the conductive through hole 120.

After the first functional chip 300 is attached to the first circuit board 100 in step 720, the second circuit board 200 may be continuously formed on the surface of the first functional chip 300 away from the first circuit board 100, that is, the rewiring layer is formed, at this time, the cavity 110 may be sealed by the second circuit board 200, and the first functional chip 300 is packaged in the cavity 110. And, the second circuit board 200 formed on the surface of the first functional chip 300 can be electrically connected to the first circuit board 100 through the conductive via 120.

Step 740, please continue to refer to fig. 8, and the second functional chip 400 is disposed on a side of the second circuit board 200 away from the first circuit board 100.

In this step 740, other functional chips, such as the second functional chip 400, may be directly disposed on the side of the second circuit board 200 away from the first circuit board 100 without turning the first circuit board 100.

In embodiment 2, it is different from embodiment 1 described above in that:

after the first functional chip 300 is embedded in the first circuit board 100 and the second circuit board 200(redistribution layer) is manufactured, the opening of the cavity 110 on the first circuit board 100 may be made upward, and the second functional chip 400 is bonded with the gold wire 900 on the second circuit board 200.

In step 750, please refer to fig. 8, a soldering portion 800 is disposed on an outward side of the first circuit board 100, or a soldering portion 800 is disposed on a side of the first circuit board 100 away from the second circuit board 200.

For example, a plurality of solder balls may be disposed on the surface of the first circuit board 100 facing the outside, which may be used for soldering the package structure of the embodiment of the present application to a main board of an electronic device.

In this embodiment 2, the second circuit board 200 (i.e., the rewiring layer) formed on the first functional chip 300 replaces the two-layer substrate of the conventional MeCP package, and can be interconnected with the substrate wiring layer of the first functional chip 300 through the conductive vias 120 on the first circuit board 100, and the conductive via technology replaces the original copper balls (Cu Core balls) or Solder balls (Solder balls), so that the overall thickness of the formed package structure is reduced.

Example 3

Referring to fig. 9 to 11, the method for packaging a package structure provided in the embodiment of the present application may include the following steps:

step 910, forming a cavity 110 on the first circuit board 100.

Referring to fig. 9, this step 910 may include the steps of:

911, providing a PCB substrate, wherein the PCB substrate can have no circuit layer;

step 912, after step 911, a cavity structure is fabricated on one side of the PCB substrate to form the cavity 110 on the first circuit board 100.

Step 920, please continue to refer to fig. 9, the first functional chip 300 is disposed in the cavity 110 and attached to the first circuit board 100, and the first circuit board 100 is provided with a conductive through hole 120 penetrating in the thickness direction.

In this step 920, the first functional chip 300 may be placed in the cavity 110 formed on the first circuit board 100, and the first functional chip 300 may be attached to the first circuit board 100 through, for example, a Die Attach Film (DAF). Therefore, the first functional chip 300 is fixedly packaged in the cavity 110.

In step 920, a certain number of conductive vias 120 may be formed on the first circuit board 100 at positions avoiding the cavity 110. That is, the conductive vias 120 are disposed in the non-cavity region of the first circuit board 100, and are mainly used for electrical connection with the circuit layers of other layers.

The conductive through hole 120 may be plated with a conductive metal material.

Step 930, please continue to refer to fig. 9, forming the second circuit board 200 on a side of the first functional chip 300 away from the first circuit board 100, so that the second circuit board 200 covers the cavity 110, the first functional chip 300 is electrically connected to the second circuit board 200, and the first circuit board 100 is electrically connected to the second circuit board 200 through the conductive via 120.

After the first functional chip 300 is disposed on the first circuit board 100 in step 920, the second circuit board 200 may be continuously formed on the surface of the first functional chip 300 away from the first circuit board 100, that is, the redistribution layer is formed, at this time, the cavity 110 may be sealed by the second circuit board 200, and the first functional chip 300 is encapsulated in the cavity 110. And, the second circuit board 200 formed on the surface of the first functional chip 300 can be electrically connected to the first circuit board 100 through the conductive via 120.

Step 940, referring to fig. 10 and fig. 11, one side of the first circuit board 100 is ground to expose the back side of the first functional chip 300, another layer of the second circuit board 200 is formed on the back side of the first functional chip 300, and the second functional chip 400 is mounted on one side of the layer of the second circuit board 200 away from the first functional chip 300.

Step 950, providing a soldering portion 800 on a side facing outward of the second circuit board 200 covering the cavity 110.

This embodiment 3 differs from the above-described embodiments 1 and 2 in that:

the circuit layer is not required to be manufactured on the first circuit board 100, after the first functional chip 300 is embedded into the first circuit board, the conductive through hole 120 and the second circuit board 200 covering the first functional chip 300 are manufactured, then the excess first circuit board 100 on the other side is ground off to expose the back side of the first functional chip 300, and then the second circuit board 200 is manufactured on the first functional chip 300. That is, a layer of the second circuit board 200 is formed on each of opposite sides of the first functional chip 300. The second circuit boards 200 on both sides of the first functional chip 300 may be electrically connected to each other through the conductive via 120 on the first circuit board 100.

A fan-out area may be formed on the back side of the first functional chip 300, and a Layer of second board 200 (RDL) may be formed in the fan-out area to distribute the circuits of the first functional chip 300 to a desired place.

In embodiment 3, the thickness of the first circuit board 100 needs to be reduced to expose a portion of the first functional chip 300, the second circuit board 200 formed on the back side of the first functional chip 300 replaces the two-layer substrate of the conventional MeCP package, and is interconnected with the second circuit board 200 on the other side of the first functional chip through the conductive vias 120, and the conductive vias replace the original copper balls (Cu Core balls) or Solder balls (Solder balls), so that the height of the whole package structure can be reduced.

In some examples of the present application, the method for packaging a circuit board further includes plastic-sealing the second functional chip with a plastic sealant to form a plastic-sealing layer 700 on the second functional chip 400.

The second functional chip 400 is plastically packaged by using a plastic package (Compound), so that a protection structure can be formed on the second functional chip 400 to better protect the second functional chip 400 in the stacked design. The plastic package layer 700 is dustproof and waterproof, and can also properly resist impact, which is helpful for prolonging the service life of the whole packaging structure.

In some examples of the present application, the method for packaging a circuit board further includes filling the cavity 110 with a sealant 600, so that the sealant 600 covers the first functional chip 300.

The first functional chip 300 is embedded in the cavity 110 of the first circuit board 100, and the second circuit board 200 is matched with the first circuit board 100 to seal the cavity 110 on the first circuit board 100. However, the first functional chip 300 does not fill the entire cavity 110, i.e., there is a certain empty space in the cavity 110. The empty space can be filled with the colloid 600, and the design can well protect the first functional chip 300 in the cavity 110 and prevent the first functional chip 300 from being damaged after the packaging structure is accidentally dropped or impacted. Meanwhile, the fixing of the first functional chip 300 can be more stable.

According to another embodiment of the present application, there is provided an electronic device including the package structure as described above.

Because the packaging structure adopted in the electronic equipment has the characteristic of obviously reducing the height, the electronic equipment can realize the light and thin design.

It should be noted that the electronic device may be a terminal, and may also be another device besides the terminal. For example, the electronic Device may be a Mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic Device, a Mobile Internet Device (MID), an Augmented Reality (AR)/Virtual Reality (VR) Device, a robot, a wearable Device, an ultra-Mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and may also be a server, a Network Attached Storage (Network Attached Storage, NAS), a personal computer (NAS), a Television (TV), a teller machine, a self-service machine, and the like, and the embodiments of the present application are not limited thereto.

In the description herein, reference to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the application, the scope of which is defined by the claims and their equivalents.

Claims

1. A package structure, comprising:

the circuit board comprises a first circuit board (100), wherein a cavity (110) and a conductive through hole (120) are arranged on the first circuit board (100);

a first functional chip (300), the first functional chip (300) being disposed within the cavity (110);

the second circuit board (200) is arranged on at least one side of the first functional chip (300) and covers the cavity (110), the first functional chip (300) is electrically connected with the second circuit board (200), and the second circuit board (200) is electrically conducted with the first circuit board (100) through the conductive through hole (120); and

a second functional chip (400), the second functional chip (400) disposed on at least one of the first circuit board (100) and the second circuit board (200).

2. The package structure of claim 1, wherein the first functional chip (300) is attached to at least one of the first circuit board (100) and the second circuit board (200) by an adhesive film (500).

3. The package structure according to claim 1, wherein the cavity (110) is filled with a gel (600) covering the first functional chip (300).

4. The package structure according to claim 1, wherein the number of the first functional chips (300) is at least one;

when the number of the first functional chips (300) is multiple, the multiple first functional chips (300) are arranged in one cavity (110), or the first circuit board (100) comprises the multiple cavities (110) with different depths, and the multiple first functional chips (300) are respectively arranged in the cavities (110) with different depths.

5. The package structure according to claim 1, wherein the number of the second functional chips (400) is at least one;

when the number of the second functional chips (400) is plural, the plural second functional chips (400) are sequentially stacked, and two adjacent second functional chips (400) are bonded by a bonding film (500).

6. The package structure according to claim 1, wherein the second functional chip (400) is covered with a molding compound layer (700).

7. The package structure according to claim 1, wherein a solder portion (800) is provided on a side of the first circuit board (100) and the second circuit board (200) facing the outside.

8. A method of encapsulating a package structure according to any of claims 1 to 7, comprising:

arranging a cavity on the first circuit board;

9. The method of claim 8, further comprising:

arranging the first functional chip in the cavity and attaching the first functional chip to the first circuit board;

forming the second circuit board on one side of the first functional chip, which is far away from the first circuit board, so that the cavity is covered by the second circuit board;

turning over the first circuit board, and attaching the second functional chip to one side of the first circuit board, which is far away from the second circuit board;

a soldering portion is provided on a side of the second circuit board facing the outside.

10. The method of claim 8, further comprising:

attaching the second functional chip to one side of the second circuit board, which is far away from the first circuit board;

a soldering portion is provided on a side of the first circuit board facing the outside.

11. The method of claim 8, further comprising:

grinding one side of the first circuit board to expose the back side of the first functional chip, forming another layer of the second circuit board on the back side of the first functional chip, and mounting the second functional chip on one side of the layer of the second circuit board, which is far away from the first functional chip; and

and arranging a welding part on one side of the second circuit board covering the cavity facing to the outside.

12. The method of claim 8, further comprising: and plastic packaging is carried out outside the second functional chip by adopting plastic packaging adhesive so as to form a plastic packaging layer on the second functional chip.

13. The method of claim 8, further comprising: and filling the cavity with a colloid so that the colloid covers the first functional chip.

14. An electronic device comprising the encapsulation structure according to any one of claims 1 to 7.