CN220474621U - Circuit carrier and electronic package - Google Patents
Circuit carrier and electronic package Download PDFInfo
- Publication number
- CN220474621U CN220474621U CN202322045565.9U CN202322045565U CN220474621U CN 220474621 U CN220474621 U CN 220474621U CN 202322045565 U CN202322045565 U CN 202322045565U CN 220474621 U CN220474621 U CN 220474621U
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- CN
- China
- Prior art keywords
- circuit
- boards
- sub
- redistribution
- electronic package
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- 239000010410 layer Substances 0.000 claims abstract description 72
- 238000007789 sealing Methods 0.000 claims abstract description 21
- 238000005538 encapsulation Methods 0.000 claims abstract description 11
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 7
- 239000012945 sealing adhesive Substances 0.000 claims abstract description 7
- 239000003292 glue Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 19
- 230000001681 protective effect Effects 0.000 claims description 6
- 230000017525 heat dissipation Effects 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000004744 fabric Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Abstract
The utility model discloses a circuit carrier board and an electronic package, wherein the circuit carrier board is suitable for mounting a plurality of chip elements. The circuit carrier comprises a plurality of circuit sub-boards, a sealing adhesive layer and a rerouting circuit structure. The sealing glue layer wraps the circuit sub-boards and fills gaps among the circuit sub-boards. One side of the encapsulant layer exposes one side of each of the circuit sub-boards. The rerouting circuit structure is arranged on a side of the encapsulation layer remote from the line sub-boards and is adapted to have the chip elements mounted thereon such that the chip elements are electrically connected to the line sub-boards via the rerouting circuit structure.
Description
Technical Field
The present utility model relates to electronic components, and more particularly, to a circuit board and an electronic package.
Background
Circuit carriers for chip packaging are used to secure Integrated Circuit (IC) chips and as a medium for electrical connection to other electronic components. The wiring carrier boards can be classified into a core type and a coreless type according to whether there is a dielectric core (dielectric core). In the case of multi-chip packages, a large-sized wiring carrier board is required. However, the large-sized circuit carrier board has lower typesetting utilization rate and yield in mass production, which increases production cost.
Disclosure of Invention
The utility model provides a circuit carrier board which is used for reducing production cost.
The utility model provides an electronic package body for reducing production cost.
A circuit carrier of an embodiment of the present utility model is adapted to mount a plurality of chip components. The circuit carrier comprises a plurality of circuit sub-boards, a sealing adhesive layer and a rerouting circuit structure. The sealing glue layer wraps the circuit sub-boards and fills gaps among the circuit sub-boards. One side of the encapsulant layer exposes one side of each of the circuit sub-boards. The rerouting circuit structure is arranged on a side of the encapsulation layer remote from the line sub-boards and is adapted to have the chip elements mounted thereon such that the chip elements are electrically connected to the line sub-boards via the rerouting circuit structure.
In one embodiment of the present utility model, the chip elements are electrically connected to each other through the redistribution circuit structure.
In one embodiment of the present utility model, the circuit sub-boards are electrically connected to each other via the redistribution circuit structure.
In an embodiment of the present utility model, the redistribution circuit structure includes a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly and electrically connected to at least two of the circuit sub-boards.
In one embodiment of the present utility model, the rectangular dimensions of the line sub-boards are different.
In an embodiment of the present utility model, the thicknesses of the line sub-boards are different.
In an embodiment of the present utility model, the circuit sub-boards in the sealing layer are insulated from each other.
In an embodiment of the present utility model, the circuit carrier further includes: and the circuit substrates are arranged on the circuit substrates and are electrically connected with the circuit substrates.
An electronic package according to an embodiment of the utility model includes a plurality of chip elements and a circuit carrier. The circuit carrier comprises a plurality of circuit sub-boards, a sealing adhesive layer and a rerouting circuit structure. The sealing glue layer wraps the circuit sub-boards and fills gaps among the circuit sub-boards. One side of the encapsulant layer exposes one side of each of the circuit sub-boards. The rerouting circuit structure is disposed on a side of the encapsulant layer farther from the line sub-boards and has the chip elements mounted thereon such that the chip elements electrically connect the line sub-boards via the rerouting circuit structure.
In one embodiment of the present utility model, the chip elements are electrically connected to each other through the redistribution circuit structure.
In one embodiment of the present utility model, one of the chip elements is a bare chip or a chip package.
In one embodiment of the present utility model, the chip elements are electrically connected to each other through the redistribution circuit structure.
In one embodiment of the present utility model, the circuit sub-boards are electrically connected to each other via the redistribution circuit structure.
In an embodiment of the present utility model, the redistribution circuit structure includes a redistribution patterned conductive layer, and the redistribution patterned conductive layer is directly and electrically connected to at least two of the circuit sub-boards.
In one embodiment of the present utility model, the rectangular dimensions of the line sub-boards are different.
In an embodiment of the present utility model, the thicknesses of the line sub-boards are different.
In an embodiment of the present utility model, the circuit sub-boards in the sealing layer are insulated from each other.
In an embodiment of the utility model, the electronic package further includes a protective cover mounted on the redistribution circuit structure and covering the chip elements.
In an embodiment of the utility model, the protection cover has a heat dissipation function.
In an embodiment of the utility model, the electronic package further includes a chip molding compound disposed on the redistribution circuit structure and filling gaps between the chip components.
In an embodiment of the present utility model, the circuit carrier further includes a circuit substrate, and the circuit sub-boards are mounted on the circuit substrate
Based on the above, the present utility model has the advantages that a plurality of circuit sub-boards are covered with a sealing glue layer and the circuit sub-boards are electrically connected on the sealing glue layer by configuring the re-wiring circuit structure. Compared with the traditional large-size circuit carrier board for chip packaging, the small-size circuit carrier board has obviously higher typesetting utilization rate and yield. Therefore, the circuit carrier board with a large size is formed by adopting the circuit carrier board with a small size as the circuit sub-board, and the production cost can be reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of an electronic package according to an embodiment of the utility model;
FIG. 2A is a schematic top view of an arrangement of chip components, wiring sub-boards and rerouting circuit structures of the electronic package of FIG. 1;
FIG. 2B is a schematic top view of another arrangement of chip components, wiring sub-boards, and rerouting circuit structures of the electronic package of FIG. 1;
FIG. 2C is a schematic top view of yet another arrangement of chip components, wiring sub-boards, and rerouting circuit structures of the electronic package of FIG. 1;
FIG. 3 is a schematic cross-sectional view of an electronic package according to another embodiment of the present utility model;
FIG. 4 is a schematic cross-sectional view of an electronic package according to another embodiment of the present utility model;
FIG. 5 is a schematic cross-sectional view of an electronic package according to another embodiment of the present utility model;
FIG. 6 is a schematic cross-sectional view of an electronic package according to another embodiment of the present utility model;
fig. 7A to 7F are schematic views illustrating a method for fabricating an electronic structure according to another embodiment of the present utility model;
fig. 8 is a schematic cross-sectional view of a circuit carrier according to another embodiment of the utility model;
fig. 9 is a schematic cross-sectional view of a circuit carrier according to another embodiment of the utility model.
Symbol description
50: electronic package
51: chip element
52: protective cover
52a: chip sealing adhesive
53: conductive bump
53a: pre-connection pad
100: circuit carrier plate
110. 110a, 110b: line sub-board
112: daughter board dielectric layer
114: sub-board patterned conductive layer
116: conductive duct of sub-board
120: sealing adhesive layer
130: re-wiring circuit structure
132: heavy cloth dielectric layer
134. 134a: heavy cloth patterned conductive layer
136: heavy cloth conductive duct
140: conductive ball for daughter board
150: circuit substrate
160: substrate conductive ball
202: temporary bonding layer
204: temporary carrier
P: conductive pad
Detailed Description
Referring to fig. 1, in the present embodiment, an electronic package 50 includes a plurality of chip devices 51 and a circuit carrier 100. These chip elements 51 are, for example, integrated circuit bare chips or small chip packages (e.g., multi-chip packages, stacked chip packages, chip scale packages, etc.). These chip elements 51 are mounted to the wiring carrier 100, for example via conductive bumps 53 to the wiring carrier 100.
In the present embodiment, the circuit carrier 100 includes a plurality of circuit sub-boards 110, a sealing layer 120 and a redistribution structure 130. The encapsulation layer 120 encapsulates the line sub-boards 110 and fills up gaps between the line sub-boards 110, i.e., the line sub-boards 110 in the encapsulation layer 120 are insulated from each other. One side of the encapsulant layer 120 exposes one side of each of the circuit sub-boards 110 to connect with electronic components (e.g., a motherboard or a module board, etc.) of a next level. The rerouting circuit structure 130 is disposed on a side of the encapsulation layer 120 farther from the line sub-boards 110 and has the chip elements 51 mounted thereon such that the chip elements 51 are electrically connected to the line sub-boards 110 via the rerouting circuit structure 130. Because the line sub-boards 110 in the encapsulation layer 120 are insulated from each other and cannot be directly electrically connected at the encapsulation layer 120, the line sub-boards 110 can be electrically connected to each other via the rerouting circuit structure 130. In addition, the circuit sub-boards 110 may be mounted to electronic components of a next level, such as a motherboard or a module board, via a plurality of sub-board conductive balls 140.
In the present embodiment, each circuit sub-board 110 may include a plurality of sub-board dielectric layers 112, a plurality of sub-board patterned conductive layers 114, and a plurality of sub-board conductive vias 116. The sub-board patterned conductive layers 114 are alternately stacked with the sub-board dielectric layers 112. The daughter board conductive vias 116 connect the daughter board patterned conductive layers 114, respectively. In addition, the redistribution circuit structure 130 may include a plurality of redistribution dielectric layers 132, a plurality of redistribution patterned conductive layers 134, and a plurality of redistribution conductive vias 136. The redistribution patterned conductive layers 134 are alternately stacked with the redistribution dielectric layers 132. The redistribution conductive vias 136 are respectively connected to the redistribution patterned conductive layers 134. In one embodiment, the redistribution circuit structure 130 further includes a redistribution patterned conductive layer 134a, which may be directly electrically connected to at least 2 circuit sub-boards 110 to transmit signals. In addition, the chip elements 51 may also be electrically connected to each other via the redistribution circuit structure 130 to transmit signals.
Referring to fig. 2A, 2B, and 2C, the chip elements 51 and the line sub-boards 110 are arranged within the redistribution circuit structure 130. The line sub-boards 110 may have a rectangular shape, and the length and width thereof may be equal or unequal. The rectangular dimensions of these line sub-boards 110 may vary. These line sub-boards 110 may be arranged in a planar array or in a straight line. In addition, some chip elements 51 may be located on the corresponding line sub-boards 110, respectively, and some chip elements 51 may be located on a plurality of line sub-boards 110 at the same time, i.e., at least bridging two adjacent line sub-boards 110.
Referring to fig. 3, the circuit sub-board 110a of the electronic package 50 of fig. 3 may have a small thickness compared to the electronic package 50 of fig. 1, i.e. the thickness of the circuit sub-boards 110, 110a is different, while the thickness of the circuit sub-boards 110 of fig. 1 is not different, and may be the same type of circuit sub-board. Referring to fig. 4, the circuit sub-board 110 and the circuit sub-board 110b of the electronic package 50 of fig. 4 may be of different types compared to the electronic package 50 of fig. 1. For example, the circuit board 110 is a coreless circuit board, and the circuit board 110b may be a core circuit board. In other words, in different embodiments, the thickness or type of the line sub-board can be selected and combined according to different requirements.
Referring to fig. 1 again, in the present embodiment, the electronic package 50 may further include a protection cover 52 or other components with heat dissipation function, and the protection cover 52 may also have heat dissipation function. The protective cap 52 is mounted on the rerouting circuit structure 130 and encloses the chip elements 51. In addition, referring to fig. 5, compared to the embodiment of fig. 1, the electronic package 50 of fig. 6 may include a die-sealing compound 52a, and the die-sealing compound 52a is disposed on the redistribution circuit structure 130 and fills the gaps between the die elements 51, and in one embodiment, the die-sealing compound 52a exposes the back surfaces (non-active surfaces) of the die elements 51. In addition, referring to fig. 6, compared with the embodiment of fig. 1, the circuit carrier board 100 of the electronic package 50 of fig. 6 may include a circuit substrate 150, the circuit sub-boards 110 are mounted on the circuit substrate 150, for example, the circuit sub-boards 110 may be mounted on the circuit substrate 150 via a plurality of sub-board conductive balls 140. In addition, the circuit substrate 150 may be mounted to a next level of electronic components, such as a motherboard or a module board, via a plurality of substrate conductive balls 160.
A method for fabricating an electronic structure according to another embodiment of the present utility model will be described with reference to fig. 7A to 7F.
Referring to fig. 7A, a plurality of circuit sub-boards 110 are fixed to a temporary carrier 204 through a temporary bonding layer 202. In the present embodiment, the circuit board 110 has a plurality of conductive pads P thereon. In one embodiment, the material of the conductive pad P is copper, which includes a bottom copper pad and an upper copper pillar.
Referring to fig. 7B, a sealing layer 120 is formed to cover the temporary bonding layer 202 and the circuit sub-boards 110. The encapsulation layer 120 fills the gaps between the circuit sub-boards 110, in other words, the circuit sub-boards 110 in the encapsulation layer 120 are insulated from each other and cannot be directly electrically connected at the encapsulation layer 120. In the present embodiment, the sealing layer 120 also covers the conductive pads P.
Referring to fig. 7C, a portion of the sealing layer 120 is removed to expose a portion of each of the conductive pads P, for example, to expose the top surface of the conductive pad P. This step may planarize the surface of the electronic structure for subsequent steps.
Referring to fig. 7D, a redistribution structure 130 is formed on the encapsulant layer 120, wherein the redistribution structure 130 is electrically connected to the circuit sub-boards 110. In the present embodiment, a plurality of redistribution conductive vias 136 and a redistribution patterned conductive layer 134 of the redistribution circuit structure 130 are fabricated from the top surfaces of the conductive pads P to electrically connect with the circuit sub-boards 110. In one embodiment, the redistribution circuit structure 130 further includes a redistribution patterned conductive layer 134a, which may be directly electrically connected to at least 2 circuit sub-boards 110. In addition, pre-pads 53a may be formed on the redistribution patterned conductive layer 134 of the redistribution circuit structure 130, and then may be used to connect other components. In another embodiment, not shown, the temporary bonding layer 202 and the temporary carrier 204 may be removed to form the circuit carrier 100 of fig. 8. These circuit sub-boards 110 can then be mounted on the circuit substrate 150 of fig. 6 to form the circuit carrier board 100 of fig. 9.
Referring to fig. 7E, a plurality of chip elements 51 are mounted on the rerouting circuit structure 130 such that the chip elements 51 are electrically connected to the line sub-boards 110 via the rerouting circuit structure 130. In addition, the chip elements 51 may also be electrically connected to each other via the redistribution circuit structure 130. In the present embodiment, the chip elements 51 may be connected to the pre-pads 53a of the redistribution circuit structure 130 through a plurality of conductive bumps 53. In another embodiment, not shown, a protective cap 52 as shown in fig. 1 may be mounted over the rerouting circuit structure 130 of fig. 7E and housing the chip elements 51. In another embodiment, which is not shown, a die paste 52a as shown in fig. 5 may be formed on the redistribution circuit structure 130 of fig. 7E and encapsulate the die elements 51, and expose the back surfaces of the die elements 51.
Referring to fig. 7F, the temporary bonding layer 202 and the temporary carrier 204 of fig. 7E are removed to expose the circuit sub-boards 110. In another embodiment, not shown, the circuit sub-boards 110 may be mounted on the circuit substrate 150 of fig. 6.
In summary, the plurality of circuit sub-boards are covered by the sealing layer and the redistribution circuit structure is electrically connected to the circuit sub-boards on the sealing layer. Compared with the traditional large-size circuit carrier board for chip packaging, the circuit carrier board with small size has lower yield and obviously higher typesetting utilization rate and yield. Therefore, the circuit carrier board with a small size is adopted as the circuit sub-board to form the circuit carrier board with a large size, so that the production cost can be reduced.
Claims (21)
1. A circuit carrier adapted to mount a plurality of chip components, the circuit carrier comprising:
a plurality of line sub-boards;
a sealing layer covering the circuit sub-boards and filling gaps among the circuit sub-boards, wherein one surface of the sealing layer exposes one surface of each of the circuit sub-boards; and
and the re-wiring circuit structure is arranged on one surface of the sealing adhesive layer, which is far away from the circuit sub-boards, and is suitable for the chip elements to be installed on, so that the chip elements are electrically connected with the circuit sub-boards through the re-wiring circuit structure.
2. The circuit carrier of claim 1, wherein the chip components are electrically connected to each other via the redistribution circuit structure.
3. The circuit carrier of claim 1, wherein the circuit sub-boards are electrically connected to each other via the redistribution circuit structure.
4. The circuit carrier of claim 3, wherein the redistribution circuit structure comprises a redistribution patterned conductive layer, and wherein the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit sub-boards.
5. The circuit carrier of claim 1, wherein the rectangular dimensions of the circuit sub-boards are different.
6. The circuit carrier of claim 1, wherein the plurality of circuit sub-boards have different thicknesses.
7. The circuit carrier of claim 1, wherein the plurality of circuit sub-boards in the encapsulation layer are insulated from each other.
8. The circuit carrier of claim 1, further comprising:
and the circuit substrates are arranged on the circuit substrates and are electrically connected with the circuit substrates.
9. An electronic package, comprising:
a plurality of chip elements; and
a circuit carrier board comprising:
a plurality of line sub-boards;
a sealing layer covering the circuit sub-boards and filling gaps among the circuit sub-boards, wherein one surface of the sealing layer exposes one surface of each of the circuit sub-boards; and
and the re-wiring circuit structure is arranged on one surface of the sealing adhesive layer, which is far away from the circuit sub-boards, and is used for mounting the chip elements thereon, so that the chip elements are electrically connected with the circuit sub-boards through the re-wiring circuit structure.
10. The electronic package of claim 9, wherein the chip components are electrically connected to each other via the redistribution circuit structure.
11. The electronic package of claim 9, wherein one of the chip components is a bare chip or a chip package.
12. The electronic package of claim 11, wherein the chip components are electrically connected to each other via the redistribution circuit structure.
13. The electronic package of claim 9, wherein the plurality of circuit sub-boards are electrically connected to each other via the redistribution circuit structure.
14. The electronic package of claim 13, wherein the redistribution circuit structure comprises a redistribution patterned conductive layer, and wherein the redistribution patterned conductive layer is directly electrically connected to at least two of the circuit sub-boards.
15. The electronic package of claim 9, wherein the rectangular dimensions of the circuit sub-boards are different.
16. The electronic package of claim 9, wherein the plurality of circuit sub-boards have different thicknesses.
17. The electronic package of claim 9, wherein the plurality of circuit sub-boards in the encapsulant layer are insulated from each other.
18. The electronic package of claim 9, further comprising:
and a protective cover mounted on the rerouting circuit structure and covering the chip elements.
19. The electronic package of claim 18, wherein the protective cover has a heat dissipation function.
20. The electronic package of claim 9, further comprising:
and the chip sealing glue is arranged on the rerouting circuit structure and fills the gap between the chip elements.
21. The electronic package of claim 9, wherein the circuit carrier further comprises:
and the circuit substrates are arranged on the circuit substrates.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW112126084 | 2023-07-12 | ||
| TW112126084 | 2023-07-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220474621U true CN220474621U (en) | 2024-02-09 |
Family
ID=89798837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322045565.9U Active CN220474621U (en) | 2023-07-12 | 2023-08-01 | Circuit carrier and electronic package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220474621U (en) |
-
2023
- 2023-08-01 CN CN202322045565.9U patent/CN220474621U/en active Active
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |