CN110299329A - A kind of encapsulating structure and preparation method thereof, electronic equipment - Google Patents

A kind of encapsulating structure and preparation method thereof, electronic equipment Download PDF

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Publication number
CN110299329A
CN110299329A CN201810237199.8A CN201810237199A CN110299329A CN 110299329 A CN110299329 A CN 110299329A CN 201810237199 A CN201810237199 A CN 201810237199A CN 110299329 A CN110299329 A CN 110299329A
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China
Prior art keywords
layer
chip
substrate
encapsulating structure
recessed portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201810237199.8A
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Chinese (zh)
Inventor
符会利
郭茂
张晓东
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201810237199.8A priority Critical patent/CN110299329A/en
Priority to PCT/CN2018/121620 priority patent/WO2019179184A1/en
Publication of CN110299329A publication Critical patent/CN110299329A/en
Pending legal-status Critical Current

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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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  • Engineering & Computer Science (AREA)
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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

This application discloses a kind of encapsulating structures and preparation method thereof, electronic equipment, are related to technical field of electronic encapsulation, solve in POP encapsulating structure, the larger problem of lower layer's encapsulating structure thickness.The encapsulating structure includes: the first rewiring layer, has the first surface and second surface being oppositely arranged, and the second surface of the first rewiring layer is fixedly connected with printed circuit board；The side of substrate, substrate is equipped with recessed portion, and substrate is fixed on the first surface of the first rewiring layer, and recessed portion and first reroutes layer composition accommodating space, for accommodating objective chip；Objective chip is housed in accommodating space, and is electrically connected with the first surface of the first rewiring layer.

Description

A kind of encapsulating structure and preparation method thereof, electronic equipment
Technical field
This application involves technical field of electronic encapsulation more particularly to a kind of encapsulating structure and preparation method thereof, electronic equipment.
Background technique
With the fast development of wireless communication, automotive electronics and other consumer electronics products, electronic device is towards more function The direction of energy is developed.Based on this, the prior art usually carries out the chip of different function when making above-mentioned electronic device respectively Encapsulation, is then integrated again, and will it is integrated after component be set in above-mentioned electronic device.
Currently used encapsulation is stacked package (Package on Package, POP) technology with integrated technology, specifically , it is superimposed another matched top layer encapsulating structure, again on lower layer's encapsulating structure to form above-mentioned POP encapsulating structure. Wherein, lower layer's encapsulating structure is packaged with the logic chip of high integration, and top layer encapsulating structure is packaged with the storage chip of large capacity. Since the connection path of logic chip and storage chip is short in POP encapsulating structure, electrical property is preferable, and the POP encapsulating structure exists Occupied space on printed circuit board (Printed Circuit Board, PCB) is smaller, thus above-mentioned POP encapsulating structure is in intelligence It is widely used in the portable electronic devices such as energy mobile phone.
In existing POP encapsulating structure, lower layer's encapsulating structure generally includes the lower substrate being oppositely arranged and organic pinboard； Above-mentioned logic chip is packaged on lower substrate by molding plastics (Molding Compound, MC)；Top layer encapsulating structure includes By molding Plastic Package in the storage chip on upper substrate.It is provided with and is used between top layer encapsulating structure and lower layer's encapsulating structure By the soldered ball of the top layer encapsulating structure and lower layer's encapsulating structure electric interconnection.
However, as the design requirement of the portable electronic devices such as smart phone towards ultrathin develops, it is corresponding to require POP encapsulating structure it is thinner.But in above-mentioned POP encapsulating structure, upper substrate, lower substrate and pinboard are limited to substrate The manufacture craft of itself is unfavorable for meeting intelligent hand so that the thickness of top layer encapsulating structure and entire POP encapsulating structure is larger The design requirement of the portable electronic products ultrathin such as machine.
Summary of the invention
The application provides a kind of encapsulating structure and preparation method thereof, electronic equipment, solves lower layer in POP encapsulating structure and seals The larger problem of assembling structure thickness.
In order to achieve the above objectives, the application adopts the following technical scheme that
The application's, in a first aspect, providing a kind of encapsulating structure, which includes chip-packaging structure.Wherein, should Chip-packaging structure includes: the first rewiring layer, has the first surface and second surface being oppositely arranged, and first reroutes layer Second surface is equipped with the device for being fixedly connected with printed circuit board；The side of substrate, the substrate is equipped with recessed portion, substrate quilt It is fixed on the first surface of the first rewiring layer, recessed portion and first reroutes layer composition accommodating space, for accommodating target Chip；Objective chip is housed in accommodating space, and is electrically connected with the first surface of the first rewiring layer.It can be seen from the above, It is provided with recessed portion in the substrate of the chip-packaging structure, may be constructed by recessed portion and the first rewiring layer for accommodating mesh The accommodating space of chip is marked, therefore after objective chip is contained in above-mentioned accommodating space, the thickness of objective chip can be made Degree is Chong Die with the caliper portion of substrate, and the above-mentioned substrate with recessed portion can replace the molding in current bottom encapsulating structure Layer and pinboard, reduce the quantity for the component being stacked in chip-packaging structure, and it is thick to have reached reduction chip-packaging structure Degree, the purpose for improving chip cooling efficiency.
Chip-packaging structure provided by the present application, with reference to first aspect, in one possible implementation, recessed portion is Groove；Objective chip is fixed on the bottom of groove by adhesive layer.
Chip-packaging structure provided by the present application, with reference to first aspect, in alternatively possible implementation, by wafer It is cut into single objective chip to be attached on support plate, during forming reconstruct wafer, on above-mentioned support plate and corresponds to recessed portion Position formed adhesive layer, at this time the recessed portion be through-hole, then the back side of the objective chip is conformed on above-mentioned adhesive layer. When by the support plate remove after, the first surface of substrate with first reroute layer first surface be bonded, through-hole in substrate second The one end on surface is filled with above-mentioned adhesive layer, and the adhesive layer is for closing above-mentioned accommodating space.
With reference to first aspect, in any one of the above mode in the cards, encapsulating structure further includes being stacked in chip Top layer encapsulating structure above encapsulating structure.In the case, the mutual connection positioned at recessed portion surrounding is additionally provided in aforesaid substrate Road, one end of interconnecting channel are electrically connected with the first surface of the first rewiring layer, and the other end and the top layer encapsulation of interconnecting channel are tied Structure electrical connection.So, top layer encapsulating structure can reroute layer by interconnecting channel and first and realize and PCB or target It is communicated between chip.
It with reference to first aspect, is the first surface and the through substrate in recessed portion in alternatively possible implementation In the case where the through-hole on two surfaces, chip-packaging structure further includes the second rewiring layer；Second rewiring layer is fixed on substrate Second surface on, the second rewiring layer reroutes layer with first by the interconnecting channels in substrate and is electrically connected.The second heavy cloth Line layer is electrically connected by the second rewiring layer with interconnecting channel for carrying top layer encapsulating structure, top layer encapsulating structure.This second Reroute layer can be set third connector for being electrically connected with top layer chip on a side surface of objective chip, this Three connectors can reroute the side surface that layer deviates from objective chip with positioned at objective chip region, and positioned at second The metal line of upper exposing is electrically connected.So, the density of above-mentioned third connector can be increased, so that with second weight The third connector that the metal line that wiring layer exposes on a side surface of objective chip is connected can be not only distributed in The periphery of objective chip can also be set in the region where the objective chip, so as to improve chip-packaging structure with The reliability of electric interconnection between top layer encapsulating structure.
With reference to first aspect and above-mentioned possible implementation, in alternatively possible implementation, interconnecting channels For the via hole filled with metallic copper.The via hole can be the PTH for being electroplate with metallic copper；Alternatively, being electroplate with metallic copper Stack Blind Via.In the case, the diameter of above-mentioned interconnecting channels can be produced on 120 μm or so.And use soldered ball structure At VIS diameter usually at 200 μm or so.Interconnecting channels provided by the present application are since diameter is smaller, so being conducive to increase The quantity and density of interconnecting channels.Furthermore the metal line more exposed can also be vacated on the second substrate surface, with In being distributed more power supplys or ground terminal, to can be improved the signal integrity of high speed signal in the transmission process of signal And Power Integrity.
With reference to first aspect, in alternatively possible implementation, substrate includes dielectric layer and metal wiring layer. The via hole of the metal line electrical connection for the upper and lower two sides of the dielectric layer will to be located at is additionally provided on the dielectric layer.
With reference to first aspect and above-mentioned possible implementation, in alternatively possible implementation, in recessed portion It is interior, and the periphery for being located at objective chip is filled with backing material, the backing material is identical as the material for defining layer in substrate.It should Backing material can reduce the probability that warpage occurs for objective chip, therefore chip-packaging structure provided by the embodiments of the present application has Preferable flatness, so preferable patch can be obtained when using only needing the surface mount process by a reflux technique Fill effect.
With reference to first aspect, in alternatively possible implementation, dielectric layer is resin material, filler and glass fibre Mixture.
With reference to first aspect, in alternatively possible implementation, have between objective chip and the first rewiring layer First connector；Multiple pads are set on the active face of objective chip, and one end of each pad and first connector is electrically connected It connects；The other end of first connector be electrically connected with the first surface of the first rewiring layer, to pass through the first connector realization the One reroutes the electric interconnection between layer and objective chip.
With reference to first aspect, in alternatively possible implementation, first is rerouted on the second surface of layer, is provided with The second connector that one end is electrically connected with the first rewiring layer second surface, the other end of second connector and above-mentioned printing electricity The electrical connection of road plate.Above-mentioned second connector realizes the electric interconnection between the first rewiring layer and PCB.
With reference to first aspect, in alternatively possible implementation, the top layer encapsulating structure include top layer chip and Third connector.One end of third connector is electrically connected with top layer chip, the other end at least with the interconnection in chip-packaging structure Channel electrical connection, third connector are set on the second surface of substrate.Above-mentioned third connector can be realized top layer chip with Electric interconnection between chip-packaging structure.
With reference to first aspect, in alternatively possible implementation, the top layer encapsulating structure include top layer chip and Third connector.One end of third connector is electrically connected with top layer chip, the other end at least with the interconnection in chip-packaging structure Channel electrical connection, third connector are set to the second rewiring layer on a side surface of objective chip.The third connector It can reroute what layer exposed on a side surface of objective chip with positioned at objective chip region, and positioned at second Metal line electrical connection.So, the density of above-mentioned third connector can be increased, so that with the second rewiring layer back The third connector being connected from the metal line exposed on a side surface of objective chip can not only be distributed in objective chip Periphery, can also be set in the region where the objective chip, be encapsulated so as to improve chip-packaging structure and top layer The reliability of electric interconnection between structure.
The second aspect of the application, provides a kind of electronic equipment, which passes through any one envelope as described above Assembling structure is equipped at least one chip.The encapsulating structure technology having the same that the electronic equipment and first aspect provide is imitated Fruit, details are not described herein again.
The third aspect of the application provides a kind of side for being made to any one encapsulating structure as described above Method, this method include the production method of chip-packaging structure: substrate of the production with recessed portion first.In the substrate, it is being recessed The interconnecting channel for the first surface and second surface that there is the surrounding in portion connection substrate to be oppositely arranged；Next, by least one Objective chip is fixedly installed in recessed portion；The active face of objective chip deviates from the second surface of substrate；Next, in substrate One surface and the side of objective chip active face production first reroute layer, are laid with signal path on the first rewiring layer, believe Number access is electrically connected with interconnecting channel and objective chip.The encapsulation that the production method and first aspect of above-mentioned encapsulating structure provide Structure technical effect having the same, details are not described herein again.
In conjunction with the third aspect, in alternatively possible implementation, it is fixedly installed in by least one objective chip After in recessed portion, before the side of substrate first surface and objective chip active face production first reroutes layer, above-mentioned side Method further include: in recessed portion, and backing material, the dielectric in the backing material and substrate are filled in the periphery for being located at objective chip The material of layer is identical.The backing material can reduce the probability that warpage occurs for objective chip, therefore provided by the embodiments of the present application Chip-packaging structure has preferable flatness, so when using only needing the surface mount process by a reflux technique, Preferable attachment effect can be obtained.
In conjunction with the third aspect, in alternatively possible implementation, states and be fixedly installed at least one objective chip It include: to form adhesive layer in the bottom surface of groove in recessed portion；It will be on the back adhesive and adhesive layer of objective chip；Wherein target core The back side of piece and the active face of objective chip are oppositely arranged.Objective chip is fixed by above-mentioned adhesive layer and there is the recessed of bottom surface In concave portion.
It is described that at least one objective chip is fixedly mounted in alternatively possible implementation in conjunction with the third aspect In include: in recessed portion on the loading end of support plate, and be located at recessed portion where region formed adhesive layer；By objective chip On back adhesive and adhesive layer.Wherein, the back side of objective chip and the active face of objective chip are oppositely arranged.Pass through adhesive layer elder generation Objective chip is fixed on support plate, after support plate removal, the objective chip can be made to be fixed in through-hole.
In conjunction with the third aspect, in alternatively possible implementation, the first surface that connection substrate is oppositely arranged is made Interconnecting channel with second surface includes: the surrounding on substrate, and positioned at recessed portion region to be formed, and production runs through substrate phase To the via hole of the first surface and second surface of setting；The plating metal copper in via hole forms interconnecting channel.The via hole It can be PTH；Alternatively, Stack Blind Via.In the case, the diameter of above-mentioned interconnecting channels can be produced on 120 μm of left sides It is right.And the diameter for the VIS for using soldered ball to constitute is usually at 200 μm or so.Interconnecting channels provided by the present application since diameter is smaller, So being conducive to increase the quantity and density of interconnecting channels.Furthermore it can also vacate on the second substrate surface and more to expose Metal line, to be used to be distributed more power supplys or ground terminal, to can be improved high speed signal in the transmission process of signal Signal integrity and Power Integrity.
In conjunction with the third aspect, in alternatively possible implementation, it is fixedly installed in by least one objective chip Before in recessed portion, this method further include: on the loading end of support plate, interval mounts at least one substrate；Second table of substrate Facing towards the loading end of support plate；The first connector is made on the active face of objective chip and is located at two neighboring first connection Passivation layer between part.Based on this, next the passivation layer can be exposed, be developed, etching technics is formed for exposing The blind hole of pad.Then, by Flip Chip Bond Technique, plant ball technique or electroplating technology, first is formed in the position of above-mentioned blind hole Connector.Next, carrying out the back side to the back side of wafer wears down technique, with the thickness of thinned wafer.Finally, being cut to wafer It cuts to obtain multiple objective chips.
In conjunction with the third aspect, in alternatively possible implementation, in substrate first surface and objective chip active face Side production first reroute layer after, method further include: first reroute layer second surface on, production with the first weight Second connector of the second surface electrical connection of wiring layer.Second connector with PCB for being fixedly connected.Wherein, the first weight The second surface of wiring layer and the first surface of the first rewiring layer are oppositely arranged.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of chip-packaging structure provided by the present application；
Fig. 2 is the structural schematic diagram of objective chip in Fig. 1；
Fig. 3 is a kind of structural schematic diagram of substrate in Fig. 1；
Fig. 4 is another structural schematic diagram of substrate in Fig. 1；
Fig. 5 is a kind of schematic perspective view of the recessed portion in Fig. 3 on substrate；
Fig. 6 is another schematic perspective view of the recessed portion in Fig. 3 on substrate；
Fig. 7 is a kind of structural schematic diagram of encapsulating structure with chip-packaging structure shown in FIG. 1；
Fig. 8 is the structural schematic diagram of another encapsulating structure provided by the present application；
Fig. 9 is the structural schematic diagram of another encapsulating structure provided by the present application；
Figure 10 is a kind of structural schematic diagram of HBPOP structure provided by the present application；
Figure 11 is a kind of structural schematic diagram of InFO POP structure provided by the present application；
Figure 12 is a kind of method flow diagram for making chip-packaging structure provided by the present application；
Figure 13 a, Figure 13 b, Figure 13 c, Figure 13 d, Figure 13 e, Figure 13 f are respectively to execute each making step shown in Figure 12 point The structural schematic diagram not obtained；
Figure 14 is a kind of corresponding structural schematic diagram of Figure 12 step S104.
Appended drawing reference:
01- chip-packaging structure；02- top layer encapsulating structure；10- objective chip；11- top layer chip；20- first is rerouted Layer；21- second reroutes layer；30- substrate；40- interconnecting channels；The first connector of 50-；The second connector of 51-；52- third connects Fitting；60- support plate；61- functional film；62- passivation layer；101- pad；201- dielectric layer；202- metal line；301- is recessed Concave portion；302- adhesive layer；303- backing material.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention is described, and shows So, described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or Implicitly include one or more of the features.In the description of the present invention, unless otherwise indicated, the meaning of " plurality " is two It is a or more than two.
The application provides a kind of encapsulating structure, which includes chip-packaging structure 01, as shown in Figure 1, the chip Encapsulating structure 01 includes that an at least objective chip 10, first reroutes layer 20, substrate 30.Wherein, first the tool of layer 20 is rerouted There are the first surface and second surface being oppositely arranged.The second surface of the first rewiring layer 20 is provided with for fixing with PCB The device of connection, for example, the device can be the second connector 51 in Fig. 1.The side of the substrate 30 is provided with as shown in Figure 3 Recessed portion 301.Substrate 30 is fixed on the first surface of the first rewiring layer 20, and the recessed portion 301 and the first heavy cloth Line layer 20 may be constructed the accommodating space for accommodating objective chip 10.Above-mentioned objective chip 10 is contained in the accommodating space, And objective chip 10 is electrically connected with the first surface of the first rewiring layer 20.Substrate 30 can provide objective chip 10 and be electrically connected Connect, support, protect and encapsulate and other effects.First rewiring layer 20 is electrically connected with objective chip 10 close to the side of above-mentioned PCB, Enable to the objective chip 10 in the case where keeping original size, have more input/output (Input/OutPut, I/O) interface quantity.
In addition, above-mentioned encapsulating structure is as shown in fig. 7, may also include top layer encapsulating structure 02, and in the case, the substrate 30 In be additionally provided with the interconnecting channel 40 positioned at 301 surrounding of recessed portion.One end of above-mentioned interconnecting channel 40 reroutes layer 20 with first First surface electrical connection, the other end of interconnecting channel is electrically connected with above-mentioned top layer encapsulating structure 02.So, top layer encapsulates Structure 02 can reroute the realization of layer 20 and the communication between PCB or objective chip 10 by interconnecting channel 40 and first.Its In, which includes top layer chip 11 and third connector 52, one end and the top layer chip of third connector 52 11 electrical connections, the other end are at least electrically connected with the interconnecting channel 40 in chip-packaging structure 01.
It should be noted that in order to enable connection path between the first surface of substrate 30 and 30 second surface of substrate Most short, above-mentioned interconnecting channel 40 can be arranged perpendicular to the first surface of the substrate 30 or the second surface of substrate 30.In this feelings Under condition, above-mentioned interconnecting channel 40 is properly termed as perpendicular interconnection system (Vertical Interconnects System, VIS).
Optionally, above-mentioned interconnecting channels 40 are the via hole filled with metallic copper.The above-mentioned via hole filled with metallic copper It can be to be filled up completely by copper, or only in the hole wall copper facing of via hole, and in the center-filled resin of the via hole.For example, The via hole can be plating via hole (Plated Through Hole, PTH), be electroplate with metallic copper in the PTH；Alternatively, adopting Constitute above-mentioned via hole with multiple stacking blind holes (Stack Blind Via), then in the via hole plating metal copper with right The via hole is filled.In other selectable embodiments, other can also be filled in addition to copper, in above-mentioned via hole and is suitable for passing The metal of delivery signal, to constitute signal path.
Objective chip 10 is before entering packaging technology, as shown in Fig. 2, making multiple aluminum welderings in surface thereof Disk (Aulminum Pad, AP), hereinafter referred to as pad 101.Objective chip 10 can be electrically connected with other component by pad 101 It connects.In the application, the surface that above-mentioned pad 101 is provided in the objective chip 10 is known as to the active face of the objective chip 10. In addition, the one side being oppositely arranged in the objective chip 10 with above-mentioned active face, the referred to as back side of the objective chip 10.Usually come It says, the active face of objective chip 10 is approximate with the back side or is substantially parallel.
It should be noted that above-mentioned pad 101 can be in the form of surrounding array or the formal distribution of face array is in this On the active face of objective chip 10.
As shown in Figure 1, above-mentioned objective chip 10 is set to the first rewiring layer (Redistribution Layer, RDL) 20 side.The first rewiring layer 20 includes dielectric layer 201 and the metal line 202 being set in dielectric layer 201.
Wherein, above-mentioned dielectric layer 201 and metal line 202 can be formed by patterning processes.For example, dielectric layer 201 can Think the resin material using insulation, such as polybenzoxazoles (Polybenzoxazole, PBO) or polyimides (Polyimide, PI) etc., the resin thin film layer formed by spin coating process, and pass through the compositions such as exposure, development, solidification Technique forms preset Thinfilm pattern.And above-mentioned metal line 202 can first use physical vapour deposition (PVD) (Physical Vapor Deposition, PVD) technique, sputtering technology or electroplating technology be initially formed one layer of metal film layer, and it then can be using etching Equal patterning processes pattern above-mentioned metal film layer, to form metal line 202.Wherein, the metal line is constituted 202 material may include the conductive materials such as metallic copper, metallic aluminium.
Optionally, one layer of Jie will be known as by the above-mentioned dielectric layer 201 formed with a composition manufacture craft in the application Electric layer 201；Additionally due to same layer metal film layer is derived from by the metal line 202 formed with a patterning processes, because The metal line 202 formed with a patterning processes is known as same layer metal line 202 by this.In the case, in production the During one reroutes layer 20, a patterning processes of production dielectric layer 201 and a composition work of production metal line 202 Skill alternately, so when this first reroute layer 20 have multilayer dielectric layer 201 and multi-layer metal wiring 202 when, one layer of gold Belong to wiring 202 to be arranged alternately with one dielectric layer 201.Multi-layer metal wiring 202 constitutes the metal in the first rewiring layer 20 Line construction.In addition, the via hole for adjacent two layers metal line 202 to be electrically connected is additionally provided on above-mentioned dielectric layer 201, In this case, the multi-layer metal wiring 202 being electrically connected to each other may be constructed the signal path of the first rewiring layer 20.
In addition, the first rewiring layer 20 includes being oppositely arranged, and first surface and the second table approximate or be substantially parallel Face.The first surface of the first rewiring layer 20 is relative to second surface, closer to the active face of objective chip 10.In order to enable Metallic circuit structure in first rewiring layer 20 can be electrically connected with other component, the first surface of the first rewiring layer 20 There is the metal line 202 for exposing above-mentioned dielectric layer 201 with second surface.
Based on this, the active face of above-mentioned objective chip 10 is electrically connected with the first surface of the first rewiring layer 20, for example, should The gold that objective chip 10 can be exposed by the pad 101 being set on active face and first first surface for rerouting layer 20 Belong to 202 electrical connection of wiring.
Alternatively, as shown in Figure 1, conductive the can also be arranged between above-mentioned objective chip 10 and the first rewiring layer 20 A connection piece 50.One end of first connector 50 is electrically connected with the pad 101 on 10 active face of objective chip, first connection The other end of part 50 is electrically connected with the metal line 202 that the first surface of the first rewiring layer 20 exposes, to realize target core The active face of piece 10 is electrically connected with the first surface of the first rewiring layer 20.
Wherein, the flatness of 20 contact surface of layer is rerouted in order to improve objective chip 10 and first, it can be in objective chip Passivation layer (Passivation Layer) 62 is made on 10 active face, which is capable of providing more even curface To be in contact with the first surface of the first rewiring layer 20.In addition it is also necessary to blind hole be formed on the passivation layer 62 to expose weldering Disk 101, and above-mentioned first connector 50 is made on the pad 101.In addition, in order to improve the precision of blind hole production, the passivation Layer 62 can be transparent resin layer, so as to observe the position of pad 101.In the case, above-mentioned passivation layer 62 can It is identical to reroute the material of 20 dielectric layer 201 of layer with first.
It should be noted that above-mentioned first connector 50 can be the copper post formed using electroplating technology, or using print Brush plants the soldered ball that ball technique is formed.Wherein, above-mentioned soldered ball can be solder ball (Solder Ball), solder bump (Solder Bump), copper core solder ball (Cu-core Solder Ball, CCSB), plasticity core (Plastic-core Solder Ball) or Person's Control Collapse Chip interconnection structure (Controlled Collapse Chip Connection, C4).The application does not make this It limits.
Based on this, the application to the quantity of the objective chip 10 encapsulated in the chip-packaging structure 01, type, size and Manufacture craft is not construed as limiting.When being packaged with more objective chips 10 in the chip-packaging structure 01, each objective chip 10 The metal line 202 that all exposes with the first surface of the first rewiring layer 20 of active face be electrically connected, therefore first can be passed through It reroutes layer 20 and realizes the interconnection between more objective chips 10.
On this basis, when using fan-out-type wafer-level packaging (Fan Out Wafer Level Package, PO-WLP) When technology, as shown in Figure 1, the part pad of objective chip 10 can lead to the target core by above-mentioned first rewiring layer 20 The periphery of piece 10, and with expose first metal line for rerouting 20 first surface of layer (i.e. in 10 periphery of the objective chip) Electrical connection, so as to when the size of above-mentioned objective chip 10 reduce when so that the objective chip 10 can still be maintained it is original Input/output possessed by size (Input/OutPut, I/O) interface quantity.In the case, above-mentioned first layer 20 is rerouted Layer (FO-RDL) is rerouted for fan-out-type.
In addition, the first rewiring layer 20 also has second be oppositely arranged with the first surface of the first rewiring layer 20 Surface.On the second surface of the first rewiring layer 20, it is provided with and reroutes the hardware cloth that 20 second surface of layer exposes with first Second connector 51 of line electrical connection.The external device that second connector 51 reroutes layer 20 and such as PCB for realizing first Electric interconnection between part.Wherein, which can be above-mentioned soldered ball.Structure, material and the production of the soldered ball Method is same as above, and details are not described herein again.
Optionally, the region that above-mentioned second connector 51 is contacted with the second surface of the first rewiring layer 20 can prepare Ubm layer (under bump metallization, UBM) reroutes layer 20 to improve the second connector 51 and first The bond strength of second surface increases the Mechanical Reliability of the second connector 51.Wherein, the application to the material of UBM, structure with And technique is without limitation.
Furthermore, it is possible to according to the design needs, integrate additional capacitor (Land in the second surface that above-mentioned first reroutes layer 20 Side Capacitor, LSC).The additional capacitor is usually decoupling capacitor, such as can be to be made in the using reflow soldering process One reroutes the multi-layer ceramic capacitance (Multi-layer Ceramic Capacitor, MLCC) of 20 second surface of layer.This is additional Capacitor can remove the coupled noise of objective chip 11.Wherein, above-mentioned additional capacitor can be located at two the second connectors that are connected Between 51.Or the circuit structure in layer 20 is rerouted by change first, and the position of the second connector of part 51 is vacated, it will Second connector 51 is set at the above-mentioned position vacated.
On this basis, the substrate 30 in chip-packaging structure 01 provided by the present application may include at least one layer of dielectric layer 201 and at least one layer of metal line 202.The substrate 30 is different from the production method of above-mentioned rewiring layer.
For example, the production method of substrate 30 can be, a metallic film is formed on the initial support plate of the substrate 30 first Then layer pastes dry film on the surface of the metal film layer, and then by techniques such as exposure, development, graphic plating, strippings, obtains One layer of metal line 202.Next, semi-cured state will be in by process for pressing, and the dielectric layer 201 to insulate passes through pressing Technique, which is pressed on production, to be had on the initial support plate of above-mentioned metal line 202.By having made during pressing dielectric layer 201 Make in the metal line 202 on initial support plate to need to be embedded in the dielectric layer 201, therefore the dielectric layer pressed 201 removes It is above-mentioned semi-cured state, which also needs to have certain thickness.Then dielectric layer 201 is solidified.When When the substrate 30 has multilayer dielectric layer 201 and metal line 202, one layer of metal line 202 can be made using above-mentioned technique It is arranged alternately with one dielectric layer 201.
Wherein, the material for constituting the dielectric layer 201 of the substrate 30 is usually the mixed of resin material, filler and glass fibre etc. It is fit.The resin can be epoxy resin, bismaleimide-triazine resin or polypropylene glycol (Poly propylene Glycol, PPG) etc..The filler can be disilicon trioxide, marble etc..
On this basis, it can be made on substrate 301 by etching technics or milling process, as shown in Figure 3 or Figure 4 Make above-mentioned recessed portion 301.
Wherein, above-mentioned recessed portion 301 can be illustrated in figure 3 a groove.Base is stated alternatively, being illustrated in figure 4 and always putting on The through-hole for the first surface and second surface of plate 30 being oppositely arranged.In addition, by taking recessed portion 30 is groove as an example, the recessed portion 30 As shown in figure 5, can have four side walls being sequentially connected, aforementioned four side wall, which encloses, is set as a chamber (Cavity) type structure；Or For person as shown in fig. 6, the tool of above-mentioned recessed portion 30 is there are two the side wall being oppositely arranged, which constitutes a canal (Trench) type knot Structure.
At this point, the thickness of substrate 30 and the thickness of objective chip 10 have lap, to be conducive to reduce entire core The thickness of chip package 01.Hereinafter, objective chip 10 exists when being groove or through-hole for the recessed portion 301 on substrate 30 Set-up mode in the recessed portion 301 is described in detail.
For example, in the case where above-mentioned recessed portion 301 is illustrated in figure 3 a groove, in order to which objective chip 10 is fixed on In above-mentioned recessed portion 301, as shown in Figure 1, adhesive layer 302 is provided between the bottom surface of the groove and the back side of objective chip 10, At this point, the objective chip 10 can be fixed on the bottom of groove by adhesive layer 302.
Wherein, the material for constituting above-mentioned adhesive layer 302 may include: hot pressing non-conductive adhesive (Thermal Compression Bonding Non-Conductive Paste, TCNCP), hot pressing non-conductive film (Thermal Compression bonding Non-Conductive Paste, TCNCF), chip adhesive film (Die Aattch Film, DAF) or elargol (Epoxy) At least one of.
On this basis, can be in above-mentioned recessed portion 301, and the periphery for being located at objective chip 10 is filled with backing material 303.Wherein, the material for constituting the backing material 303 can be identical as the material of dielectric layer 201 constituted in aforesaid substrate 30, The mixture of resin material and glass fibre can be selected to make above-mentioned backing material 303, to be conducive to improve fid The rigidity of material 303.So, by above-mentioned backing material 303 can eliminate objective chip 10 and recessed portion 301 side wall it Between gap can effectively reduce the generation of objective chip 10 and under the supporting role of the backing material 303 with good stiffness The probability of warpage so that chip-packaging structure 01 have good flatness, be conducive to improve chip-packaging structure 01 with The attachment effect of PCB.Certainly, in an alternative embodiment, above-mentioned backing material 303 can also select other kinds of material Material, it is only necessary to guarantee the characteristic of material mechanics of the backing material 303 close to the dielectric layer 201 of substrate 30.
It should be noted that when being provided with more objective chips 10 in above-mentioned recessed portion 301, different objective chips 10 Between also can be filled with above-mentioned backing material 303.
It can be formed with above-mentioned top layer encapsulating structure 02 stacking using chip-packaging structure 01 shown in FIG. 1 shown in Fig. 7 Encapsulating structure, the third connector 52 in the top layer encapsulating structure 02 is set on the second surface of substrate 30, so that top layer Chip 11 reroutes layer 20 by third connector 52, the interconnecting channel 40 in substrate 30 and first and realizes and PCB or target Communication between chip 10.
Wherein, which can be above-mentioned soldered ball.Structure, material and the production method of the soldered ball are same as above institute It states, details are not described herein again.
It should be noted that above-mentioned top layer chip 11 can be memory (Memory), integrated passive devices (Integrated Passive Device, IPD), MEMS (Micro-Electro-Mechanical System, MEMS), the structures such as passive device (Passive Device), semiconductor element (Silicon Die).Above-mentioned top layer encapsulating structure 02 can also include pinboard (Interposer).In addition, above-mentioned top layer encapsulating structure 02 can use Flip-Chip Using (Flip Chip Package) structure.
In addition, in order to further decrease the thickness of substrate 30, above-mentioned recessed portion 301 is illustrated in figure 4 through substrate 30 The through-hole of first surface and second surface.It in the case, can in order to which objective chip 10 to be fixed in above-mentioned recessed portion 301 To use above-mentioned FP-WLP technique, the objective chip 10 that wafer (Wafer) is cut into single is attached on support plate (Carrier), During forming reconstruct wafer, on above-mentioned support plate and the position of corresponding recessed portion 301 forms adhesive layer 302, then will The back side of the objective chip 10 conforms on above-mentioned adhesive layer 302.After removing the support plate, as shown in figure 8, above-mentioned adhesive layer 302 can be concordant with the second surface of substrate 30 away from a side surface of objective chip 10.At this point, the first surface of substrate 30 with First reroutes the first surface fitting of layer 20, and through-hole is filled with above-mentioned adhesive layer 302 in one end of the second surface of substrate 30, The adhesive layer 302 is used to close the accommodating space of receiving objective chip 10.
In the case, same as above, equally can be set in above-mentioned through-hole can reduce objective chip 10 and sticks up The backing material 303 of bent probability.In addition, same for the set-up mode of interconnecting channels 40 in chip-packaging structure 01 shown in Fig. 8 Upper described, details are not described herein again.
It in the case, can with the top layer encapsulating structure 02 being positioned above using chip-packaging structure 01 shown in Fig. 8 It equally can be set to constitute an encapsulating structure, and in the encapsulating structure between chip-packaging structure 01 and top layer chip 11 above-mentioned Third connector 52, which is set on the second surface of substrate 30, so that top layer chip 11 passes through third Interconnecting channel 40 and first in connector 52, substrate 30 reroute layer 20 and realize and leading between PCB or objective chip 10 Letter.
Based on this, as seen from Figure 8, due to the structure that the recessed portion 301 on substrate 30 is through-hole, on substrate 30 with mesh The material in the corresponding region in position where mark chip 10 is completely removed, to form above-mentioned through-hole, therefore, is made in substrate Third connector 52 on 30 second surface can only be set to the periphery of objective chip 10.In the case, in order to improve The quantity and connection density of third connector 52 are stated, optionally, as shown in figure 9, recessed portion 301 is the feelings of through-hole on substrate 30 Under condition, which further includes the second rewiring layer 21.
The second rewiring layer 21 is fixed on the second surface of substrate 30, and second, which reroutes layer 21, passes through in substrate 30 Interconnecting channels 40 with first rewiring layer 20 be electrically connected.The second rewiring layer 20 is for carrying above-mentioned top layer encapsulating structure 02, and top layer encapsulating structure 02 can be electrically connected by the second rewiring layer 21 with interconnecting channel 40.Above-mentioned second reroutes layer 21 structure is identical as the first rewiring layer 20, also includes at least one layer of dielectric layer 201 and at least one layer of metal line 202.
It in the case, can with the top layer encapsulating structure 02 being positioned above using chip-packaging structure 01 shown in Fig. 9 To constitute an encapsulating structure, the third connector 52 in the top layer encapsulating structure 02 can be set to deviate from the second rewiring layer 21 On one side surface of objective chip 10.At this point, third connector 52 can be located at objective chip 10 region, and be located at The metal line 202 that second rewiring layer 21 exposes on a side surface of objective chip 10 is electrically connected.It so, can be with Increase the density of above-mentioned third connector 52, so that with the second rewiring layer 21 on a side surface of objective chip 10 The third connector 52 that the metal line 202 of exposing is connected can not only be distributed in the periphery of objective chip 10, can also set It is placed in the region at 10 place of objective chip, it is electric between chip-packaging structure 01 and top layer encapsulating structure 02 so as to improve The reliability of gas interconnection.
Based on this, as shown in figure 9, the top layer chip 11 in top layer encapsulating structure 02 can pass through third connector 52, Interconnecting channel 40 and first in double wiring layer 21, substrate 30 reroute layer 20 and realize between PCB or objective chip 10 Communication.
In summary, on the one hand, in encapsulating structure provided by the present application, as shown in fig. 7, the substrate of chip-packaging structure 01 The recessed portion 301 for accommodating objective chip 10 is provided in 30, so that the thickness of the thickness of objective chip 10 and substrate 30 Divide overlapping.It is recessed using being provided in chip-packaging structure 01 provided by the present application compared to bottom encapsulating structure more shown in Fig. 10 The substrate 30 of concave portion 301 reduces chip-packaging structure instead of molding layer and pinboard in the bottom encapsulating structure of Figure 10 The quantity for the component being stacked in 01, it is final to realize ultrathin height to achieve the purpose that reduce 01 thickness of chip-packaging structure The preparation of bandwidth stacked package (Ultra-tin High Bandwidth Package on Package, UT HBPOP) structure.
In addition, using first in chip-packaging structure 01 provided by the present application reroutes layer 21 instead of shown in Fig. 10 Lower substrate in bottom encapsulating structure, it can be seen from the above, the first dielectric layer 201 for rerouting in layer 21 uses coating, exposure, shows The insulating thin layer that the techniques such as shadow, solidification are formed, and the one kind of lower substrate as package substrate, internal dielectric layer is to pass through Process for pressing is on the initial support plate that the production of semi-cured state insulating layer has metal line 20.Since metal line 202 needs It is embedded in the insulating layer of the above-mentioned semi-solid preparation, the insulating layer for being accordingly used in being formed the dielectric layer in lower substrate needs to have one Fixed thickness.So the first thickness for rerouting layer 21 can be less than the thickness of lower substrate in Figure 10 in Fig. 7, so as to subtract Small chip-packaging structure 01, to realize the preparation of ultrathin high bandwidth encapsulating structure.In addition, when chip-packaging structure 01 reduces Afterwards, the heat dissipation performance of entire chip-packaging structure 01 has also obtained corresponding promotion.
On this basis, in chip-packaging structure 01 provided by the present application, as shown in figure 8, when the recessed portion on substrate 30 301 be through-hole when, the thickness of objective chip 10 and substrate 30 can be further decreased, thus reach further decrease chip envelope The purpose of 01 thickness of assembling structure.Based on this, from the above as shown in figure 9, being sealed to improve chip-packaging structure 01 and top layer The reliability of electric interconnection between assembling structure 02 can make the second rewiring layer 21 on the second surface of substrate 30, but should Second reroutes the manufacture craft that layer 21 equally reroutes layer 20 using first, so second reroutes the thickness very little of layer 21, It is little to the thickness effect of the chip-packaging structure 01.
On the other hand, it can be seen from the above, as shown in Fig. 7, Fig. 8 and Fig. 9, in chip-packaging structure 01 provided by the present application Interconnecting channels 40 are the via hole filled with metallic copper.The diameter of the interconnecting channels 40 can be produced on 120 μm or so.And Figure 10 Shown in VIS in bottom encapsulating structure usually based on soldered ball, therefore the diameter of the VIS is usually at 200 μm or so.In this feelings Under condition, interconnecting channels 40 provided by the present application are since diameter is smaller, so the spacing of two neighboring interconnecting channels 40 can also fit Work as reduction, so as to increase the quantity and density of interconnecting channels 40.Also, since the diameter of interconnecting channels 40 is smaller, so Expose the metal line 202 being in contact in metal line 202 with interconnecting channels 40 in 30 second surface of substrate and occupies second table The area in face is smaller, therefore can vacate the metal line 202 more exposed on 30 second surface of substrate, for being distributed More power supplys or ground terminal, to can be improved the signal integrity (Signal of high speed signal in the transmission process of signal Integrity, SI) and Power Integrity (Power Integrity, PI).
On this basis, interconnecting channel 40 is the via hole filled by metallic copper in the application, due to the heat dissipation of metallic copper Better performances, therefore for the VIS being made of in Figure 10 soldered ball, chip-packaging structure provided by the present application 01 is in chip The heat dissipation performance of vertical direction is more preferably.
In addition, relative to fan-out-type stacked package (Integrated Fan Out Package on is integrated shown in Figure 11 Package, InFO POP) in for VIS in bottom encapsulating structure, the interconnection in chip-packaging structure 01 provided by the present application The manufacturing process in channel 40 is to form via hole (PTH or Stack Blind Via) on substrate 30, and then electro-coppering leads this Through-hole is filled.However the VIS in Figure 11 needs the first plating preparation copper post on RDL then to form molding to form VIS Layer, so that the periphery of copper post is molded layer package.Therefore for plating forms the technique of three-dimensional copper post, in the application The technical process of plating filling metallic copper is simpler in molded via hole, and required precision is low, cost of manufacture is not high.
Encapsulating structure in the embodiment of the present invention is by way of being fanned out to by least one chip package at a new core Piece entity.This new chip entity is installed in the electronic equipments such as injection mobile terminal, the network equipment, so that at least one The external pin and electronic equipment for the chip entity that chip is obtained by this encapsulation carry out data communication, can be improved data band Pin configuration scheme wide and that offer is more flexible.
The application provides a kind of electronic equipment, which is equipped at least one by any one of the above encapsulating structure A chip.The electronic equipment has technical effect identical with the sealed in unit that previous embodiment provides, and details are not described herein again.
The application provides a kind of method for being made to any one encapsulating structure as described above, such as Figure 12 institute Show, the above method includes the production method of chip-packaging structure 01.The production method of the chip-packaging structure 01 may include:
S101, production such as Fig. 5 or as shown in FIG. 6 have the substrate 30 of recessed portion 301.It should with connection in the substrate 30 The interconnecting channel 40 for the first surface and second surface that substrate 30 is oppositely arranged.
For example, forming a metal film layer on an initial support plate, dry film then is pasted on the surface of the metal film layer, into And by techniques such as exposure, development, graphic plating, strippings, obtain one layer of metal line 202.Next, will by process for pressing In semi-cured state, and the dielectric layer 201 to insulate is pressed on to make by process for pressing the initial of above-mentioned metal line 202 On support plate.Then dielectric layer 201 is solidified.It repeats the above steps, being formed has multi-layer metal wiring 202 and multilayer dielectric The substrate 30 of layer 201.Wherein, one layer of metal line 202 in the substrate 30 is arranged alternately with one dielectric layer 201.
On this basis, it is oppositely arranged in the surrounding in the region to be formed of above-mentioned recessed portion 301, production through substrate 30 The via hole of first surface and second surface.Wherein, which can be PTH (as depicted in fig. 13 a) or Stack Blind Via.Next, the plating metal copper in above-mentioned via hole is ultimately formed with being filled to the via hole for connection substrate The interconnecting channel 40 of 30 first surface and second surface.
Then, using etching technics or milling process, the region to be formed of above-mentioned recessed portion 301 is corresponded on substrate 30 Position, make above-mentioned recessed portion 301, above-mentioned interconnecting channel 40 is located at the surrounding of the recessed portion 301.
S102, the objective chip 10 of acquisition as illustrated in fig. 13b.
For example, making passivation layer 62 on target wafer (Wafer).Wherein, it includes poly- for constituting the material of the passivation layer 62 Amide (PI), polyparaphenylene's benzo dioxazole fiber (PBO), at least one of organic materials such as benzocyclobutene (BCB).It connects Get off, which is exposed, is developed, etching technics forms the blind hole for being used for exposed pad 101.Then, by falling Welding equipment (Bumping) technique plants ball technique or electroplating technology, forms the first connector 50 in the position of above-mentioned blind hole.It connects down Come, the back side is carried out to the back side of wafer (with the surface for being formed with the first connector 50 and being oppositely arranged) and wears down (Back side Grinding, BG) technique, with the thickness of thinned wafer.Finally, being cut (Dicing) to wafer obtains multiple objective chips 10。
S103, as shown in figure 13 c, on the loading end of support plate 60, interval mounts at least one aforesaid substrate 30.Wherein, Loading end of the second surface of substrate towards support plate 60.
It should be noted that above-mentioned support plate 60 can be identical as wafer shape, size employed in above-mentioned steps S102, Manufacture craft provided by the present application is FO-WLP technique at this time.Alternatively, in view of forming reconstruct wafer on round support plate 60, so that The utilization rate of the objective chip 10 of rectangle is lower, and optionally, above-mentioned support plate 60 can also be rectangle, at this point, provided by the present application Manufacture craft is panel fan-out-type (Panel FO) packaging technology.The step of above two packaging technology, is identical, and difference is only that The shape of support plate 60 is different.
In addition, the position of substrate 30 is fixed in order to during making chip-packaging structure 01, and when above-mentioned After manufacturing process, convenient for being removed to above-mentioned support plate 60.Optionally, after above-mentioned steps S102, before step S103, Functional film 61 can be formed on the loading end of support plate 60.Wherein, which can be adhesion layer film (Adhesive Layer), thin film sacrificial layer (Sacrificial Layer) or buffer layer thin film (Buffer Layer) are situated between Electric layer film (Dielectric Layer) etc..Wherein, above-mentioned adherency layer film or thin film sacrificial layer can be ultraviolet light solidification (Ultra-Violet, UV) glue, photothermal conversion (Light-to-Heat Conversion, LTHC) film, or have similar Function and the material compatible with the manufacture craft parameter or manufacturing conditions of encapsulating structure.
S104, as shown in figure 13 c, at least one objective chip 10 is fixedly installed in recessed portion 301.Wherein, the mesh The active face for marking chip 10 deviates from the second surface of substrate 30.
For example, above-mentioned steps S104 includes: firstly, being recessed so that above-mentioned recessed portion 301 is with the groove of bottom surface as an example Adhesive layer 302 is formed on the bottom surface in portion 301；Then, by the back adhesive of objective chip 10 on the adhesive layer 302.
S105, as shown in figure 13d, in recessed portion 301, and backing material 303 is filled on the periphery for being located at objective chip 10.
Wherein, in order to enable backing material 303 can preferably inhibit objective chip 10 that warpage occurs, it is filled in the target The height of the backing material 303 on 10 periphery of chip is at least higher than the active face of objective chip 10.
In addition, needing to grind it after above-mentioned backing material 303 is populated, so that the thickness of backing material 303 be thinned Degree enables the first connector 50 on 10 active face of objective chip and the interconnecting channel 40 that is set in substrate 30 to reveal Out.
S106, as shown in figure 13e makes the first heavy cloth in the side of 10 active face of 30 first surface of substrate and objective chip Line layer 20.
Wherein, it is not provided with signal path on the first rewiring layer 20, the signal path and interconnecting channel 40 and target core Piece 10 is electrically connected.In the case, above-mentioned first rewiring layer 20 can be with the region at 10 place of coverage goal chip and substrate 30 first surface.The first surface of the first connector 50 and the first rewiring layer 20 on 10 active face of objective chip realizes electricity Gas interconnection.Furthermore the first rewiring layer 20 is fanned out to the first surface for being routed to substrate 30, and mutual in the substrate 30 with being set to 40 electric interconnection of connection road.
It should be noted that after being provided with multiple objective chip 10 in above-mentioned recessed portion 301, different objective chips 10 Between can pass through it is above-mentioned first reroute 20 electric interconnection of layer.In addition, the first rewiring layer 20 being fanned out to can also realize mesh It marks chip 10 and encapsulates the electric interconnection between external pin.
In addition, the structure and production method of the first rewiring layer 20 are same as above, details are not described herein again.
S107, as shown in figure 13f is made in the first rewiring layer 10 on the second surface that first reroutes layer 10 Second connector 51 of second surface electrical connection.
For example, above-mentioned second connector 51 can be soldered ball, structure, material and the manufacture craft of the soldered ball are same as above institute It states, details are not described herein again.In addition, in order to improve the bond strength of the second connector 51 and the first rewiring 20 second surface of layer, The region that above-mentioned second connector 51 is contacted with the second surface of the first rewiring layer 20 can prepare ubm layer (under bump metallization, UBM).
S108, support plate 60 is removed using ultraviolet light or laser, and one single chip encapsulation knot is obtained using cutting technique Structure 01.
The production method of said chip encapsulating structure 01 is saying of carrying out so that recessed portion 301 is the groove for having bottom surface as an example It is bright.In addition, the production method of chip-packaging structure 01 can similarly obtain, and difference exists when recessed portion 301 is using through-hole structure In it includes: support plate first as shown in figure 14 that at least one objective chip 10, which is fixedly installed in recessed portion 301, in step S104 On 60 loading end, and it is located at the region formation adhesive layer 302 where recessed portion 301.Next, by the back side of objective chip 10 In bonding and adhesive layer 302.
The chip-packaging structure skill having the same that the production method and previous embodiment of said chip encapsulating structure provide Art effect, details are not described herein again.
On this basis, the reliability of electric interconnection between chip-packaging structure 01 and top layer encapsulating structure 02 is improved, such as Shown in Fig. 9, when being provided with the second rewiring layer 21 in the chip-packaging structure 01.The system of chip-packaging structure 01 shown in Fig. 9 Making method can similarly obtain, the difference is that, executing above-mentioned steps S103, i.e., on the loading end of support plate 60, interval attachment Before at least one aforesaid substrate 30, above-mentioned second is formed on the loading end of the support plate 60 and reroutes layer 21.
In addition, the above-mentioned chip-packaging structure 01 and top layer chip 11 connect, encapsulating structure can be formed.For example, this Shen Please in above-mentioned top layer chip 11 and the connection type of chip-packaging structure 01 can use surface mount process (Surface Mount Technology, SMT), or technique (pre-Stack) can also be stacked using with pre-.
Wherein, surface mount process refers to, firstly, the single chip encapsulating structure 01 that above-mentioned steps S108 is obtained is used Above-mentioned surface mount process is attached on PCB；Then, above-mentioned top layer chip 11 is attached to chip-packaging structure by modes such as soldering paste 01 top；Finally, being integrated on PCB by a reflux technique, while by top layer chip 11 and chip-packaging structure 01.
In addition, above-mentioned pre- stacking technique refers to, firstly, it is necessary to which a reflux technique, top layer chip 11 is passed through such as Fig. 9 institute The third connector 52 and top layer chip 11 shown interconnects.Wherein, the mode of above-mentioned interconnection can use hot wind remelting (Mass Reflow), other equivalent welding manners such as thermocompression bonding (Thermo Compression Bonding).Then, using Secondary back technique interconnects the chip-packaging structure 01 for being connected with top layer chip 11 by the second connector 51 and PCB.
Based on this, it can be seen from the above, being set in recessed portion 301, and it is located at the backing material 303 on 10 periphery of objective chip The probability that warpage occurs for objective chip 10 can be reduced, therefore chip-packaging structure provided by the embodiments of the present application 01 has preferably Flatness can obtain preferable attachment effect so when using only needing the surface mount process by a reflux technique Fruit.
In addition, between chip-packaging structure 01 and PCB have different thermal expansion coefficients, therefore chip-packaging structure 01 with PCB can apply different stress to the second connector 51 between chip-packaging structure 01 and PCB, therefore in order to avoid Two connectors 51 are torn under above-mentioned stress, to improve the reliability of stacked package, can be rerouted first Between 20 and PCB of layer, and stress-buffer layer (Under Fill) is filled on the periphery for being located at the second connector 51.Similarly, chip seals Also there is different thermal expansion coefficients between assembling structure 01 and top layer chip 11, in order to avoid third connector 52 is torn, Optionally, can also be between chip-packaging structure 01 and top layer chip 11, and the periphery for being located at third connector 52 is also filled Above-mentioned stress-buffer layer.Wherein, the stress-buffer layer of different location can be by being prepared with a fill process.

Claims (21)

1. a kind of encapsulating structure, which is characterized in that the encapsulating structure includes chip-packaging structure；The chip-packaging structure packet It includes:
First reroutes layer, has the first surface and second surface being oppositely arranged, and described first reroutes the second surface of layer It is fixedly connected with printed circuit board；
Substrate, the side of the substrate are equipped with recessed portion, and the substrate is fixed on the described first first surface for rerouting layer On, the recessed portion and described first reroutes layer composition accommodating space, for accommodating objective chip；
The objective chip is housed in the accommodating space, and is electrically connected with the first surface of the first rewiring layer.
2. encapsulating structure according to claim 1, which is characterized in that the recessed portion is groove, and the objective chip is logical Cross the bottom that adhesive layer is fixed on the groove.
3. encapsulating structure according to claim 1, which is characterized in that the recessed portion is to be oppositely arranged through the substrate First surface and second surface through-hole, the first surface of the substrate and it is described first reroute layer first surface paste It closes, the through-hole is filled with adhesive layer in one end of the second surface of the substrate, and the adhesive layer is for closing the receiving Space.
4. encapsulating structure according to claim 1, which is characterized in that the encapsulating structure further includes being stacked in the chip Top layer encapsulating structure above encapsulating structure；
The interconnecting channels positioned at the recessed portion surrounding, one end of the interconnecting channel and described first are additionally provided in the substrate The first surface electrical connection of layer is rerouted, the other end of the interconnecting channel is electrically connected with the top layer encapsulating structure.
5. encapsulating structure according to claim 4, which is characterized in that in the recessed portion for through the first of the substrate In the case where the through-hole of surface and second surface, the chip-packaging structure further includes the second rewiring layer；
The second rewiring layer is fixed on the second surface of the substrate, and described second, which reroutes layer, passes through the substrate In interconnecting channels with it is described first rewiring layer be electrically connected；The second rewiring layer is for carrying the top layer encapsulation knot Structure, the top layer encapsulating structure are electrically connected by the second rewiring layer with the interconnecting channel.
6. encapsulating structure according to claim 4, which is characterized in that the interconnecting channels are the conducting filled with metallic copper Hole.
7. encapsulating structure according to claim 1-6, which is characterized in that the substrate includes dielectric layer, and Metal wiring layer.
8. encapsulating structure according to claim 7, which is characterized in that in the recessed portion and be located at the objective chip Periphery is filled with backing material, and the backing material is identical as the material of dielectric layer in the substrate.
9. encapsulating structure as claimed in claim 7, which is characterized in that the dielectric layer is resin material, filler and glass fibers The mixture of dimension.
10. encapsulating structure according to claim 1, which is characterized in that the objective chip and described first reroutes layer Between have the first connector；
Multiple pads, one end of each pad and first connector are set on the active face of the objective chip Electrical connection；The other end of first connector is electrically connected with the first surface of the first rewiring layer.
11. encapsulating structure according to claim 1, which is characterized in that described first reroutes on the second surface of layer, if Be equipped with one end and second connector that be electrically connected of the first rewiring layer second surface, the other end of second connector and The printed circuit board electrical connection.
12. encapsulating structure according to claim 4, which is characterized in that
The top layer encapsulating structure includes top layer chip and third connector；One end of the third connector and the top layer Chip electrical connection, the other end are at least electrically connected with the interconnecting channel in chip-packaging structure；The third connector is set to institute It states on the second surface of substrate.
13. encapsulating structure according to claim 5, which is characterized in that the top layer encapsulating structure include top layer chip with And third connector；One end of the third connector is electrically connected with the top layer chip, the other end at least with chip package knot Interconnecting channel electrical connection in structure；
The third connector is set to described second and reroutes layer on a side surface of the objective chip.
14. a kind of electronic equipment, which is characterized in that the electronic equipment passes through the described in any item encapsulation knots of claim 1-13 Structure is equipped at least one chip.
15. a kind of method for being made to such as described in any item encapsulating structures of claim 1-13, which is characterized in that The method includes the production methods of chip-packaging structure:
Make the substrate with recessed portion；In the substrate, have substrate described in connection is opposite to set in the surrounding of the recessed portion The interconnecting channel for the first surface and second surface set；
At least one described objective chip is fixedly installed in the recessed portion；The active face of the objective chip is away from described The second surface of substrate；
In the side of the substrate first surface and the objective chip active face, production first reroutes layer, the first heavy cloth Signal path is laid on line layer, the signal path is electrically connected with the interconnecting channel and the objective chip.
16. according to the method for claim 15, which is characterized in that described at least one objective chip to be fixedly installed in After in recessed portion, in the side of the substrate first surface and the objective chip active face production first reroute layer it Before, the method also includes:
In the recessed portion, and backing material, the backing material and the base are filled in the periphery for being located at the objective chip The material of dielectric layer in plate is identical.
17. according to the method for claim 15, which is characterized in that described to incite somebody to action in the case where the recessed portion is groove At least one objective chip is fixedly installed in the recessed portion
Adhesive layer is formed in the bottom surface of the groove；
It will be on the back adhesive of the objective chip and the adhesive layer；
Wherein, the back side of the objective chip and the active face of the objective chip are oppositely arranged.
18. according to the method for claim 15, which is characterized in that described to incite somebody to action in the case where the recessed portion is through-hole At least one objective chip is fixedly installed in the recessed portion
On the loading end of support plate, and it is located at the region formation adhesive layer where the recessed portion；
It will be on the back adhesive of the objective chip and the adhesive layer；
Wherein, the back side of the objective chip and the active face of the objective chip are oppositely arranged.
19. according to the method for claim 15, which is characterized in that the first surface that substrate described in production connection is oppositely arranged Interconnecting channel with second surface includes:
On the substrate, and the surrounding positioned at recessed portion region to be formed, production run through what the substrate was oppositely arranged The via hole of first surface and second surface；
The plating metal copper in the via hole, forms the interconnecting channel.
20. according to the method for claim 15, which is characterized in that after the production has the substrate of recessed portion, It is described at least one described objective chip is fixedly installed in the recessed portion before, the method also includes:
On the loading end of support plate, interval mounts at least one described substrate；The second surface of the substrate is towards the support plate Loading end；
The first connector and blunt between two neighboring first connector is made on the active face of objective chip Change layer.
21. according to the method for claim 15, which is characterized in that described in the substrate first surface and the target core After the side production first of piece active face reroutes layer, the method also includes:
On the second surface that described first reroutes layer, the second surface that production reroutes layer with described first be electrically connected the Two connectors；
Wherein, the second surface of the first rewiring layer and the first surface of the first rewiring layer are oppositely arranged.
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