CN101656246B - Chip-stacked package structure of substrate with opening and packaging method thereof - Google Patents
Chip-stacked package structure of substrate with opening and packaging method thereof Download PDFInfo
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- CN101656246B CN101656246B CN 200810213646 CN200810213646A CN101656246B CN 101656246 B CN101656246 B CN 101656246B CN 200810213646 CN200810213646 CN 200810213646 CN 200810213646 A CN200810213646 A CN 200810213646A CN 101656246 B CN101656246 B CN 101656246B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention provides a chip stacking structure, which comprises a substrate, a first chip, a second chip, a first lead, a second lead, a first packaging body, a second packaging body and a conducting element, wherein the substrate is provided with a front and a back which are respectively provided with circuit layout, and the substrate is provided with an opening running through the substrate; the first chip is provided with an active surface and a back, wherein the active surface of the first chip is downwards, partial back of the first chip is attached to the back of the substrate through a first adhesion layer, and partial back of the first chip which is not covered by the first adhesion layer is exposed; the second chip is provided with an active surface and a back, wherein the active surface of the second chip is upwards, and the back of the second chip is fixed on the back of the first chip through a second adhesion layer; the first lead is electrically connected with the active surface of the first chip and the back of the substrate; the second lead is electrically connected with the active surface of the second chip and the front of the substrate; the first packaging body coats the first chip, the first adhesion layer, the first lead and the back of the substrate; the second packaging body coats the second chip, the second adhesion layer, the second lead, the partial back of the first chip and partial front of the substrate; and the conducting element is arranged on the front of the substrate.
Description
Technical field
Relevant a kind of encapsulating structure of the present invention and method thereof, particularly relevant a kind of chip stack package structure and method for packing thereof with substrate of opening.
Background technology
Semiconductor package with substrate of opening is advanced encapsulation technology, be characterized in: on substrate, form at least one through hole (opening), and allow the chip setting and cover the through hole of substrate, and the lead and substrate electric connection that engage by the routing that passes through hole.The mode of this kind setting can effectively shorten the length of the lead of routing joint, forms whereby to electrically connect between substrate and chip.The encapsulating structure of existing substrate with opening as shown in Figure 1, wherein substrate 100 has a upper surface and a lower surface and has an opening 102 and runs through substrate 100.Then, a chip 120 is with active surface (expression) in the drawings mode and the opening 102 that is exposed to substrate 100 of the weld pad 122 on its active surface down.And then, many leads 130 engage (bondingwires) with routing mode is connected to the weld pad 122 of the chip 120 that is exposed to opening 102 by the opening 102 of substrate 100, electrically connects the lower surface of substrate 100 and the active surface of chip 120 whereby.Then, the mode of a packaging body 140 by printing is formed on the lower surface of substrate 100 in order to coated wire 130 and with the opening 102 of substrate 100 and seals up.
Yet, because the thermal coefficient of expansion (CTE between the chip 120 that packaging body (especially by the formed packaging body of resin material) 140 reaches with packaging body 140 contacts, not not matching coefficient of thermal expansion), under the condition of high temperature, the for example curing of packaging body 140 (curing) step or follow-up thermal cycle step, particularly can produce the burst apart problem of (chip-crack) of chip because come from the thermal stress (thermal stress) of packaging body 140 in the part of chip 120, and with respect to the chip than long and large-size, its reliability and yield all can reduce.In addition, in the forming process of packaging body 140, the lead of its wire bonds contacts in the time of can forming packaging body with the mode that resin material flows with mould, makes to have problem of short-circuit.
Summary of the invention
In view of above problem, main purpose of the present invention is that the substrate that provides a kind of utilization to have opening carries out piling up of chip, so as to reducing the package thickness of entire chip stacked structure.
According to above-mentioned purpose, the present invention discloses a kind of chip stack structure, comprises: a substrate has a front and a back side and disposes a configuration respectively and have an opening and runs through substrate; One first chip, has an active surface and a back side, wherein the active surface of first chip and is attached on the back side of substrate by the part back side of one first adhesion layer with first chip down, and exposes not the part back side of first chip that is covered by first adhesion layer; Second chip has an active surface and a back side, and wherein the active surface of second chip and is fixed on the back side of first chip by the back side of one second adhesion layer with second chip up; Many first leads are in order to the active surface that electrically connects first chip and the back side of substrate; Many second leads are in order to the active surface that electrically connects second chip and the front of substrate; First packaging body is in order to coat the back side of first chip, first adhesion layer, many first leads and substrate; One second packaging body is in order to coat second chip, second adhesion layer, many second leads, the part back side of first chip and the partial front of substrate; And a plurality of conducting elements, it is arranged on the front of substrate.
The present invention also discloses another chip stack structure, comprises: a substrate has a front and a back side and disposes a configuration respectively and have an opening and runs through substrate; One first chip has an active surface and a back side, and wherein the active surface of first chip and is attached to the back side of first chip on the part back side of substrate and adhesion layer covers a surface of opening down by an adhesion layer; One second chip has an active surface and a surface, wherein the active surface of second chip up, and the back side of second chip is fixed on the back side of first chip by adhesion layer; Many first leads are in order to the active surface that electrically connects first chip and the back side of substrate; Many second leads are in order to the active surface that electrically connects second chip and the front of substrate; First packaging body is in order to coat the back side of first chip, adhesion layer, many first leads and substrate; Second packaging body is in order to coat second chip, the partial front of adhesion layer, many second leads and substrate partly; A plurality of conducting elements, it is arranged on the front of substrate.
According to above-mentioned chip stack structure, the present invention discloses a kind of method that forms chip stack structure, comprises: provide a substrate to have a positive and back side, and dispose a configuration respectively, and have the front and the back side that an opening runs through substrate; Attach first chip on the part back side of substrate, be with the active surface of first chip down, the back side of first chip is attached on the part back side of substrate and exposes in opening the back side of first chip that is not covered by first adhesion layer of first chip by one first adhesion layer; Attaching second chip on the back side of first chip, is with the active surface of second chip up, and a back side of second chip is attached to not on the back side of first chip that is covered by first adhesion layer by one second adhesion layer; Form many first leads, with the active surface that electrically connects first chip and the back side of substrate; Form many second leads, with the active surface that electrically connects second chip and the front of substrate; Form one first packaging body, in order to coat the back side of first chip, first adhesion layer, many first leads and substrate; Form one second packaging body, in order to the partial front of the part back side that coats second chip, second adhesion layer, first chip, many second leads and substrate; And form a plurality of conducting elements, be formed on the front of substrate.
The present invention discloses a kind of chip-stacked method that forms again, comprises: a substrate is provided, and it has a positive and back side and disposes a configuration respectively, and has the front and the back side that an opening runs through substrate; Attaching one first chip on the part back side of substrate, is with the active surface of first chip down, a back side of first chip is attached to the back side of substrate by an adhesion layer; Attaching one second chip on the back side of first chip, is with an active surface of second chip up and be fixed in the back side of second chip on the back side of first chip by adhesion layer; Form many first leads with the active surface that electrically connects first chip and the back side of substrate; Form many second leads with the active surface that electrically connects second chip and the front of substrate; Form one first packaging body in order to coat the back side of first chip, adhesion layer, many first leads and substrate; Form the partial front of second packaging body in order to the part back side that coats second chip, adhesion layer, first chip, many second leads and substrate; And form a plurality of conducting elements, be that a plurality of conducting elements are formed on the front of substrate.
Description of drawings
For can clearer understanding purpose of the present invention, structure, feature and function thereof, below conjunction with figs. is elaborated to preferred embodiment of the present invention, wherein:
Fig. 1 is according to prior art, and expression has the schematic diagram of encapsulating structure of the substrate of opening;
Fig. 2 A to Fig. 2 F is according to technology of the present invention, and expression has each step schematic diagram that the chip stack package structure of the substrate of opening forms; And
Fig. 3 A to Fig. 3 F is according to another embodiment of the present invention, and expression has each step schematic diagram that the chip stack package structure of the substrate of opening forms.
Embodiment
The present invention is a kind of encapsulating structure and method for packing thereof in this direction of inquiring into, provides the substrate with opening, makes the chip of different size can cover crystal type and is attached on the substrate towards opening, carries out chip-stacked method then.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention does not limit in the mode of Chip Packaging and is the specific details that the technical staff was familiar with of art technology.For preferred embodiment of the present invention, then can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention is not limited, but is as the criterion with appended the application's claim institute restricted portion.
Fig. 2 A to Fig. 2 B represents to have each step schematic diagram that the chip stack package structure of the substrate of opening forms.At first, with reference to figure 2A, one substrate 10 is provided earlier, and it has a positive and back side, and in the front and the back side be respectively arranged with a configuration (layout) (expression in the drawings), at this, front at substrate 10 is to dispose configuration identical or inequality with the back side, and in the present embodiment, is to be its main invention technical characterictic in order to the chip that piles up different size and function, therefore, be with the explanation of substrate 10 with different configurations as embodiment.Yet, be noted that the formation and the structure thereof of the configuration of substrate 10 is not technical characterictic of the present invention, only the substrate that has a configuration with application illustrates as embodiments of the invention, therefore no longer adds statement.
Then, be to utilize semiconductor technology, above substrate 10, form the photoresist layer (not expression in the drawings) of a patterning; Then develop and etching, removing partly substrate, and form the front and the back side that an opening 12 runs through substrate 10.At this, the material of substrate 10 can be individual layer or the circuit board of multilayer or sheet metal (metal foil).
And then, Fig. 2 B is the schematic diagram that expression is attached to one first chip at the back side of substrate.In Fig. 2 B, be that first chip 30 is provided earlier, it has an active surface one back side, and has a plurality of weld pads 32 on active surface.Then, be down with the active surface of first chip 30, and by the opening 12 of first adhesion layer 20 with the back side align substrates 10 of first chip 30, the part back side of first chip 30 is anchored on the back side of substrate 10, and expose the part back side of first chip 30 in the opening 12 of substrate 10.In this embodiment, first adhesion layer 20 can be two-stage hot-setting adhesive (B-stage).
Next, please refer to Fig. 2 C, it is that expression is with the second chip-stacked schematic diagram on first chip.In Fig. 2 C, provide one second chip 50, it has an active surface and a back side, and has a plurality of weld pads 52 on active surface.Then, with the active surface of second chip 50 up, the back side of its second chip 50 is attached to first chip 30 by one second adhesion layer 40 and is exposed on the back side of opening 12 of substrate 10, to form a chip stack structure.In this embodiment, second adhesion layer can be that chip sticks together glued membrane (die attach fi lm) or epoxy resin (epoxy).In addition, in the present embodiment, first chip 30 and second chip 50 are chips of difference in functionality, whereby to increase the range of application of chip stack package structure.
Then, please refer to Fig. 2 D, its schematic diagram that to be expression electrically connect first chip, second chip with substrate respectively.In Fig. 2 D, be that first chip 30 and second chip 50 that will be attached to earlier on the substrate 10 spins upside down, the active surface that makes the chip 30 of winning up and the active surface of second chip 50 down.Then, utilize routing to engage the mode of (bonding wire), two ends with many first leads 60, be respectively formed on the back side of a plurality of weld pads 32 of active surface of first chip 30 and substrate 10, and on the back side of substrate 10, dispose a configuration, therefore, utilize many first leads 60 can electrically connect first chip 30 and substrate 10.Then, again first chip 30 and second chip are gone up upset 50 times, make active surface that the active surface of the chip 30 of winning reaches second chip 50 down up.Similarly, the mode of utilizing routing to engage is respectively formed at the two ends of many second leads 70 on the front of a plurality of weld pads 52 of active surface of second chip 50 and substrate 10.Because, on the front of substrate 10, dispose a configuration equally, make many second leads 70 can electrically connect second chip 50 and substrate 10.In addition, be noted that in an embodiment of the present invention, also can be earlier on second chip 50, form many second leads 70 and then second chip 50 and first chip 30 are reversed up and down, more first leads 60 of formation on first chip 30.
And then, with reference to figure 2E, it is that expression forms the schematic diagram of packaging body on substrate.In Fig. 2 E, at first a macromolecular material (not expression in the drawings) is injected reaching in the opening 12 of substrate 10 of second chip 50 all around.Then, this macromolecular material is carried out a baking program (bake process), make macromolecular material solidify with form a packaging body 80A with envelope second chip 50, second adhesion layer 40, many first leads 60 and cover the opening 12 of substrate 10 and the partial front of substrate 10 on.Then, first chip 30 and second chip 50 are spun upside down, the active surface that makes the chip 30 of winning up.Similarly, again another macromolecular material is injected first chip 30 around.Next, macromolecular material is carried out a baking program, make the macromolecular material eventization to form another packaging body 80B to envelope the back side of first chip 30, many first leads 60 and substrate 10.In this embodiment, macromolecular material can be silica gel, epoxy resin, acrylic acid (acryl ic), reach benzocyclobutene materials such as (BCB).
And then, with reference to figure 2F, it is the schematic diagram that expression is formed on a plurality of conducting elements in the front of substrate.In Fig. 2 F, on the front of substrate 10, be the arrayed mode, form a plurality of conducting elements 90, for example metal coupling (metal bump) or tin ball (solder ball) can be finished chip-stacked encapsulating structure.
In addition, Fig. 3 A to Fig. 3 F is the embodiment of expression another chip-stacked encapsulating structure of the present invention.In Fig. 3 A, be that a substrate 10 is provided earlier, it has a positive and back side, and in the front and the back side be respectively arranged with a configuration (layout) (expression) in the drawings, at this, can dispose configuration identical or inequality with the back side in the front of substrate 10, and in the present embodiment, being to be its main invention technical characterictic in order to the chip that piles up different size and function, therefore, is with the explanation as embodiment of substrate 10 with different configurations.Yet, be noted that the formation and the structure thereof of the configuration of substrate 10 is not technical characterictic of the present invention, only the substrate that has a configuration with application illustrates as embodiments of the invention, therefore no longer adds statement.
Then, be to utilize semiconductor technology, above substrate 10, form the photoresist layer (not expression in the drawings) of a patterning; Then develop and etching, removing partly substrate, and form the front and the back side that an opening 12 runs through substrate 10.At this, the material of substrate 10 can be individual layer or the circuit board of multilayer or sheet metal (metal foil).
And then, Fig. 3 B is the schematic diagram that expression is attached to one first chip at the back side of substrate.In Fig. 3 B, be that first chip 30 is provided earlier, it has an active surface one back side, and has a plurality of weld pads 32 on active surface.Then, be down with the active surface of first chip 30, and, with the opening 12 of the back side align substrates 10 of first chip 30 the part back side of first chip 30 is anchored on the part back side of substrate 10 by adhesion layer 20B, and cover the opening 12 of substrate 10 and expose adhesion layer 20B.In this embodiment, adhesion layer 20B can be that chip sticks together glued membrane (DAF; Die attach fi lm) or epoxy resin (epoxy).
Next, please refer to Fig. 3 C, it is that expression is with the second chip-stacked schematic diagram on first chip.In Fig. 3 C, provide one second chip 50, it has an active surface and a back side, and has a plurality of weld pads 52 on active surface.Then, with the active surface of second chip 50 up, the back side of its second chip 50 anchors at by adhesion layer 20B on the back side of first chip 30, to form a chip stack structure.In this embodiment, first chip 30 and second chip 50 are chips of difference in functionality, whereby to increase the range of application of chip stack package structure.
Then, please refer to Fig. 3 D, its schematic diagram that to be expression electrically connect first chip, second chip with substrate respectively.In Fig. 3 D, be that first chip 30 and second chip 50 that will be attached to earlier on the substrate 10 spins upside down, the active surface that makes the chip 30 of winning up and the active surface of second chip 50 down.Then, utilize routing to engage the mode of (bonding wire), two ends with many first leads 60, be respectively formed on the back side of a plurality of weld pads 32 of active surface of first chip 30 and substrate 10, and on the back side of substrate 10, dispose a configuration, therefore, utilize many first leads 60 can electrically connect first chip 30 and substrate 10.Then, again first chip 30 and second chip are gone up upset 50 times, make active surface that the active surface of the chip 30 of winning reaches second chip 50 down up.Similarly, the mode of utilizing routing to engage is respectively formed at the two ends of many second leads 70 on the front of a plurality of weld pads 52 of active surface of second chip 50 and substrate 10.Because, on the front of substrate 10, dispose a configuration equally, make many second leads 70 can electrically connect second chip 50 and substrate 10.In addition, be noted that in an embodiment of the present invention, also can be earlier on second chip 50, form many second leads 70 and then second chip 50 and first chip 30 are reversed up and down, more first leads 60 of formation on first chip 30.
And then, with reference to figure 3E, it is that expression forms the schematic diagram of packaging body on substrate.In Fig. 3 E, at first a macromolecular material (not expression in the drawings) is injected reaching in the opening 12 of substrate 10 of second chip 50 all around.Then, this macromolecular material is carried out a baking program (bake process), make macromolecular material solidify with form a packaging body 80A with envelope second chip 50, be exposed to the adhesion layer 20B of opening 12, many first leads 60 and cover the opening 12 of substrate 10 and the partial front of substrate 10 on.Then, first chip 30 and second chip 50 are spun upside down, the active surface that makes the chip 30 of winning up.Similarly, again another macromolecular material is injected first chip 30 around.Next, macromolecular material is carried out a baking program, make the macromolecular material eventization to form another packaging body 80B to envelope first chip 30, the back side of adhesion layer 20B, many first leads 60 and substrate 10 partly.In this embodiment, macromolecular material can be silica gel, epoxy resin, acrylic acid (acrylic), reach benzocyclobutene materials such as (BCB).
And then, with reference to figure 3F, it is the schematic diagram that expression is formed on a plurality of conducting elements in the front of substrate.In Fig. 3 F, on the front of substrate 10, be the arrayed mode, form a plurality of conducting elements 90, for example metal coupling (metal bump) or tin ball (solder ball) can be finished chip-stacked encapsulating structure.
Though the present invention discloses as above with aforesaid preferred embodiment; yet it is not in order to limit the present invention; anyly be familiar with those skilled in the art; without departing from the spirit and scope of the present invention; when can making all changes that is equal to or replacement, therefore scope of patent protection of the present invention must be looked being as the criterion that the appended the application's claim scope of this specification defined.
Claims (10)
1. chip stack structure comprises:
One substrate has a front and a back side and disposes a configuration respectively and have an opening and runs through this substrate;
One first chip, has an active surface and a back side, wherein this active surface of this first chip down, and be attached on this back side of this substrate by one first adhesion layer this back side of part, and expose not by this back side of part of this first chip of this first adhesion layer covering with this first chip;
One second chip, has an active surface and a back side, wherein this active surface of this second chip and is fixed on this back side of this first chip by one second adhesion layer this back side with this second chip up, makes this second chip be placed in the opening of this substrate;
Many first leads are in order to this active surface of electrically connecting this first chip and this back side of this substrate;
Many second leads are in order to this active surface of electrically connecting this second chip and this front of this substrate;
One first packaging body is in order to coat this back side of this first chip, this first adhesion layer, these first leads and this substrate;
One second packaging body should the front in order to the part of this back side of part of coating this second chip, this second adhesion layer, these second leads, this first chip and this substrate; And
A plurality of conducting elements, it is arranged on this front of this substrate.
2. chip stack structure according to claim 1 is characterized in that this first adhesion layer is the two-stage hot-setting adhesive.
3. chip stack structure according to claim 1 is characterized in that this second adhesion layer is that epoxy resin or chip stick together film.
4. chip stack structure comprises:
One substrate has a front and a back side and disposes a configuration respectively and have an opening and runs through this substrate;
One first chip has an active surface and a back side, wherein this active surface of this first chip down, and this back side of this first chip is attached on this back side of part of this substrate by an adhesion layer and this adhesion layer covers a surface of this opening;
One second chip has an active surface and a back side, wherein this active surface of this second chip up, and this back side of this second chip is fixed on this back side of this first chip by this adhesion layer, makes this second chip be placed in the opening of this substrate;
Many first leads are in order to this active surface of electrically connecting this first chip and this back side of this substrate;
Many second leads are in order to this active surface of electrically connecting this second chip and this front of this substrate;
One first packaging body is in order to coat this back side of this first chip, this adhesion layer, these first leads and this substrate;
One second packaging body, in order to coat this second chip, partly the part of this adhesion layer, these second leads and this substrate should the front; And
A plurality of conducting elements, it is arranged on this front of this substrate.
5. chip stack structure according to claim 4 is characterized in that this adhesion layer is epoxy resin or chip adhesion layer.
6. method that forms chip stack structure comprises:
Provide a substrate to have a positive and back side and dispose a configuration respectively, and have this front and this back side that an opening runs through this substrate;
Attach one first chip on this back side of part of this substrate, be with an active surface of this first chip down, a back side of this first chip is attached on this back side of part of this substrate and exposes not in this opening this back side of this first chip that is covered by this first adhesion layer by one first adhesion layer;
Attach one second chip on this back side of this first chip, be up with an active surface of this second chip, one back side of this second chip is attached to not on this back side of this first chip that is covered by this first adhesion layer by one second adhesion layer, makes this second chip be placed in the opening of this substrate;
Form many first leads with this active surface of electrically connecting this first chip and this back side of this substrate;
Form many second leads with this active surface of electrically connecting this second chip and this front of this substrate;
Form one first packaging body, in order to coat this back side of this first chip, this first adhesion layer, these first leads and this substrate;
Form one second packaging body, should the front in order to the part of this back side of part, these second leads and this substrate that coat this second chip, this second adhesion layer, this first chip; And
Forming a plurality of conducting elements, is that these conducting elements are formed on this front of this substrate.
7. method according to claim 6 is characterized in that the size difference of this first chip and this second chip.
8. method that forms chip stack structure comprises:
One substrate is provided, and it has a positive and back side and disposes a configuration respectively, and has this front and this back side that an opening runs through this substrate;
Attaching one first chip on this back side of part of this substrate, is with an active surface of this first chip down, a back side of this first chip is attached to this back side of this substrate by an adhesion layer;
Attach one second chip on this back side of this first chip, be that an active surface of this second chip is fixed on this back side of this first chip by this adhesion layer up and with the back side of this second chip, make this second chip be placed in the opening of this substrate;
Form many first leads with this active surface of electrically connecting this first chip and this back side of this substrate;
Form many second leads with this active surface of electrically connecting this second chip and this front of this substrate;
Form one first packaging body in order to coat this back side of this first chip, this adhesion layer, these first leads and this substrate;
Forming one second packaging body should the front in order to the part of this back side of part, these second leads and this substrate that coat this second chip, this adhesion layer, this first chip; And
Forming a plurality of conducting elements, is that these conducting elements are formed on this front of this substrate.
9. method according to claim 8 is characterized in that the size difference of this first chip and this second chip.
10. method according to claim 8 is characterized in that adhesion layer is that epoxy resin or chip stick together film.
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| US9147600B2 (en) * | 2013-01-03 | 2015-09-29 | Infineon Technologies Ag | Packages for multiple semiconductor chips |
| US11139341B2 (en) * | 2018-06-18 | 2021-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Protection of MRAM from external magnetic field using magnetic-field-shielding structure |
| CN110233113A (en) * | 2019-06-17 | 2019-09-13 | 青岛歌尔微电子研究院有限公司 | A kind of packaging method of chip |
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| US20030015782A1 (en) * | 2001-06-29 | 2003-01-23 | Choi Hee Kook | Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture |
| US20040152235A1 (en) * | 2002-12-30 | 2004-08-05 | Dongbu Electronics Co., Ltd. | Double side stack packaging method |
| US20070164402A1 (en) * | 2006-01-17 | 2007-07-19 | Advanced Semiconductor Engineering Inc. | Semiconductor package and process for making the same |
| CN101026144A (en) * | 2006-02-24 | 2007-08-29 | 日月光半导体制造股份有限公司 | Radiating type stereo package structure and its manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030015782A1 (en) * | 2001-06-29 | 2003-01-23 | Choi Hee Kook | Double-sided circuit board and multi-chip package including such a circuit board and method for manufacture |
| US20040152235A1 (en) * | 2002-12-30 | 2004-08-05 | Dongbu Electronics Co., Ltd. | Double side stack packaging method |
| US20070164402A1 (en) * | 2006-01-17 | 2007-07-19 | Advanced Semiconductor Engineering Inc. | Semiconductor package and process for making the same |
| CN101026144A (en) * | 2006-02-24 | 2007-08-29 | 日月光半导体制造股份有限公司 | Radiating type stereo package structure and its manufacturing method |
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