CN101656247A - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
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- CN101656247A CN101656247A CN200810213649A CN200810213649A CN101656247A CN 101656247 A CN101656247 A CN 101656247A CN 200810213649 A CN200810213649 A CN 200810213649A CN 200810213649 A CN200810213649 A CN 200810213649A CN 101656247 A CN101656247 A CN 101656247A
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- adhesion layer
- active surface
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 143
- 239000000463 material Substances 0.000 claims description 14
- 239000013078 crystal Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000011469 building brick Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000012163 sequencing technique Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004568 cement Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention provides a semiconductor packaging structure, which comprises a substrate, a first chip, a first lead, a second adhesion layer, a second chip, a second lead, a first packaging body, a second packaging body and a conducting element, wherein the substrate is provided with a front and a back, and is also provided with an opening penetrating the substrate; the first chip is provided withan active surface and a back, covers the opening through a first adhesion layer in a mode that the active surface is upwards, and is attached to the back of the substrate through the first adhesion layer; the first lead is electrically connected with the first chip and the front of the substrate through the opening; the second adhesion layer coats the first lead and covers a solder pad on the active surface of the first chip and partial front of the substrate; the second chip is provided with an active surface and a back, the back of the second chip is downwards and the active surface is upwards relative to the first chip, and the second chip is attached to the front of the substrate through the second adhesion layer; the second lead is electrically connected with the active surface of the second chip and the front of the substrate; the first packaging body coats the first chip, the first adhesion layer, the first lead and partial back of the substrate; the second packaging body coststhe second chip, the second adhesion layer, the second lead and the partial front of the substrate; and the conducting element is arranged on the back of the substrate.
Description
Technical field
Relevant a kind of encapsulating structure of the present invention and method thereof, particularly relevant a kind of encapsulating structure and method thereof with substrate of opening.
Background technology
Semiconductor package with substrate of opening is advanced encapsulation technology, be characterized in: on substrate, form at least one through hole (opening), and allow the chip setting and cover the through hole of substrate, and the lead and substrate electric connection that engage by the routing that passes through hole.The mode of this kind setting can effectively shorten the length of the lead of routing joint, forms whereby to electrically connect between substrate and chip.The encapsulating structure of existing substrate with opening as shown in Figure 1, wherein substrate 100 has a upper surface and a lower surface and has an opening 102 and runs through substrate 100.Then, a chip 120 is the openings 102 that are exposed to substrate 100 with active surface (not expression in the drawings) mode and the weld pad 122 on its active surface down.And then, many leads 130 engage (bondingwires) with routing mode is connected to the weld pad 122 of the chip 120 that is exposed to opening 102 by the opening 102 of substrate 100, electrically connects the lower surface of substrate 100 and the active surface of chip 120 whereby.Then, the mode of a packaging body 140 by printing is formed on the lower surface of substrate 100 in order to coated wire 130 and with the opening 102 of substrate 100 and seals up.
Yet, because the thermal coefficient of expansion (CTE between the chip 120 that packaging body (especially by the formed packaging body of resin material) 140 reaches with packaging body 140 contacts, not not matching coefficient of thermal expansion), under the condition of high temperature, the for example curing of packaging body 140 (curing) step or follow-up thermal cycle step, particularly can produce the burst apart problem of (chip-crack) of chip because come from the thermal stress (thermal stress) of packaging body 140 in the part of chip 120, and with respect to the chip than long and large-size, its reliability and yield all can reduce.In addition, in the forming process of packaging body 140, the lead of its wire bonds contacts in the time of can forming packaging body with the mode that resin material flows with mould, makes to have problem of short-circuit.
Summary of the invention
In view of above problem, main purpose of the present invention is to provide a kind of semiconductor package with window (window), whereby with the electrical and usefulness of the electrical transmission between the conductor length increase chip that shortens substrate with the lifting semiconductor package.
According to the above object, the invention provides a kind of semiconductor package, comprise: a substrate has a positive and back side, and has an opening and penetrated substrate; One first chip has an active surface and a back side, and wherein the active surface of first chip is up, and covers on the opening by first adhesion layer, and is attached to by first adhesion layer on the back side of substrate; Many first leads electrically connect the front of first chip and substrate by opening; Second adhesion layer is in order to coat many first leads and to cover many weld pads on the active surface of first chip; One second chip has an active surface and a back side, the back side of second chip be with respect to first chip down and active surface up, be attached to by second adhesion layer on the front of substrate; Many second leads are in order to the active surface that electrically connects second chip and the front of substrate; First packaging body is in order to coat the part back side of first chip, first adhesion layer, many first leads and substrate; Second packaging body is in order to coat the partial front of second chip, second adhesion layer, many second leads and substrate; And a plurality of conductive components, be arranged on the back side of substrate.
The present invention also discloses a kind of semiconductor package, comprises: a substrate has a positive and back side, and has an opening and penetrated substrate; First chip has an active surface and a back side, and wherein the active surface of first chip is to cover on the opening and be attached to by first adhesion layer on the back side of substrate up and by first adhesion layer; Second chip has an active surface and a back side, and wherein the back side of second chip is to cover on the opening by second adhesion layer down with respect to first chip, and is attached to by second adhesion layer on the front of substrate; One the 3rd chip has an active surface and a back side, is to connect on the outward extending front of substrate by a plurality of first conductive components down to cover crystal type; Many first leads are in order to electrically connect the front of first chip and substrate; Many second leads are in order to the active surface that electrically connects second chip and the front of substrate; First packaging body is in order to coat the part back side of first chip, first adhesion layer, many first leads and substrate; Second packaging body is in order to coat the partial front of second chip, second adhesion layer, many second leads and substrate; And a plurality of second conductive components, be arranged on the back side of substrate.
The present invention discloses a kind of semiconductor package again, comprises: a substrate has a positive and back side, and has an opening and penetrated substrate and be provided with a plurality of conduction end points in an end of substrate; One first chip has an active surface and a back side, and wherein the active surface of first chip is up, and covers on the opening by first adhesion layer, and is attached to by first adhesion layer on the back side of substrate; Many first leads electrically connect the front of first chip and substrate by opening; Second adhesion layer is in order to coat many first leads and to cover on the active surface of first chip; One second chip has an active surface and a back side, and the back side of second chip is with respect to first chip down and with active surface up, is attached to by second adhesion layer on the front of substrate; The 3rd chip has an active surface and a back side, is to be electrically connected on a plurality of connection end points in outward extending front of substrate by a plurality of first conductive components down to cover crystal type; Many second leads are in order to the active surface that electrically connects second chip and the front of substrate; First packaging body is in order to coat the part back side of first chip, first adhesion layer, many first leads and substrate; Second packaging body is in order to coat the partial front of second chip, second adhesion layer, many second leads and substrate; And a plurality of second conductive components, be arranged on the back side of substrate and partly second conductive component be with substrate on a plurality of connection end points electrically connect.
Description of drawings
For can clearer understanding purpose of the present invention, structure, feature and function thereof, below conjunction with figs. is elaborated to preferred embodiment of the present invention, wherein:
Fig. 1 is according to prior art, and expression has the schematic diagram of encapsulating structure of the substrate of opening;
Fig. 2 A to Fig. 2 F is according to technology of the present invention, represents each step schematic diagram of formation of a kind of semiconductor package of the substrate with opening;
Fig. 3 A to Fig. 3 B is according to technology of the present invention, represents each step schematic diagram of formation of another preferred embodiment of the semiconductor package of the substrate that another has opening; And
Fig. 4 A to Fig. 4 B is according to technology of the present invention, and expression has each step schematic diagram of formation of a preferred embodiment again of semiconductor package of the substrate of opening.
Embodiment
The present invention is a kind of encapsulating structure and method for packing thereof in this direction of inquiring into, provides the substrate with opening, makes upper and lower chip be attached on the substrate method that encapsulates then towards opening to cover crystal type.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention do not limit Chip Packaging mode be specific details that those skilled in the art were familiar with.For preferred embodiment of the present invention, then can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention is not limited, and it is as the criterion with appended claim institute restricted portion.
Please refer to Fig. 2 A to Fig. 2 F, it is each step schematic diagram of formation of the semiconductor package of disclosed a kind of substrate with opening according to the present invention.Fig. 2 A is the schematic diagram that expression has the substrate of opening.In Fig. 2 A, its substrate 10 has the front and the back side, and has the front and the back side that an opening 12 penetrated substrate 10, and at this, the material of substrate 10 can be circuit board or sheet metal.In addition, in an embodiment of the present invention, the front and the back side at substrate 10 are so that different configuration (layout) (not expression in the drawings) to be set earlier, to use as each assembly of follow-up electric connection, yet, in the front of substrate 10 and the configuration at the back side is not to be technical characterictic of the present invention, therefore, is not added to describe at this.
Then, please refer to Fig. 2 B, it is to represent first chip to cover the schematic diagram that crystal type is formed on the back side of substrate 10.In Fig. 2 B, provide one first chip 30A, and this first chip 30A has an active surface and the back side, and partly have a plurality of weld pad 31A in the center of active surface., and the opening 12 of align substrates 10, then the active surface of the first chip 30A is attached on the back side of substrate 10 by first adhesion layer 20 up earlier and covers a side of opening 12 active surface of the first chip 30A.In this embodiment, first adhesion layer 20 can be formed on earlier on the back side of substrate 10, and then with the active surface of the first chip 30A towards the back side of substrate 10, and anchor at the back side of substrate 10 by first adhesion layer 20.In addition, in another embodiment, first adhesion layer 20 is formed on earlier on the active surface of the first chip 30A, similarly, again with the active surface of first chip 30A opening 12 places of align substrates 10 up, then the first chip 30A is attached and is bonded on the back side of substrate 10 by first adhesion layer 20, and the weld pad 31A of the first chip 30A is exposed to the opening 12 of substrate 10.At this, the material of first adhesion layer 20 can be a second order segmentation thermosetting cement material (B-stage).
Then, please refer to Fig. 2 C, is that expression utilizes many leads to electrically connect the schematic diagram of first chip and substrate.In Fig. 2 C, be to utilize the backhander line to engage the mode of (reverse wire bonding), many first lead 40A are respectively formed at a plurality of connection end points of being exposed on the front of substrate 10 (expression in the drawings) and are formed on the center weld pad 31A of the first chip 30A, so as to electrically connecting the substrate 10 and the first chip 30A by opening 12.
Then, please refer to Fig. 2 D, it is that expression second chip is formed on the schematic diagram on the substrate.In Fig. 2 D, be that film is covered bonding wire (FOW; Film over wire) 50 forms enveloping many first lead 40A, and simultaneously film is covered bonding wire 50 and seal up the opening 12 of substrate 10 and cover on the active surface of the first chip 30A and on the partial front of substrate 10.And then, same with reference to figure 2D, be up with the active surface (representing in the drawings) of the second chip 32A, anchor on the substrate 10 by film covering bonding wire 50.Next, a plurality of weld pad 31B that to be the mode (wiring bonding) of utilizing routing be respectively formed at the active surface of the second chip 30B with the two ends of many second lead 40B go up and a plurality of connection end points that the front exposed (expression in the drawings) of substrate 10 on, so as to electrically connecting second chip 32 and substrate 10.At this, the weld pad 31B of the second chip 30B is not to be the center that is arranged on the second chip 30B, and the function of the second chip 30B and size are different with the first chip 30A.
Next, please refer to Fig. 2 E, it is the schematic diagram that expression forms encapsulating structure.In the 5th figure, be earlier first macromolecular material (not expression in the drawings) to be formed on the part back side of the first chip 30A and substrate 10, then first macromolecular material be cured to form the first packaging body 60A to envelope the part back side of the first chip 30A and substrate 10.Similarly, second macromolecular material (expression) in the drawings is formed on the partial front of the second chip 30B, many second lead 40B and substrate 10, then second macromolecular material is cured to form the second packaging body 60B to envelope the second chip 30B, many second lead 40B, partly
Film covers weldering Line 
50 and the partial front of substrate 10.
Then, Fig. 2 F is illustrated in the schematic diagram that forms a plurality of conductive components on the back side of substrate.In Fig. 2 F, be that a plurality of conductive components 70 are formed on a plurality of connection end points (expression in the drawings) on the back side of substrate 10, in order to electrically connect with other outside electronic building brick.At this, conductive component 70 can be tin ball (solder ball).
In addition, Fig. 3 A to Fig. 3 B is disclosed another preferred embodiment of the present invention.At this, formation step, material and the function of Fig. 3 A is identical with aforesaid Fig. 2 A to Fig. 2 E, no longer adds to describe at this.Yet the difference of Fig. 3 A and Fig. 2 E is, in Fig. 3 A, be to be provided with one the 3rd chip 30C on the front of an outward extending at least end of substrate 10, and electrically connect to cover a plurality of connection end points (not expression in the drawings) that exposed to the open air on brilliant mode and the front by a plurality of second conductive component 70B and substrate 10.Then, please refer to Fig. 3 B, is that a plurality of first conductive component 70A are formed on a plurality of connection end points that the back side exposed (expression) in the drawings of substrate 10, and with its electric connection.In this embodiment, can form at the back side of substrate 10 earlier a plurality of first conductive component 70A or earlier with the 3rd chip 30C to cover crystal type and to be formed on the front of substrate 10 by more than second conductive component 70B, therefore, both sequencings of being formed on the substrate 10 are not limited.In addition, what deserves to be mentioned is that the size of the 3rd chip 30C can be all inequality with the first chip 30A and the second chip 30B, also or identical with one of them chip (the first chip 30A or the second chip 30B).
Moreover Fig. 4 A to Fig. 4 B is the disclosed preferred embodiment again of the present invention.At this, formation step, material and the function of Fig. 4 A is identical with aforesaid Fig. 2 A to Fig. 2 E, no longer adds to describe at this.Yet the otherness of Fig. 4 A to Fig. 4 B and previous embodiment is, in Fig. 4 A, at least be provided with a plurality of connection end points 80 in the outward extending end of substrate 10, this connection end point 80 can be golden finger (golden finger) structure, so as to electrically connecting other electronic building brick.Then, be on having stretched out of substrate 10 is provided with an end of connection end point 80, one the 3rd chip 30C to be set, and to cover a plurality of connection end points 80 electric connections that exposed to the open air on the brilliant front of mode by a plurality of second conductive component 70B and substrate 10.Then, please refer to Fig. 4 B, is that a plurality of first conductive component 70A are formed on a plurality of connection end points that the back side exposed of substrate 10, and with its electric connection.Same, in this embodiment, can form at the back side of substrate 10 earlier a plurality of first conductive component 70A or earlier with the 3rd chip 30C to cover crystal type and to be formed on the front of substrate 10 by a plurality of second conductive component 70B, therefore, both sequencings of being formed on the substrate 10 are not limited.In addition, what deserves to be mentioned is that the size of the 3rd chip 30C can be all inequality with the first chip 30A and the second chip 30B, also or identical with one of them chip (the first chip 30A or the second chip 30B).In the present embodiment, the first conductive component 70A and the second conductive component 70B can be tin ball (solder ball).
Though the present invention discloses as above with aforesaid preferred embodiment; yet it is not in order to limit the present invention; any person skilled in the art person; without departing from the spirit and scope of the present invention; when can making all changes that is equal to or replacement, therefore scope of patent protection of the present invention must be looked being as the criterion that the appended the application's claim scope of this specification defined.
Claims (10)
1. semiconductor package comprises:
One substrate has a positive and back side, and has an opening and penetrated this substrate;
One first chip has an active surface and a back side, and this active surface covers on this opening and is attached to by this first adhesion layer on this back side of this substrate up and by one first adhesion layer;
Many first leads electrically connect this front of this first chip and this substrate by opening;
One second adhesion layer is in order to coat these first leads and to cover these weld pads on this active surface of this first chip and be formed on the partial front of this substrate;
One second chip has an active surface and a back side, and this back side of this second chip is to be attached on this front of this substrate by this second adhesion layer down;
Many second leads are in order to this active surface of electrically connecting this second chip and this front of this substrate;
One first packaging body is in order to coat this back side of this first chip, this first adhesion layer, these first leads and this substrate of part;
One second packaging body is in order to coat this front of this second chip, this second adhesion layer, these second leads and this substrate of part; And
A plurality of conductive components are arranged on this back side of this substrate.
2. semiconductor package according to claim 1, the material that it is characterized in that this substrate are to be circuit board or sheet metal.
3. semiconductor package according to claim 1 is characterized in that the size difference of this first chip and this second chip.
4. semiconductor package comprises:
One substrate has a positive and back side, and has an opening and penetrated this substrate;
One first chip has an active surface and a back side, and wherein this active surface of this first chip is to cover on this opening and be attached to by this first adhesion layer on this back side of this substrate up and by one first adhesion layer;
Many first leads are in order to electrically connect this front of this first chip and this substrate;
One second adhesion layer is in order to coat these first leads and to cover on this active surface of this first chip;
One second chip has an active surface and a back side, this back side of this second chip be with respect to this first chip down and this active surface up, be attached to by this second adhesion layer on this front of this substrate;
Many second leads are in order to this active surface of electrically connecting this second chip and this front of this substrate;
One first packaging body is in order to coat this back side of this first chip, this first adhesion layer, these first leads and this substrate of part;
One second packaging body is in order to coat this front of this second chip, this second adhesion layer, these second leads and this substrate of part;
A plurality of second conductive components are arranged on this back side of this substrate; And
One the 3rd chip has an active surface and a back side, be with cover crystal type down by a plurality of first conductive components connect this substrate outward extending should the front on.
5. semiconductor package according to claim 4, the material that it is characterized in that this substrate are circuit board or sheet metal.
6. semiconductor package according to claim 4 is characterized in that the size difference of this first chip, this second chip and the 3rd chip.
7. semiconductor package comprises:
One substrate has a positive and back side, and has an opening and penetrated this substrate and be provided with a plurality of connection end points in an end of this substrate;
One first chip has an active surface and a back side, and wherein this active surface of this first chip is to cover on this opening and be attached to by this first adhesion layer on this back side of this substrate up and by one first adhesion layer;
Many first leads are in order to electrically connect this front of this first chip and this substrate;
One second adhesion layer is in order to coat these first leads and to cover on this active surface of this first chip;
One second chip has an active surface and a back side, and wherein this back side of this second chip is to cover on this opening by this second adhesion layer down with respect to this first chip, and is attached to by this second adhesion layer on this front of this substrate;
Many second leads are in order to this active surface of electrically connecting this second chip and this front of this substrate;
One first packaging body is in order to coat this back side of this first chip, this first adhesion layer, these first leads and this substrate of part;
One second packaging body is in order to coat this front of this second chip, this second adhesion layer, these second leads and this substrate of part;
One the 3rd chip has an active surface and a back side, be with cover crystal type down by a plurality of first conductive components be electrically connected at this substrate outward extending should these connection end points in front on; And
A plurality of second conductive components, be arranged on this back side of this substrate and partly these second conductive components be to electrically connect with these connection end points on this back side of this substrate.
8. semiconductor package according to claim 7, the material that it is characterized in that this substrate are circuit board or sheet metal.
9. semiconductor package according to claim 7, these connection end points that it is characterized in that this substrate are golden finger.
10. semiconductor package according to claim 7 is characterized in that the size difference of this first chip, this second chip and the 3rd chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810213649A CN101656247A (en) | 2008-08-19 | 2008-08-19 | Semiconductor packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200810213649A CN101656247A (en) | 2008-08-19 | 2008-08-19 | Semiconductor packaging structure |
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| CN101656247A true CN101656247A (en) | 2010-02-24 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034801A (en) * | 2010-06-04 | 2011-04-27 | 日月光半导体制造股份有限公司 | Semiconductor package structure |
| CN103915405A (en) * | 2013-01-03 | 2014-07-09 | 英飞凌科技股份有限公司 | Semiconductor device and method of making a semiconductor device |
| CN112242387A (en) * | 2019-07-16 | 2021-01-19 | Tdk株式会社 | Electronic component package |
-
2008
- 2008-08-19 CN CN200810213649A patent/CN101656247A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034801A (en) * | 2010-06-04 | 2011-04-27 | 日月光半导体制造股份有限公司 | Semiconductor package structure |
| CN102034801B (en) * | 2010-06-04 | 2012-10-10 | 日月光半导体制造股份有限公司 | Semiconductor package structure |
| CN103915405A (en) * | 2013-01-03 | 2014-07-09 | 英飞凌科技股份有限公司 | Semiconductor device and method of making a semiconductor device |
| CN103915405B (en) * | 2013-01-03 | 2017-05-24 | 英飞凌科技股份有限公司 | Semiconductor device and method of making a semiconductor device |
| CN112242387A (en) * | 2019-07-16 | 2021-01-19 | Tdk株式会社 | Electronic component package |
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