J290759 九、發明說明： 【發明所屬之技術領域】 本發明係有關於半導體封裝技術，特別 種半導體封裝構造，以提昇溫度循環測試 可靠度。 【先前技術】 傳統上’半導體封裝構造會在底部設有 端子，例如銲球（solder ball)或錫膏等，藉 至一外部印刷電路板。在產品製成後應 度’其中溫度循環測試（Temperature Cycle 是目前半導體封裝產品之可靠度試驗項目 半導體封裝構造與外部印刷電路板之間會 膨脹係數的差異（CTE mismatch)，在重覆 循環過程中，對外端子會遭受熱應力而斷 如第1圖所示，一種習知的半導體封裝 要包含一基板110、一晶片120、一封膠體 個對外端子1 4 0。該晶片1 2 0係以一黏晶 著方式設置於該基板110之一上表面ιιΐϋ 使其銲墊122電性連接至該基板120。該 僅形成於該基板1 1 〇之上表面1 1 1，以 1 2 0。該些對外端子1 4 0係設置於該基板1 面112。由於該封膠體130在熟化後具有 構強度，使得被結合該晶片1 20與在該基 之對外端子 140。溫度循環測試中產生的 係有關於〜 效能之產品 複數個對外 以表面接合 測試其可靠 Test，TCT) 之一。由於 存在有一熱 的昇降溫的 裂。 構造100主 1 3 0與複數 層1 2 1之黏 L以銲線1 5 0 封膠體1 3 0 保護該晶片 1 0之該下表 相當硬的結 板11 0下方 熱應力會集 、1290759 中在部分之對外端子140，尤其是在該基板iio之邊 緣與角隅處的對外端子140常常斷裂。目前一種已知 的補救措施是在該半導體封叢構造1 〇〇上板後利用角 隅接合劑（corner bond)固定住該基板1 1 〇之角隅，以 避免對外端子斷裂，但是必須在上板之後方可進行， 非屬於元件上板之標準製程，須額外執行一膠體熟化 製程’會增加SMT成本。且在角隅接合劑熟化後，該 半導體封裝構造100不可被重工修補或更換。 • Tessera公司於美國專利第5,679,977號提出一種解 決方法’在一半導體晶片組合件（semiconductor chip assembly)中，利用軟性基板之軟性引腳連接對外端子 與晶片，並將原設在該晶片與軟性基板之間的黏晶層 變更為一具有彈性或低模數的順從層（c〇mpHant layer) ’使得對外端子相對於晶片為可移動。然而這種 方式僅能應用在無封膠體之半導體晶片組合件，並不 適用於傳統需要堅硬封膠體之半導體封裝構造 籲 （semiconductor package)，當封膠體熟化之後會重新結 合固定基板與晶片，使得對外端子相對於晶片又重新 變為不可移動（immovable)。 【發明内容】 為了解決上述之問題，本發明之主要目的係在於提 供一種半導體封裝構造，即使在封膠之後，對外端子仍 可相對於晶片為可移動，避免半導體封裝構造在上板後受 到昇降溫度變化產生的熱應力集中於部份之對外端子，亦不 .1290759 會轉移至晶片，以維持對外端子*會有斷裂之情事。 乂發明之次一目的係在於提供—種半導體封裝構 此避免封膠體直接結合基板，以使該基板與對外 %子可作水平向應力伸縮與移動。 ▲ ^發明之再一目的係在於提供一種半導體封裝構 月b避免銲線連接於基板之一端發生斷裂。J290759 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor packaging technology, and in particular to semiconductor package construction, to improve temperature cycle test reliability. [Prior Art] Conventionally, a semiconductor package structure is provided with a terminal at the bottom, such as a solder ball or a solder paste, to an external printed circuit board. After the product is manufactured, the temperature cycle test (Temperature Cycle is the current semiconductor package product reliability test project semiconductor package structure and the external printed circuit board between the expansion coefficient difference (CTE mismatch), in the repeated cycle process The external terminal may be subjected to thermal stress as shown in FIG. 1. A conventional semiconductor package includes a substrate 110, a wafer 120, and a colloidal external terminal 140. The wafer is 1200. A bonding film is disposed on an upper surface of the substrate 110 to electrically connect the pad 122 to the substrate 120. The surface is formed only on the upper surface of the substrate 1 1 1 to 1 2 0. The external terminals 140 are disposed on the surface 112 of the substrate 1. Since the encapsulant 130 has a structural strength after curing, the wafers 20 are bonded to the external terminals 140 of the substrate. One of the reliable Tests, TCTs for the product of ~ efficiencies to test externally with surface bonding. Because there is a hot rise and fall of the temperature. Constructing the adhesive L of the main 1300 and the plurality of layers 1 2 1 to the bonding wire 1 50, the sealing body 1 3 0, protecting the wafer 10, the table below the relatively hard junction plate 10 0 under the thermal stress gathering, 1290759 The outer terminal 140 at the portion of the external terminal 140, particularly at the edge and corner of the substrate iio, often breaks. A currently known remedy is to fix the corners of the substrate 1 1 with a corner bond after the semiconductor package is mounted on the upper plate to avoid breakage of the external terminals, but must be on After the board can be carried out, the standard process of the board is not part of the component, and an additional colloidal curing process must be performed to increase the SMT cost. And after the corner joint cement is cured, the semiconductor package structure 100 cannot be repaired or replaced. A solution is proposed by Tessera in U.S. Patent No. 5,679,977. In a semiconductor chip assembly, the flexible terminals of the flexible substrate are used to connect the external terminals to the wafer, and the original substrate and the flexible substrate are disposed on the wafer and the flexible substrate. The bond between the layers is changed to a flexible or low modulus pair of layers (c〇mpHant layer) such that the external terminals are movable relative to the wafer. However, this method can only be applied to a semiconductor wafer assembly without a sealant, and is not suitable for a semiconductor package design that requires a hard sealant. When the sealant is cured, the substrate and the wafer are re-bonded, so that The external terminal is again immovable relative to the wafer. SUMMARY OF THE INVENTION In order to solve the above problems, the main object of the present invention is to provide a semiconductor package structure, the external terminal can be moved relative to the wafer even after sealing, and the semiconductor package structure is prevented from being lifted after the upper plate. The thermal stress caused by the temperature change is concentrated on some of the external terminals, and no. 1290759 will be transferred to the wafer to maintain the external terminal * breakage. The second object of the invention is to provide a semiconductor package structure which avoids directly bonding the sealing body to the substrate so that the substrate and the external element can be horizontally stretched and moved. ▲ Another object of the invention is to provide a semiconductor package structure b to prevent the bonding of the bonding wires to one end of the substrate.
本發明的目的及解決其技術問題是採用以下技術 案來實現的。依據本發明，—種半導體封裝構造主 要包含—基板、—晶片、-封膠體、複數個對外端子以及 -應力釋放層(stress release layer)。該基板係具有一上表面 與下表面。該晶片係藉由一黏晶層設置於該基板之該上表 面並電性連接至該基板。該封膠㈣至少形成㈣基板之上 表面。該些對外端子係設置於該基板之該下表面。該應力釋 放層係形成於該基板與該封膠體之界面，以使該些對外端子 相對於該晶片為可移動(removable)。另揭示該半導體封裝 構造之製程。 本發明的目的及解決其技術問題還可採用以下技 術措施進一步實現。 别述的半導體封裝構造，其中該應力釋放層與該黏晶 層之揚氏模數均小於該封膠體。 前述的半導體封裝構造，其中該應力釋放層與該黏晶 層係為相同材質。 刚述的半導體封裝構造，其中該應力釋放層係覆蓋於 該基板之上表面在封膠前之大部份顯露表面，以使該封膠體 7 .1290759 不直接結合該基板。 别述的半導體封裝構造，其中該應力釋放層之厚度係 不小於該黏晶層之厚度。 前述的半導體封裝構造，另包含有複數個銲線，其係 電性連接該晶片與該基板。 前述的半導體封裝構造，其中該些銲線連接該基板之 一端係被該應力釋放層所密封。The object of the present invention and solving the technical problems thereof are achieved by the following techniques. In accordance with the present invention, a semiconductor package construction primarily includes a substrate, a wafer, a sealant, a plurality of external terminals, and a stress release layer. The substrate has an upper surface and a lower surface. The wafer is disposed on the upper surface of the substrate by a die bonding layer and electrically connected to the substrate. The sealant (4) forms at least (4) a surface above the substrate. The external terminals are disposed on the lower surface of the substrate. The stress relief layer is formed at an interface between the substrate and the encapsulant such that the external terminals are movable relative to the wafer. A process for fabricating the semiconductor package structure is also disclosed. The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures. In a semiconductor package structure, the Young's modulus of the stress relief layer and the die layer are both smaller than the sealant. In the above semiconductor package structure, the stress relief layer and the die bond layer are made of the same material. The semiconductor package structure just described, wherein the stress relieving layer covers a majority of the exposed surface of the upper surface of the substrate before sealing, so that the encapsulant 7.1290759 does not directly bond to the substrate. A semiconductor package structure, wherein the thickness of the stress relief layer is not less than the thickness of the die layer. The semiconductor package structure described above further includes a plurality of bonding wires electrically connecting the wafer to the substrate. In the foregoing semiconductor package structure, one end of the bonding wires connected to the substrate is sealed by the stress releasing layer.
前述的半導體封裝構造’其中該基板係具有一槽孔， 該些銲、㈣通㈣槽孔，以純連接至該晶片。 月，j述的半導體封裝構造，其中該應力釋放層更形成於 該槽孔内。 【實施方式】 在本發明之第—具體實施例中m圖所示，-種半導體封裝構造200主要包含一基板21〇、一晶片 220、-封膠冑跡複數個對外端子⑽以及—應力釋放層 250。該基板21G係為-種適用於半導體封裝之晶片載體， 例如高密度印刷電路板、陶荼其4 At# j免基板、電路薄膜等等。該基板 210係具有-上表面211與一下表面212，並具有電性傳遞 該晶片22G至該些對㈣子24〇之線路結構，可為單層或多 層線路層，或可包含鍍通孔等。 該晶片220係為半導體材質，可包含有各式微小型元件， 例如積體電路、微機電元件、光電元件等。該晶片22〇係且 有-主動自222與-相對向之背面221，複數個銲藝⑶係 可形成於該主動面222。或者’利用晶圓之通孔製程，該此 8 .1290759 銲墊223係可形成於晶片220之背面221(圖未繪出）。藉由 一黏晶層224將該晶片220之一表面（例如該背面221)設置 於該基板210之該上表面211。通常該黏晶層224之材質係 為環氧物或有機樹脂類，不具有無機填料，其揚氏模數可以 低於該封膠體230，而更加柔軟。並可利用複數個銲線26〇 等電連接元件電性連接該晶片22〇至該基板21〇。在本實施 例中’該封裝構造200係為一般晶片朝上之球格陣列封裝構 ie該些知線260之一端係連接該晶片220之該些銲塾223, 另一端係連接該基板210位於該上表面211之内接指（圖未 繪出），該些銲線260之形成係在該應力釋放層25〇與該封 膠體230的形成之前。 該封膠體230係至少形成於該基板210之上表面211，用 以保護該晶片220。在本實施例中，該封膠體23〇更密封該 些銲線260。該封膠體230係可由壓模或印刷方式形成，其 材質包含熱固性樹脂、無機填料、分散劑、色料。在熟化之 後，該封膠體230係具有良好電絕緣性與較強的結構硬度。 該封膠體230在熟化後的楊氏模數約在2〇 GPa左右，通常 依配比不同其範圍介於1〇〜35 GPa，使得該封膠體230與該 晶片220之間相對地變得不可移動。通常該封膠體230之形 成係應在該應力釋放層250形成之後。 該些對外端子240係設置於該基板210之該下表面212, 以供SMT技術接合至一外部印刷電路板（圖未繪出）。在本實 施例中，該些對外端子240係包含銲球。 该應力釋放層250係形成於該基板210與該封膠體230 9 .1290759 之界面’該封膠體230直接結合該基板21〇之面積減少。也 就是說，該封膠體230不再「抓住」該基板21〇，故可使該 些對外端子240相對於該晶片22〇為可移動。通常該應力釋 放層250與該黏晶層224之揚氏模數均小於該封膠體23〇， 例如控制在lOGPa以下。該應力釋放層250與該黏晶層224 係可為相同材質’或為不同材質，例如該應力釋放層250之 材質可為橡膠類或是矽膠類。當該應力釋放層250有外露於 該封膠體230之外侧緣時，應加強該應力釋放層25〇之抗濕 性。較佳地’該應力釋放層250之厚度係不小於該黏晶層224 之厚度’以發揮較佳的應力釋放效果，由該些對外端子24〇 傳導之熱應力將分散與停止在該應力釋放層25〇，不會再傳 導至該晶片220。此外，該應力釋放層25〇可覆蓋於該基板 210之上表面211在封膠前之大部份顯露表面，以使該封膠 體230不直接結合該基板21〇。另，在本實施例中，該應力 釋放層250之形成係在該些銲線260形成之後，該些銲線260 連接該基板210之一端係被該應力釋放層25〇所密封，以避 免銲線260連接於基板210之一端發生斷裂，另該些 銲線260之線部本身具有延展性，亦不會有斷裂問題。 因此’當運用該半導體封裝構造2〇〇，使其表面接合至一 外部印刷電路板之後，由於熱膨脹係數的不匹配（CTE mismatch)，在溫度循環測試與實際運算使用，該些對外 端子24〇可隨著外部印刷電路板之膨脹收縮作適當的移 動’其移動是相對於該晶片220與該封膠體230，熱 應力會通過該些對外端子240並釋放於該應力釋放層 1290759 250。因此，每一單顆之對外端子24〇(特別指在該基板 210之邊緣或角隅處之對外端子24〇)不會承擔到過大 的熱應力’也不會有斷裂的問題，故可以得到較佳等 級的溫度循環測試（TCT)結果。 關於該半導體封裝構造200之一種製程配合第3A與3B 圖說明如後。如第3A圖所示，首先提供一基板210，未切 割之基板210係一體形成於一基板條内；之後，進行黏晶作 業’藉由黏晶層224將複數個晶片220設置於對應基板210 之該上表面2 11 ;接著，以打線技術形成複數個銲線26〇， 以電性連接該晶片220至該基板210。之後，如第3B圖所 示，利用印刷、點塗畫膠、數位噴墨或噴塗等技術將一應力 釋放層250形成於該基板210之該上表面211。最後，請再 參閱第2圖，形成一封膠體23 0於該基板210之上表面211 之上，此時，該應力釋放層250係位於該基板210與該封膠 體230之間的界面。最後，設置複數個對外端子24〇於該基 板2 1 0之該下表面212，藉此使該些對外端子240相對於該 晶片2 2 0為可移動。在基板2 1 0切割之後即可得到前述之半 導體封裝構造200。 本發明於第二具體實施例中揭示另一種半導體封裝構 造。如第4圖所示，該半導體封裝構造300主要包含一 基板310、一晶片320、一封膠體330、複數個對外端子340 以及一應力釋放層350。該基板310係具有一上表面311、 一下表面312以及一槽孔313。該晶片320之一主動面321 係藉由一黏晶層324設置於該基板3 1 0之該上表面3 11，而 .1290759 使該晶片320之銲塾323顯露在該槽孔313内，而該晶片320 之一背面322則遠離該基板3 10。複數個銲線360係通過該 槽孔313並電性連接該晶片320之銲墊323至該基板310。 该封膠體330係至少形成於該基板310之上表面311，更可 形成於該槽孔313内。該些對外端子340係設置於該基板310 之該下表面312。該應力釋放層350係形成於該基板310與 該封膠體330之界面，以使該些對外端子340相對於該晶片 320為可移動。在本實施例中，該應力釋放層35〇更形成於 •該槽孔313内，以使該槽孔313處之該應力釋放層350不直 接接觸至該晶片320之該主動面321。 如第5圖所示，當該半導體封裝構造3〇〇表面接合至 一外部印刷電路板1 〇，受到溫度變化影響，該外部印 刷電路板10會有比該封膠體33 0更大的伸縮現象，導 致該些對外端子340之移動。由於該應力釋放層35〇能在 該封膠體3 3 0與該基板3 10之間達到應力釋放效果，因此， φ 本發明係提供一種已封膠半導體產品之對外端子34〇可相對 於該晶片32〇可移動之解決方素，克服傳統半導體晶只組奋 件（semiconductor chip assemblies)在封膠體形成之後，對外 端子不可移動的問題，以達到較佳等級的溫度循環測試。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，雖然本發明已以較佳實 . 施例揭露如上’然而並非用以限定本發明，任何熟悉 • 本項技術者，在不脫離本發明之技術範圍内，所作的 任何簡單修改、等效性變化與修飾，均仍屬於本發明 12 ,1290759 的技術範圍内。 【圖式簡單說明】 第1圖：習知一種半導體封裝構造之截面示意圖。 第2圖.依據本發明之第一具體實施例，一種半導體封 裝構造之截面示意圖。 第3A與3B圖：依據本發明之第一具體實施例，該半 導體封裝構造在封膠前製程之基板條示意圖。 第4圖·依據本發明之第二具體實施例，一種半導體封 •裝構造之截面示意圖。 第5圖：依據本發明之第二具體實施例，該半導體封裝 構造在使用狀態之截面示意圖。 【主要元件符號說明】 10 外部印刷電路板 100 半導體封裝構造 110 基板 111 上 表 面 112 下表 面 120 晶片 121 黏 晶 層 122 銲墊 130 封膠體 140 對 外 端子 150 輝線 200 半導體封裝構造 210 基板 211 上 表 面 212 下表 面 220 晶片 221 背 面 222 主動 面 223 銲墊 224 黏 晶 層 230 封膠體 240 對外端子 250 應 力 釋放層 260 銲線 300 半導體封|構造 310 基板 311 上 表 面 312 下表 面 13 /1290759The foregoing semiconductor package structure 'where the substrate has a slot, the solder, (four) through (four) slot, is purely connected to the wafer. The semiconductor package structure described in the above, wherein the stress relief layer is formed in the slot. [Embodiment] In the first embodiment of the present invention, the semiconductor package structure 200 mainly includes a substrate 21, a wafer 220, a package of a plurality of external terminals (10), and a stress relief. Layer 250. The substrate 21G is a wafer carrier suitable for a semiconductor package, such as a high-density printed circuit board, a ceramic substrate, a circuit film, and the like. The substrate 210 has an upper surface 211 and a lower surface 212, and has a line structure for electrically transferring the wafer 22G to the pair of (four) sub- 24 ,, which may be a single layer or a plurality of wiring layers, or may include plated through holes, etc. . The wafer 220 is made of a semiconductor material and may include various types of micro-miniature components such as an integrated circuit, a microelectromechanical element, a photovoltaic element, and the like. The wafer 22 is 且- and has an active 222 and a facing back 221, and a plurality of solders (3) can be formed on the active surface 222. Alternatively, the 8.412759 pad 223 can be formed on the back side 221 of the wafer 220 (not shown). A surface (e.g., the back surface 221) of the wafer 220 is disposed on the upper surface 211 of the substrate 210 by a die layer 224. Usually, the material of the adhesive layer 224 is an epoxy or an organic resin, and has no inorganic filler, and the Young's modulus can be lower than that of the sealant 230, and is softer. The wafer 22 can be electrically connected to the substrate 21 by using a plurality of bonding wires 26 〇. In the present embodiment, the package structure 200 is a general wafer-up ball grid array package. One of the wires 260 is connected to the pads 223 of the wafer 220, and the other end is connected to the substrate 210. The inner surface of the upper surface 211 is connected (not shown), and the wire 260 is formed before the stress relief layer 25 and the sealant 230 are formed. The encapsulant 230 is formed on at least the upper surface 211 of the substrate 210 to protect the wafer 220. In the present embodiment, the encapsulant 23 further seals the bonding wires 260. The encapsulant 230 can be formed by stamping or printing, and the material thereof comprises a thermosetting resin, an inorganic filler, a dispersing agent, and a coloring material. After curing, the encapsulant 230 has good electrical insulation and strong structural rigidity. The Young's modulus of the encapsulant 230 after aging is about 2 〇 GPa, and the range is usually between 1 〇 and 35 GPa depending on the ratio, so that the encapsulant 230 and the wafer 220 become relatively incomparable. mobile. Typically, the formation of the encapsulant 230 should be after the stress relief layer 250 is formed. The external terminals 240 are disposed on the lower surface 212 of the substrate 210 for SMT technology to be bonded to an external printed circuit board (not shown). In the present embodiment, the external terminals 240 comprise solder balls. The stress relieving layer 250 is formed at the interface between the substrate 210 and the encapsulant 230 9 . 1290759. The area of the encapsulant 230 directly bonded to the substrate 21 is reduced. That is, the encapsulant 230 no longer "grabs" the substrate 21, so that the external terminals 240 can be moved relative to the wafer 22. Generally, the Young's modulus of the stress release layer 250 and the adhesion layer 224 are both smaller than the sealant 23, for example, controlled below 10 GPa. The stress relief layer 250 and the adhesive layer 224 may be of the same material or different materials. For example, the stress relief layer 250 may be made of rubber or silicone. When the stress relief layer 250 is exposed to the outer edge of the sealant 230, the moisture resistance of the stress relief layer 25 is strengthened. Preferably, the thickness of the stress relief layer 250 is not less than the thickness of the die layer 224 to exert a better stress release effect, and the thermal stress transmitted by the external terminals 24 will be dispersed and stopped at the stress release. Layer 25 is no longer conducted to the wafer 220. In addition, the stress relief layer 25 can cover most of the exposed surface of the upper surface 211 of the substrate 210 before sealing, so that the encapsulant 230 does not directly bond to the substrate 21 . In addition, in this embodiment, the stress relief layer 250 is formed after the bonding wires 260 are formed, and one end of the bonding wires 260 connected to the substrate 210 is sealed by the stress releasing layer 25〇 to avoid soldering. The wire 260 is connected to one end of the substrate 210 to be broken, and the wire portions of the bonding wires 260 are themselves malleable and have no fracture problem. Therefore, when the semiconductor package structure is used and its surface is bonded to an external printed circuit board, the external terminals are used in the temperature cycle test and the actual operation due to the thermal expansion coefficient mismatch (CTE mismatch). The movement can be appropriately moved as the outer printed circuit board expands and contracts. The movement is relative to the wafer 220 and the encapsulant 230, and thermal stress is transmitted through the outer terminals 240 and released to the stress relief layer 1290759 250. Therefore, each of the individual external terminals 24A (especially the external terminal 24〇 at the edge or corner of the substrate 210) does not suffer from excessive thermal stresses, and there is no problem of breakage, so that it can be obtained. A preferred level of temperature cycling test (TCT) results. A description of the process of the semiconductor package structure 200 in conjunction with FIGS. 3A and 3B is as follows. As shown in FIG. 3A, a substrate 210 is first provided. The uncut substrate 210 is integrally formed in a substrate strip. Thereafter, a die bonding operation is performed. 'The plurality of wafers 220 are disposed on the corresponding substrate 210 by the adhesion layer 224. The upper surface 2 11 ; then, a plurality of bonding wires 26 形成 are formed by a wire bonding technique to electrically connect the wafer 220 to the substrate 210 . Thereafter, as shown in Fig. 3B, a stress releasing layer 250 is formed on the upper surface 211 of the substrate 210 by a technique such as printing, dot painting, digital ink jet or spray coating. Finally, please refer to FIG. 2 to form a colloid 230 on the upper surface 211 of the substrate 210. At this time, the stress relief layer 250 is located at the interface between the substrate 210 and the encapsulant 230. Finally, a plurality of external terminals 24 are disposed on the lower surface 212 of the substrate 2 10 , whereby the external terminals 240 are movable relative to the wafer 2 2 0 . The semiconductor package structure 200 described above can be obtained after the substrate 210 is diced. Another semiconductor package construction is disclosed in the second embodiment of the present invention. As shown in FIG. 4, the semiconductor package structure 300 mainly includes a substrate 310, a wafer 320, a gel 330, a plurality of external terminals 340, and a stress relief layer 350. The substrate 310 has an upper surface 311, a lower surface 312, and a slot 313. An active surface 321 of the wafer 320 is disposed on the upper surface 3 11 of the substrate 310 by a die bonding layer 324. The 1290759 exposes the pad 323 of the wafer 320 in the slot 313. One of the back faces 322 of the wafer 320 is remote from the substrate 3 10. A plurality of bonding wires 360 pass through the slots 313 and are electrically connected to the pads 323 of the wafer 320 to the substrate 310. The encapsulant 330 is formed on at least the upper surface 311 of the substrate 310, and is formed in the slot 313. The external terminals 340 are disposed on the lower surface 312 of the substrate 310. The stress relief layer 350 is formed on the interface between the substrate 310 and the encapsulant 330 such that the external terminals 340 are movable relative to the wafer 320. In the present embodiment, the stress relief layer 35 is further formed in the slot 313 such that the stress relief layer 350 at the slot 313 does not directly contact the active surface 321 of the wafer 320. As shown in FIG. 5, when the surface of the semiconductor package structure 3 is bonded to an external printed circuit board 1 , the external printed circuit board 10 has a larger expansion and contraction than the seal body 33 0 due to temperature changes. , causing the movement of the external terminals 340. Since the stress relieving layer 35 can achieve a stress releasing effect between the encapsulant 310 and the substrate 3 10, the present invention provides an external terminal 34 of the encapsulated semiconductor product relative to the wafer. The 32 〇 movable solution overcomes the problem that the semiconductor chips are not movable after the formation of the sealant after the formation of the sealant to achieve a better temperature cycle test. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the present invention has been disclosed in the preferred embodiments. Any simple modifications, equivalent changes and modifications made by those skilled in the art without departing from the technical scope of the present invention are still within the technical scope of the present invention 12, 1290759. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a semiconductor package structure. Fig. 2 is a cross-sectional view showing a semiconductor package structure in accordance with a first embodiment of the present invention. 3A and 3B are views showing a substrate strip of the semiconductor package structure before the sealing process according to the first embodiment of the present invention. Figure 4 is a cross-sectional view showing a semiconductor package structure in accordance with a second embodiment of the present invention. Figure 5 is a cross-sectional view showing the semiconductor package in a state of use in accordance with a second embodiment of the present invention. [Main component symbol description] 10 External printed circuit board 100 Semiconductor package structure 110 Substrate 111 Upper surface 112 Lower surface 120 Wafer 121 Silicone layer 122 Solder pad 130 Sealant 140 External terminal 150 Bright wire 200 Semiconductor package structure 210 Substrate 211 Upper surface 212 Lower surface 220 wafer 221 back surface 222 active surface 223 solder pad 224 adhesive layer 230 encapsulant 240 external terminal 250 stress relief layer 260 bonding wire 300 semiconductor package | construction 310 substrate 311 upper surface 312 lower surface 13 / 1290759
3 1 3槽孔 320晶片 321主動面 322背面 323銲墊 324黏晶層 330封膠體 340對外端子 350應力釋放層 360銲線 143 1 3 slot 320 chip 321 active surface 322 back 323 pad 324 adhesive layer 330 sealant 340 external terminal 350 stress release layer 360 wire 14