CN111490019B - Integrated circuit structure and manufacturing method thereof - Google Patents

Integrated circuit structure and manufacturing method thereof Download PDF

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Publication number
CN111490019B
CN111490019B CN202010332408.4A CN202010332408A CN111490019B CN 111490019 B CN111490019 B CN 111490019B CN 202010332408 A CN202010332408 A CN 202010332408A CN 111490019 B CN111490019 B CN 111490019B
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sealing layer
compressive stress
layer
groove
sealing
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CN111490019A (en
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杨振洲
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TIANJIN HENGLI YUANDA INSTRUMENTS CO.,LTD.
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TIANJIN HENGLI YUANDA INSTRUMENTS CO Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/54—Providing fillings in containers, e.g. gas fillings
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides an integrated circuit structure and a manufacturing method thereof, wherein a first sealing layer is formed in a substrate, a second sealing layer is formed on the substrate, and the first sealing layer and the second sealing layer are both under compressive stress to offset the warping force of the substrate. And the filling ratios of the inorganic fillers of the first sealing layer and the second sealing layer are different, so that the first sealing layer and the second sealing layer have pressure stress difference, the substrate is not warped, and the bonding force of the first sealing layer and the second sealing layer is ensured.

Description

Integrated circuit structure and manufacturing method thereof
Technical Field
The invention relates to the field of integrated circuit packaging test manufacturing, in particular to an integrated circuit structure and a manufacturing method thereof.
Background
The existing embedded semiconductor integrated package structure is often in a form of embedding a chip by forming a groove on a substrate, and in particular, refer to fig. 1. In fig. 1, a substrate 1 is a substrate with a large area, which can integrate a plurality of chips to realize different integrated circuit packaging functions, and in order to embed the chips in the substrate 1, a groove 2 is required to be formed in the center of the chip to place at least one chip. Although the method can save longitudinal space and thin the packaging body, the edge of the substrate 1 is bent towards the opening direction of the groove 2 along with the heating effect in the subsequent packaging process. If a plurality of devices are stacked, the thermal effect experienced is greater, and the bending may be more severe, thereby causing problems such as peeling of the substrate from the encapsulation layer and crack generation of the substrate.
Disclosure of Invention
In order to solve the above problems, the present invention provides an integrated circuit structure, which includes:
a substrate comprising opposing first and second surfaces; the first surface comprises a groove and a plurality of connecting pieces surrounding the groove, and the substrate has stress which enables the edge of the substrate to bend towards the opening direction of the groove;
the first semiconductor chip is arranged in the groove;
the first sealing layer fills the groove and exposes the bonding pad of the first semiconductor chip, and the upper surface of the first sealing layer is flush with the first surface;
a circuit layer formed on the upper surface and the first surface and electrically connecting the bonding pad and the plurality of connectors;
the second semiconductor chip is inversely arranged on the circuit layer;
a second sealing layer sealing the second semiconductor chip and completely covering the upper surface and the first surface;
the first sealing layer has a first compressive stress, the second sealing layer has a second compressive stress, the direction of the first compressive stress faces the side wall of the groove, and the pressure value of the first compressive stress is smaller than that of the second compressive stress.
Wherein the ratio of the pressure value of the first compressive stress to the pressure value of the second compressive stress is 0.3-0.5; wherein the pressure value of the first pressure stress is 0.3-0.7MPa, and the pressure value of the second pressure stress is 1-1.2 MPa.
The first sealing layer and the second sealing layer both comprise an organic plastic package body and an inorganic filler, wherein the weight percentage of the inorganic filler in the second sealing layer is greater than that of the inorganic filler in the first sealing layer.
Wherein the plurality of connection members include a first portion and a second portion communicating with each other, the first portion having a first aperture and being a through hole filled with a conductive material on the first surface, the second portion having a second aperture and being a recess filled with the conductive material on the second surface, wherein the first aperture is smaller than the second aperture.
Wherein the device further comprises other recesses on the second surface, wherein the other recesses are not filled with conductive materials and surround the edge of the second surface.
According to the above package structure, the present invention also provides a method for manufacturing an integrated circuit structure, comprising:
(1) providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
(2) forming a groove on the first surface, and forming a plurality of recesses which are arranged in a ring shape on the edge of the second surface;
(3) fixing a first semiconductor chip in the groove;
(4) filling a first sealing material in the groove, and pre-curing the first sealing material at a first temperature to form a semi-cured first sealing layer;
(5) grinding the first surface to expose a bonding pad of the first semiconductor chip;
(6) forming a plurality of through holes on the first surface, the plurality of through holes communicating with a portion of the plurality of recesses to form a plurality of connection holes;
(7) filling a conductive material in the connecting holes to form a plurality of connecting pieces;
(8) forming a circuit layer on the first surface, wherein the circuit layer is electrically connected with the plurality of connectors and the bonding pads;
(9) a second semiconductor chip is inverted on the circuit layer;
(10) sealing the second semiconductor chip with a second sealing material while allowing the second sealing material to cover the first surface to form a second sealing layer; and simultaneously curing the first sealing layer and the second sealing layer at a second temperature so that the first sealing layer has a first compressive stress, the second sealing layer has a second compressive stress, the direction of the first compressive stress faces the side wall of the groove, and the pressure value of the first compressive stress is smaller than that of the second compressive stress.
And (11) forming a passivation layer on the second surface, patterning to expose the connectors, and then planting and forming solder balls through a reflow soldering process.
Wherein the ratio of the pressure value of the first compressive stress to the pressure value of the second compressive stress is 0.3-0.5; wherein the pressure value of the first pressure stress is 0.3-0.7MPa, and the pressure value of the second pressure stress is 1-1.2 MPa.
The first sealing layer and the second sealing layer both comprise an organic plastic package body and an inorganic filler, wherein the weight percentage of the inorganic filler in the second sealing layer is greater than that of the inorganic filler in the first sealing layer.
Wherein the second temperature is greater than the first temperature; and in the step (10), when the first sealing layer and the second sealing layer are simultaneously cured at the second temperature, the cooling speed is less than or equal to 2 ℃/min.
The main contributions of the present invention with respect to the prior art are the following:
(1) adopting sealing materials with organic fillers with different weight percentages to realize different stress values of the first sealing layer and the second sealing layer;
(2) curing the first sealing layer and the second sealing layer by adopting slow cooling so as to form compressive stress in the first sealing layer and the second sealing layer;
(3) the compressive stress of the first sealing layer and the compressive stress of the second sealing layer are superposed to offset the warping force of the substrate, and the first sealing layer is formed in the substrate (namely in the groove), and the compressive stress of the first sealing layer is applied to the side wall of the groove, so that the stress of the central position of the substrate can be prevented from being too large;
(4) the stress of the first sealing layer and the stress of the second sealing layer are compressive stress, and the difference is not large, so that the overlarge stress at the interface of the first sealing layer and the second sealing layer can be prevented, and the delamination at the interface can be further prevented;
(5) the plurality of recesses formed on the lower surface of the substrate can buffer the edge stress of the substrate to alleviate the stress imbalance problem of the substrate, and meanwhile, the plurality of recess parts serve as connecting pieces, self-alignment can be achieved, and conductive materials can be filled conveniently.
Drawings
FIG. 1 is a cross-sectional view of a prior art embedded substrate;
FIG. 2 is a cross-sectional view of an integrated circuit structure of the present invention;
FIG. 3 is a top view of an integrated circuit structure of the present invention;
fig. 4-15 are flow diagrams illustrating a method of fabricating an integrated circuit structure according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.
Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
An integrated circuit structure and a method of fabricating the same according to the disclosed embodiments of the invention will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2 and 3, the integrated circuit structure of the present invention includes a substrate 10, and the substrate 10 is a silicon substrate, a silicon-on-insulator substrate, or a relatively hard substrate such as a ceramic substrate or a glass substrate. In this embodiment, the substrate 10 is a ceramic substrate, and includes a first surface 11 and a second surface 12 opposite to each other, and the thickness of the substrate 10 is 1-5 mm. The substrate 10 has a stress (already described in the background section and not described in detail here) that causes the edge of the substrate 10 to bend toward the opening of the recess 13.
A groove 13 is disposed at the center of the first surface 11 of the substrate 10, the groove 13 may be rectangular, square, polygonal or circular, and the groove 13 is formed by a grooving process, and has a depth of 500-. The recess 13 may accommodate at least one semiconductor chip, i.e. a first semiconductor chip 14.
There are a plurality of connection members 19 at the periphery of the recess 13, the connection members 19 are of an inverted T-shaped structure including a first portion and a second portion which communicate with each other, the first portion having a first aperture and being a through hole 18 filled with a conductive material on the first surface 11, the second portion having a second aperture and being a recess 17 filled with the conductive material on the second surface, wherein the first aperture is smaller than the second aperture. Referring to fig. 3, the plurality of recesses 17 are only partially filled with the conductive material to form the second portion, and the other recesses 17 are not filled, and are configured to buffer the edge stress of the substrate to alleviate the stress imbalance problem of the substrate.
The first semiconductor chip 14 may be a high-power or heat-generating element, such as a bare chip like an IGBT, a HEMT, a MOSFET, etc., or a packaged chip like a logic chip, a control chip, a transmission gate chip, a rectifier chip, etc., and has a thickness of approximately 200-. The first semiconductor chip 14 may fix the non-active surface to the bottom of the recess 13 by an adhesive layer. The active surface of the first semiconductor chip 14 has a plurality of pads 15.
The groove 13 is filled with a first sealing layer 16, and the upper surface of the first sealing layer 16 is flush with the first surface 11 and exposes the pad 15, which forms a flat surface.
On the first surface 11 there is a wiring layer 20, which wiring layer 20 may be a patterned metal layer, such as a copper layer, an aluminum layer, a silver layer, etc. The circuit layer 20 can be reasonably arranged in a pattern according to actual needs, and the circuit layer 20 at least electrically connects the bonding pad 15 of the first semiconductor chip 14 to the connecting piece 19 so as to realize back extraction.
A second flip-chip semiconductor chip 21 is disposed on the first surface 11, and the second semiconductor chip 21 is flip-chip mounted on the wiring layer 20 through solder balls 22. The second semiconductor chip 21 may be selected from a fingerprint chip, an image sensor chip, a memory chip, etc., and may be one or more, which may be a stacked body or a plurality of chips arranged in a lateral direction.
A second sealing layer 23 is provided on the first surface 11, the second sealing layer 23 sealing the second semiconductor chip 21 and completely covering the first surface 11. The thickness of the second sealant layer 23 is typically greater than the thickness of the first sealant layer 16.
A passivation layer 24 is formed on the second surface and patterned to expose the plurality of connections 19, and a plurality of solder balls 25 electrically connect the plurality of connections 19.
In the present invention, the most important design is that the first sealant 16 has a first compressive stress F1, the second sealant 23 has a second compressive stress F2, the direction of the first compressive stress F1 is toward the side wall of the groove 13, and the pressure value of the first compressive stress F1 is smaller than that of the second compressive stress F2.
Wherein the first sealing layer 16 is formed in the substrate 10 (i.e. in the groove 13), and the first compressive stress F1 is applied to the side wall of the groove, so as to prevent the stress at the center of the substrate 10 from being too large. The pressure value of the first compressive stress F1 may not be too large, preferably is less than that of the second compressive stress F2, which is to prevent F1 from applying a concentrated stress to the substrate 10 in a small area to cause damage to the substrate 10.
Also, the compressive stresses of the first sealing layer 16 and the second sealing layer 23 add up to counteract the warping force of the substrate, as is apparent from fig. 1. The stresses of the first sealing layer 16 and the second sealing layer 23 are compressive stresses, and the difference is not large, and the ratio of the pressure value of the first compressive stress to the pressure value of the second compressive stress is preferably 0.3-0.5; the pressure value of the first pressure stress is 0.3-0.7MPa, the pressure value of the second pressure stress is 1-1.2MPa, and the overlarge stress at the interface of the first sealing layer and the second sealing layer can be prevented, so that the delamination at the interface can be prevented.
In order to realize the first sealing layer 16 having the first compressive stress F1, the second sealing layer 23 having the second compressive stress F2, the first sealing layer 16 and the second sealing layer 23 each include an organic plastic package and an inorganic filler, except for the weight percentage of the inorganic filler. The organic plastic package body is a thermosetting material, such as polymer materials of epoxy resin, polyimide and the like, and the inorganic filler can be one or more of silicon oxide particles, silicon nitride particles, aluminum oxide particles and silicon carbide particles.
The weight percentage of the inorganic filler in the second sealing layer 23 is greater than that of the inorganic filler in the first sealing layer 16, so that the compressive stress of the first sealing layer 16 is less than that of the second sealing layer 23 after the same curing process, which will be described in detail below. The weight percentage of the inorganic filler in the first sealing layer 16 is 1-5%, and the weight percentage of the inorganic filler in the second sealing layer 23 is 7-15%.
In order to obtain the integrated circuit structure, the invention also provides a manufacturing method of the integrated circuit structure, which comprises the following steps: (1) providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
(2) forming a groove on the first surface, and forming a plurality of recesses which are arranged in a ring shape on the edge of the second surface;
(3) fixing a first semiconductor chip in the groove;
(4) filling a first sealing material in the groove, and pre-curing the first sealing material at a first temperature to form a semi-cured first sealing layer;
(5) grinding the first surface to expose a bonding pad of the first semiconductor chip;
(6) forming a plurality of through holes on the first surface, the plurality of through holes communicating with a portion of the plurality of recesses to form a plurality of connection holes;
(7) filling a conductive material in the connecting holes to form a plurality of connecting pieces;
(8) forming a circuit layer on the first surface, wherein the circuit layer is electrically connected with the plurality of connectors and the bonding pads;
(9) a second semiconductor chip is inverted on the circuit layer;
(10) sealing the second semiconductor chip with a second sealing material while allowing the second sealing material to cover the first surface to form a second sealing layer; simultaneously curing the first sealing layer and the second sealing layer at a second temperature so that the first sealing layer has a first compressive stress, the second sealing layer has a second compressive stress, the direction of the first compressive stress faces the side wall of the groove, and the pressure value of the first compressive stress is smaller than that of the second compressive stress;
(11) and forming a passivation layer on the second surface, patterning to expose the connectors, and then planting and forming solder balls through a reflow soldering process.
In particular, referring to fig. 4-15, it includes the following steps:
referring to fig. 4, a substrate 10 is provided, the substrate 10 is a ceramic substrate including a first surface 11 and a second surface 12 opposite to each other, and the thickness of the substrate 10 is 1-5 mm.
Referring to fig. 5, the substrate 10 is etched to form a groove 13 on the first surface 11 and a plurality of recesses 17 on the second surface 12 surrounding the groove 13. Forming the recesses 13 and 17 can be accomplished using conventional wet etching, dry etching, mechanical grooving, laser grooving, and the like. The depth of the groove is 500-.
Referring to fig. 6, a first semiconductor chip 14 is fixed in the recess 13, the active surface of the first semiconductor chip 14 faces upward, and the active surface has a plurality of pads 15. In the present invention, the first semiconductor chip 14 may be fixed by an adhesive layer, and a commonly used adhesive layer may be selected from an adhesive tape, a thermal conductive adhesive, and the like.
Referring to fig. 7, the groove 13 is filled with a first sealing material, and the first sealing material is pre-cured at a temperature of about 50 ℃ to form a semi-cured first sealing layer 16. The pre-cure time is approximately 10 minutes or so, which cures the first seal material, but the stress is not as great as that required by the present invention. Wherein, the weight percentage of the inorganic filler in the first sealing layer 16 is 1-5%.
Referring to fig. 8, by grinding the first surface 11 so that the pads 15 are exposed, a relatively flat surface is obtained.
Referring to fig. 9, a plurality of through holes 18 are formed on the upper surface of the substrate 10, the through holes 18 communicate with the recesses 17 of the portions, and the through holes 18 can be obtained by etching from the recesses 17 of the rear surface to facilitate alignment. The aperture of the through hole 18 is smaller than the aperture of the recess 17.
Referring to fig. 10, a conductive material, such as copper, is filled in the through hole 18 and the partial recess 17 to form a connection member 19, and the connection member 19 has an inverted T shape.
Referring to fig. 11, a wiring layer 20 is formed on the first surface 11, and the wiring layer 20 electrically connects the plurality of connectors 19 and the pads 15. The circuit layer 20 may be formed by patterning after metal tiling by electroless plating or the like, and may be made of copper or the like.
Referring to fig. 12, a second semiconductor chip 21 is flip-chip mounted on the wiring layer 20 through solder balls 22, which is required to undergo a reflow process.
Referring to fig. 13, the second semiconductor chip 21 is sealed with a second sealing material while the second sealing material is caused to cover the first surface to form a second sealing layer 23; wherein, the weight percentage of the inorganic filler of the second sealing layer 23 is 7-15%; and simultaneously curing the first sealant 16 and the second sealant 23 at a temperature of 80 ℃ so that the first sealant 16 has a first compressive stress F1, the second sealant has a second compressive stress F2, the direction of the first compressive stress F1 is towards the side wall of the groove 13, and the pressure value of the first compressive stress F1 is smaller than that of the second compressive stress F2.
The curing process is extremely severe, and the inventors have found that when the cooling curve is extremely gentle, i.e., the cooling rate is relatively slow, the stress value is expressed as compressive stress, and the compressive stress makes the first sealing layer 16 and the second sealing layer 23 sufficiently offset the thermal stress of the substrate 10. In the invention, the semi-finished product is placed in a baking furnace, baked for ten minutes at the temperature of about 80 ℃, and then cooled to normal temperature, wherein the cooling rate of the cooling is less than or equal to 2 ℃/min. When natural cooling is carried out, the cooling speed is high, the compressive stress is extremely small, the compressive stress is moderate and is enough to ensure that the warping force is counteracted at the temperature of less than or equal to 2 ℃/min, so that the pressure value of the first compressive stress F1 is 0.3-0.7MPa, and the pressure value of the second compressive stress F2 is 1-1.2 MPa.
Referring to fig. 14, a passivation layer 24 is formed on the second surface 12. The passivation layer 24 is made of silicon oxide, silicon nitride, or the like, and is formed by CVD or the like.
Referring to fig. 15, the passivation layer 25 is patterned to expose the lower bottom surfaces of the plurality of connection members 19, and then the solder balls 25 are formed by ball-mounting and reflow soldering processes.
The invention adopts the sealing material with organic fillers with different weight percentages to realize different stress values of the first sealing layer and the second sealing layer; curing the first sealing layer and the second sealing layer by adopting slow cooling so as to form compressive stress in the first sealing layer and the second sealing layer; the compressive stress of the first sealing layer and the compressive stress of the second sealing layer are superposed to offset the warping force of the substrate, and the first sealing layer is formed in the substrate (namely in the groove), and the compressive stress of the first sealing layer is applied to the side wall of the groove, so that the stress of the central position of the substrate can be prevented from being too large; the stress of the first sealing layer and the stress of the second sealing layer are compressive stress, and the difference is not large, so that the overlarge stress at the interface of the first sealing layer and the second sealing layer can be prevented, and the delamination at the interface can be further prevented; the plurality of recesses formed on the lower surface of the substrate can buffer the edge stress of the substrate to alleviate the stress imbalance problem of the substrate, and meanwhile, the plurality of recess parts serve as connecting pieces, self-alignment can be achieved, and conductive materials can be filled conveniently.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims (8)

1. An integrated circuit structure, comprising:
a substrate comprising opposing first and second surfaces; the first surface comprises a groove and a plurality of connecting pieces surrounding the groove, and the substrate has stress which enables the edge of the substrate to bend towards the opening direction of the groove;
the first semiconductor chip is arranged in the groove;
the first sealing layer fills the groove and exposes the bonding pad of the first semiconductor chip, and the upper surface of the first sealing layer is flush with the first surface;
a circuit layer formed on the upper surface and the first surface and electrically connecting the bonding pad and the plurality of connectors;
the second semiconductor chip is inversely arranged on the circuit layer;
a second sealing layer sealing the second semiconductor chip and completely covering the upper surface and the first surface;
the first sealing layer is provided with a first compressive stress, the second sealing layer is provided with a second compressive stress, the direction of the first compressive stress faces the side wall of the groove, and the pressure value of the first compressive stress is smaller than that of the second compressive stress; wherein the ratio of the pressure value of the first compressive stress to the pressure value of the second compressive stress is 0.3-0.5; wherein the pressure value of the first pressure stress is 0.3-0.7MPa, and the pressure value of the second pressure stress is 1-1.2 MPa.
2. The integrated circuit structure of claim 1, wherein: the first sealing layer and the second sealing layer both comprise an organic plastic package body and an inorganic filler, wherein the weight percentage of the inorganic filler in the second sealing layer is greater than that of the inorganic filler in the first sealing layer.
3. The integrated circuit structure of claim 1 or 2, wherein: the plurality of connection members include a first portion and a second portion communicating with each other, the first portion having a first aperture and being a through hole filled with a conductive material on the first surface, the second portion having a second aperture and being a recess filled with the conductive material on the second surface, wherein the first aperture is smaller than the second aperture.
4. The integrated circuit structure of claim 3, wherein: further comprising other recesses on the second surface not filled with conductive material, the other recesses surrounding an edge of the second surface.
5. A method of fabricating an integrated circuit structure, comprising:
(1) providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite;
(2) forming a groove on the first surface, and forming a plurality of recesses which are arranged in a ring shape on the edge of the second surface;
(3) fixing a first semiconductor chip in the groove;
(4) filling a first sealing material in the groove, and pre-curing the first sealing material at a first temperature to form a semi-cured first sealing layer;
(5) grinding the first surface to expose a bonding pad of the first semiconductor chip;
(6) forming a plurality of through holes on the first surface, the plurality of through holes communicating with a portion of the plurality of recesses to form a plurality of connection holes;
(7) filling a conductive material in the connecting holes to form a plurality of connecting pieces;
(8) forming a circuit layer on the first surface, wherein the circuit layer is electrically connected with the plurality of connectors and the bonding pads;
(9) a second semiconductor chip is inverted on the circuit layer;
(10) sealing the second semiconductor chip with a second sealing material while allowing the second sealing material to cover the first surface to form a second sealing layer; simultaneously curing the first sealing layer and the second sealing layer at a second temperature so that the first sealing layer has a first compressive stress, the second sealing layer has a second compressive stress, the direction of the first compressive stress faces the side wall of the groove, and the pressure value of the first compressive stress is smaller than that of the second compressive stress; wherein the ratio of the pressure value of the first compressive stress to the pressure value of the second compressive stress is 0.3-0.5; wherein the pressure value of the first pressure stress is 0.3-0.7MPa, and the pressure value of the second pressure stress is 1-1.2 MPa.
6. The method of claim 5, wherein: the method further comprises the step (11) of forming a passivation layer on the second surface, patterning the passivation layer to expose the connectors, and then planting balls and forming solder balls through a reflow soldering process.
7. The method of claim 5, wherein: the first sealing layer and the second sealing layer both comprise an organic plastic package body and an inorganic filler, wherein the weight percentage of the inorganic filler in the second sealing layer is greater than that of the inorganic filler in the first sealing layer.
8. The method of claim 5, wherein: the second temperature is greater than the first temperature; and in the step (10), when the first sealing layer and the second sealing layer are simultaneously cured at the second temperature, the cooling speed is less than or equal to 2 ℃/min.
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