CN101894811A - Quad flat package structure having exposed heat sink, electronic assembly and manufacturing methods thereof - Google Patents
Quad flat package structure having exposed heat sink, electronic assembly and manufacturing methods thereof Download PDFInfo
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- CN101894811A CN101894811A CN2009101634037A CN200910163403A CN101894811A CN 101894811 A CN101894811 A CN 101894811A CN 2009101634037 A CN2009101634037 A CN 2009101634037A CN 200910163403 A CN200910163403 A CN 200910163403A CN 101894811 A CN101894811 A CN 101894811A
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- radiating block
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H01L2924/01029—Copper [Cu]
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- H01L2924/0105—Tin [Sn]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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Abstract
The invention provides a quad flat package structure having exposed heat sink, an electronic assembly and manufacturing methods thereof. The QDP structure includes a leadframe, a chip, a heat sink and a molding compound. The leadframe includes a die pad and multiple leads surrounding the die pad. Each lead comprises an internal lead and an external lead. The chip is disposed on the die pad and electrically connected to the die pad and the leads. The heat sink has a top surface, a bottom surface opposite thereto, and a side surface connected to the top and the bottom surfaces. The die pad is disposed in a central area of the top surface of the heat sink and electrically connected to the heat sink. The molding compound encapsulates the chip, the die pad, an inner lead portion of each lead and heat sink, and exposes the bottom surface of the heat sink and an outer lead portion of each lead.
Description
Technical field
The invention relates to a kind of manufacture of semiconductor and structure thereof, and particularly relevant for a kind of flat-four-side encapsulating structure, electronic assembly and processing procedure with exposed heat.
Background technology
Dwindle the volume of integrated circuit component product, be for a long time one of target on the electronics manufacturing always.Small product size dwindle the reduction that means production cost, also represent the shortening of the transmission path of signal, the advantage of bringing properties of product to improve simultaneously.
Influence one of key factor of integrated circuit component volume, then be the improvement of encapsulation technology.Be the packaged type of wafer carrier (carrier) with lead frame (leadframe) now, be still the technology of quite popularizing with extensive use.Flat-four-side encapsulation (Quad Flat Package; Hereinafter to be referred as: QFP) structure promptly is a common example.
Traditional flat-four-side encapsulating structure mainly comprises a lead frame, a wafer, a radiating block and a packing colloid.A plurality of pins that lead frame comprises a wafer holder and is looped around the wafer holder periphery.Wafer configuration is at the upper surface of wafer holder, and by the pin electric connection of routing joining technique with lead frame.Wafer holder is configured on the radiating block via its lower surface, and the heat energy that the time produced of wafer running can dissipate to the external world via wafer holder and radiating block.Packing colloid coated wire frame, wafer and radiating block make moist to protect said elements to avoid being undermined.
Summary of the invention
The invention provides a kind of flat-four-side encapsulating structure with exposed heat, its wafer can electrically connect with external circuit by the radiating block of wafer holder and below thereof.
The invention provides a kind of flat-four-side encapsulating structure with exposed heat, its insulating barrier covers the surrounding zone and the side of the end face of radiating block, can effectively prevent to form in the packing colloid process, the hydraulic pressure that the pin portion of each pin of surrounding zone top of end face that is positioned at radiating block is applied during because of encapsulating contacts with radiating block, produce short circuit, can keep good process yield.
The invention provides a kind of electronic assembly, it has preferable electrical property efficiency and heat-sinking capability.
The present invention also provides the encapsulation procedure of making aforementioned flat-four-side encapsulating structure with exposed heat and the processing procedure of electronic assembly.
The present invention proposes a kind of flat-four-side encapsulating structure with exposed heat, and it comprises a lead frame, a wafer, a radiating block and a packing colloid.Lead frame comprises a wafer holder and a plurality of pin around wafer holder, and wherein wafer holder has a upper surface and a lower surface with respect to upper surface, and each pin has in one a pin portion and an outer pin portion.Wafer configuration and is electrically connected to wafer holder and these pins of lead frame on the upper surface of wafer holder.Radiating block has an end face, a bottom surface and a side that connects between end face and the bottom surface with respect to end face, and wherein end face has a central area and a surrounding zone around central area.Wafer holder is configured in the central area of the end face of radiating block via its lower surface, and is electrically connected to radiating block.The interior pin position of each pin is above the surrounding zone.The interior pin portion and the radiating block of packing colloid coating wafer, wafer holder, each pin, and expose the outer pin portion of the bottom surface of radiating block and each pin, wherein the bottom surface of radiating block can externally electrically conduct.
In one embodiment of this invention, the above-mentioned flat-four-side encapsulating structure with exposed heat also comprises an insulating barrier, and wherein insulating barrier covers the surrounding zone or the side of the end face of radiating block at least.
In one embodiment of this invention, radiating block has a containing groove, is positioned at central area, and wafer holder is positioned at containing groove.
In one embodiment of this invention, the above-mentioned flat-four-side encapsulating structure with exposed heat also comprises at least one first bonding wire and at least one second bonding wire, wherein first bonding wire electrically connects the interior pin portion and the wafer of pairing pin, and second bonding wire electrically connects wafer and wafer holder.
In one embodiment of this invention, above-mentioned first bonding wire and the material of second bonding wire comprise gold, copper, silver, aluminium or its alloy.
In one embodiment of this invention, the above-mentioned flat-four-side encapsulating structure with exposed heat also comprises at least one the 3rd bonding wire, and wherein the 3rd bonding wire electrically connects the interior pin portion of pairing wafer holder and pin.
In one embodiment of this invention, the material of the 3rd above-mentioned bonding wire comprises gold, copper, silver, aluminium or its alloy.
In one embodiment of this invention, the above-mentioned flat-four-side encapsulating structure with exposed heat comprises that also one attaches layer (wetting layer), is configured in the bottom surface of radiating block, and covers the bottom surface of radiating block.
The present invention also proposes a kind of electronic assembly, and it comprises a flat-four-side encapsulating structure, a circuit board, at least one welding cover layer and a solder layer.The flat-four-side encapsulating structure comprises a lead frame, a wafer, a radiating block and a packing colloid.Lead frame comprises a wafer holder and a plurality of pin around wafer holder, and wherein wafer holder has a upper surface and a lower surface with respect to upper surface, and each pin has in one a pin portion and an outer pin portion.Wafer configuration and is electrically connected to wafer holder and these pins of lead frame on the upper surface of wafer holder.Radiating block has an end face, a bottom surface and a side that connects between end face and the bottom surface with respect to end face, wherein end face has a central area and a surrounding zone around central area, wafer holder is configured in the central area of the end face of radiating block via its lower surface, and being electrically connected to radiating block, the interior pin position of each pin is above the surrounding zone.The interior pin portion and the radiating block of packing colloid coating wafer, wafer holder, each pin, and expose the outer pin portion of the bottom surface of radiating block and each pin, wherein the bottom surface of radiating block can externally electrically conduct.The flat-four-side encapsulating structure is configured on the circuit board, circuit board has a first surface and with respect to a second surface of first surface, wherein first surface is covered with at least one patterned conductive layer and at least one line layer, patterned conductive layer has at least the first connection pad and at least the second connection pad, first connection pad is suitable for electrically connecting mutually with the bottom surface of radiating block, and second connection pad is suitable at least one end electric connection with outer pin portion.Welding cover layer is configured on the patterned conductive layer.At least one opening of welding cover layer is used and is exposed first connection pad and second connection pad.Solder layer is configured between the bottom surface of radiating block of encapsulating structure and the circuit board and between outer pin portion and the circuit board, and electrically connects flat-four-side encapsulating structure and circuit board.
In one embodiment of this invention, above-mentioned flat-four-side encapsulating structure also comprises an insulating barrier, and insulating barrier covers the surrounding zone or the side of the end face of radiating block at least.
In one embodiment of this invention, the flat-four-side encapsulating structure also comprises at least the first bonding wire and second bonding wire, and first bonding wire is electrically connected between the interior pin portion and wafer of pairing pin, and second bonding wire is electrically connected between wafer and the wafer holder.
In one embodiment of this invention, the flat-four-side encapsulating structure also comprises at least the three bonding wire, and the 3rd bonding wire is electrically connected between the interior pin portion of pairing wafer holder and pin.
In one embodiment of this invention, the flat-four-side encapsulating structure comprises that also one attaches layer (Wettinglayer), is configured between the bottom surface and solder layer of radiating block, and covers the bottom surface of radiating block.
The present invention also proposes a kind of flat-four-side encapsulation procedure with exposed heat.At first, provide a radiating block.Radiating block has an end face, a bottom surface and a side that connects between end face and the bottom surface with respect to end face, and wherein end face has a central area and a surrounding zone around central area.Then, engage a lead frame on radiating block, lead frame comprises a wafer holder and a plurality of pin around wafer holder, wherein wafer holder has a upper surface and a lower surface with respect to upper surface, wafer holder is configured in the central area of the end face of radiating block via its lower surface, and be electrically connected to radiating block, and each pin has in one a pin portion and an outer pin portion, and the interior pin position of each pin is above the surrounding zone.Engage a wafer on the upper surface of wafer holder, wherein wafer is electrically connected to wafer holder and these pins of lead frame.Form interior pin portion and the radiating block of a packing colloid with coating wafer, wafer holder, each pin, and expose the outer pin portion of the bottom surface of radiating block and each pin, wherein the bottom surface of radiating block can externally electrically conduct.
In one embodiment of this invention, the above-mentioned flat-four-side encapsulation procedure with exposed heat also comprises formation one insulating barrier on radiating block, and wherein insulating barrier covers the surrounding zone or the side of the end face of radiating block at least.
In one embodiment of this invention, at least one interior pin portion is electrically connected to wafer by the first wire bonds mode, and wafer holder is electrically connected to wafer by the second wire bonds mode.
In one embodiment of this invention, at least one interior pin portion is electrically connected to wafer holder by the 3rd wire bonds mode.
In one embodiment of this invention, form the step of insulating barrier on radiating block, comprising: attach central area or the bottom surface of an adhesive tape at the end face of radiating block.Form surrounding zone or the side of insulating barrier in the mode of electroplating at the end face of radiating block.Remove central area and the bottom surface of adhesive tape to expose radiating block.
In one embodiment of this invention, above-mentioned attaching adhesive tape before on the radiating block, also comprise forming the central area of a containing groove, and wafer holder is positioned at containing groove at radiating block.
In one embodiment of this invention, the above-mentioned flat-four-side encapsulation system with exposed heat comprises that also forming one in the mode of electroplating attaches layer on the bottom surface of radiating block, and covers the bottom surface of radiating block.
The present invention also proposes a kind of electronics assembling processing procedure.At first, provide a flat-four-side encapsulating structure.The flat-four-side encapsulating structure has a wafer, one lead frame, one radiating block and a packing colloid, wherein lead frame has a wafer holder and a plurality of pin around wafer holder, each pin has in one a pin portion and an outer pin portion, radiating block has an end face and a bottom surface with respect to end face, and end face has a central area, packing colloid institute coating wafer, wafer holder, the interior pin portion and the radiating block of each pin, and expose the outer pin portion of the bottom surface of radiating block and each pin, wafer holder is configured in the central area of the end face of radiating block, makes wafer be electrically connected to radiating block via wafer holder.Then, provide a circuit board.Circuit board has a first surface and a relative second surface at first surface, wherein first surface is covered with at least one patterned conductive layer and at least one line layer, patterned conductive layer has first connection pad and second connection pad at least, first connection pad is suitable for electrically connecting mutually with the radiating block bottom surface, and second connection pad is suitable at least one end electric connection with outer pin portion.Engage a welding cover layer on patterned conductive layer, at least one opening of welding cover layer exposes first connection pad and second connection pad.Form a solder layer between the bottom surface of radiating block and circuit board and outside between pin portion and the circuit board, and electrically connect flat-four-side encapsulating structure and circuit board.
In one embodiment of this invention, above-mentioned flat-four-side encapsulating structure also comprises formation one insulating barrier on radiating block, and wherein insulating barrier covers the surrounding zone or the side of the end face of radiating block at least.
In one embodiment of this invention, above-mentioned flat-four-side encapsulating structure comprises that also forming one attaches layer between the bottom surface and solder layer of radiating block.
Based on above-mentioned, because the insulating barrier of encapsulating structure of the present invention covers the surrounding zone or the side of the end face of radiating block at least, therefore in the time of can effectively preventing to carry out manufacture procedure of adhesive, the hydraulic pressure that the pin portion of each pin of surrounding zone top of end face that is positioned at radiating block is applied during because of encapsulating contacts with radiating block, produce short circuit, can keep good process yield.In addition, because insulating barrier does not cover the central area and the bottom surface of the end face of radiating block, therefore be configured in the central area of end face of radiating block and wafer configuration on wafer holder the time when the wafer holder of lead frame, wafer holder can be directly and radiating block electrically connect, and wafer can electrically connect with external circuit by the radiating block of wafer holder and below thereof, and the heat energy that wafer produced can directly not be insulated a layer zone that is covered by radiating block and is passed to the external world apace.So this encapsulating structure has preferable electrical property efficiency and heat-sinking capability.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the generalized section of a kind of encapsulating structure of one embodiment of the invention.
Fig. 2 is the making flow process of a kind of encapsulating structure of one embodiment of the invention.
Fig. 3 A to Fig. 3 C is the generalized section of formation insulating barrier on radiating block of one embodiment of the invention.
Fig. 4 is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.
Fig. 5 is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.
Fig. 6 is the schematic top plan view of the circuit board of Fig. 5.
The main element symbol description:
100a～100c: encapsulating structure 110: lead frame
112: wafer holder 112a: upper surface
112b: lower surface 114: pin
114a: the interior pin 114b of portion: outer pin portion
120: wafer 130a, 130b: radiating block
132: end face 132a: central area
132b: surrounding zone 134: bottom surface
136: side 138: containing groove
140: insulating barrier 150: packing colloid
164: the second bonding wires of 162: the first bonding wires
170: the first adhesion coatings of 166: the three bonding wires
190: adhesive tape 200: circuit board
200a: first surface 200b: second surface
210: solder layer 220: patterned conductive layer
224: the second connection pads of 222: the first connection pads
230: line layer 240: welding cover layer
242: open S 301～S305: step
Embodiment
Fig. 1 is the generalized section of a kind of encapsulating structure of one embodiment of the invention.Please refer to Fig. 1, in the present embodiment, encapsulating structure 100a comprises a lead frame 110, a wafer 120, a radiating block 130a and a packing colloid 150.
In the present embodiment, wafer 120 is to be fixed on the upper surface 112a of wafer holder 112 by one first adhesion coating 170, and wafer 120 is to electrically connect by many pin 114 and the wafer holder 112 with formed first bonding wire 162 of routing joining technique and second bonding wire 164 and lead frame 110.That is to say that first bonding wire 162 is connected between the interior pin 114a of portion and wafer 120 of pairing pin 114, and second bonding wire 164 is connected between wafer 120 and the wafer holder 112.First bonding wire 162 herein and the material of second bonding wire 164 can be gold, copper, silver, aluminium or its alloy.In addition, wafer holder 112 is to electrically connect with the interior pin portion 114a of formed the 3rd bonding wire 166 of routing joining technique with pin 114 by many, and meaning is the interior pin 114a of portion that the 3rd bonding wire 166 is connected pairing wafer holder 112 and pin 114.The material of the 3rd bonding wire 166 herein can be gold, copper, silver, aluminium or its alloy.In addition, the material of first adhesion coating 170 is a conducting resinl, for example is elargol.
What deserves to be mentioned is, present embodiment can be selected by with line connection process the interior pin 114a of portion and the wafer holder 112 of each pin 114 being electrically connected to wafer 120, and the interior pin 114a of portion of each pin 114 is electrically connected to wafer holder 112, that is, form electric connection pin 114 and second bonding wire 164 of first bonding wire 162, electric connection wafer 120 and the wafer holder 112 of wafer 120 and the 3rd bonding wire 166 that electrically connects wafer holder 112 and pin 114 simultaneously.Yet wafer 120 also can electrically connect by the pin 114 and the wafer holder 112 of other modes and lead frame 110, for example be the chip bonding mode, so the present invention does not impose any restrictions for the mode that electrically connects between wafer 120 and the lead frame 110.
Radiating block 130a has an end face 132, a bottom surface 134 and a side 136 that connects between end face 132 and the bottom surface 134 with respect to end face 132, and wherein end face 132 has a central area 132a and a surrounding zone 132b around central area 132a.Wafer holder 112 is configured in the central area 132a of the end face 132 of radiating block 130a via its lower surface 112b, and is electrically connected to radiating block 130a, and wherein the heat energy that is produced during wafer 120 running can dissipate to the external world via wafer holder 112 and radiating block 130a.The interior pin 114a of portion of each pin 114 is positioned at the surrounding zone 132b top of the end face 132 of radiating block 130a.In addition, the material of radiating block 130a can be a metal, for example is copper or aluminium, or the good material of other thermal conductivity.
In the present embodiment, encapsulating structure 100a also can comprise one second adhesion coating 172, wherein second adhesion coating 172 is configured between wafer holder 112 and the radiating block 130a, in order to adherence and the conducting power between increase wafer holder 112 and the radiating block 130a, and the material of second adhesion coating 172 for example adds copper foil for conducting resinl or conducting resinl.In addition, encapsulating structure 100a also can comprise an insulating barrier 140, wherein insulating barrier 140 covers the surrounding zone 132b or the side 136 of the end face 132 of radiating block 130a at least, and in other words, insulating barrier 140 does not cover the central area 132a of end face 132 of radiating block 130a and the bottom surface 134 of radiating block 130a.
The interior pin 114a of portion and the radiating block 130a of packing colloid 150 coating wafers 120, wafer holder 112, each pin 114, and expose the bottom surface 134 of radiating block 130a and the outer pin 114b of portion of each pin 114, the bottom surface 134 of the radiating block 130a that wherein exposes can externally electrically connect, and the bottom surface 134 of radiating block 130a and the lower surface copline of packing colloid 150.Because insulating barrier 140 covers the surrounding zone 132b of the end face 132 of radiating block 130a, that is to say, the surrounding zone 132b of the end face 132 of radiating block 130a is an insulating regions, therefore when carrying out manufacture procedure of adhesive, be positioned at the hydraulic pressure that the 114a of pin portion of each pin 114 of surrounding zone 132b top of the end face 132 of radiating block 130a applied can be because of encapsulating the time and contact the generation short circuit with radiating block 130a.The outer pin 114b of portion of pin 114 can bend downwards and be suitable shape, to be connected with other external circuits.
In addition, bottom surface 134 electrodepositables one of the radiating block 130a that packing colloid 150 is exposed attach layer 180, meaning promptly attaches the bottom surface 134 that layer 180 covers radiating block 130a, except can be in order to the heat-sinking capability that increases radiating block 130a, when encapsulating structure 100a desires with other external circuit electric connection, this attaches layer 180 and also can use as an adhesion coating, to increase the adhesive force between encapsulating structure 100a and the external circuit.In the present embodiment, attaching layer 180 material for example is tin or ashbury metal.
In detail, because the insulating barrier 140 of present embodiment does not cover the central area 132a and the bottom surface 134 of the end face 132 of radiating block 130a, therefore the central area 132a and the bottom surface 134 of the end face 132 of radiating block 130a have preferable conduction and heat sinking function, so wafer holder 112 directly with the central area 132a electric connection of the end face 132 of radiating block 130a, and wafer 120 can electrically connect with external circuit by the radiating block 130a of wafer holder 112 and below thereof, and the heat energy that wafer 120 is produced also can directly be passed to the external world by radiating block 130a apace.By radiating block 130a, the encapsulating structure 100a of present embodiment can keep outside the normal operation of wafer 120 except having good heat-sinking capability, also has preferable electrical property efficiency.
Fig. 2 is the making flow process of a kind of encapsulating structure of one embodiment of the invention, and the making flow process of aforementioned encapsulating structure 100a promptly further is shown.Please also refer to Fig. 1 and Fig. 2, at first, shown in step S301, radiating block 130a is provided, radiating block 130a carry as described above have end face 132, with respect to the bottom surface 134 of end face 132 and connect side 136 between end face 132 and the bottom surface 134, and end face 132 has central area 132a and around the surrounding zone 132b of central area 132a, wherein the material of radiating block 130a comprises copper or aluminium.
Then, shown in step S302, can form insulating barrier 140 on radiating block 130a, wherein insulating barrier 140 covers the surrounding zone 132b and the side 136 of the end face 132 of radiating block 130a at least.Specifically, form the step of insulating barrier 140 on radiating block 130a, at first, as shown in Figure 3A, attach central area 132a and the bottom surface 134 of an adhesive tape 190 at the end face 132 of radiating block 130a.Then, shown in Fig. 3 B, form surrounding zone 132b and the side 136 of insulating barrier 140 at the end face 132 of radiating block 130a in the mode of electroplating, meaning is surrounding zone 132b and the side 136 that insulating barrier 140 coats the end face 132 of radiating block 130a.At last, shown in Fig. 3 C, remove adhesive tape 190, with central area 132a and the bottom surface 134 that exposes radiating block 130a.
In order to increase the radiating effect of radiating block 130a, the bottom surface 134 of the radiating block 130a that can be exposed at insulating barrier 140 forms in the mode of electroplating and attaches layer 180, wherein this attaches the bottom surface 134 that layer 180 covers radiating block 130a, and this material that attaches layer 180 for example is tin or ashbury metal.What this must illustrate be, this attaches layer 180 except can be in order to the heat-sinking capability that increases radiating block 130a, when encapsulating structure 100a desires with other external circuit electric connection, this attaches layer 180 and also can use as an adhesion coating, in order to increase the adhesive force between encapsulating structure 100a and the external circuit.
Then, shown in step S303, wire bonds frame 110 is on radiating block 130a.Lead frame 110 institute's bag is as described above drawn together wafer holder 112 and a plurality of pin 114 around wafer holder 112, wherein wafer holder 112 is configured in the central area 132a of the end face 132 of radiating block 130a via its lower surface 112b, and be electrically connected to radiating block 130a, and each pin 114 has interior pin 114a of portion and the outer pin 114b of portion, and the interior pin 114a of portion of each pin 114 is positioned at surrounding zone 132b top.
In order to increase the adherence conducting power between wafer holder 112 and the radiating block 130a, also can be before radiating block 130a at wire bonds frame 110, form second adhesion coating 172 on radiating block 130a, wafer holder 112 can be fixed on the radiating block 130a by second adhesion coating 172, and wherein the material of second adhesion coating 172 for example adds copper foil for conducting resinl or conducting resinl.
Then, form first adhesion coating 170 on the upper surface 112a of wafer holder 112, wherein the material of first adhesion coating 170 comprises conducting resinl, then, shown in step S304, joint wafer 120 makes wafer 120 be fixed on the wafer holder 112 by first adhesion coating 170 on the upper surface 112a of wafer holder 112.Then, carry out line connection process, to form first bonding wire 162, second bonding wire 164 and the 3rd bonding wire 166, wherein first bonding wire 162 is in order between the interior pin 114a of portion and wafer 120 that are connected pairing pin 114, second bonding wire 164 is in order to being connected between wafer 120 and the wafer holder 112, and the 3rd bonding wire 166 is in order between the interior pin 114a of portion and wafer holder 112 that connect pairing pin 114.Wafer 120 is electrically connected to the pin 114 and wafer holder 112 of lead frame 110 by first bonding wire 162 and second bonding wire 164.In the present embodiment, the material of first bonding wire 162, second bonding wire 164 and the 3rd bonding wire 166 can comprise gold, copper, silver, aluminium or its alloy.
At last, shown in step S305, carry out sealing action (molding), to form the interior pin 114a of portion and the radiating block 130a of packing colloid 150 coating wafers 120, wafer holder 112, each pin 114, and expose the bottom surface 134 of radiating block 130a and the outer pin 114b of portion of each pin 114, wherein the bottom surface 134 of radiating block 130a forms copline with the lower surface of packing colloid 150.In the present embodiment, because insulating barrier 140 covers the surrounding zone 132b of the end face 132 of radiating block 130a, that is to say, the surrounding zone 132b of the end face 132 of radiating block 130a is an insulating regions, therefore when carrying out manufacture procedure of adhesive, be positioned at the hydraulic pressure that the 114a of pin portion of each pin 114 of surrounding zone 132b top of the end face 132 of radiating block 130a applied can be because of encapsulating the time and contact the generation short circuit with radiating block 130a, in other words, the encapsulation procedure of present embodiment has good process yield.So far, finished the making of encapsulating structure 100a.
Certainly, Fig. 3 A to Fig. 3 C is the generalized section of formation insulating barrier on radiating block of one embodiment of the invention, and promptly the processing procedure that illustrated of Fig. 2 and Fig. 3 A to 3C only is to illustrate as an example, and part steps is a technology common in the present encapsulation procedure.Those skilled in the art, gives unnecessary details to meet process requirement when can or increasing possible step according to actual state adjustment, omission herein no longer one by one.
Fig. 4 is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Present embodiment is continued to use the element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has omitted the explanation of constructed content.Explanation about clipped can be with reference to previous embodiment, and present embodiment no longer repeats to give unnecessary details.
Please refer to Fig. 4, the main difference of the encapsulating structure 100b of present embodiment and the encapsulating structure 100a of previous embodiment is to be: radiating block 130b has a containing groove 138.This containing groove 138 is positioned at the central area 132a of end face 132, and wafer holder 112 is positioned at containing groove 138.Because radiating block 130b has containing groove 138, therefore except the position that can limit wafer holder 112, can also avoid producing the phenomenon of peeling off (delamination) between wafer holder 112 and the radiating block 130b.
On processing procedure, the encapsulating structure 100b of present embodiment can adopt the production method roughly the same with the encapsulating structure 100a of previous embodiment, and before step S302, promptly formed insulating barrier 140 before radiating block 130b, form the central area 132a of a containing groove 138 at end face 132, then, carry out step S303～S305 in regular turn, can roughly finish the making of encapsulating structure 100b.
Fig. 5 is the generalized section of a kind of encapsulating structure of another embodiment of the present invention.Present embodiment is continued to use the element numbers and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate element, and has omitted the explanation of constructed content.Explanation about clipped can be with reference to previous embodiment, and present embodiment no longer repeats to give unnecessary details.
Please refer to Fig. 5, the main difference of the encapsulating structure 100c of present embodiment and the encapsulating structure 100a of previous embodiment is to be: encapsulating structure 100c (being electronic assembly) also comprises a circuit board 200, one solder layer 210 and a welding cover layer (not illustrating), wherein solder layer 210 is configured between the bottom surface 134 of radiating block 130a and the circuit board 200 and between outer pin 114b of portion and the circuit board 200, make radiating block 130a and wafer holder 112 be electrically connected to circuit board 200, and the outer pin 114b of portion of each pin 114 also is electrically connected to circuit board 200 via solder layer 210 via solder layer 210.The material of solder layer 210 comprises tin or leypewter.
Specifically, Fig. 6 is the schematic top plan view of the circuit board of Fig. 5, please also refer to Fig. 5 and Fig. 6, in the present embodiment, circuit board 200 comprises a first surface 200a and with respect to the second surface 200b of first surface 200a, wherein first surface 200a is covered with at least one patterned conductive layer 220 and at least one line layer 230.Patterned conductive layer 220 has first connection pad 222 and second connection pad 224 at least, and wherein first connection pad 222 is suitable for electrically connecting mutually with the bottom surface 134 of radiating block 130a, and second connection pad 224 is suitable for electrically connecting with at least one end of the outer pin 114b of portion.Welding cover layer 240 is configured on the patterned conductive layer 220, and welding cover layer 240 at least one openings 242 are used and exposed first connection pad 222 and second connection pad 224.In addition, first connection pad 222 is a power supply connection pad or a ground connection connection pad, and second connection pad 224 is a signal bonding pad or a ground connection connection pad.
Because the 130a of radiating block is not insulated layer 140 bottom surfaces that covered, 134 covering and attaches layer 180, therefore when radiating block 130a and wafer holder 112 are electrically connected to circuit board 200 via solder layer 210, attaching layer 180 can use as an adhesion coating, in order to increase the adhesive force between radiating block 130a and the solder layer 210.In addition, radiating block 130a and wafer holder 112 are a power end (not illustrating) or the earth terminals (not illustrating) that are electrically connected to circuit board 200.
In addition, in the embodiment that other do not illustrate, the also optional mentioned radiating block 130b of embodiment as described above that is used in containing groove 138, those skilled in the art works as can be with reference to the explanation of previous embodiment, according to actual demand, and select aforementioned components for use, to reach required technique effect.
On processing procedure, the encapsulating structure 100c of present embodiment can adopt the production method roughly the same with the encapsulating structure 100a of previous embodiment, and after step S305, promptly form after the packing colloid 150, circuit board 200 is provided, and wherein the outer pin 114b of portion of each pin 114 and circuit board 200 electrically connect, then, engage welding cover layer 240 on patterned conductive layer 220, and the opening 242 of welding cover layer 240 exposes outside first connection pad 222 and second connection pad 224.At last, form solder layer 210 between the bottom surface 134 and circuit board 200 of radiating block 130a, make radiating block 130a and wafer holder 112 be electrically connected to circuit board 200, and can roughly finish the processing procedure of encapsulating structure 100c (being electronic assembly) via solder layer 210.
In sum, because the insulating barrier of encapsulating structure of the present invention covers the surrounding zone and the side of the end face of radiating block, therefore in the time of can effectively preventing to carry out manufacture procedure of adhesive, the hydraulic pressure that the pin portion of each pin of surrounding zone top of end face that is positioned at radiating block is applied during because of encapsulating contacts with radiating block, produce short circuit, can keep good process yield.In addition, because the insulating barrier of encapsulating structure of the present invention does not cover the central area and the bottom surface of the end face of radiating block, therefore be configured in the central area of end face of radiating block and wafer configuration on wafer holder the time when the wafer holder of lead frame, wafer can electrically connect with external circuit by the radiating block of wafer holder and below thereof, and the heat energy that wafer produced can directly not be insulated a layer zone that is covered by radiating block and is passed to the external world apace.So encapsulating structure of the present invention has preferable electrical property efficiency and heat-sinking capability.In addition, radiating block also can have containing groove, except the position that can limit wafer holder, can also avoid producing between wafer holder and the radiating block phenomenon of peeling off.
It should be noted that at last: above embodiment is only in order to technical scheme of the present invention to be described but not limit it, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, and these modifications or be equal to replacement and also can not make amended technical scheme break away from the spirit and scope of technical solution of the present invention.
Claims (23)
1. flat-four-side encapsulating structure with exposed heat comprises:
One lead frame comprises a wafer holder and a plurality of pin around described wafer holder, and wherein said wafer holder has a upper surface and a lower surface with respect to described upper surface, and each pin has in one a pin portion and an outer pin portion;
One wafer is configured on the described upper surface of described wafer holder, and is electrically connected to described wafer holder and a plurality of pin of described lead frame;
One radiating block, have an end face, a bottom surface and a side that connects between described end face and the described bottom surface with respect to described end face, wherein said end face has the surrounding zone in a central area and a surrounding said central district, described wafer holder is configured in the described central area of the described end face of described radiating block via its lower surface, and being electrically connected to described radiating block, the described interior pin portion of each pin is positioned at top, described surrounding zone; And
One packing colloid, coat the described interior pin portion and the described radiating block of described wafer, described wafer holder, each pin, and expose the described outer pin portion of the described bottom surface of described radiating block and each pin, the described bottom surface of wherein said radiating block externally electrically conducts.
2. the flat-four-side encapsulating structure with exposed heat according to claim 1 also comprises an insulating barrier, and wherein said insulating barrier covers the described surrounding zone or the described side of the described end face of described radiating block at least.
3. the flat-four-side encapsulating structure with exposed heat according to claim 1, wherein said radiating block has a containing groove, be positioned at described central area, and described wafer holder is positioned at described containing groove.
4. the flat-four-side encapsulating structure with exposed heat according to claim 1, also comprise at least one first bonding wire and at least one second bonding wire, wherein said first bonding wire electrically connects the described interior pin portion and the described wafer of pairing described pin, and described second bonding wire electrically connects described wafer and described wafer holder.
5. the flat-four-side encapsulating structure with exposed heat according to claim 4, the material of wherein said first bonding wire and described second bonding wire comprises gold, copper, silver, aluminium or its alloy.
6. the flat-four-side encapsulating structure with exposed heat according to claim 1 also comprises at least one the 3rd bonding wire, and wherein said the 3rd bonding wire electrically connects the described interior pin portion of pairing described wafer holder and described pin.
7. the flat-four-side encapsulating structure with exposed heat according to claim 6, the material of wherein said the 3rd bonding wire comprises gold, copper, silver, aluminium or its alloy.
8. the flat-four-side encapsulating structure with exposed heat according to claim 1 comprises that also one attaches layer, is configured in the described bottom surface of described radiating block, and covers the described bottom surface of described radiating block.
9. electronic assembly comprises:
One flat-four-side encapsulating structure comprises:
One lead frame comprises a wafer holder and a plurality of pin around described wafer holder, and wherein said wafer holder has a upper surface and a lower surface with respect to described upper surface, and each pin has in one a pin portion and an outer pin portion;
One wafer is configured on the described upper surface of described wafer holder, and is electrically connected to described wafer holder and described a plurality of pin of described lead frame;
One radiating block, have an end face, a bottom surface and a side that connects between described end face and the described bottom surface with respect to described end face, wherein said end face has the surrounding zone in a central area and a surrounding said central district, described wafer holder is configured in the described central area of the described end face of described radiating block via its lower surface, and being electrically connected to described radiating block, the described interior pin portion of each pin is positioned at top, described surrounding zone;
One packing colloid, coat the described interior pin portion and the described radiating block of described wafer, described wafer holder, each pin, and expose the described outer pin portion of the described bottom surface of described radiating block and each pin, the described bottom surface of wherein said radiating block externally electrically conducts;
One circuit board, described flat-four-side encapsulating structure is configured on the described circuit board, described circuit board has a first surface and with respect to a second surface of described first surface, wherein said first surface is covered with at least one patterned conductive layer and at least one line layer, described patterned conductive layer has at least the first connection pad and at least the second connection pad, described first connection pad is suitable for electrically connecting mutually with the described bottom surface of described radiating block, and described second connection pad is suitable for electrically connecting with at least one end of described outer pin portion;
At least one welding cover layer is configured on the described patterned conductive layer, and at least one opening of described welding cover layer is to expose described first connection pad and described second connection pad; And
One solder layer is configured between the described bottom surface of described radiating block of described encapsulating structure and the described circuit board and between described outer pin portion and the described circuit board, and electrically connects described encapsulating structure and described circuit board.
10. electronic assembly according to claim 9, wherein said flat-four-side encapsulating structure also comprises an insulating barrier, described insulating barrier covers the described surrounding zone or the described side of the described end face of described radiating block at least.
11. electronic assembly according to claim 9, wherein said flat-four-side encapsulating structure also comprises at least the first bonding wire and second bonding wire, described first bonding wire is electrically connected between the described interior pin portion and described wafer of pairing described pin, and described second bonding wire is electrically connected between described wafer and the described wafer holder.
12. electronic assembly according to claim 9, wherein said flat-four-side encapsulating structure also comprises at least the three bonding wire, and described the 3rd bonding wire is electrically connected between the described interior pin portion of pairing described wafer holder and described pin.
13. electronic assembly according to claim 9, wherein said flat-four-side encapsulating structure comprises that also one attaches layer, is configured between described radiating block bottom surface and the described solder layer, and covers the described bottom surface of described radiating block.
14. the flat-four-side encapsulation procedure with exposed heat comprises:
One radiating block is provided, and described radiating block has an end face, a bottom surface and a side that connects between described end face and the described bottom surface with respect to described end face, and wherein said end face has the surrounding zone in a central area and a surrounding said central district;
Engage a lead frame on described radiating block, described lead frame comprises a wafer holder and a plurality of pin around described wafer holder, wherein said wafer holder has a upper surface and a lower surface with respect to described upper surface, described wafer holder is configured in the described central area of the described end face of described radiating block via its lower surface, and be electrically connected to described radiating block, and each pin has in one a pin portion and an outer pin portion, and pin portion is positioned at above the described surrounding zone in each pin described;
Engage a wafer on the described upper surface of described wafer holder, wherein said wafer is electrically connected to described wafer holder and a plurality of pin of described lead frame; And
Form a packing colloid, to coat the described interior pin portion and the described radiating block of described wafer, described wafer holder, each pin, and expose the described outer pin portion of the described bottom surface of described radiating block and each pin, the described bottom surface of wherein said radiating block can externally electrically conduct.
15. the flat-four-side encapsulation procedure with exposed heat according to claim 14 comprises also forming an insulating barrier on described radiating block that wherein said insulating barrier covers the described surrounding zone or the described side of the described end face of described radiating block at least.
16. the flat-four-side encapsulation procedure with exposed heat according to claim 14, wherein at least one described interior pin portion is electrically connected to described wafer by the first wire bonds mode, and described wafer holder is electrically connected to described wafer by the second wire bonds mode.
17. the flat-four-side encapsulation procedure with exposed heat according to claim 14, wherein at least one described interior pin portion is electrically connected to described wafer holder by the 3rd wire bonds mode.
18. the flat-four-side encapsulation procedure with exposed heat according to claim 15 wherein forms the step of described insulating barrier on described radiating block, comprising:
Attach described central area or the described bottom surface of an adhesive tape at the described end face of described radiating block;
Form described surrounding zone or the described side of described insulating barrier in the mode of electroplating at the described end face of described radiating block; And
Remove described adhesive tape, with described central area and the described bottom surface that exposes described radiating block.
19. the flat-four-side encapsulation procedure with exposed heat according to claim 18, also be included in and attach described adhesive tape before on the described radiating block, form the described central area of a containing groove, and described wafer holder is positioned at described containing groove at described radiating block.
20. the flat-four-side encapsulation procedure with exposed heat according to claim 14 comprises that also forming one in the mode of electroplating attaches layer on the described bottom surface of described radiating block, and covers the described bottom surface of described radiating block.
21. an electronics assembling processing procedure comprises:
One flat-four-side encapsulating structure is provided, described encapsulating structure has a wafer, one lead frame, one radiating block and a packing colloid, wherein said lead frame has a wafer holder and a plurality of pin around described wafer holder, each pin has in one a pin portion and an outer pin portion, described radiating block has an end face and a bottom surface with respect to described end face, and described end face has a central area, described packing colloid coats described wafer, the described interior pin portion and the described radiating block of described each pin of wafer holder, and expose the described outer pin portion of the bottom surface of described radiating block and each pin, described wafer holder is configured in the described central area of the described end face of described radiating block, makes described wafer be electrically connected to described radiating block via described wafer holder;
One circuit board is provided, described circuit board has a first surface and with respect to a second surface of described first surface, wherein said first surface is covered with at least one patterned conductive layer and at least one line layer, described patterned conductive layer has at least one first connection pad and at least one second connection pad, described first connection pad is suitable for electrically connecting mutually with the described bottom surface of described radiating block, and described second connection pad is suitable for electrically connecting with at least one end of described outer pin portion;
Engage a welding cover layer on described patterned conductive layer, at least one opening of described welding cover layer exposes described first connection pad and described second connection pad; And
Form a solder layer between the described bottom surface of described radiating block and described circuit board and outside described between pin portion and the described circuit board, and electrically connect described flat-four-side encapsulating structure and described circuit board.
22. electronics assembling processing procedure according to claim 21, wherein said flat-four-side encapsulating structure, also comprise forming an insulating barrier on described radiating block, wherein said insulating barrier covers the described surrounding zone or the described side of the described end face of described radiating block at least.
23. electronics assembling processing procedure according to claim 21, wherein said flat-four-side encapsulating structure comprise that also forming one attaches layer between the described bottom surface and described solder layer of described radiating block.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US18043409P | 2009-05-22 | 2009-05-22 | |
| US61/180,434 | 2009-05-22 |
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| CN101894811A true CN101894811A (en) | 2010-11-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101634037A Pending CN101894811A (en) | 2009-05-22 | 2009-08-17 | Quad flat package structure having exposed heat sink, electronic assembly and manufacturing methods thereof |
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| Country | Link |
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| CN (1) | CN101894811A (en) |
| TW (1) | TW201042734A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315135A (en) * | 2010-07-09 | 2012-01-11 | 联咏科技股份有限公司 | Chip package and manufacturing process thereof |
| CN114449739A (en) * | 2022-01-27 | 2022-05-06 | 华为数字能源技术有限公司 | Packaging module, preparation method thereof and electronic equipment |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI715234B (en) | 2019-10-04 | 2021-01-01 | 瑞昱半導體股份有限公司 | Chip package module |
-
2009
- 2009-06-30 TW TW098122148A patent/TW201042734A/en unknown
- 2009-08-17 CN CN2009101634037A patent/CN101894811A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102315135A (en) * | 2010-07-09 | 2012-01-11 | 联咏科技股份有限公司 | Chip package and manufacturing process thereof |
| CN102315135B (en) * | 2010-07-09 | 2014-08-20 | 联咏科技股份有限公司 | Chip package and manufacturing process thereof |
| CN114449739A (en) * | 2022-01-27 | 2022-05-06 | 华为数字能源技术有限公司 | Packaging module, preparation method thereof and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201042734A (en) | 2010-12-01 |
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Application publication date: 20101124 |