CN103219324A - Stackable semiconductor chip packaging structure and process thereof - Google Patents

Stackable semiconductor chip packaging structure and process thereof Download PDF

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Publication number
CN103219324A
CN103219324A CN2012100160177A CN201210016017A CN103219324A CN 103219324 A CN103219324 A CN 103219324A CN 2012100160177 A CN2012100160177 A CN 2012100160177A CN 201210016017 A CN201210016017 A CN 201210016017A CN 103219324 A CN103219324 A CN 103219324A
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China
Prior art keywords
top layer
packaging
base plate
encapsulation
semiconductor chip
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CN2012100160177A
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Chinese (zh)
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刘胜
陈润
陈照辉
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刘胜
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Priority to CN2012100160177A priority Critical patent/CN103219324A/en
Priority to PCT/CN2012/000612 priority patent/WO2013106973A1/en
Publication of CN103219324A publication Critical patent/CN103219324A/en
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a stackable semiconductor chip packaging structure and a process of the stackable semiconductor chip packaging structure. The packaging structure comprises a top layer package and a bottom layer package, a groove is formed in a bottom layer package substrate, a semiconductor chip of the bottom layer package is arranged in the groove, a pad is arranged on the substrate, the bottom layer semiconductor chip is connected with the pad through a bond lead wire, the top layer package is packaged on the upper surface of a top layer package substrate by one or a plurality of semiconductor chips in a stacked mode, a pad is arranged on the top layer package substrate, the semiconductor chips are connected with the pad through the bond lead wires, the top layer package portion is sealed through sealants, a solder ball array is connected between the top layer package and the bottom layer package through the pads, and sealants are filled between the top layer package substrate and the bottom layer package substrate. The packaging structure process includes a step of top layer packaging, a step of bottom layer packaging, and a step of connection between the top layer package and the bottom layer package. The stackable semiconductor chip packaging structure and the process of the stackable semiconductor chip packaging structure have the advantages of being capable of effectively improving packaging intensity, simple in process procedure, high in substrate rigidity, not prone to warp, low in overall thickness, and high in reliability.

Description

Stacked semiconductor chip encapsulating structure and technology
Technical field
The present invention relates to a kind of semiconductor packaging, particularly a kind of stacked semiconductor chip encapsulating structure and technology.
Background technology
Because people are urgent day by day for the demand of miniaturization of electronic products, lightness, three-dimension packaging has been complied with this trend, and the three-dimensional electronic encapsulation technology has obtained the development of advancing by leaps and bounds recently.Encapsulating stacked (package on package) technology is a kind of three-dimension packaging solution with low cost, it can be incorporated into logic chip and storage chip in the packaging body, and control storage capacity flexibly as required, therefore, in electronic products such as mobile phone, obtained at present using widely.The base plate for packaging that traditional PoP encapsulation is adopted is thinner, and in technological process, the basal plate heated expansion produces warpage, has caused interconnection difficulty between bottom and the top layer packaging body, produces fatigue easily in conjunction with soldered ball, and crackle etc. cause reliability of products to reduce.
Summary of the invention
The objective of the invention is at the defective that exists in the prior art, a kind of stacked semiconductor chip encapsulating structure and technology are provided.The present invention includes the top layer encapsulation, the bottom encapsulation, welded ball array between top layer encapsulation and the bottom encapsulation, sealant between top layer encapsulation and the bottom encapsulation, it is characterized in that described bottom base plate for packaging is provided with an inverted trapezoidal groove, the upper surface of bottom base plate for packaging is a first surface, the lower surface of bottom base plate for packaging is a second surface, surface in the bottom base plate for packaging groove is the 3rd surface, the semiconductor chip of bottom encapsulation is arranged in the groove, first, second, be equipped with pad on the 3rd surface, the bottom semiconductor chip links to each other with the 3rd lip-deep pad by bonding wire, top layer encapsulation by one or several semiconductor chip laminate packaging on the upper surface of top layer base plate for packaging, the upper surface and the lower surface of top layer base plate for packaging are equipped with pad, semiconductor chip in the top layer encapsulation links to each other by the pad of bonding wire with top layer base plate for packaging upper surface, the top layer packed part seals through sealant, be connected with welded ball array by pad between top layer encapsulation and the bottom encapsulation, filling sealing agent between top layer base plate for packaging and the bottom base plate for packaging is referring to Fig. 2.
The present invention's bottom base plate for packaging is provided with groove, and the bottom packaged chip is fixed on bottom portion of groove, therefore can not cause the packaging body integral thickness to increase.Therefore this encapsulating structure has thin thickness, the advantage that reliability is high, as shown in Figure 1.The base plate for packaging that the bottom encapsulation is adopted is big than conventional base plate for packaging thickness, so the rigidity of substrate can be bigger, is difficult for producing warpage.
Fig. 1 is traditional PoP encapsulation cross sectional representation, and comparison diagram 1 can find that the essential difference of the two is that the substrate of patent bottom encapsulation of the present invention is provided with groove.Traditional PoP packaging bottom layer substrate is thinner, but the bottom packaged chip directly is bonded on the upper surface of bottom base plate for packaging, and the thickness t 1 that this bottom that causes the integral thickness t2 of conventional P oP packaging bottom layer encapsulation to provide unlike present embodiment encapsulates is thin.And because conventional package bottom base plate for packaging is thin, in the packaging technology flow process, more be easy to generate warpage, cause combination difficulty between glob top and the bottom package body, this will certainly produce problems such as fatigue failure, fracture in soldered ball, reduced the reliability of encapsulating products.
Groove on the described bottom base plate for packaging is for trapezoidal, and the semiconductor chip of bottom encapsulation is bonded in bottom portion of groove by Heraeus, perhaps is welded on bottom portion of groove with face-down bonding technique, and semiconductor chip is connected with the bottom portion of groove soldered ball.Be provided with the circuit that is connected usefulness in bottom base plate for packaging and the top layer base plate for packaging.The second surface of bottom base plate for packaging is provided with welded ball array, and welded ball array is that the mode of silk screen printing or plating or evaporation is coated with scolder, refluxes to produce welded ball array, and its material is SnAg, Sn, SnAgCu, PbSn.
The semiconductor chip of described top layer encapsulation is the stacked in layers structure, and the semiconductor chip of top layer encapsulation and bonding wire adopt the sealant sealing, and sealant is an epoxy molding plastic.Between top layer encapsulation and the bottom encapsulation is individual layer or double-deck welded ball array, by reflux technique top layer encapsulation and bottom encapsulation are linked together, perhaps deposit solder layer after the lower surface pad of top layer base plate for packaging powers on copper plated pillars, deposit solder layer after the first surface pad of bottom base plate for packaging powers on copper plated pillars, the material of solder layer can be SnAg, Sn, SnAgCu, PbSn, by reflux technique top layer base plate for packaging and bottom base plate for packaging are linked together, finish the electrical interconnection between top layer packaging body and the bottom packaging body.
The technology of stacked semiconductor chip encapsulating structure is characterized in that comprising successively following steps:
A. preparation has the bottom base plate for packaging of groove;
B. on three surfaces of bottom base plate for packaging, prepare pad;
C. the semiconductor chip that bottom is encapsulated is installed in the groove and finishes the lead-in wire bonding;
D. on the upper and lower surface of top layer base plate for packaging, prepare pad;
E. with stacked being installed on the top layer base plate for packaging of semiconductor chip of top layer encapsulation;
F. carry out the lead-in wire bonding of the stacked semiconductor chip of top layer encapsulation;
G. carry out the top layer sealed package;
H. on the pad of top layer base plate for packaging lower surface, plant soldered ball, carry out the connection between top layer encapsulation and the bottom encapsulation;
I. carry out the filling sealing between top layer encapsulation and the bottom encapsulation, and on bottom package second surface pad, plant soldered ball.
Advantage of the present invention is effectively to improve packaging density, and technological process is simple, and substrate rigidity is big, is difficult for producing warpage, and general thickness is thin, the reliability height.
Description of drawings
The PoP encapsulating structure cutaway view that Fig. 1 is traditional;
Fig. 2 structural representation of the present invention;
The cutaway view of Fig. 3 bottom base plate for packaging of the present invention;
Fig. 4 bottom base plate for packaging is by the fixing cutaway view of semiconductor chip of Heraeus;
The schematic diagram of Fig. 5 bottom semiconductor chip bonding wire;
The cutaway view of Fig. 6 top layer base plate for packaging;
The fixing cutaway view of semiconductor chip on Fig. 7 top layer base plate for packaging;
Fig. 8 fixes the cutaway view of two layers of semiconductor chip by Heraeus;
Fig. 9 is by the fixing cutaway view of three-layer semiconductor chip of Heraeus;
The schematic diagram of Figure 10 top layer semiconductor chip bonding wire;
Figure 11 adopts the schematic diagram of sealant with top layer semiconductor chip and bonding wire sealing;
Figure 12 plants the schematic diagram of soldered ball on the pad of top layer base plate for packaging lower surface;
The schematic diagram that Figure 13 links together top encapsulation and bottom package;
The schematic diagram of Figure 14 filling sealing agent between top encapsulation and bottom package;
Figure 15 plants the schematic diagram of soldered ball on bottom package second surface pad;
The structural representation of Figure 16 embodiment two;
The structural representation of Figure 17 embodiment three;
The structural representation of Figure 18 embodiment four;
The structural representation of Figure 19 embodiment five.
Among the figure: 1 Heraeus, 2 semiconductor chips, 3 Heraeus, the 3a wall, 4 semiconductor chips, 5 Heraeus, the 5a wall, 6 semiconductor chips, 7 pads, 8 bonding wires, 9 bonding wires, 10 bonding wires, 11 top layer base plate for packaging upper surface pads, 12 top layer base plate for packaging, 13 top layer base plate for packaging lower surface pad, 14 sealants, 15 soldered balls, 16 bottom base plate for packaging, 17 bottom base plate for packaging second surface pads, 18 soldered balls, 19 bottom base plate for packaging the 3rd surface pads, 20 Heraeus, 21 semiconductor chips, 22 pads, 23 bonding wires, 24 sealants, 25 pads, 26 pads, 27 bottom base plate for packaging first surface pads, 28 soldered balls, 29 underfill materials, 30 semiconductor chips, 31 bottom base plate for packaging the 3rd surface pads, 32 bronze medal posts, 33 solder layers, 34 bronze medal posts, 35 chips, 2 surface pads, 36 underfill materials, 37 welded ball arrays, 38 bottom base plate for packaging first surface pads.
Embodiment
Further specify embodiments of the invention below in conjunction with accompanying drawing.
Embodiment one
Fig. 2 is the structural representation of the embodiment of the invention one, and this encapsulation comprises the welded ball array of top encapsulation, bottom package, interconnected bases encapsulation and top encapsulation, and the sealant between top layer encapsulation and the bottom encapsulation.The substrate 16 of bottom package is provided with an inverted trapezoidal groove, and semiconductor chip 21 is fixed on bottom portion of groove by Heraeus 20.Top encapsulation comprises at least one semiconductor chip, and top encapsulation has comprised three semiconductor chips among Fig. 2, and three semiconductor chips are stacked in layers by Heraeus and wall to be placed, and wall is the bonding wire headspace.Pad 11 on pad on the semiconductor chip and top encapsulation substrate 12 first surfaces is connected through bonding wire realizes electrical interconnection.Sealant 24 covers the top of the upper surface of top layer base plate for packaging, the semiconductor chip and the lead-in wire of the encapsulation of sealing top layer.The electrical interconnection of top layer encapsulation and bottom encapsulation realizes by welded ball array 15.Realize sealing by sealant 14 between the lower surface of the substrate of top layer encapsulation and the first surface of bottom base plate for packaging and the 3rd surface.The second surface of the substrate 16 of bottom encapsulation arranges that welded ball array is to realize packaging body and outside electrical interconnection.
The packaging technology of present embodiment comprises following steps:
Steps A
Preparation has the bottom base plate for packaging of groove; The upper surface of bottom base plate for packaging 16 is a first surface, the lower surface of bottom base plate for packaging is a second surface, surface in the bottom base plate for packaging groove is the 3rd surface, groove location is arranged on the substrate first surface, this groove is arranged on the center of bottom base plate for packaging, bottom portion of groove forms the 3rd surface, and substrate can be selected pcb board or FR4 version or BT plate for use, as shown in Figure 3.
Step B
On three surfaces of bottom base plate for packaging, prepare pad; Preparation pad 27 on the first surface of bottom base plate for packaging 16, preparation pad 17, the three surface preparation pads 19 on the second surface.Circuit and interconnect pad 27, pad 17, pad 19 in bottom base plate for packaging inside comprises.
Step C
Be installed in the semiconductor chip of bottom encapsulation in the groove and finish the lead-in wire bonding; The bottom portion of groove of bottom base plate for packaging 16 passes through fixedly semiconductor chip 21 of Heraeus 20, Heraeus 20 adopts organic polymer elargol or inorganic polymer elargol, earlier Heraeus is coated on bottom portion of groove, semiconductor chip 21 is installed then, solidify, the cooling back just can be fixed on semiconductor chip 21 the adhesive layer top, as shown in Figure 4.By bonding wire 23 interconnection semiconductor chip pads 22 and bottom portion of groove pad 19, bottom portion of groove pad 19 links to each other with the second surface pad 17 of bottom base plate for packaging 16 by bottom base plate for packaging 16 internal circuits, and realization semiconductor chip 21 is connected with external circuit.Bonding wire can adopt gold thread, copper cash or aluminum steel, and bonding technology can adopt hot ultrasonic bonding or thermocompression bonding, as shown in Figure 5.The semiconductor chip that the bottom encapsulation is adopted comprises logic chip.
Step D
On the upper and lower surface of top layer base plate for packaging, prepare pad; Upper surface at top encapsulation substrate 12 prepares pad 11, prepares pad 13 at the lower surface of top encapsulation substrate 12, and substrate inside is provided with interior circuit, and substrate can adopt pcb board or FR4 plate or BT plate, as shown in Figure 6.
Step e
Stacked being installed on the top layer base plate for packaging of semiconductor chip with the top layer encapsulation; The top layer of present embodiment is encapsulated as three stacked dresses, upper surface at top encapsulation substrate 12 is installed semiconductor chip 2, earlier at top encapsulation substrate 12 upper surfaces coating Heraeus 1, after placing semiconductor chip 2, reflux, be cooled to room temperature then and can fix chip 2, Heraeus 1 adopts organic polymer elargol or inorganic polymer elargol, as shown in Figure 7.By Heraeus 3 and wall 3a semiconductor chip 4 is fixed on the upper surface of semiconductor chip 2, Heraeus 3 is coated on semiconductor chip 2 upper surfaces, and wall is the bonding wire headspace, as shown in Figure 8.Semiconductor chip 6 is fixed on the upper surface of semiconductor chip 4 by Heraeus 5 and wall 5a, Heraeus 5 areas are slightly less than semiconductor chip 4 upper surfaces to expose semiconductor chip 4 upper surface pads, wall is semiconductor chip 4 bonding wire headspaces, as shown in Figure 9.The top encapsulation semiconductor chip adopts memory chip, and selects the number of plies of piling up as required.
Step F
Carry out the lead-in wire bonding of the stacked semiconductor chip of top layer encapsulation; Be connected with pad 11 bondings of top layer base plate for packaging 12 upper surfaces by the upper surface pad 7 of bonding wire 8 semiconductor chip 2, be connected with pad 11 bondings of top layer base plate for packaging upper surface by the upper surface pad 25 of bonding wire 9 semiconductor chip 4, be connected with pad 11 bondings of top layer base plate for packaging upper surface by the upper surface pad 26 of bonding wire 10, as shown in figure 10 semiconductor chip 6.Bonding wire adopts gold thread, copper cash or aluminum steel, and the bonding mode adopts thermocompression bonding or hot ultrasonic bonding.
Step G
Carry out the top layer sealed package; By sealant 24 top layer is encapsulated bonding wire 8,9,10 and semiconductor chip 2,4,6 sealed package, sealant is positioned at top layer base plate for packaging 12 upper surfaces top, sealant adopts the plastic package process sealing, and sealant can adopt epoxy molding plastic, as shown in figure 11.
Step H
On the pad of top layer base plate for packaging lower surface, plant soldered ball, carry out the connection between top layer encapsulation and the bottom encapsulation; On top layer base plate for packaging 12 lower surface pad 13, plant soldered ball 15, scolder can adopt the mode of screen printing technique, plating or evaporation to be coated with, form welded ball array 15 after refluxing, scolder can adopt SnAg, Sn, SnAgCu or PbSn scolder, as shown in figure 12.Soldered ball 15 on top layer base plate for packaging 12 lower surfaces is welded on the bottom base plate for packaging 16 first surface pads 27, realizes the electrical interconnection between top layer encapsulation and the bottom encapsulation, as shown in figure 13.
Step I
Carry out the filling sealing between top layer encapsulation and the bottom encapsulation, and on bottom package second surface pad, plant soldered ball; Filling sealing agent 24 between top layer encapsulation and bottom encapsulation, sealant 24 adopts epoxy molding plastics, adopts injection molding way to fill, in order to protection welded ball array 15 and bottom packaged chip 21 and go between 23, as shown in figure 14.Plant soldered ball on pad 17, form before the soldered ball, earlier scolder is coated on the pad top, the mode by silk-screen printing technique or evaporation or plating realizes.Back formation soldered ball refluxes.Scolder adopts SnAg, Sn, SnAgCu or PbSn scolder, as shown in figure 15.
Embodiment two
Embodiment two is identical with embodiment one, different is bottom packaged chip 30 active faces down, on active face, make soldered ball 28, by the mode that hot pressing is welded, hot sonic soldering connects or scolder welds, the pad 31 of soldered ball 28 with bottom base plate for packaging 16 the 3rd surface is interconnected to, realizes the transmission of the signal of telecommunication between chip 30 and the substrate 16.After welded ball array 28 and pad 31 welding are finished, fill underfill material in the bottom of chip 30, underfill material adopts to be made up of the filler of thermosetting polymer and silicon dioxide, as shown in figure 16.
Embodiment three
Embodiment three is identical with embodiment one, and different is after top layer encapsulation making finishes, and makes soldered ball again on the lower surface pad 13 of top layer base plate for packaging 12, makes soldered ball simultaneously on bottom encapsulation first surface pad 27.Finish after the manufacture craft of soldered ball, adopt welding procedure, the soldered ball on soldered ball on the pad 13 and the pad 27 is linked together by backflow, finish the electrical interconnection of top layer encapsulation and bottom encapsulation.Filling sealing agent between top layer encapsulation and bottom encapsulation more afterwards is with protection soldered ball 15 and semiconductor chip 21, as shown in figure 17.
Embodiment four
Embodiment four is identical with embodiment one, and different is to go up 12 making of top layer base plate for packaging to finish, and carries out before the follow-up packaging technology, electroplates a bronze medal post 32 on the lower surface pad 13 of substrate 11, deposits one deck solder layer afterwards again.Simultaneously, after bottom base plate for packaging 16 is made and finished, on bottom base plate for packaging 16 first surface pads 27, electroplate a bronze medal post 34, deposit solder layer afterwards, the material of solder layer can be Sn, SnAg, SnAgCu or PbSn scolder.Adopt reflux technique, solder layer on solder layer on the copper post 32 and the copper post 34 is linked together, finish the electrical interconnection of top layer encapsulation and bottom encapsulation.Afterwards, the gap filling sealing agent between top layer encapsulation and bottom encapsulation, as shown in figure 18.
Embodiment five
Embodiment five is identical with embodiment one, different is that semiconductor chip 2 is inverted structure, on the active layer surface pads 35 of semiconductor chip 2, make solder bump 37 earlier, employing hot pressing is welded or hot sonic soldering connects or the mode of reflow soldering is welded on solder bump 37 on the pad 38 of top layer base plate for packaging upper surface, and the material of salient point 37 can be au bump or Sn, SnAg, SnAgCu or PbSn solder bump.Afterwards, fill underfill material 36 again between semiconductor chip 2 and top layer base plate for packaging, finish curing, underfill material is made up of the filler of thermosetting polymer and silicon dioxide, as shown in figure 19.

Claims (7)

1. stacked semiconductor chip encapsulating structure, comprise the top layer encapsulation, the bottom encapsulation, welded ball array between top layer encapsulation and the bottom encapsulation, sealant between top layer encapsulation and the bottom encapsulation, it is characterized in that described bottom base plate for packaging is provided with a groove, the upper surface of bottom base plate for packaging is a first surface, the lower surface of bottom base plate for packaging is a second surface, surface in the bottom base plate for packaging groove is the 3rd surface, the semiconductor chip of bottom encapsulation is arranged in the groove, first, second, be equipped with pad on the 3rd surface, the bottom semiconductor chip links to each other with the 3rd lip-deep pad by bonding wire, top layer encapsulation by one or several semiconductor chip laminate packaging on the upper surface of top layer base plate for packaging, the upper surface and the lower surface of top layer base plate for packaging are equipped with pad, semiconductor chip in the top layer encapsulation links to each other by the pad of bonding wire with top layer base plate for packaging upper surface, the top layer packed part seals through sealant, be connected filling sealing agent between top layer base plate for packaging and the bottom base plate for packaging with welded ball array by pad between top layer encapsulation and the bottom encapsulation.
2. stacked semiconductor chip encapsulating structure according to claim 1, it is characterized in that groove on the described bottom base plate for packaging is for trapezoidal, the semiconductor chip of bottom encapsulation is bonded in bottom portion of groove by Heraeus, perhaps be welded on bottom portion of groove with face-down bonding technique, semiconductor chip is connected by soldered ball with bottom portion of groove.
3. stacked semiconductor chip encapsulating structure according to claim 1, the semiconductor chip that it is characterized in that described top layer encapsulation is the stacked in layers structure, top layer encapsulates between first semiconductor chip and the substrate can realize interconnection by paster technique or flip chip bonding technology, the semiconductor chip of top layer encapsulation and bonding wire adopt the sealant sealing, sealed dose of encapsulation of the upper surface of top layer base plate for packaging, sealant is an epoxy molding plastic.
4. stacked semiconductor chip encapsulating structure according to claim 1 is characterized in that being provided with the circuit that is connected usefulness in described bottom base plate for packaging and the top layer base plate for packaging.
5. stacked semiconductor chip encapsulating structure according to claim 1, the second surface that it is characterized in that described bottom base plate for packaging is provided with welded ball array, welded ball array is that the mode of silk screen printing or plating or evaporation is coated with scolder, produce welded ball array by refluxing, its material is SnAg or Sn or SnAgCu or PbSn.
6. stacked semiconductor chip encapsulating structure according to claim 1, it is characterized in that being individual layer or double-deck welded ball array between described top layer encapsulation and the bottom encapsulation, by reflux technique top layer encapsulation and bottom encapsulation are linked together, perhaps deposit solder layer after the lower surface pad of top layer base plate for packaging powers on copper plated pillars, deposit solder layer after the first surface pad of bottom base plate for packaging powers on copper plated pillars, the material of solder layer is SnAg or Sn or SnAgCu or PbSn, by reflux technique top layer base plate for packaging and bottom base plate for packaging are linked together, finish the electrical interconnection between top layer packaging body and the bottom packaging body.
7. the technology of a stacked semiconductor chip encapsulating structure is characterized in that comprising successively following steps:
A. preparation has the bottom base plate for packaging of groove;
B. on three surfaces of bottom base plate for packaging, prepare pad;
C. the semiconductor chip that bottom is encapsulated is installed in the groove and finishes the lead-in wire bonding;
D. on the upper and lower surface of top layer base plate for packaging, prepare pad;
E. with stacked being installed on the top layer base plate for packaging of semiconductor chip of top layer encapsulation;
F. carry out the lead-in wire bonding of the stacked semiconductor chip of top layer encapsulation;
G. carry out the top layer sealed package;
H. on the pad of top layer base plate for packaging lower surface, plant soldered ball, carry out the connection between top layer encapsulation and the bottom encapsulation;
I. carry out the filling sealing agent between top layer encapsulation and the bottom encapsulation, and on bottom package second surface pad, plant soldered ball.
CN2012100160177A 2012-01-18 2012-01-18 Stackable semiconductor chip packaging structure and process thereof Pending CN103219324A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109461719A (en) * 2016-07-17 2019-03-12 高燕妮 A kind of integrated circuit package structure
CN110024116A (en) * 2016-12-27 2019-07-16 英特尔公司 The encapsulation of stacked tubes core cavity
CN110289252A (en) * 2018-03-19 2019-09-27 东芝存储器株式会社 Semiconductor device and its manufacturing method
CN110690208A (en) * 2019-10-08 2020-01-14 中国电子科技集团公司第二十四研究所 Power hybrid integrated circuit packaging structure
CN110692135A (en) * 2019-06-14 2020-01-14 深圳市汇顶科技股份有限公司 Chip packaging structure and electronic equipment
CN111613585A (en) * 2020-05-28 2020-09-01 华进半导体封装先导技术研发中心有限公司 Chip packaging structure and method
CN111933623A (en) * 2020-06-29 2020-11-13 中国航空工业集团公司北京长城航空测控技术研究所 Packaging interconnection structure and method based on substrate side bonding pad

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115188746B (en) * 2021-04-07 2024-05-24 中国科学院国家空间科学中心 Electronic packaging structure for computer microsystem
CN116299850B (en) * 2023-05-15 2023-09-05 甬矽电子(宁波)股份有限公司 Silicon photon packaging structure and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040207058A1 (en) * 2002-12-30 2004-10-21 Sohn Young Ho Side braze packages
CN101432876A (en) * 2006-04-27 2009-05-13 住友电木株式会社 Semiconductor device and semiconductor device manufacturing method
CN101656248A (en) * 2008-08-19 2010-02-24 南茂科技股份有限公司 Chip-stacked package structure of substrate with groove and packaging method thereof
CN101872749A (en) * 2009-04-24 2010-10-27 南茂科技股份有限公司 Recess chip packaging structure and laminated packaging structure using same
CN202434509U (en) * 2012-01-18 2012-09-12 刘胜 Stackable semiconductor chip packaging structure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG87046A1 (en) * 1999-08-17 2002-03-19 Micron Technology Inc Multi-chip module with stacked dice
US6780751B2 (en) * 2002-10-09 2004-08-24 Freescale Semiconductor, Inc. Method for eliminating voiding in plated solder
KR100836663B1 (en) * 2006-02-16 2008-06-10 삼성전기주식회사 Package on package with cavity and Method for manufacturing thereof
US7989950B2 (en) * 2008-08-14 2011-08-02 Stats Chippac Ltd. Integrated circuit packaging system having a cavity
US20110024899A1 (en) * 2009-07-28 2011-02-03 Kenji Masumoto Substrate structure for cavity package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040207058A1 (en) * 2002-12-30 2004-10-21 Sohn Young Ho Side braze packages
CN101432876A (en) * 2006-04-27 2009-05-13 住友电木株式会社 Semiconductor device and semiconductor device manufacturing method
CN101656248A (en) * 2008-08-19 2010-02-24 南茂科技股份有限公司 Chip-stacked package structure of substrate with groove and packaging method thereof
CN101872749A (en) * 2009-04-24 2010-10-27 南茂科技股份有限公司 Recess chip packaging structure and laminated packaging structure using same
CN202434509U (en) * 2012-01-18 2012-09-12 刘胜 Stackable semiconductor chip packaging structure

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109524387A (en) * 2016-07-17 2019-03-26 高燕妮 A kind of manufacturing method of integrated circuit package structure
CN109461719A (en) * 2016-07-17 2019-03-12 高燕妮 A kind of integrated circuit package structure
CN110024116A (en) * 2016-12-27 2019-07-16 英特尔公司 The encapsulation of stacked tubes core cavity
US11705377B2 (en) 2016-12-27 2023-07-18 Intel Corporation Stacked die cavity package
CN110289252A (en) * 2018-03-19 2019-09-27 东芝存储器株式会社 Semiconductor device and its manufacturing method
CN113035795B (en) * 2019-06-14 2022-11-08 深圳市汇顶科技股份有限公司 Chip packaging structure and electronic equipment
CN110692135A (en) * 2019-06-14 2020-01-14 深圳市汇顶科技股份有限公司 Chip packaging structure and electronic equipment
CN113035795A (en) * 2019-06-14 2021-06-25 深圳市汇顶科技股份有限公司 Chip packaging structure and electronic equipment
US11545517B2 (en) 2019-06-14 2023-01-03 Shenzhen GOODIX Technology Co., Ltd. Chip package structure, electronic device and method for preparing a chip package structure
CN110690208A (en) * 2019-10-08 2020-01-14 中国电子科技集团公司第二十四研究所 Power hybrid integrated circuit packaging structure
CN111613585A (en) * 2020-05-28 2020-09-01 华进半导体封装先导技术研发中心有限公司 Chip packaging structure and method
CN111613585B (en) * 2020-05-28 2022-07-26 华进半导体封装先导技术研发中心有限公司 Chip packaging structure and method
CN111933623A (en) * 2020-06-29 2020-11-13 中国航空工业集团公司北京长城航空测控技术研究所 Packaging interconnection structure and method based on substrate side bonding pad
CN111933623B (en) * 2020-06-29 2024-02-27 中国航空工业集团公司北京长城航空测控技术研究所 Packaging interconnection structure and method based on substrate side bonding pad

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