CN109244058A - Semiconductor package and preparation method thereof - Google Patents

Semiconductor package and preparation method thereof Download PDF

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Publication number
CN109244058A
CN109244058A CN201811093393.XA CN201811093393A CN109244058A CN 109244058 A CN109244058 A CN 109244058A CN 201811093393 A CN201811093393 A CN 201811093393A CN 109244058 A CN109244058 A CN 109244058A
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CN
China
Prior art keywords
supply control
chip
substrate
power supply
semiconductor package
Prior art date
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Pending
Application number
CN201811093393.XA
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Chinese (zh)
Inventor
朱耀明
江子标
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Ambrose Power Semiconductor Co Ltd
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Shenzhen Ambrose Power Semiconductor Co Ltd
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Application filed by Shenzhen Ambrose Power Semiconductor Co Ltd filed Critical Shenzhen Ambrose Power Semiconductor Co Ltd
Priority to CN201811093393.XA priority Critical patent/CN109244058A/en
Publication of CN109244058A publication Critical patent/CN109244058A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The invention discloses a kind of semiconductor package and preparation method thereof, encapsulating structure includes substrate, and soldered ball is provided on the bottom face of substrate, and plastic-sealed body is provided on the top end face of substrate, and plastic-sealed body is built-in with stacked multi-chip interconnection architecture；The groove of embedded energy supply control module is offered on the top end face of substrate setting plastic-sealed body, the energy supply control module bottom face being inlaid in groove is electrically connected with the RDL wiring in substrate, and the top end face of energy supply control module is electrically connected with the weld pad of multi-chip interconnection architecture bottom face；Groove is not provided with positioning by the filled layer formed by filler between remaining cavity and energy supply control module and multi-chip interconnection architecture of energy supply control module.The present invention solves the problems, such as that functional module and energy supply control module manufacture craft are incompatible, so that the utilization rate of crystal column surface is maximized, while also effectively increasing the working efficiency of energy supply control module, reduces package thickness, reduces costs.

Description

Semiconductor package and preparation method thereof
Technical field
The present invention relates to conductor chip encapsulation technology field, especially a kind of semiconductor package and preparation method thereof.
Background technique
With the development of electronic engineering, people are small for integrated circuit (Integrated Circuit, abbreviation IC) chip The demand of type, lightweight and functionalization increasingly increases, and the development phase of the single component since most has progressed into collection The system development stage for tying multiple components, at the same time under the requirement that product is high-effect and appearance is frivolous, the core of different function Piece starts to march toward stage of integration, therefore the continuous development and breakthrough of encapsulation technology, becomes one of the strength for pushing integration.Especially It is the appearance of mobile consumer-elcetronics devices, increases the demand to compact high-performance storage device, the requirement to encapsulation is also more next It is higher, to reach relatively high demand on electric property as far as possible.
During the chip layout design of semiconductor package, every particle requires design energy supply control module Control the power supply supply of chip.Conventional semiconductor package structure is as depicted in figs. 1 and 2, and the encapsulating structure of Fig. 1 is Multi-chip laminating It encapsulates, a functional module P and an energy supply control module 8 is respectively set on each chip, it then will by way of routing Functional module and energy supply control module are connected respectively on substrate；The encapsulating structure liquid level multi-chip of Fig. 2 once must encapsulate, Mei Gexin A functional module and an energy supply control module is respectively set on piece, then chip is passed through using TSV, by functional module and electricity Source control module is connected on substrate, and TSV can shorten the total length of certain signal paths of the stacking by device, accelerates certain The transmission speed of a little signals, helps have a degree of reduction on encapsulation volume.
Although above two mode can realize the laminate packaging of chip, with the quick hair of chip fabrication techniques Exhibition, many high end chips (such as NAND chip) all use nanoscale making technology at present, and energy supply control module generally only needs It can be formed using micron-sized making technology, the two differs thousands of times on making technology, if power supply is controlled mould Block is integrated in high end chip, it may appear that following problems: 1) since high end chip manufacturing process is not suitable for energy supply control module Formation, the efficiency that will lead to energy supply control module reduces, such as drops to 50% or so from common 80% efficiency；2) advanced core Piece making technology is expensive, and the making technology cost of energy supply control module is relatively cheap, energy supply control module is integrated in advanced In chip, chip area can be occupied, improves the manufacturing cost of high end chip；3) excessive energy supply control module setting, causes core The waste of piece surface area, reduces the utilization rate of wafer.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of semiconductor packages and preparation method thereof, are solving function On the basis of energy module and power supply control chip technique are incompatible, the work effect of crystal round utilization ratio and power supply control chip is improved Rate.
In order to solve the above technical problems, the technical solution used in the present invention is as follows.
Semiconductor package, including substrate are provided with soldered ball on the bottom face of substrate, are provided on the top end face of substrate Plastic-sealed body, plastic-sealed body are built-in with the stacked multi-chip interconnection architecture being electrically connected with substrate；It is characterized by: the substrate setting The groove that embedded power supply control chip is offered on the top end face of plastic-sealed body, the power supply control chip bottom face being inlaid in groove It is electrically connected with the RDL wiring in substrate, the weld pad of the top end face and multi-chip interconnection architecture bottom face of power supply control chip is electrically connected It connects；The groove is not provided between remaining cavity and power supply control chip and multi-chip interconnection architecture of power supply control chip It is positioned by the filled layer formed by filler.
Above-mentioned semiconductor package, the multi-chip interconnection architecture include multiple independent chips, neighbouring core It is connected between piece by adhesive layer, is provided with the silicon perforation placed for connecting neighbouring chip electric connection structure in adhesive layer.
Above-mentioned semiconductor package, the electric connection structure of neighbouring chip chamber are copper-connection or soldered ball and weld pad Connection.
The RDL wiring of groove is arranged in the middle substrate lower than substrate other positions for above-mentioned semiconductor package RDL wiring height.
Above-mentioned semiconductor package, the multi-chip are stacked vertically on power supply control chip.
The preparation method of above-mentioned semiconductor package, specifically includes the following steps:
Step 1 opens up more slightly larger than power supply control chip volume recessed on the substrate for being built-in with RDL wiring according to design requirement Slot；
The power supply control chip for having formed TSV is put into the groove of substrate by step 2, and bottom end and the substrate in the hole TSV are electrically connected It connects；
The multi-chip interconnection architecture being laminated is electrically connected by step 3 using welding manner with power supply control chip；
Step 4 is filled shape to the gap between the cavity and multi-chip interconnection architecture and power supply control chip in groove At filled layer；
Step 5 carries out plastic packaging to whole, and is implanted into soldered ball in substrate bottom face.
The preparation method of above-mentioned semiconductor package, the multichip interconnection structure includes silicon perforation；The groove Consistency of thickness of the depth at least with the power supply control chip；The filled layer is formed as carrying out in the way of capillary Filling；The material of the filled layer is epoxy resin.
Due to using above technical scheme, the invention technological progress is as follows.
The present invention is controlled by the way that pervious independent current source control chip is changed to unified power supply in the packaging body of stacking Chip, and be embedded in substrate, technologic cumbersome processing procedure is changed, functional module is solved and power supply control chip makes The incompatible problem of technique so that the utilization rate of crystal column surface is maximized, while also effectively increasing power supply control core The working efficiency of piece, reduces package thickness, reduces costs.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of conventional semiconductor package；
Fig. 2 is the structural schematic diagram of another conventional semiconductor package；
Fig. 3 is the structure chart that step 1 of the present invention is formed；
Fig. 4 is the structure chart that step 2 of the present invention is formed；
Fig. 5 is the structure chart that step 3 of the present invention is formed；
Fig. 6 is the structure chart that step 4 of the present invention is formed；
Fig. 7 is the structural schematic diagram of semiconductor package of the present invention.
Wherein: 1. plastic-sealed bodies, 2. weld pads, 3. adhesive layers, 4. silicon perforations, 5.RDL wiring, 6. substrates, 7. soldered balls, 8. power supplys Control chip, 9. filled layers, P. functional module.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention will be described in further detail.
A kind of semiconductor package, structure are provided with RDL wiring, substrate as shown in fig. 7, comprises substrate 6 in substrate Bottom face on be provided with soldered ball, plastic-sealed body 1 is provided on the top end face of substrate, plastic-sealed body is built-in with the layer being electrically connected with substrate Stacked multi-chip interconnection architecture.
It opens up fluted on the top end face of substrate of the present invention setting plastic-sealed body, controls core embedded with power supply in groove Piece, the bottom face of power supply control chip 8 are electrically connected with the RDL wiring in substrate, the top end face and multi-chip of power supply control chip The weld pad of interconnection architecture bottom face is electrically connected.The present invention is to meet being embedded in for power supply control chip, will be provided with the RDL of groove Wiring is routed height lower than the RDL of substrate other positions；The jail being connect for guarantee power supply control chip with multi-chip interconnection architecture Solidity, between remaining cavity and power supply control chip and multi-chip interconnection architecture that groove is not provided with power supply control chip It is positioned by the filled layer formed by filler.
Multi-chip interconnection architecture includes multiple independent chips, and neighbouring chip chamber is connected by adhesive layer 3, is bonded The silicon perforation 4 placed for connecting neighbouring chip electric connection structure is provided in layer；The electricity of the neighbouring chip chamber Connection structure is the connection of copper-connection or soldered ball and weld pad.Chip scale model in the present invention, in multi-chip interconnection architecture It may be the same or different.
The present invention also provides a kind of preparation methods of above-mentioned semiconductor package, specifically includes the following steps:
Step 1 opens up more slightly larger than power supply control chip volume recessed on the substrate for being built-in with RDL wiring according to design requirement Slot；The depth of groove and the thickness of power supply control chip are identical, after guaranteeing that power supply control chip installs, top end face and base The top end face of plate is located at sustained height, as shown in Figure 3.
The power supply control chip for having formed TSV is put into the groove of substrate by step 2, the bottom end in the hole TSV and substrate Electrical connection；As shown in Figure 4.
The multi-chip interconnection architecture being laminated is electrically connected by step 3 using welding manner with power supply control chip；Make more Chip Vertical is stacked on power supply control chip, as shown in Figure 5.
Step 4 fills out the gap between the cavity and multi-chip interconnection architecture and power supply control chip in groove It fills to form filled layer；As shown in Figure 6.In the present embodiment, epoxy resin is filled into groove by the way of capillary In gap between cavity and multi-chip interconnection architecture and power supply control chip.
Step 5 carries out plastic packaging to whole, and is implanted into soldered ball in substrate bottom face, as shown in fig. 7, to complete semiconductor Encapsulation.

Claims (10)

1. semiconductor package, including substrate (6), it is provided with soldered ball on the bottom face of substrate, is arranged on the top end face of substrate Have plastic-sealed body (1), plastic-sealed body is built-in with the stacked multi-chip interconnection architecture being electrically connected with substrate；It is characterized by: the base The groove that embedded power supply control chip (8) are offered on the top end face of plate setting plastic-sealed body, the power supply control being inlaid in groove Chip (8) bottom face is electrically connected with the RDL wiring in substrate, the top end face of power supply control chip and multi-chip interconnection architecture bottom end The weld pad in face is electrically connected；The groove be not provided with power supply control chip remaining cavity and power supply control chip and multi-chip it is mutual It is coupled between structure and is positioned by the filled layer formed by filler.
2. semiconductor package according to claim 1, it is characterised in that: the multi-chip interconnection architecture includes multiple Independent chip, neighbouring chip chamber are connected by adhesive layer (3), and placement is provided in adhesive layer for connecting phase up and down The silicon perforation (4) of adjacent chip electric connection structure.
3. semiconductor package according to claim 2, it is characterised in that: the electric connection structure of neighbouring chip chamber For the connection of copper-connection or soldered ball and weld pad.
4. semiconductor package according to claim 1, it is characterised in that: the RDL of groove is arranged in the substrate Wiring is routed height lower than the RDL of substrate other positions.
5. semiconductor package according to claim 1, it is characterised in that: the multi-chip is stacked vertically in power supply control Coremaking on piece.
6. the preparation method of the semiconductor package as described in claim 1 to 5, which is characterized in that specifically include following step It is rapid:
Step 1 opens up more slightly larger than power supply control chip volume recessed on the substrate for being built-in with RDL wiring according to design requirement Slot；
The power supply control chip for having formed TSV is put into the groove of substrate by step 2, and bottom end and the substrate in the hole TSV are electrically connected It connects；
The multi-chip interconnection architecture being laminated is electrically connected by step 3 using welding manner with power supply control chip；
Step 4 is filled shape to the gap between the cavity and multi-chip interconnection architecture and power supply control chip in groove At filled layer；
Step 5 carries out plastic packaging to whole, and is implanted into soldered ball in substrate bottom face.
7. the preparation method of semiconductor package according to claim 6, which is characterized in that the multichip interconnection knot Structure includes silicon perforation.
8. the preparation method of semiconductor package according to claim 6, which is characterized in that the depth of the groove is extremely Few consistency of thickness with the power supply control chip.
9. the preparation method of semiconductor package according to claim 6, which is characterized in that the formation of the filled layer To be filled in the way of capillary.
10. the preparation method of semiconductor package according to claim 6, which is characterized in that the material of the filled layer Material is epoxy resin.
CN201811093393.XA 2018-09-19 2018-09-19 Semiconductor package and preparation method thereof Pending CN109244058A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021073256A1 (en) * 2019-10-18 2021-04-22 天津大学 Multiplexer

Citations (8)

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CN201708153U (en) * 2010-04-23 2011-01-12 矽格微电子(无锡)有限公司 Laminated encapsulation structure of LED module
KR20110105159A (en) * 2010-03-18 2011-09-26 주식회사 하이닉스반도체 Stacked semiconductor package and method for forming the same
US20120314511A1 (en) * 2011-06-08 2012-12-13 Elpida Memory, Inc. Semiconductor device
US20130032390A1 (en) * 2011-08-05 2013-02-07 Industrial Technology Research Institute Packaging substrate having embedded interposer and fabrication method thereof
US20130153898A1 (en) * 2011-12-20 2013-06-20 Elpida Memory, Inc. Semiconductor device having plural semiconductor chip stacked with one another
US20140246781A1 (en) * 2013-03-04 2014-09-04 Kabushiki Kaisha Toshiba Semiconductor device, method of forming a packaged chip device and chip package
US20170236809A1 (en) * 2016-02-16 2017-08-17 Xilinx, Inc. Chip package assembly with power management integrated circuit and integrated circuit die
CN208674106U (en) * 2018-09-19 2019-03-29 深圳铨力半导体有限公司 Semiconductor package

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110105159A (en) * 2010-03-18 2011-09-26 주식회사 하이닉스반도체 Stacked semiconductor package and method for forming the same
CN201708153U (en) * 2010-04-23 2011-01-12 矽格微电子(无锡)有限公司 Laminated encapsulation structure of LED module
US20120314511A1 (en) * 2011-06-08 2012-12-13 Elpida Memory, Inc. Semiconductor device
US20130032390A1 (en) * 2011-08-05 2013-02-07 Industrial Technology Research Institute Packaging substrate having embedded interposer and fabrication method thereof
US20130153898A1 (en) * 2011-12-20 2013-06-20 Elpida Memory, Inc. Semiconductor device having plural semiconductor chip stacked with one another
US20140246781A1 (en) * 2013-03-04 2014-09-04 Kabushiki Kaisha Toshiba Semiconductor device, method of forming a packaged chip device and chip package
US20170236809A1 (en) * 2016-02-16 2017-08-17 Xilinx, Inc. Chip package assembly with power management integrated circuit and integrated circuit die
CN208674106U (en) * 2018-09-19 2019-03-29 深圳铨力半导体有限公司 Semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021073256A1 (en) * 2019-10-18 2021-04-22 天津大学 Multiplexer

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