CN208674106U - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- CN208674106U CN208674106U CN201821531098.3U CN201821531098U CN208674106U CN 208674106 U CN208674106 U CN 208674106U CN 201821531098 U CN201821531098 U CN 201821531098U CN 208674106 U CN208674106 U CN 208674106U
- Authority
- CN
- China
- Prior art keywords
- chip
- supply control
- substrate
- power supply
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
The utility model discloses a kind of semiconductor package, including substrate, it is provided with soldered ball on the bottom face of substrate, plastic-sealed body is provided on the top end face of substrate, plastic-sealed body is built-in with the stacked multi-chip interconnection architecture being electrically connected with substrate；The groove of embedded energy supply control module is offered on the top end face of substrate setting plastic-sealed body, the energy supply control module bottom face being inlaid in groove is electrically connected with the RDL wiring in substrate, and the top end face of energy supply control module is electrically connected with the weld pad of multi-chip interconnection architecture bottom face；Groove is not provided with positioning by the filled layer formed by filler between remaining cavity and energy supply control module and multi-chip interconnection architecture of energy supply control module.The utility model solves the problems, such as that functional module and energy supply control module manufacture craft are incompatible, so that the utilization rate of crystal column surface is maximized, while also effectively increasing the working efficiency of energy supply control module, reduces package thickness, reduces costs.
Description
Technical field
The utility model relates to be related to conductor chip encapsulation technology field, especially a kind of semiconductor package.
Background technique
With the development of electronic engineering, people are small for integrated circuit (Integrated Circuit, abbreviation IC) chip
The demand of type, lightweight and functionalization increasingly increases, and the development phase of the single component since most has progressed into collection
The system development stage for tying multiple components, at the same time under the requirement that product is high-effect and appearance is frivolous, the core of different function
Piece starts to march toward stage of integration, therefore the continuous development and breakthrough of encapsulation technology, becomes one of the strength for pushing integration.Especially
It is the appearance of mobile consumer-elcetronics devices, increases the demand to compact high-performance storage device, the requirement to encapsulation is also more next
It is higher, to reach relatively high demand on electric property as far as possible.
During the chip layout design of semiconductor package, every particle requires design power supply control chip
Control the power supply supply of chip.Conventional semiconductor package structure is as depicted in figs. 1 and 2, and the encapsulating structure of Fig. 1 is Multi-chip laminating
It encapsulates, a functional module P and a power supply control chip 8 is respectively set on each chip, it then will by way of routing
Functional module and power supply control chip are connected respectively on substrate；The encapsulating structure liquid level multi-chip of Fig. 2 once must encapsulate, Mei Gexin
A functional module and a power supply control chip is respectively set on piece, then chip is passed through using TSV, by functional module and electricity
Source control chip is connected on substrate, and TSV can shorten the total length of certain signal paths of the stacking by device, accelerate certain
The transmission speed of a little signals, helps have a degree of reduction on encapsulation volume.
Although above two mode can realize the laminate packaging of chip, with the quick hair of chip fabrication techniques
Exhibition, many high end chips (such as NAND chip) all use nanoscale making technology at present, and power supply control chip generally only needs
It can be formed using micron-sized making technology, the two differs thousands of times on making technology, if power supply is controlled core
Piece is integrated in high end chip, it may appear that following problems: 1) since high end chip manufacturing process is not suitable for power supply control chip
Formation, the efficiency that will lead to power supply control chip reduces, such as drops to 50% or so from common 80% efficiency；2) advanced
Chip making technology is expensive, and the making technology cost of power supply control chip is relatively cheap, and power supply control chip is integrated in height
In grade chip, chip area can be occupied, the manufacturing cost of high end chip is improved；3) excessive power supply control chip setting, is caused
Chip surface area loss reduces the utilization rate of wafer.
Utility model content
The utility model technical issues that need to address are to provide a kind of semiconductor package, solve functional module with
On the basis of power supply control chip technique is incompatible, the working efficiency of crystal round utilization ratio and power supply control chip is improved.
In order to solve the above technical problems, technical solution adopted in the utility model is as follows.
Semiconductor package, including substrate are provided with soldered ball on the bottom face of substrate, are provided on the top end face of substrate
Plastic-sealed body, plastic-sealed body are built-in with the stacked multi-chip interconnection architecture being electrically connected with substrate；It is characterized by: the substrate setting
The groove that embedded power supply control chip is offered on the top end face of plastic-sealed body, the power supply control chip bottom face being inlaid in groove
It is electrically connected with the RDL wiring in substrate, the weld pad of the top end face and multi-chip interconnection architecture bottom face of power supply control chip is electrically connected
It connects；The groove is not provided between remaining cavity and power supply control chip and multi-chip interconnection architecture of power supply control chip
It is positioned by the filled layer formed by filler.
Above-mentioned semiconductor package, the multi-chip interconnection architecture include multiple independent chips, neighbouring core
It is connected between piece by adhesive layer, is provided with the silicon perforation placed for connecting neighbouring chip electric connection structure in adhesive layer.
Above-mentioned semiconductor package, the electric connection structure of neighbouring chip chamber are copper-connection or soldered ball and weld pad
Connection.
Above-mentioned semiconductor package, the RDL wiring that groove is arranged in the substrate are lower than the RDL of substrate other positions
Wiring height.
Above-mentioned semiconductor package, the multi-chip interconnection architecture are stacked vertically on the power supply control chip.
Due to using above technical scheme, technological progress acquired by the utility model is as follows.
The utility model is by being changed to unified power supply for pervious independent current source control chip in the packaging body of stacking
Chip is controlled, and is embedded in substrate, technologic cumbersome processing procedure is changed, solves functional module and power supply control chip
The incompatible problem of manufacture craft so that the utilization rate of crystal column surface is maximized, while also effectively increasing power supply control
The working efficiency of coremaking piece, reduces package thickness, reduces costs.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of conventional semiconductor package；
Fig. 2 is the structural schematic diagram of another conventional semiconductor package；
Fig. 3 is the structure chart that step 1 described in the utility model is formed；
Fig. 4 is the structure chart that step 2 described in the utility model is formed；
Fig. 5 is the structure chart that step 3 described in the utility model is formed；
Fig. 6 is the structure chart that step 4 described in the utility model is formed；
Fig. 7 is the structural schematic diagram of semiconductor package described in the utility model.
Wherein: 1. plastic-sealed bodies, 2. weld pads, 3. adhesive layers, 4. silicon perforations, 5.RDL wiring, 6. substrates, 7. soldered balls, 8. power supplys
Control chip, 9. filled layers, P. functional module.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, the present invention will be further described in detail.
A kind of semiconductor package, structure are provided with RDL wiring, base as shown in fig. 7, comprises substrate 6 in substrate
It it is provided with soldered ball on the bottom face of plate, is provided with plastic-sealed body 1 on the top end face of substrate, plastic-sealed body is built-in with to be electrically connected with substrate
Stacked multi-chip interconnection architecture.
It opens up fluted on the top end face of substrate described in the utility model setting plastic-sealed body, is controlled in groove embedded with power supply
Chip, the bottom face of power supply control chip 8 are electrically connected with the RDL wiring in substrate, the top end face and multicore of power supply control chip
The weld pad of piece interconnection architecture bottom face is electrically connected.The utility model is to meet being embedded in for power supply control chip, will be arranged fluted
The RDL wiring at place is routed height lower than the RDL of substrate other positions；To guarantee that power supply control chip and multi-chip interconnection architecture connect
The fastness connect is not provided with remaining cavity and power supply control chip and multi-chip interconnection architecture of power supply control chip in groove
Between positioned by the filled layer that is formed by filler.
Multi-chip interconnection architecture includes multiple independent chips, and neighbouring chip chamber is connected by adhesive layer 3, is bonded
The silicon perforation 4 placed for connecting neighbouring chip electric connection structure is provided in layer；The electricity of the neighbouring chip chamber
Connection structure is the connection of copper-connection or soldered ball and weld pad.Chip scale in the utility model, in multi-chip interconnection architecture
Model may be the same or different.
The preparation method of the utility model is as described below.
Step 1 opens up more slightly larger than power supply control chip volume on the substrate for being built-in with RDL wiring according to design requirement
Groove；The depth of groove and the thickness of power supply control chip are identical, after guaranteeing that power supply control chip installs, top end face
It is located at sustained height with the top end face of substrate, as shown in Figure 3.
The power supply control chip for having formed TSV is put into the groove of substrate by step 2, the bottom end in the hole TSV and substrate
Electrical connection；As shown in Figure 4.
The multi-chip interconnection architecture being laminated is electrically connected by step 3 using welding manner with power supply control chip；Make more
Chip Vertical is stacked on power supply control chip, as shown in Figure 5.
Step 4 fills out the gap between the cavity and multi-chip interconnection architecture and power supply control chip in groove
It fills to form filled layer；As shown in Figure 6.In the present embodiment, epoxy resin is filled into groove by the way of capillary
In gap between cavity and multi-chip interconnection architecture and power supply control chip.
Step 5 carries out plastic packaging to whole, and is implanted into soldered ball in substrate bottom face, as shown in fig. 7, to complete semiconductor
Encapsulation.
Claims (5)
1. semiconductor package, including substrate (6), it is provided with soldered ball on the bottom face of substrate, is arranged on the top end face of substrate
Have plastic-sealed body (1), plastic-sealed body is built-in with the stacked multi-chip interconnection architecture being electrically connected with substrate；It is characterized by: the base
The groove that embedded power supply control chip (8) are offered on the top end face of plate setting plastic-sealed body, the power supply control being inlaid in groove
Chip (8) bottom face is electrically connected with the RDL wiring in substrate, the top end face of power supply control chip and multi-chip interconnection architecture bottom end
The weld pad in face is electrically connected；The groove be not provided with power supply control chip remaining cavity and power supply control chip and multi-chip it is mutual
It is coupled between structure and is positioned by the filled layer formed by filler.
2. semiconductor package according to claim 1, it is characterised in that: the multi-chip interconnection architecture includes multiple
Independent chip, neighbouring chip chamber are connected by adhesive layer (3), and placement is provided in adhesive layer for connecting phase up and down
The silicon perforation (4) of adjacent chip electric connection structure.
3. semiconductor package according to claim 2, it is characterised in that: the electric connection structure of neighbouring chip chamber
For the connection of copper-connection or soldered ball and weld pad.
4. semiconductor package according to claim 1, it is characterised in that: the RDL of groove is arranged in the substrate
Wiring is routed height lower than the RDL of substrate other positions.
5. semiconductor package according to claim 1, it is characterised in that: the multi-chip interconnection architecture vertical stacking
In on the power supply control chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821531098.3U CN208674106U (en) | 2018-09-19 | 2018-09-19 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821531098.3U CN208674106U (en) | 2018-09-19 | 2018-09-19 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208674106U true CN208674106U (en) | 2019-03-29 |
Family
ID=65842551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821531098.3U Expired - Fee Related CN208674106U (en) | 2018-09-19 | 2018-09-19 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208674106U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109244058A (en) * | 2018-09-19 | 2019-01-18 | 深圳铨力半导体有限公司 | Semiconductor package and preparation method thereof |
-
2018
- 2018-09-19 CN CN201821531098.3U patent/CN208674106U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109244058A (en) * | 2018-09-19 | 2019-01-18 | 深圳铨力半导体有限公司 | Semiconductor package and preparation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190329 Termination date: 20210919 |