CN110957306A - Multi-layer chip substrate and packaging method, multifunctional chip packaging method and wafer - Google Patents
Multi-layer chip substrate and packaging method, multifunctional chip packaging method and wafer Download PDFInfo
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- CN110957306A CN110957306A CN201811128123.8A CN201811128123A CN110957306A CN 110957306 A CN110957306 A CN 110957306A CN 201811128123 A CN201811128123 A CN 201811128123A CN 110957306 A CN110957306 A CN 110957306A
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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Abstract
The invention discloses a multilayer chip substrate and a packaging method, a multifunctional chip packaging method and a wafer, wherein the multilayer chip substrate packaging method comprises the steps of respectively manufacturing circuit layers at the bottom and the top of a detachable bearing plate with copper foil; manufacturing a metal column and a first through hole; flip-chip welding the micro-bump chip and the large solder ball chip on the circuit layer, placing the micro-bump chip and the large solder ball chip in the first through hole, covering the surface of the micro-bump chip with the large solder ball chip, and enabling the height of the metal column to be larger than that of the large solder ball chip; manufacturing a first organic resin layer; cutting off the first organic resin layer to expose the metal posts; manufacturing a metal layer and at least one first inner layer circuit layer; manufacturing a first solder mask layer; splitting the multilayer chip wafer and the bearing plate, and exposing the copper foil; and removing the copper foil to expose the circuit layer. By implementing the invention, the micro bump chip and the large solder ball chip are packaged in a fan-out type, so that a multi-layer chip substrate is formed, the process efficiency and the integration level are improved, the size of a structural module is reduced, and the packaging cost is reduced.
Description
Technical Field
The invention relates to the technical field of microelectronic packaging, in particular to a multilayer chip substrate, a packaging method, a multifunctional chip packaging method and a wafer.
Background
With the increasing requirements of the technical development on the performance, size, cost and the like of microelectronic devices, especially the requirements of consumer products (such as mobile terminals and the like) on the thickness and the like of products are higher, so that the chip packaging scheme which can be smaller, lighter, better in performance and lower in price becomes the current technical research direction.
The fan-out wafer level packaging process has become a development direction of electronic consumer products due to its thinness, shortness, smallness, and small size, however, the existing wafer level packaging process is complex in process, requires high equipment and packaging materials, causes high packaging cost, and is only suitable for high-end products.
At present, in order to reduce cost and improve chip universality, a stacked chip fan-in type packaging method is mostly adopted in a multilayer chip packaging method, a plurality of chips are stacked on a substrate layer by layer, interconnection is realized through leads, and then curing packaging is carried out by adopting a traditional plastic package adhesive mode. However, in the chip structure packaged by the existing stacked chip fan-in type packaging method, because a plurality of chips are tiled on the substrate in two dimensions, the module has a large volume, long electrical leads and low integration level, and a multi-layer chip fan-out type packaging structure cannot be realized.
Disclosure of Invention
The invention aims to overcome the defects that a multilayer chip packaging structure in the prior art is large in size, low in integration level and incapable of realizing a fan-out type packaging structure of a multilayer chip, and provides a multilayer chip substrate, a packaging method, a multifunctional chip packaging method and a wafer.
The technical scheme of the invention provides a multilayer chip substrate packaging method, which comprises the following steps:
respectively manufacturing a circuit layer at the bottom and the top of the detachable bearing plate with the copper foil;
manufacturing a metal column on the circuit layer, and manufacturing a first through hole on the metal column, wherein the metal column is electrically interconnected with the circuit layer;
flip-chip bonding a micro-bump chip and a large solder ball chip on the circuit layer, wherein the micro-bump chip and the large solder ball chip are arranged in the first through hole, the large solder ball chip covers the surface of the micro-bump chip, and the height of the metal column is greater than that of the large solder ball chip;
embedding the micro bump chip and the large solder ball chip in a first organic resin layer to obtain a multilayer chip wafer;
cutting off the first organic resin layer to expose the metal column;
manufacturing a metal layer covering the first organic resin layer, and manufacturing at least one first inner layer circuit layer covering the metal layer;
manufacturing a first solder mask layer covering the first inner layer circuit layer;
detaching the multilayer chip wafer from the bearing plate at the detachable position of the bearing plate, and exposing the copper foil;
and removing the copper foil to expose the circuit layer to obtain the multilayer chip substrate.
Further, the circuit layers are respectively manufactured at the bottom and the top of the detachable substrate with the copper foil, and the method specifically comprises the following steps:
manufacturing second inner-layer circuit layers at the bottom and the top of the bearing plate respectively, and manufacturing a second through hole penetrating through the second inner-layer circuit layers on the second inner-layer circuit layers and exposing the copper foil;
manufacturing a dielectric layer covering the second inner layer circuit layer;
removing the dielectric layer at the position corresponding to the second through hole to form a blind hole;
manufacturing at least one outer layer circuit layer at a position corresponding to the blind hole, and electrically interconnecting the outer layer circuit layer and the second inner layer circuit layer;
and manufacturing a second solder mask layer covering the outer layer circuit layer to form the circuit layer.
The technical scheme of the invention provides a multifunctional chip packaging method, which comprises the following steps:
superposing a multifunctional chip on the circuit layer of the multilayer chip substrate packaged by using the multilayer chip substrate packaging method as described above;
manufacturing an electric interconnection line to electrically connect the multifunctional chip and the circuit layer of the multilayer chip substrate;
and embedding the multifunctional chip in a second organic resin layer to obtain a multifunctional chip wafer.
Further, the multifunctional chip comprises an application specific integrated circuit chip or a micro electro mechanical system chip.
Further, the embedding of the multifunctional chip in a second organic resin layer to obtain a multifunctional chip wafer further includes:
and manufacturing a solder ball array ball on the first solder mask layer of the multilayer chip substrate.
The technical scheme of the invention provides a multilayer chip substrate which comprises a substrate assembly, wherein the substrate assembly comprises a circuit layer, a metal column is arranged on the circuit layer and electrically interconnected with the circuit layer, a first through hole is formed in the metal column, a micro bump chip and a large solder ball chip which are embedded in a first organic resin layer are welded in the first through hole in an inverted mode, the large solder ball chip covers the surface of the micro bump chip, the height of the metal column is larger than that of the large solder ball chip, a metal layer is arranged on the first organic resin layer, at least one first inner layer circuit layer covering the metal layer is arranged on the metal layer, and a first solder mask layer is arranged on the first inner layer circuit layer.
Further, the circuit layer includes second inlayer circuit layer, be provided with on the second inlayer circuit layer and pierce through the second through-hole on second inlayer circuit layer, be provided with the cover on the second inlayer circuit layer the dielectric layer on second inlayer circuit layer, the dielectric layer with the position that the second through-hole corresponds is provided with the blind hole the position that the blind hole corresponds be provided with at least one deck with the outer circuit layer of second inlayer circuit layer electricity interconnection be provided with the cover on the outer circuit layer the second solder mask on outer circuit layer.
Furthermore, the multilayer chip substrate comprises at least two substrate assemblies, and the adjacent substrate assemblies are connected through a detachable loading plate with copper foil.
The technical scheme of the invention provides a multifunctional chip wafer which comprises a multifunctional chip embedded in a second organic resin layer and the multilayer chip substrate, wherein the multifunctional chip is superposed on the circuit layer of the multilayer chip substrate, and the multifunctional chip is electrically connected with the multilayer chip substrate through an electric interconnection line.
Further, the multifunctional chip comprises an application specific integrated circuit chip or a micro electro mechanical system chip.
Furthermore, the first solder mask layer of the multilayer chip substrate is provided with solder ball array balls.
After adopting above-mentioned technical scheme, have following beneficial effect: the micro-bump chips and the large solder ball chips are packaged in a fan-out mode on the two sides of the bearing plate, so that a multi-layer chip substrate is formed, the process efficiency is improved, the size of the chip can be packaged in a fan-out mode with the multifunctional chip, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro-bump chip and the large solder ball chip can be shielded and isolated from the upper multifunctional chip to be packaged through the circuit layer, thereby avoiding crosstalk and improving performance.
Drawings
The disclosure of the present invention will become more readily understood by reference to the drawings. It should be understood that: these drawings are for illustrative purposes only and are not intended to limit the scope of the present disclosure. In the figure:
fig. 1 is a schematic workflow diagram of a multilayer chip substrate packaging method according to an embodiment of the present invention;
FIG. 2 is a schematic view of a work flow of a method for packaging a multi-layered chip substrate according to an alternative embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for packaging a multifunctional chip according to an embodiment of the present invention;
FIG. 4 is a schematic workflow diagram of a method for packaging a multifunctional chip according to an alternative embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a multi-layered chip substrate according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a multi-layered chip substrate according to an alternative embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a multifunctional chip wafer according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a multifunctional chip wafer according to an alternative embodiment of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the accompanying drawings.
It is easily understood that according to the technical solution of the present invention, those skilled in the art can substitute various structures and implementation manners without changing the spirit of the present invention. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the technical aspects of the present invention, and should not be construed as limiting or restricting the technical aspects of the present invention.
The terms of orientation of up, down, left, right, front, back, top, bottom, and the like referred to or may be referred to in this specification are defined relative to the configuration shown in the drawings, and are relative terms, and thus may be changed correspondingly according to the position and the use state of the device. Therefore, these and other directional terms should not be construed as limiting terms.
Example one
As shown in fig. 1, fig. 1 is a schematic workflow diagram of a multilayer chip substrate packaging method according to an embodiment of the present invention, including:
step S101: respectively manufacturing a circuit layer 12 at the bottom and the top of a detachable bearing plate 11 with copper foil;
step S102: manufacturing a metal pillar 13 on the circuit layer 12, and manufacturing a first through hole on the metal pillar 13, wherein the metal pillar 13 is electrically interconnected with the circuit layer 12;
step S103: flip-chip bonding a micro bump chip 14 and a large solder ball chip 15 on the circuit layer 12, wherein the micro bump chip 14 and the large solder ball chip 15 are placed in the first through hole, the large solder ball chip 15 covers the surface of the micro bump chip 14, and the height of the metal column 13 is greater than that of the large solder ball chip 15;
step S104: embedding the micro bump chip 14 and the large solder ball chip 15 in a first organic resin layer 16 to obtain a multilayer chip wafer;
step S105: cutting off the first organic resin layer 16 to expose the metal posts 13;
step S106: manufacturing a metal layer covering the first organic resin layer 16, and manufacturing at least one first inner layer circuit layer 17 covering the metal layer;
step S107: manufacturing a first solder mask layer 18 covering the first inner layer circuit layer 17;
step S108: detaching the multilayer chip wafer from the carrier board 11 at a detachable portion of the carrier board 11 and exposing the copper foil;
step S109: and removing the copper foil to expose the circuit layer 12 to obtain the multilayer chip substrate 19.
Specifically, the method comprises the following steps:
step S101, manufacturing a circuit layer: manufacturing a circuit layer 12 on a bearing plate 11 with detachable ultrathin copper foils on two sides through the process steps of exposure, development, pattern electroplating, film stripping and the like;
step S102, manufacturing a metal column: processing an ultrahigh metal column (copper column) 13 in an outward leading-out area corresponding to the circuit layer 12, wherein the metal column 13 is used for interconnection between an upper layer and a lower layer and interconnection between a chip and the outside;
step S103, flip-chip bonding of a micro bump chip and a C4bump chip: flip-chip bonding of a micro bump (micro bump) chip 14 and a large solder ball (C4bump) chip 15 requires that the height of the large solder ball after reflow is greater than the overall height of the micro bump chip 14 after flip-chip bonding, and requires that the height of the metal column 13 is greater than the height of the C4bump chip 15 after flip-chip bonding, and the height of the metal column exceeds the height of the C4bump chip 15 after flip-chip bonding is realized mainly through the process steps of chemical seed layer plating, super-thick dry film mounting, exposure, development, copper column electroplating, film stripping flash etching and the like;
step S104, plastic molding (EMC): carrying out double-sided plastic package by adopting a plastic package device, so that the microbump chip 14 and the C4bump chip 15 can be embedded into the first organic resin layer 16;
step S105, EMC thinning: thinning the plastic-sealed surface of the first organic resin layer 16 until the metal column 13 is exposed to the outside;
step S106, RDL making: metallization and fabrication of the first inner layer line layer 17 are performed on the material of the EMC, and the fabrication of multiple layers of RDL on the EMC surface can be repeated to form a high-density interconnect structure;
step S107, solder resist green oil: solder resist green oil is manufactured on the first inner layer circuit layer 17, and the green oil window of the layer is mainly a green oil window for planting BGA solder balls;
step S108, splitting, processing and packaging two surfaces: and splitting the manufactured panel on the detachable copper foil surface of the bearing plate 11 to form two layers of manufactured packaging structures embedded with two layers of chip substrates.
Step S109, removing the copper foil: and etching the separated ultrathin copper foil by adopting an etching process so as to form a structure of the packaging substrate with the completely embedded chip.
According to the multilayer chip substrate packaging method provided by the embodiment, the micro-bump chips and the large solder ball chips are packaged in a fan-out mode on the two sides of the bearing plate, so that the multilayer chip substrate is formed, the process efficiency is improved, the size of the multilayer chip substrate can be packaged in a fan-out mode with the multifunctional chips, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro-bump chip and the large solder ball chip can be shielded and isolated from the upper multifunctional chip to be packaged through the circuit layer, thereby avoiding crosstalk and improving performance.
Example two
As shown in fig. 2, fig. 2 is a schematic workflow diagram of a multilayer chip packaging method according to an alternative embodiment of the present invention, including:
step S201: manufacturing a second inner-layer circuit layer 121 on the bottom and the top of the carrier board 11, respectively, and manufacturing a second through hole 122 penetrating through the second inner-layer circuit layer on the second inner-layer circuit layer 121, and exposing the copper foil;
step S202: manufacturing a dielectric layer 123 covering the second inner circuit layer 122;
step S203: removing the dielectric layer 123 at a position corresponding to the second through hole 122 to form a blind hole 124;
step S204: manufacturing at least one outer layer circuit layer 125 at a position corresponding to the blind hole 124, so that the outer layer circuit layer 125 and the second inner layer circuit layer 121 are electrically interconnected;
step S205: manufacturing a second solder mask layer 126 covering the outer layer circuit layer 125 to form a circuit layer 12;
step S206: manufacturing a metal pillar 13 on the circuit layer 12, and manufacturing a first through hole on the metal pillar 13, wherein the metal pillar 13 is electrically interconnected with the circuit layer 12;
step S207: flip-chip bonding a micro bump chip 14 and a large solder ball chip 15 on the circuit layer 12, wherein the micro bump chip 14 and the large solder ball chip 15 are placed in the first through hole, the large solder ball chip 15 covers the surface of the micro bump chip 14, and the height of the metal column 13 is greater than that of the large solder ball chip 15;
step S208: embedding the micro bump chip 14 and the large solder ball chip 15 in a first organic resin layer 16 to obtain a multilayer chip wafer;
step S209: cutting off the first organic resin layer 16 to expose the metal posts 13;
step S210: manufacturing a metal layer covering the first organic resin layer 16, and manufacturing at least one first inner layer circuit layer 17 covering the metal layer;
step S211: manufacturing a first solder mask layer 18 covering the first inner layer circuit layer 17;
step S212: detaching the multilayer chip wafer from the carrier board 11 at a detachable portion of the carrier board 11 and exposing the copper foil;
step S213: and removing the copper foil to expose the circuit layer 12 to obtain the multilayer chip substrate 19.
Specifically, the method comprises the following steps:
step S201, RDL making: the second inner circuit layer 121 pattern is manufactured on the bearing plate 11 with the detachable ultrathin copper foil on two sides through the process steps of exposure, development, pattern electroplating, film stripping and the like, and the pattern can meet the requirements of the mode of flip chip or binding assembly of the uppermost chip and the like. Supporting the assembly requirement of the upper chip of the whole system, and corresponding to the same pattern form on two sides of the core board, thereby developing the packaging process according to the simultaneous double-sided process;
step S202, laminating a dielectric layer: laminating a dielectric layer 123 on the second inner circuit layer 121 pattern by a high temperature press or a vacuum press, so as to embed the second inner circuit layer 121 into the dielectric layer 123;
step S203, manufacturing an interconnection blind hole: laser drilling an interconnection blind hole 124 at the position of the corresponding interconnection pad so as to form interconnection between the second inner layer line layer 121 and the upper layer line;
step S204, manufacturing an outer layer circuit: the outer wiring layer 125 is fabricated by electroless copper plating, film pressing, exposure, development, pattern & hole filling plating, film stripping, flash etching, and the like. Meanwhile, the steps S202-S204 can be repeated to manufacture a plurality of layers of RDLs, and then a plurality of layers of interconnected redistribution layers are manufactured;
step S205, solder resist green oil preparation: a second solder resist layer 126 is formed on the wiring layer of the outer wiring layer 125 for solder resist required for flip chip bonding and corresponding to the size of the bump of the chip in the green oil window to form the wiring layer 12.
According to the multilayer chip substrate packaging method provided by the embodiment, the micro-bump chips and the large solder ball chips are packaged in a fan-out mode on the two sides of the bearing plate, so that the multilayer chip substrate is formed, the process efficiency is improved, the size of the multilayer chip substrate can be packaged in a fan-out mode with the multifunctional chips, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro-bump chip and the large solder ball chip can be shielded and isolated from the upper multifunctional chip to be packaged through the circuit layer, thereby avoiding crosstalk and improving performance.
EXAMPLE III
As shown in fig. 3, fig. 3 is a schematic workflow diagram of a multifunctional chip packaging method according to an embodiment of the present invention, including:
step S301: superposing a multifunctional chip 20 on the wiring layer 12 of the multilayer chip substrate 19 packaged using the multilayer chip substrate packaging method as described previously;
step S302: making an electrical interconnection line 21 to electrically connect the multifunctional chip 20 with the circuit layer 12 of the multilayer chip substrate 19;
step S303: the multifunctional chip 20 is embedded in the second organic resin layer 22 to obtain a multifunctional chip wafer.
Specifically, the method comprises the following steps:
step S301, mounting a multifunctional chip: the multi-layer chip substrate 19 is used as a substrate for mounting or flip-chip bonding of the multi-functional chip 20, such as an integrated circuit chip, a micro electro mechanical system chip and the like, and particularly, the mounting of the multi-functional chip 20 can be realized in a way of mounting adhesive during normal mounting or the bonding can be directly realized in a flip-chip bonding way;
step S302, manufacturing an interconnection line: when the multifunction chip 20 is mounted in the face-up mounting manner, the multifunction chip 20 is electrically interconnected with the wiring layer 12 of the multilayer chip substrate 19 by binding the electrical interconnection 21. When the multifunction chip 20 is mounted by flip-chip bonding, the multifunction chip 20 is electrically interconnected with the wiring layer 12 of the multilayer chip substrate 19 by underfill (underfill).
Step S303, plastic molding (EMC): and (3) performing plastic packaging by using a plastic packaging device, so that the multifunctional chip 20 can be embedded into the second organic resin layer 22, and obtaining the multifunctional chip wafer.
It should be noted that there may be one or more multifunctional chips 20, and the multifunctional chips 20 are packaged in steps S301 to S303, respectively, and only a circuit layer needs to be fabricated between the adjacent multifunctional chips 20, so as to interconnect the adjacent multifunctional chips 20. When the size of the plurality of multifunction chips 20 is small, two or more of the multifunction chips 20 may be stacked in parallel on the wiring layer 12 of the multilayer chip substrate 19, and then steps S302 to S303 may be performed.
According to the multifunctional chip packaging method provided by the embodiment, the multifunctional chip is stacked on the circuit layer of the multilayer chip substrate and packaged, so that the fan-out type packaging of the multifunctional chip and the multilayer chip substrate is realized, the process efficiency is improved, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro bump chip, the large solder ball chip and the multifunctional chip can be shielded and isolated through the circuit layer, so that crosstalk is avoided, and the performance is improved.
Example four
As shown in fig. 4, fig. 4 is a schematic workflow diagram of a multifunctional chip packaging method according to an alternative embodiment of the present invention, including:
step S401: superposing a multifunctional chip 20 on the wiring layer 12 of the multilayer chip substrate 19 packaged using the multilayer chip substrate packaging method as described previously;
step S402: making an electrical interconnection line 21 to electrically connect the multifunctional chip 20 with the circuit layer 12 of the multilayer chip substrate 19;
step S403: embedding the multifunctional chip 20 in a second organic resin layer 22 to obtain a multifunctional chip wafer;
step S404: and manufacturing solder ball array balls 23 on the first solder mask layer 18 of the multilayer chip substrate 19.
Specifically, the method comprises the following steps:
step S404, planting BGA balls: and (4) planting balls at the positions of the corresponding BGA solder ball bonding pads so as to finish the direct connection port between the BGA solder ball bonding pads and the outside, and performing singulation and sorting to finish the whole packaging.
According to the multifunctional chip packaging method provided by the embodiment, the multifunctional chip is stacked on the circuit layer of the multilayer chip substrate and packaged, so that the fan-out type packaging of the multifunctional chip and the multilayer chip substrate is realized, the process efficiency is improved, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro bump chip, the large solder ball chip and the multifunctional chip can be shielded and isolated through the circuit layer, so that crosstalk is avoided, and the performance is improved. Meanwhile, the BGA ball is directly manufactured on the back surface of the first solder mask layer of the multi-layer chip substrate and led out to the outside, so that the transmission of high-speed signals of the multifunctional chip can be guaranteed.
EXAMPLE five
As shown in fig. 5, fig. 5 is a schematic structural diagram of a multi-layer chip substrate according to an embodiment of the present invention, which includes a substrate assembly, the substrate assembly includes a circuit layer 12, a metal pillar 13 is disposed on the circuit layer, the metal pillar 13 is electrically interconnected with the circuit layer 12, a first through hole is disposed on the metal pillar 13, a micro bump chip 14 and a large solder ball chip 15 embedded in a first organic resin layer 16 are flip-chip bonded in the first through hole, the large solder ball chip 15 covers a surface of the micro bump chip 14, a height of the metal pillar 13 is greater than a height of the large solder ball chip 15, a metal layer is disposed on the first organic resin layer 16, at least one first inner layer circuit layer 17 covering the metal layer is disposed on the metal layer, and a first solder resist layer 18 is disposed on the first inner layer circuit layer 17.
The multilayer chip substrate provided by the embodiment adopts fan-out type packaging to the micro-bump chip and the large solder ball chip to form the multilayer chip substrate, so that the process efficiency is improved, the size of the multilayer chip substrate can be enabled to realize fan-out type packaging with the multifunctional chip, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro-bump chip and the large solder ball chip can be shielded and isolated from the upper multifunctional chip to be packaged through the circuit layer, thereby avoiding crosstalk and improving performance.
Optionally, the circuit layer includes a second inner circuit layer 121, a second through hole 122 penetrating through the second inner circuit layer 121 is provided on the second inner circuit layer 121, a dielectric layer 123 covering the second inner circuit layer 121 is provided on the second inner circuit layer 121, a blind hole 124 is provided at a position corresponding to the second through hole 122 at least one layer of an outer circuit layer 125 electrically interconnected with the second inner circuit layer 121 is provided at a position corresponding to the blind hole 124, and a second solder resist layer 126 covering the outer circuit layer 125 is provided on the outer circuit layer 125.
The multilayer chip substrate provided by the embodiment further improves the process efficiency, improves the integration level, reduces the size of the structure module and reduces the cost by arranging the dielectric layer and the outer layer circuit layer on the second inner layer circuit layer and arranging the second solder mask layer covering the outer layer circuit layer on the outer layer circuit layer.
EXAMPLE six
As shown in fig. 6, fig. 6 is a schematic structural diagram of a multi-layer chip substrate according to an alternative embodiment of the present invention, which includes two substrate assemblies, where adjacent substrate assemblies are connected by a detachable carrier 11 with copper foil, each substrate assembly includes a circuit layer 12, a metal pillar 13 is disposed on the circuit layer, the metal pillar 13 is electrically connected to the circuit layer 12, a first through hole is disposed on the metal pillar 13, a micro bump chip 14 and a large solder ball chip 15 embedded in a first organic resin layer 16 are flip-chip bonded in the first through hole, the large solder ball chip 15 covers the surface of the micro bump chip 14, the height of the metal pillar 13 is greater than that of the large solder ball chip 15, a metal layer is disposed on the first organic resin layer 16, at least one first inner-layer circuit layer 17 covering the metal layer is disposed on the metal layer, a first solder resist layer 18 is provided on the first inner layer wiring layer 17.
The multilayer chip substrate provided by the embodiment adopts fan-out type packaging to the micro-bump chip and the large solder ball chip on two sides of the bearing plate simultaneously to form the multilayer chip substrate, so that the process efficiency is improved, the size of the multilayer chip substrate can be realized with the multifunctional chip to realize fan-out type packaging, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro-bump chip and the large solder ball chip can be shielded and isolated from the upper multifunctional chip to be packaged through the circuit layer, thereby avoiding crosstalk and improving performance.
Optionally, the circuit layer includes a second inner circuit layer 121, a second through hole 122 penetrating through the second inner circuit layer 121 is provided on the second inner circuit layer 121, a dielectric layer 123 covering the second inner circuit layer 121 is provided on the second inner circuit layer 121, a blind hole 124 is provided at a position corresponding to the second through hole 122 at least one layer of an outer circuit layer 125 electrically interconnected with the second inner circuit layer 121 is provided at a position corresponding to the blind hole 124, and a second solder resist layer 126 covering the outer circuit layer 125 is provided on the outer circuit layer 125.
The multilayer chip substrate provided by the embodiment further improves the process efficiency, improves the integration level, reduces the size of the structure module and reduces the cost by arranging the dielectric layer and the outer layer circuit layer on the second inner layer circuit layer and arranging the second solder mask layer covering the outer layer circuit layer on the outer layer circuit layer.
EXAMPLE seven
As shown in fig. 7, fig. 7 is a schematic structural diagram of a multifunctional chip wafer according to an embodiment of the present invention, which includes a multifunctional chip 20 embedded in a second organic resin layer 22, and the multilayer chip substrate 19 as described above, wherein the multifunctional chip 20 is stacked on the circuit layer 12 of the multilayer chip substrate 19, and the multifunctional chip 20 is electrically connected to the multilayer chip substrate 19 through an electrical interconnection 21.
The multifunctional chip wafer provided by the embodiment is stacked on the circuit layer of the multilayer chip substrate through the multifunctional chip and packaged, so that the fan-out type packaging of the multifunctional chip and the multilayer chip substrate is realized, the process efficiency is improved, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro bump chip, the large solder ball chip and the multifunctional chip can be shielded and isolated through the circuit layer, so that crosstalk is avoided, and the performance is improved.
Example eight
As shown in fig. 8, fig. 8 is a schematic structural diagram of a multifunctional chip wafer according to an alternative embodiment of the present invention, which includes a multifunctional chip 20 embedded in a second organic resin layer 22, and the multilayer chip substrate 19 as described above, where the multifunctional chip 20 is stacked on the circuit layer 12 of the multilayer chip substrate 19, the multifunctional chip 20 is electrically connected to the multilayer chip substrate 19 through an electrical interconnection line 21, and a solder ball array ball 23 is disposed on the first solder mask layer 18 of the multilayer chip substrate 19.
The multifunctional chip wafer provided by the embodiment is stacked on the circuit layer of the multilayer chip substrate through the multifunctional chip and packaged, so that the fan-out type packaging of the multifunctional chip and the multilayer chip substrate is realized, the process efficiency is improved, the integration level is improved, the size of the structural module is reduced, and the packaging cost is reduced. And the micro bump chip, the large solder ball chip and the multifunctional chip can be shielded and isolated through the circuit layer, so that crosstalk is avoided, and the performance is improved. Meanwhile, the BGA ball is directly manufactured on the back surface of the first solder mask layer of the multi-layer chip substrate and led out to the outside, so that the transmission of high-speed signals of the multifunctional chip can be guaranteed.
The foregoing is considered as illustrative only of the principles and preferred embodiments of the invention. It should be noted that, for those skilled in the art, several other modifications can be made on the basis of the principle of the present invention, and the protection scope of the present invention should be regarded.
Claims (11)
1. A method for packaging a multi-layer chip substrate, comprising:
respectively manufacturing a circuit layer at the bottom and the top of the detachable bearing plate with the copper foil;
manufacturing a metal column on the circuit layer, and manufacturing a first through hole on the metal column, wherein the metal column is electrically interconnected with the circuit layer;
flip-chip bonding a micro-bump chip and a large solder ball chip on the circuit layer, wherein the micro-bump chip and the large solder ball chip are arranged in the first through hole, the large solder ball chip covers the surface of the micro-bump chip, and the height of the metal column is greater than that of the large solder ball chip;
embedding the micro bump chip and the large solder ball chip in a first organic resin layer to obtain a multilayer chip wafer;
cutting off the first organic resin layer to expose the metal column;
manufacturing a metal layer covering the first organic resin layer, and manufacturing at least one first inner layer circuit layer covering the metal layer;
manufacturing a first solder mask layer covering the first inner layer circuit layer;
detaching the multilayer chip wafer from the bearing plate at the detachable position of the bearing plate, and exposing the copper foil;
and removing the copper foil to expose the circuit layer to obtain the multilayer chip substrate.
2. The method for packaging a multi-layered chip substrate according to claim 1, wherein the step of respectively forming circuit layers on the bottom and the top of the detachable substrate with copper foil comprises:
manufacturing second inner-layer circuit layers at the bottom and the top of the bearing plate respectively, and manufacturing a second through hole penetrating through the second inner-layer circuit layers on the second inner-layer circuit layers and exposing the copper foil;
manufacturing a dielectric layer covering the second inner layer circuit layer;
removing the dielectric layer at the position corresponding to the second through hole to form a blind hole;
manufacturing at least one outer layer circuit layer at a position corresponding to the blind hole, and electrically interconnecting the outer layer circuit layer and the second inner layer circuit layer;
and manufacturing a second solder mask layer covering the outer layer circuit layer to form the circuit layer.
3. A multifunctional chip packaging method is characterized by comprising the following steps:
superposing a multifunctional chip on the wiring layer of the multilayer chip substrate packaged using the multilayer chip substrate packaging method according to claim 1 or 2;
manufacturing an electric interconnection line to electrically connect the multifunctional chip and the circuit layer of the multilayer chip substrate;
and embedding the multifunctional chip in a second organic resin layer to obtain a multifunctional chip wafer.
4. The multi-function chip packaging method of claim 3, wherein the multi-function chip comprises an application specific integrated circuit chip or a micro electro mechanical system chip.
5. The multi-function chip packaging method according to claim 3 or 4, wherein said embedding said multi-function chip in a second organic resin layer to obtain a multi-function chip wafer, further comprising:
and manufacturing a solder ball array ball on the first solder mask layer of the multilayer chip substrate.
6. The utility model provides a multilayer chip substrate, a serial communication port, including the base plate subassembly, the base plate subassembly includes the circuit layer, be provided with the metal post on the circuit layer, the metal post with circuit layer electricity interconnection, be provided with first through-hole on the metal post, the welding of falling the dress in the first through-hole has the little bump chip of embedding in first organic resin layer and big solder ball chip, big solder ball chip covers the surface of little bump chip, the height of metal post is greater than the height of big solder ball chip set up the metal level on the first organic resin layer be provided with at least one deck cover on the metal level the first inlayer circuit layer of metal level set up first solder mask on the first inlayer circuit layer.
7. The multilayer chip substrate according to claim 6, wherein the circuit layer comprises a second inner circuit layer, the second inner circuit layer is provided with a second through hole penetrating through the second inner circuit layer, the second inner circuit layer is provided with a dielectric layer covering the second inner circuit layer, the dielectric layer is provided with a blind hole at a position corresponding to the second through hole, at least one outer circuit layer electrically interconnected with the second inner circuit layer is provided at a position corresponding to the blind hole, and a second solder resist layer covering the outer circuit layer is provided on the outer circuit layer.
8. The multilayer chip substrate according to claim 6 or 7, wherein the multilayer chip substrate comprises at least two of the substrate assemblies, and adjacent substrate assemblies are connected by a detachable copper foil-bearing carrier plate.
9. A multifunctional chip wafer comprising a multifunctional chip embedded in a second organic resin layer, and the multilayer chip substrate according to any one of claims 6 to 8, the multifunctional chip being superimposed on the wiring layer of the multilayer chip substrate, the multifunctional chip being electrically connected to the multilayer chip substrate through an electrical interconnection line.
10. The multifunctional chip wafer of claim 9, wherein the multifunctional chip comprises an application specific integrated circuit chip or a microelectromechanical system chip.
11. The multifunctional chip wafer according to claim 9 or 10, wherein a ball array ball is provided on the first solder resist layer of the multilayer chip substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811128123.8A CN110957306A (en) | 2018-09-27 | 2018-09-27 | Multi-layer chip substrate and packaging method, multifunctional chip packaging method and wafer |
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| CN201811128123.8A CN110957306A (en) | 2018-09-27 | 2018-09-27 | Multi-layer chip substrate and packaging method, multifunctional chip packaging method and wafer |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038321A (en) * | 2020-08-10 | 2020-12-04 | 唯捷创芯(天津)电子技术股份有限公司 | Metal via hole connection packaging structure, substrate and packaging method |
| CN112652542A (en) * | 2020-12-22 | 2021-04-13 | 厦门通富微电子有限公司 | Three-dimensional stacked fan-out type chip packaging method and packaging structure |
| CN112670278A (en) * | 2020-12-23 | 2021-04-16 | 成都海光集成电路设计有限公司 | Chip packaging structure and chip packaging method |
-
2018
- 2018-09-27 CN CN201811128123.8A patent/CN110957306A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112038321A (en) * | 2020-08-10 | 2020-12-04 | 唯捷创芯(天津)电子技术股份有限公司 | Metal via hole connection packaging structure, substrate and packaging method |
| CN112652542A (en) * | 2020-12-22 | 2021-04-13 | 厦门通富微电子有限公司 | Three-dimensional stacked fan-out type chip packaging method and packaging structure |
| CN112652542B (en) * | 2020-12-22 | 2023-06-16 | 厦门通富微电子有限公司 | Three-dimensional stacked fan-out chip packaging method and packaging structure |
| CN112670278A (en) * | 2020-12-23 | 2021-04-16 | 成都海光集成电路设计有限公司 | Chip packaging structure and chip packaging method |
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