CN112652542B - Three-dimensional stacked fan-out chip packaging method and packaging structure - Google Patents
Three-dimensional stacked fan-out chip packaging method and packaging structure Download PDFInfo
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- CN112652542B CN112652542B CN202011528251.9A CN202011528251A CN112652542B CN 112652542 B CN112652542 B CN 112652542B CN 202011528251 A CN202011528251 A CN 202011528251A CN 112652542 B CN112652542 B CN 112652542B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
Abstract
The invention provides a three-dimensional stacked fan-out chip packaging method and a packaging structure, wherein the method comprises the following steps: providing a bearing sheet, wherein the bearing sheet comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the bearing sheet; forming a metal through hole on the first surface of the carrier sheet, and forming a first solder ball on the metal through hole; flip-chip the first chip on the first solder ball; forming a first metal wiring on the second surface of the carrier sheet, wherein the first metal wiring is electrically connected with the metal through hole; and forming second solder balls on the first metal wiring, and flip-chip mounting a second chip on the second solder balls to complete the three-dimensional stacked fan-out chip package. The invention realizes three-dimensional stacking of chips in such a way, cancels a lead structure, reduces the size of the chips and improves the utilization rate of the whole packaging structure.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to a three-dimensional stacked fan-out chip packaging method and a three-dimensional stacked fan-out chip packaging structure.
Background
With the trend of miniaturization of electronic products, electronic assembly technology with high heat dissipation efficiency is particularly important in new generation of electronic products. In order to match with the development of new generation electronic products, especially the development of smart phones, palm computers, super books and other products, the size of the chip is developed towards the directions of higher density, faster speed, smaller size, lower cost and the like. The three-dimensional stacked packaging structure of multiple chips meets the requirements of thinner chip product size, material saving and the like, and the three-dimensional stacked packaging is necessary because the three-dimensional stacked packaging can reduce the chip size and improve the utilization rate of the whole packaging structure.
The traditional method realizes the packaging of the chip by a wire bonding mode, and has the defects of large chip size, high cost and material waste. The lead frame packaging structure needs to manufacture the lead frame first and then attach the chip, so that the whole structure is large in size.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art and provides a three-dimensional stacked fan-out chip packaging method and a three-dimensional stacked fan-out chip packaging structure.
In one aspect of the invention, a method of three-dimensionally stacking fan-out core plates is provided, the method comprising:
providing a bearing sheet, wherein the bearing sheet comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the bearing sheet;
forming a metal through hole on the first surface of the carrier sheet, and forming a first solder ball on the metal through hole;
flip-chip the first chip on the first solder ball;
forming a first metal wiring on the second surface of the carrier sheet, wherein the first metal wiring is electrically connected with the metal through hole;
and forming second solder balls on the first metal wiring, and flip-chip mounting a second chip on the second solder balls to complete the three-dimensional stacked fan-out chip package.
In some alternative embodiments, after flip-chip the first chip on the first solder balls, the method further comprises:
and forming a first adhesive layer on the first surface of the carrier, wherein the first adhesive layer coats the first chip so as to fix the first chip on the first surface of the carrier.
In some alternative embodiments, the forming a first metal wire on the second surface of the carrier sheet includes:
forming a first passivation layer on a second surface of the carrier sheet;
patterning the first passivation layer to form a first via hole at a position corresponding to the metal via hole;
the first metal wiring is formed on the first via hole and the first passivation layer.
In some alternative embodiments, the forming a second solder ball on the first metal wire, flip-chip a second chip on the second solder ball, includes:
forming a first protection layer on the first metal wiring, and forming a second via hole on the first protection layer;
and forming the second solder ball in the second via hole, and flip-chip the second chip on the second solder ball.
In some alternative embodiments, after flip-chip mounting a second chip on the second solder balls, the method further comprises:
and forming a second adhesive layer on the first protective layer, wherein the second adhesive layer coats the second chip so as to fix the second chip on the second surface of the carrier sheet.
In some alternative embodiments, after forming a second glue layer on the first protective layer, the method further comprises:
forming a metal column penetrating through the second adhesive layer, wherein the metal column is electrically connected with the first metal wiring;
forming a second metal wiring on the second adhesive layer, wherein the second metal wiring is electrically connected with the metal column;
and forming a third solder ball on the second metal wiring.
In some optional embodiments, the forming a second metal wire on the second glue layer includes:
forming a second passivation layer on the second adhesive layer;
patterning the second passivation layer to form a third via hole at a position corresponding to the metal column;
and forming the second metal wiring on the third via hole and the second passivation layer.
In some optional embodiments, the forming a third solder ball on the second metal wire includes:
forming a second protection layer on the second metal wiring, and forming a fourth via hole on the second protection layer;
and forming the third solder ball in the fourth via hole.
In another aspect of the present invention, there is provided a three-dimensionally stacked fan-out chip package structure, the package structure including:
the bearing piece comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the bearing piece, and the bearing piece is provided with a metal through hole penetrating through the first surface and the second surface;
the first solder balls are arranged on the first surface of the carrier sheet and are electrically connected with the metal through holes;
the first chip is flip-chip mounted on the first solder balls;
the first metal wiring is arranged on the second surface of the carrier sheet and is electrically connected with the metal through hole;
the second solder balls are arranged on the first metal wiring;
and the second chip is inversely arranged on the second solder ball.
In some alternative embodiments, the package structure further includes:
the first adhesive layer is arranged on the first surface of the carrier sheet and coats the first chip;
the first passivation layer is arranged between the second surface of the carrier sheet and the first metal wiring, a first through hole is formed in the first passivation layer at a position corresponding to the metal through hole, and the first metal wiring is electrically connected with the metal through hole through the first through hole;
the first metal wiring is covered by the first protection layer, a second via hole is formed in the first protection layer, and the second solder ball is arranged in the second via hole.
In some alternative embodiments, the package structure further includes:
the second adhesive layer is arranged on one side of the first protective layer, which is away from the first passivation layer, and coats the second chip;
the metal column penetrates through the second adhesive layer and is electrically connected with the first metal wiring;
the second passivation layer is arranged on one side, away from the first protection layer, of the second adhesive layer, and a third via hole is formed in the second passivation layer at a position corresponding to the metal column;
the second metal wiring is arranged on one side, away from the second adhesive layer, of the second passivation layer, and the second metal wiring is electrically connected with the metal column through the third via hole;
the second protection layer is used for coating the second metal wiring, a fourth via hole is formed in the second protection layer, and a third solder ball is arranged in the fourth via hole.
According to the invention, the metal through holes, the first metal wiring, the first solder balls and the second solder balls are designed on the bearing piece, the metal through holes are respectively and electrically connected with the first metal wiring and the first solder balls, the first metal wiring is electrically connected with the second solder balls, then the first chip is directly and reversely arranged on the first solder balls, and the second chip is reversely arranged on the second solder balls, so that three-dimensional stacking of the chips is realized, a lead structure is omitted, the chip size is reduced, and the utilization rate of the whole packaging structure is improved.
Drawings
FIG. 1 is a process flow diagram of a three-dimensional stacked fan-out chip packaging method according to an embodiment of the invention;
fig. 2 to 17 are schematic flow diagrams of a three-dimensional stacked fan-out chip packaging method according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below with reference to the drawings and detailed description for the purpose of better understanding of the technical solution of the present invention to those skilled in the art.
In one aspect of the present invention, as shown in fig. 1, there is provided a three-dimensional stacked fan-out chip packaging method S100, including:
s110, providing a bearing sheet, wherein the bearing sheet comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the bearing sheet.
Illustratively, in conjunction with fig. 2, a carrier sheet 101 is provided, where the carrier sheet 101 includes a first surface 101a and a second surface 101b disposed opposite to each other along a thickness direction thereof. In this step, the carrier sheet 101 may be a flat plate made of materials such as silicon, glass, metal, and organic substrate, and those skilled in the art may select carrier sheets made of other materials according to actual needs, which is not limited in this embodiment.
S120, forming a metal through hole on the first surface of the carrier sheet, and forming a first solder ball on the metal through hole.
For example, in this step, there are various manufacturing processes for forming the metal through hole on the carrier sheet, for example, a through hole penetrating through the second surface may be directly manufactured on the first surface of the carrier sheet through etching or the like, and then the through hole may be manufactured into the metal through hole through electroplating, electroless plating or the like. Alternatively, the blind hole may be first formed on the first surface of the carrier by etching, electroplating, electroless plating, etc., and then the second surface of the carrier is thinned by physical grinding to form a metal through hole.
As shown in fig. 2, a blind hole is first formed on the first surface 101a of the carrier 101 by etching, etc., and then the blind hole is formed into a metal blind hole 102a by electroplating, electroless plating, etc. Thereafter, as shown in fig. 3, the first solder ball 103 is formed on the metal blind hole 102a by a process such as ball placement, printing, electroplating, electroless plating, etc. Then, as shown in fig. 4, the first chip 104 mentioned in the following steps is flip-chip mounted on the first solder balls 103. In order to firmly arrange the first chip 104 on the carrier 101, as shown in fig. 5, a first adhesive layer 105 may also be formed on the first surface 101a of the carrier 101, where the first adhesive layer 105 encapsulates the first chip 104. Finally, as shown in fig. 6, a thinning process is performed on the second surface 101b of the carrier sheet 101 by using a physical grinding method or the like, so that the metal blind holes penetrate through the second surface 101b of the carrier sheet 101 to form metal through holes 102.
S130, the first chip is flipped on the first solder balls.
Illustratively, as shown in fig. 4, in this step, the first chip 104 may be flip-chip mounted on the first solder balls 103 by soldering, reflow, or the like. Of course, those skilled in the art may also flip the first chip onto the first solder ball in other manners, which is not limited in this embodiment.
S140, forming a first adhesive layer on the first surface of the carrier, wherein the first adhesive layer coats the first chip so as to fix the first chip on the first surface of the carrier.
As illustrated in fig. 5, in this step, a first adhesive layer 105 may be formed on the first surface 101a of the carrier sheet 101 by coating a polymer adhesive, where the first adhesive layer 105 encapsulates the first chip 104 to fix the first chip 104 on the first surface 101a of the carrier sheet 101. The coating process may be a screen printing, dispensing, stamping, etc. process, or other processes, which is not limited in this embodiment. Of course, those skilled in the art may form the first adhesive layer on the first surface of the carrier sheet by other methods, which is not limited in this embodiment.
It should be noted that, in the actual manufacturing process, the step of forming the first adhesive layer on the first surface of the carrier sheet is not necessarily present, and a person skilled in the art may choose from the steps according to actual needs.
S150, forming a first metal wiring on the second surface of the carrier sheet, wherein the first metal wiring is electrically connected with the metal through hole.
Preferably, in the step, forming the first metal wiring on the second surface of the carrier sheet specifically includes the following steps:
a first passivation layer is formed on the second surface of the carrier sheet.
Specifically, in this step, as shown in fig. 7, a first passivation layer 106 is formed on the second surface 101b of the carrier sheet 101. The first passivation layer 106 may be any material that can perform passivation, insulation, etc., and the specific thickness of the first passivation layer is not limited in this embodiment, and may be selected by those skilled in the art according to actual needs. The process of forming the first passivation layer in this step may be deposition, sputtering, etc., which is not limited in this embodiment. The material of the first passivation layer may be silicon dioxide, silicon nitride, or other materials, and those skilled in the art may select the material according to actual needs, which is not limited in this embodiment.
And patterning the first passivation layer to form a first via hole at a position corresponding to the metal via hole.
Specifically, in this step, as shown in fig. 7, the first passivation layer may be patterned in the following manner: first, a patterned first mask layer is formed on the first passivation layer 106, and then, the first passivation layer 106 is etched at a position corresponding to the metal via 102 by using the first mask layer as a mask, so as to form a first via. The material of the first mask layer may be photoresist, or other materials may be selected according to actual needs, which is not limited in this embodiment. The process of etching the first passivation layer may be a dry etching process or other processes, which is not limited in this embodiment. Of course, those skilled in the art may choose to pattern the first passivation layer in other ways to form the first via hole at a location corresponding to the metal via hole, which is not limited in this embodiment.
The first metal wiring is formed on the first via hole and the first passivation layer.
Specifically, as shown in fig. 8, in this step, a first metal wiring 107 may be formed on the first via hole and the first passivation layer 106 by using a process such as electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, so that the first metal wiring 107 is electrically connected to the metal via hole 102. Of course, those skilled in the art may alternatively form the first metal wiring such that the first metal wiring is electrically connected to the metal via, which is not limited in this embodiment.
S160, forming second solder balls on the first metal wiring, and flip-chip mounting a second chip on the second solder balls to complete the three-dimensional stacked fan-out chip package.
Preferably, the present step further comprises the steps of:
and forming a first protection layer on the first metal wiring, and forming a second via hole on the first protection layer.
Specifically, as shown in fig. 9, in this step, the first protective layer 108 may be formed on the first metal wiring 107 by lamination, coating, printing, or the like, or the first protective layer 108 may be formed on the first metal wiring 107 by other means, which is not limited thereto in this embodiment. The first protective layer may be made of an insulating material such as an organic resin, or other materials, and those skilled in the art may select the material according to actual needs. In forming the second via hole on the first protection layer 108, a suitable position may be selected to be formed by a photolithography process, or a suitable position may be selected to be formed by another process, which is not limited in this embodiment.
And forming the second solder ball in the second via hole, and flip-chip the second chip on the second solder ball.
Specifically, as shown in fig. 10, in this step, the second solder ball 109 may be formed in the second via hole by a process of ball mounting, printing, electroplating, electroless plating, or the like, so that the second solder ball 109 is formed on the first metal wiring 107, and the second solder ball 109 is electrically connected to the first metal wiring 107. Of course, those skilled in the art may form the second solder balls by other processes, which is not limited in this embodiment. As shown in fig. 11, in this step, the second chip 110 may be mounted on the second solder ball 109 by soldering, reflow, or other methods, and those skilled in the art may select the second chip according to actual needs.
Preferably, after the second chip is flipped on the second solder ball, the method further comprises the steps of:
and forming a second adhesive layer on the first protective layer, wherein the second adhesive layer coats the second chip so as to fix the second chip on the second surface of the carrier sheet.
Illustratively, as shown in fig. 12, on the first protective layer 108, a second adhesive layer 111 may be formed by coating a polymer adhesive. The coating process can be screen printing, dispensing, stamping and the like, and can be selected by a person skilled in the art according to actual needs. Of course, the second adhesive layer 111 may be formed on the first protective layer 108 by other processes, which is not limited in this embodiment. As shown in fig. 12, the second adhesive layer 111 encapsulates the second chip 110, so as to fix the second chip 110 on the second surface 101b of the carrier sheet 101.
Preferably, after forming the second adhesive layer on the first protective layer, the method further comprises the following steps:
and forming a metal column penetrating through the second adhesive layer, wherein the metal column is electrically connected with the first metal wiring.
Illustratively, as shown in fig. 13, in this step, a via penetrating the second adhesive layer 111 may be formed by a photolithography process, and a metal pillar 112 may be formed in the via by a plating, electroless plating, or the like process, such that the metal pillar 112 is electrically connected with the first metal wiring 107. Of course, those skilled in the art may alternatively form the metal pillars penetrating the second glue layer so that the metal pillars are electrically connected with the first metal wires, which is not limited in this embodiment.
And forming a second passivation layer on the second adhesive layer.
As illustrated in fig. 14, in this step, the second passivation layer 113 may be formed on the second adhesive layer 111 by deposition, or the second passivation layer 113 may be formed on the second adhesive layer 111 by other means, which is not limited in this embodiment. It should be noted that, the second passivation layer only needs to perform passivation, insulation, and other functions, and the embodiment is not limited to a specific thickness of the second passivation layer, and those skilled in the art may select according to actual needs. The material of the second passivation layer may be silicon dioxide, silicon nitride, or other materials, and those skilled in the art may select the material according to actual needs, which is not limited in this embodiment.
And patterning the second passivation layer to form a third via hole at a position corresponding to the metal column.
As shown in fig. 14, in this step, the second passivation layer may be patterned in the following manner: first, a patterned second mask layer is formed on the second passivation layer 113, and then, the second passivation layer 113 is etched at a position corresponding to the metal pillar 112 by using the second mask layer as a mask, so as to form a third via hole. The material of the second mask layer may be photoresist, or other materials may be selected according to actual needs, which is not limited in this embodiment. The process of etching the second passivation layer may be a dry etching process or other processes, which is not limited in this embodiment. Of course, those skilled in the art may choose to pattern the second passivation layer in other ways to form a third via at a location corresponding to the metal pillar, which is not limited in this embodiment.
And forming the second metal wiring on the third via hole and the second passivation layer.
As shown in fig. 15, in this step, the second metal wiring 114 may be formed on the third via hole and the second passivation layer 113 by using a process such as electroplating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, so that the second metal wiring 114 is electrically connected to the metal pillar 112. Of course, those skilled in the art may alternatively form the second metal wiring such that the second metal wiring is electrically connected to the metal pillar, which is not limited in this embodiment.
And forming a second protection layer on the second metal wiring, and forming a fourth via hole on the second protection layer.
As illustrated in fig. 16, the second protective layer 115 may be formed on the second metal wiring 114 by lamination, coating, printing, or the like, or the second protective layer 115 may be formed on the second metal wiring 114 by other means in this step, which is not limited in this embodiment. The second protective layer may be made of an insulating material such as an organic resin, or other materials, and those skilled in the art may choose the material according to actual needs. In forming the fourth via hole on the second protection layer 115, a suitable position may be selected to be formed by a photolithography process, or a suitable position may be selected to be formed by another process, which is not limited in this embodiment.
And forming the third solder ball in the fourth via hole.
As shown in fig. 17, in this step, the third solder ball 116 may be formed in the fourth via hole by a process of ball mounting, printing, electroplating, electroless plating, or the like, so that the third solder ball 116 is formed on the second metal wiring 114, and the third solder ball 116 is electrically connected to the second metal wiring 114. Of course, those skilled in the art may form the third solder balls by other processes, which is not limited in this embodiment.
According to the fan-out chip packaging method for the three-dimensional stack, the metal through holes, the first metal wiring, the first solder balls and the second solder balls are designed on the bearing chip, the metal through holes are respectively and electrically connected with the first metal wiring and the first solder balls, the first metal wiring is electrically connected with the second solder balls, then the first chip is directly and reversely arranged on the first solder balls, and the second chip is reversely arranged on the second solder balls, so that the three-dimensional stack of the chip is realized, a lead structure is omitted, the chip size is reduced, and the utilization rate of the whole packaging structure is improved.
It should be noted that both the second passivation layer and the second protection layer are not necessary, and those skilled in the art may choose from one another according to actual needs. For example, a second metal wire may be directly fabricated on the second glue layer, and then a third solder ball may be fabricated directly on the second metal wire. Or, a second passivation layer is formed on the second adhesive layer, then a third via hole is formed in the second passivation layer, then a second metal wiring is formed on the third via hole and the second passivation layer, and finally a third solder ball is directly manufactured on the second metal wiring. Or, the second metal wiring may be directly prepared on the second adhesive layer, then the second protective layer may be prepared on the second metal wiring, the fourth via hole may be prepared in the second protective layer, and then the third solder ball may be prepared in the fourth via hole.
In another aspect of the present invention, a three-dimensional stacked fan-out chip package structure is provided, and the package structure may be formed by using the preparation method described above, and the description thereof may be referred to herein for details.
As shown in fig. 17, a three-dimensionally stacked fan-out core chip package structure 100, the package structure 100 includes a carrier sheet 101, first solder balls 103, first chips 104, first metal wirings 107, second solder balls 109, and second chips 110. The carrier sheet 101 includes a first surface 101a and a second surface 101b disposed opposite to each other in a thickness direction thereof, and the carrier sheet 101 is provided with a metal through hole 102 penetrating the first surface 101a and the second surface 101b thereof. The first solder balls 103 are disposed on the first surface 101a of the carrier 101 and electrically connected to the metal vias 102. The first chip 104 is flip-chip mounted on the first solder balls 103. The first metal wiring 107 is disposed on the second surface 101b of the carrier sheet 101, and the first metal wiring 107 is electrically connected to the metal via 102. The second solder ball 109 is disposed on the first metal wiring 107. The second chip 110 is flip-chip mounted on the second solder balls 109.
According to the three-dimensional stacked fan-out chip packaging structure, the metal through holes, the first metal wiring, the first solder balls and the second solder balls are designed on the bearing sheet, the metal through holes are respectively electrically connected with the first metal wiring and the first solder balls, the first metal wiring is electrically connected with the second solder balls, then the first chip is directly and reversely arranged on the first solder balls, and the second chip is reversely arranged on the second solder balls, so that three-dimensional stacking of the chips is realized, a lead structure is omitted, the chip size is reduced, and the utilization rate of the whole packaging structure is improved.
Preferably, as shown in fig. 17, the package structure 100 further includes a first adhesive layer 105, a first passivation layer 106, and a first protection layer 108. The first adhesive layer 105 is disposed on the first surface 101a of the carrier sheet 101 and encapsulates the first chip 104. The first passivation layer 106 is disposed between the second surface 101b of the carrier sheet 101 and the first metal wiring 107, the first passivation layer 106 is provided with a first via hole at a position corresponding to the metal via hole 102, and the first metal wiring 107 is electrically connected to the metal via hole 102 through the first via hole. The first protection layer 108 encapsulates the first metal wiring 107, a second via hole is disposed on the first protection layer 108, and a second solder ball 109 is disposed in the second via hole.
It should be noted that, the specific materials of each structure are not limited in this embodiment, and may be selected by those skilled in the art according to actual needs. For example, the first adhesive layer may be made of polymer adhesive, the first passivation layer may be made of silicon dioxide, and the first protection layer may be made of an insulating material such as organic resin.
Preferably, as shown in fig. 17, the package structure 100 further includes a second adhesive layer 111, a metal pillar 112, a second passivation layer 113, a second metal wiring 114, and a second protection layer 115. The second adhesive layer 111 is disposed on a side of the first protective layer 108 facing away from the first passivation layer 106, and encapsulates the second chip 110. The metal posts 112 penetrate through the second glue layer 111 and are electrically connected with the first metal wires 107. The second passivation layer 113 is disposed on a side of the second adhesive layer 111 facing away from the first protection layer 108, and the second passivation layer 113 is provided with a third via hole at a position corresponding to the metal pillar 112. The second metal wiring 114 is disposed on a side of the second passivation layer 113 facing away from the second glue layer 111, and the second metal wiring 114 is electrically connected to the metal pillar 112 through the third via hole. The second protective layer 115 covers the second metal wiring 114. In order to facilitate the subsequent chip to be directly used, a fourth via hole may be further disposed on the second protection layer 115, and a third solder ball 116 is disposed in the fourth via hole.
It should be noted that, the specific materials of each structure are not limited in this embodiment, and may be selected by those skilled in the art according to actual needs. For example, the second adhesive layer may be made of polymer adhesive, the metal pillars and the metal wirings may be made of copper, gold, etc., the second passivation layer may be made of silicon dioxide, etc., the second protection layer may be made of organic resin, etc., and the embodiment is not limited thereto.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (8)
1. A method of three-dimensionally stacked fan-out chip packaging, the method comprising:
providing a carrier sheet, wherein the carrier sheet comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the carrier sheet, and the carrier sheet is a flat plate of silicon, glass, metal or organic substrate material;
forming a metal through hole on the first surface of the carrier sheet, and forming a first solder ball on the metal through hole;
flip-chip the first chip on the first solder ball;
forming a first adhesive layer on the first surface of the carrier sheet, wherein the first adhesive layer coats the first chip so as to fix the first chip on the first surface of the carrier sheet;
forming a first metal wiring on the second surface of the carrier sheet, wherein the first metal wiring is electrically connected with the metal through hole;
forming a second solder ball on the first metal wiring, and flip-chip mounting a second chip on the second solder ball;
forming a second adhesive layer on the first metal wiring, wherein the second adhesive layer coats the second chip so as to fix the second chip on the second surface of the carrier sheet;
forming a metal column penetrating through the second adhesive layer, wherein the metal column is electrically connected with the first metal wiring;
forming a second metal wiring on the second adhesive layer, wherein the second metal wiring is electrically connected with the metal column;
and forming third solder balls on the second metal wiring to complete the three-dimensional stacked fan-out chip package.
2. The method of claim 1, wherein forming a first metal wire on the second surface of the carrier sheet comprises:
forming a first passivation layer on a second surface of the carrier sheet;
patterning the first passivation layer to form a first via hole at a position corresponding to the metal via hole;
the first metal wiring is formed on the first via hole and the first passivation layer.
3. The method of claim 1 or 2, wherein forming second solder balls on the first metal wires, flip-chip a second chip on the second solder balls, comprises:
forming a first protection layer on the first metal wiring, and forming a second via hole on the first protection layer;
and forming the second solder ball in the second via hole, and flip-chip the second chip on the second solder ball.
4. The method of claim 3, wherein forming a second metal wire on the second glue layer comprises:
forming a second passivation layer on the second adhesive layer;
patterning the second passivation layer to form a third via hole at a position corresponding to the metal column;
and forming the second metal wiring on the third via hole and the second passivation layer.
5. The method of claim 4, wherein forming a third solder ball on the second metal wire comprises:
forming a second protection layer on the second metal wiring, and forming a fourth via hole on the second protection layer;
and forming the third solder ball in the fourth via hole.
6. A three-dimensional stacked fan-out chip package structure fabricated using the method of any of claims 1-5, the package structure comprising:
the bearing piece comprises a first surface and a second surface which are oppositely arranged along the thickness direction of the bearing piece, the bearing piece is a flat plate made of silicon, glass, metal or organic substrate material, and the bearing piece is provided with a metal through hole penetrating through the first surface and the second surface;
the first solder balls are arranged on the first surface of the carrier sheet and are electrically connected with the metal through holes;
the first chip is flip-chip mounted on the first solder balls;
the first adhesive layer is arranged on the first surface of the carrier sheet and coats the first chip;
the first metal wiring is arranged on the second surface of the carrier sheet and is electrically connected with the metal through hole;
the second solder balls are arranged on the first metal wiring;
the second chip is flip-chip mounted on the second solder balls;
the second adhesive layer is arranged on the first metal wiring and coats the second chip;
the metal column penetrates through the second adhesive layer and is electrically connected with the first metal wiring;
the second metal wiring is arranged on the second adhesive layer and is electrically connected with the metal column;
and third solder balls formed on the second metal wiring.
7. The package structure of claim 6, further comprising:
the first passivation layer is arranged between the second surface of the carrier sheet and the first metal wiring, a first through hole is formed in the first passivation layer at a position corresponding to the metal through hole, and the first metal wiring is electrically connected with the metal through hole through the first through hole;
the first metal wiring is covered by the first protection layer, a second via hole is formed in the first protection layer, and the second solder ball is arranged in the second via hole.
8. The package structure of claim 7, further comprising:
the second adhesive layer is arranged on one side of the first protective layer, which is away from the first passivation layer; the second passivation layer is arranged on one side, away from the first protection layer, of the second adhesive layer, and a third via hole is formed in the second passivation layer at a position corresponding to the metal column;
the second metal wiring is arranged on one side, away from the second adhesive layer, of the second passivation layer, and is electrically connected with the metal column through the third via hole;
the second protection layer is used for coating the second metal wiring, a fourth via hole is formed in the second protection layer, and the third solder ball is arranged in the fourth via hole.
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| CN106098676A (en) * | 2016-08-15 | 2016-11-09 | 黄卫东 | Multichannel stack package structure and method for packing |
| CN110957306A (en) * | 2018-09-27 | 2020-04-03 | 北京万应科技有限公司 | Multi-layer chip substrate and packaging method, multifunctional chip packaging method and wafer |
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|---|---|---|---|---|
| IL175011A (en) * | 2006-04-20 | 2011-09-27 | Amitech Ltd | Coreless cavity substrates for chip packaging and their fabrication |
| US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
| US8350377B2 (en) * | 2008-09-25 | 2013-01-08 | Wen-Kun Yang | Semiconductor device package structure and method for the same |
| US9263370B2 (en) * | 2013-09-27 | 2016-02-16 | Qualcomm Mems Technologies, Inc. | Semiconductor device with via bar |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098676A (en) * | 2016-08-15 | 2016-11-09 | 黄卫东 | Multichannel stack package structure and method for packing |
| CN110957306A (en) * | 2018-09-27 | 2020-04-03 | 北京万应科技有限公司 | Multi-layer chip substrate and packaging method, multifunctional chip packaging method and wafer |
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