CN106098676A - Multichannel stack package structure and method for packing - Google Patents
Multichannel stack package structure and method for packing Download PDFInfo
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- CN106098676A CN106098676A CN201610664483.4A CN201610664483A CN106098676A CN 106098676 A CN106098676 A CN 106098676A CN 201610664483 A CN201610664483 A CN 201610664483A CN 106098676 A CN106098676 A CN 106098676A
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- infrabasal plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention discloses the multichannel stack package structure of one and the method for packing in integrated antenna package field.nullIncluding superstructure and lower package body，Superstructure and lower package body form the entirety interconnected up and down by electrical connection mechanism，Described superstructure is provided with substrate，The substrate of superstructure is referred to as upper substrate，Lower package body includes infrabasal plate、Lower package body chip、Embed substrate and plastic packaging glue，Lower package body chip is positioned on the upper surface of infrabasal plate and is electrically connected with infrabasal plate formation by electrical connection mechanism，Embed the baseplate-laminating non-chip rest area on infrabasal plate upper surface，Plastic packaging glue covers other regions of infrabasal plate upper surface and fills out the space between envelope embedding substrate and lower package body chip，By the conductive material embedding the upper and lower both sides of substrate and the electrical connection embedded between circuit realiration superstructure and the lower package body within substrate，Lower package body infrabasal plate lower surface can be formed with the printed circuit board (PCB) being positioned at lower section or other devices or object and electrically connect.
Description
Technical field
The present invention relates to a kind of stacked package technology (POP) in integrated antenna package field is formed ultra fine-pitch multichannel
Stack package structure and method for packing.
Background technology
Along with the continuous progress of microelectric technique, the characteristic size of integrated circuit constantly reduces, interconnection density improves constantly,
Future Society needs information processing more at a high speed and the more preferable mobile product Consumer's Experience thus brought, and this needs are right
The encapsulation technology of integrated circuit proposes deep challenge.
Stacked package (POP, Package on Package) is a kind of typical three-dimensional packaging technology, is mainly used in each
Electronic product processor is integrated with memory system.POP is formed by stacking by upper and lower two packaging bodies, upper packaging body and lower package body
Between by be electrically interconnected passage formed electrical connection.Usually baseband element or the application processor etc. of encapsulation in lower package body, and
Upper packaging body is usually memorizer etc..Along with memory bandwidth demand improves constantly, the Main Bottleneck of restriction POP package application is
Channel number is electrically interconnected between upper lower package body in tradition POP limited, i.e. the effective port number of internal memory is limited, and internal memory is therefore significantly increased
Effectively port number (i.e. going up the electrical interconnection port number between lower package body) is a challenge of encapsulation technology now.
At present POP technology mainly by peace by only a few world major company monopolizations such as (Amkor), that is released can volume production
POP packing forms is mainly two kinds: molding through hole (TMV, Through Mold Via) POP as shown in Figure 1 encapsulates and such as Fig. 2
Shown non-molding through hole POP encapsulation.Wherein, upper lower package body chips can use wire bonding, face-down bonding or both
Combining form, stackable also can tile.Non-molding through hole POP encapsulation realizes the electrical connection of upper lower package body, molding with soldered ball
Through hole POP encapsulation fills through hole the electrical connection of the upper lower package body of the realization that connects with top soldered ball with conductive material.In order to carry
High memory bandwidth, the size of connection soldered ball/molding through hole (TMV) that each major company is devoted to reduce between upper lower package body and
Away from, namely reduce the spacing between adjacency channel, but it is subjected to technique and the restriction of yield rate and cannot realize.Molding through hole
For non-molding through hole POP encapsulation is compared in POP encapsulation, there is less adjacency channel spacing, the molding through hole POP of current volume production
The minimum adjacency channel spacing that encapsulation can reach is 0.4mm, this be current POP encapsulation technology the most in the world reach can
Power.The major technical difficulty reducing adjacency channel spacing further is: need less connection soldered ball/molding for reducing spacing
The size of through hole (TMV), thus causes less ball height cannot connect lower package body, less but deeper molding through hole
(TMV) it is difficult to processing and is difficult to filling conductive material.To molding in pacifying patent US7671457B1 and US8319338B1 leaned on
Through hole POP is packaged with detailed description.
Summary of the invention
It is an object of the invention to overcome in existing multichannel stacked package technique and restrict the encapsulation up and down in POP package application
Deficiency that channel number limited is electrically interconnected between body,
A kind of new ultra fine-pitch POP method for packing and packaging technology are proposed, to increase considerably the effective port number of internal memory, thus
Realize the circulation of faster data and more preferable Consumer's Experience.
The present invention is achieved by the following technical solutions:
A kind of multichannel stack package structure, including superstructure and lower package body, superstructure and lower package body by being electrically connected
Connection mechanism forms the entirety interconnected up and down, it is characterised in that: described superstructure is provided with substrate, and the substrate of superstructure is referred to as
Upper substrate, lower package body includes infrabasal plate, lower package body chip, embeds substrate and plastic packaging glue, and lower package body chip is positioned over down
Electrically connect with infrabasal plate formation on the upper surface of substrate and by electrical connection mechanism, embed baseplate-laminating on infrabasal plate upper surface
Non-chip rest area, plastic packaging glue cover other regions of infrabasal plate upper surface and fill out envelope embed substrate and lower package body chip it
Between space, have packing material in embedding the gap between substrate and infrabasal plate, have through hole to run through packing material, embed under substrate
Side has conductive material to make formation between embedding substrate and infrabasal plate electrically connect in through hole, embeds and also has conduction material on the upside of substrate
Material makes to be formed between embedding substrate and upper substrate to electrically connect, by embedding the conductive material of the upper and lower both sides of substrate and embedding in substrate
Electrical connection between circuit realiration superstructure and the lower package body in portion.
Being further limited technique scheme, described plastic packaging glue is completely covered lower package body chip and embeds base
Plate, or described plastic packaging glue be not completely covered lower package body chip or embed substrate, but by lower package body chip upper surface and/
Or embedding upper surface of base plate comes out；
Being further limited technique scheme, when described embedding substrate is covered by plastic packaging glue, the conductive material on the upside of it is worn
Cross the plastic packaging glue embedding surface to electrically connect with upper substrate formation；Filling in gap between described embedding substrate and infrabasal plate
Material is plastic packaging glue；
Technique scheme is further limited, is seamless applying between described upper substrate and lower package body or existence seam
Gap, time seamless applying, upper substrate lower surface is covered by described plastic packaging glue, retain gap or in gap all or part of region set
Put seal, sealing materials, embed the conductive material on the upside of substrate when being provided with seal, sealing materials and be electrically connected with upper substrate formation through seal, sealing materials
Connect；
Technique scheme is further limited, described plastic packaging glue completely or partially can be by the bonding material of other sealing
Material or filler are replaced；
Being further limited technique scheme, described lower package body chip comprises one or more chip, with stacking, puts down
Paving or both compound modes are positioned on infrabasal plate upper surface, and with wire bonding, flip chip bonding or both combination or other modes
Formed with infrabasal plate and electrically connect；Described infrabasal plate lower surface can be with printed circuit board (PCB) or other devices or the object being positioned at lower section
Form electrical connection；
Being further limited technique scheme, described superstructure is provided with upper substrate perforation or windows, or upper substrate
For above metal framework structure, or upper substrate partly or entirely not by plastic packaging；Described superstructure is and lower package body shape
Become at least one random devices electrically connected or object or a combination thereof；
Technique scheme is further limited, in described superstructure, places one or more chips, described chip
For superstructure chip, superstructure chip is positioned in superstructure with stacking, tiling or both compound modes, and with lead-in wire
Bonding, flip chip bonding or both combinations or other modes are formed with upper substrate and electrically connect；
Technique scheme is further limited, places passive device at described upper substrate upper surface or infrabasal plate upper surface
Or the electronic devices and components encapsulated；
Being further limited technique scheme, on the upside of described embedding substrate, the conductive material with downside is one or
Plant with intercommunication material or a combination thereof of powering on, form at least one between embedding substrate and described upper substrate and electrically connect, embed substrate
Electrically connect with also forming at least one between described infrabasal plate.
The method for packing of a kind of multichannel stack package structure, including the system of superstructure (referred to herein as upper packaging body)
Make technique, the processing technology of lower package body and the interconnection process of upper and lower encapsulation, it is characterised in that:
Described lower package body processing technology includes step:
1) solder ball is implanted at infrabasal plate upper surface；
2) embed substrate to be positioned on solder ball, make embedding baseplate-laminating above infrabasal plate through Reflow Soldering；
3) upper surface of base plate implantation solder ball is being embedded；
4) with upside-down mounting mode by one or more chip attachment the upper surface of infrabasal plate and with infrabasal plate formed electrically connect；
5) carrying out plastic packaging at infrabasal plate upper surface, plastic packaging glue is packed in the gap embedded between substrate and infrabasal plate, and plastic packaging
Glue is completely covered flip-chip, embeds substrate and embed the solder ball on the upside of substrate；Seam between flip-chip and infrabasal plate
A underfill may material of filling in advance is had in gap, or the most unfilled but in plastic package process, plastic packaging glue is filled into upside-down mounting core
In gap between sheet and infrabasal plate.
6) use the plastic packaging glue above solder ball on the upside of laser ablation process removal embedding substrate, expose its top；
The processing technology of described upper packaging body includes step:
One or more chips are encapsulated at upper substrate upper surface；
Implant multiple thin space soldered balls in the bottom surface of upper substrate, the position of these soldered balls is corresponding is embedding the solder ball on the upside of substrate
Top.
The present invention has following technical effect that
Owing to embedding the existence of substrate, the interval between original upper substrate and infrabasal plate is divided into two, two seams separated
Gap spacing is the least, therefore when making the conductive material such as soldered ball connected, can reduce the size of conductive material such as soldered ball, thus
Reach the purpose of ultra fine-pitch encapsulation, by existing technological ability, the ability of 0.2mm channel pitch can be reached, far above mesh
The ability of the 0.4mm that front POP product is reached, so can arrange the effective passage of more internal memory, greatly improve internal memory band
Width, makes chipset meet the demand that more supercomputing processes with more high flow capacity, thus brings for each electronic product and more preferably use
Family is experienced.
Accompanying drawing explanation
Fig. 1 is molding through hole (TMV) POP encapsulating structure figure.
Fig. 2 is non-molding through hole POP encapsulating structure figure.
Fig. 3 is the structure chart of multichannel stacked package (POP).
Fig. 4 is embodiment one structure chart.
Fig. 5 is embodiment two structure chart.
Fig. 6 is embodiment two lower package body formation process flow chart.
Fig. 7 is packaging body formation process flow chart in embodiment two.
Fig. 8 is lower package body combined process flow chart in embodiment two.
In figure: 1 bottom soldered ball, 2 infrabasal plates, 3 plastic packaging glue, 4 upper substrates, electrical interconnection between 5 upper substrates and lower package body
Passage (brazing metal), 6 superstructures (upper packaging body) plastic packaging layer, 7 embedding substrates, gap between 8 embedding substrates and infrabasal plate
In packing material (can be replaced by plastic packaging glue), 9 embed conductive material on the downside of substrates, 10 embed the conduction material on the upside of substrates
Material, seal, sealing materials (optional) between 11 lower package body chips and 12 upper substrates and lower package body.
Detailed description of the invention
With specific embodiment, present disclosure is further described below in conjunction with the accompanying drawings:
It is illustrated in figure 3 multichannel stack package structure schematic diagram, including 1 bottom soldered ball, 2 infrabasal plates, 3 plastic packaging glue, base on 4
Plate, 6 superstructures (upper packaging body) plastic packaging layer, 7 embedding substrates, 8 packing materials embedded between substrates and infrabasal plate in gap
Conductive material on the downside of (can be replaced by plastic packaging glue), 9 embedding substrates, the conductive material on the upside of 10 embedding substrates, 11 times encapsulation
Seal, sealing materials (optional) between body chip and 12 upper substrates and lower package body.
Embodiment one
Fig. 4 show a kind of POP(Package On Package) stack package structure and method for packing, including upper and lower two mutually
Packaging body even, the substrate of upper packaging body is referred to as upper substrate, and the substrate of lower package body is referred to as infrabasal plate, under lower package body includes
Substrate, lower package body flip-chip, embedding substrate and plastic packaging glue, lower package body flip-chip is positioned over the upper surface of infrabasal plate
Go up and pass through chip surface salient point and electrically connect with infrabasal plate formation, embed the baseplate-laminating non-chip on infrabasal plate upper surface and put
Putting district, plastic packaging glue is by other regions of infrabasal plate upper surface and embeds substrate and flip-chip is completely covered and fills out envelope and embeds base
Space between plate and flip-chip, plastic packaging glue is filled into the gap and flip-chip embedded between substrate and infrabasal plate simultaneously
And the gap between infrabasal plate, has through hole to run through and embeds substrate and the plastic packaging glue in infrabasal plate gap, embed and have gold on the downside of substrate
Belong to solder ball make in through hole between embedding substrate and infrabasal plate formed electrically connect, the upper surface of the plastic packaging glue of lower package body and
It is provided with seal, sealing materials between substrate (upper substrate) lower surface of upper packaging body, embeds the metal soldered ball connected on the upside of substrate and moulded
Sealing covers, and uses laser ablation process to remove the plastic packaging glue above it, exposes its top, the gold that upper substrate lower surface is connected
Belong to soldered ball to merge with the metal welding pellet embedded on the upside of substrate through seal, sealing materials, thus make shape between embedding substrate and upper substrate
Become electrical connection, from there through embed the brazing metal of the upper and lower both sides of substrate and embed on the circuit realiration that substrate is internal packaging body and
Electrical connection between lower package body.Infrabasal plate lower surface is implanted with soldered ball.
Owing to embedding the existence of substrate, the interval between original upper substrate and infrabasal plate is divided into two, two separated
Individual gap spacing is the least, therefore when making the soldered ball connected, can reduce size of solder ball, thus reach ultra fine-pitch encapsulation
Purpose, by existing technological ability, can reach the ability of 0.2mm through-hole spacing, is reached far above current POP product
The ability of 0.4mm, so can arrange the effective passage of more internal memory, greatly improve memory bandwidth, makes chipset meet more
The demand that supercomputing processes with more high flow capacity, thus bring more preferably Consumer's Experience for each electronic product.
Embodiment two
Fig. 5 show a kind of POP(Package On Package) stack package structure and method for packing, including upper and lower two mutually
Packaging body even, the substrate of upper packaging body is referred to as upper substrate, and the substrate of lower package body is referred to as infrabasal plate, under lower package body includes
Substrate, lower package body flip-chip, embedding substrate and plastic packaging glue, lower package body flip-chip is positioned over the upper surface of infrabasal plate
Go up and pass through chip surface salient point and electrically connect with infrabasal plate formation, embed the baseplate-laminating non-chip on infrabasal plate upper surface and put
Putting district, other regions and the flip-chip of infrabasal plate upper surface are completely covered and fill out envelope and embed substrate and upside-down mounting core by plastic packaging glue
Space between sheet, but the upper surface embedding substrate is exposed, simultaneously plastic packaging glue be filled into embedding substrate and infrabasal plate it
Between gap and flip-chip and infrabasal plate between gap, have through hole to run through the plastic packaging embedded in substrate and infrabasal plate gap
Glue, embeds and has metal welding pellet to make formation between embedding substrate and infrabasal plate electrically connect in through hole on the downside of substrate, lower encapsulation
Being provided with seal, sealing materials between upper surface and substrate (upper substrate) lower surface of upper packaging body of body, upper substrate lower surface is connected
Metal soldered ball be connected through seal, sealing materials with embedding upper surface of base plate, so that being formed and be electrically connected between embedding substrate and upper substrate
Connect, from there through embedding the brazing metal of the upper and lower both sides of substrate and embedding packaging body and lower encapsulation on the circuit realiration within substrate
Electrical connection between body.Infrabasal plate lower surface is implanted with soldered ball.
Owing to embedding the existence of substrate, the interval between original upper substrate and infrabasal plate is divided into two, two separated
Individual gap spacing is the least, therefore when making the soldered ball connected, can reduce size of solder ball, thus reach ultra fine-pitch encapsulation
Purpose, by existing technological ability, can reach the ability of 0.2mm through-hole spacing, is reached far above current POP product
The ability of 0.4mm, so can arrange the effective passage of more internal memory, greatly improve memory bandwidth, makes chipset meet more
The demand that supercomputing processes with more high flow capacity, thus bring more preferably Consumer's Experience for each electronic product.
Method for packing technological process is as follows:
It is illustrated in figure 6 lower package body formation process:
1) infrabasal plate upper surface plants soldered ball；
2) embed substrate to fit with infrabasal plate, after Reflow Soldering, form electrical connection；
3) lower package body flip-chip attachment；
4) lower package body plastic packaging；
It is illustrated in figure 7 packaging body formation process:
1) upper packaging body molding；
2) upper substrate lower surface plants soldered ball；
Go up lower package body combined process as shown in Figure 8:
1) lower package body upper surface is covered with seal, sealing materials (epoxy flux), and upper packaging body is mounted on above lower package body；
2) close POP encapsulation is formed after Reflow Soldering；
3) infrabasal plate lower surface plants soldered ball.
General description:
All material solution that can realize electricity intercommunication are included with the conductive material of downside on the upside of the embedding substrate that the present invention mentions
With implementation, therefore it is not limited to use such as various methodologies such as brazing metal (ball), wire bonding projection, plating or spray metals
Or a combination thereof, no matter use which kind of methods or a combination thereof, as long as embed substrate and lower package body substrate (infrabasal plate) it
Between or embed and form at least one between substrate and upper substrate and electrically connect, just belong to the scope of patent protection of the present invention.
In the stacking POP encapsulating structure that the present invention proposes, in embedding the gap between substrate and infrabasal plate, there is packing material,
This packing material can be substituted by the plastic packaging glue above infrabasal plate, by plastic package process plastic packaging glue can be filled into embedding substrate with
Gap between infrabasal plate.
In the stacking POP encapsulating structure that the present invention proposes, in the gap between flip-chip and the infrabasal plate of lower package body
Having underfill may material, this underfill may material can be substituted by the plastic packaging glue above infrabasal plate, permissible by plastic package process plastic packaging glue
The gap being filled between flip-chip and infrabasal plate.
In the stacking POP encapsulating structure that the present invention proposes, in most cases go up between packaging body and lower package body necessary
Having seal, sealing materials (generally epoxy flux or other can play the material of phase same-action), this seal, sealing materials must possess and helps
The function of solder flux is firmly bonded simultaneously again, mainly strengthens combination and the bulk strength of upper lower package body, improves product reliable
Property, but have minority product may not use seal, sealing materials.Patent right requirement of the present invention includes and does not use seal, sealing materials
Encapsulating structure, regardless of whether use seal, sealing materials, all belongs to the scope of patent protection of the present invention.
Claims (10)
1. a multichannel stack package structure, including superstructure and lower package body, superstructure and lower package body by electricity
Bindiny mechanism forms the entirety interconnected up and down, it is characterised in that: described superstructure is provided with substrate, and the substrate of superstructure claims
For upper substrate, lower package body includes infrabasal plate, lower package body chip, embeds substrate and plastic packaging glue, and lower package body chip is positioned over
Electrically connect with infrabasal plate formation on the upper surface of infrabasal plate and by electrical connection mechanism, embed baseplate-laminating at infrabasal plate upper surface
On non-chip rest area, plastic packaging glue covers other regions of infrabasal plate upper surface and fills out envelope and embed substrate and lower package body chip
Between space, have packing material in embedding the gap between substrate and infrabasal plate, have through hole to run through packing material, embed substrate
Downside has conductive material to make formation between embedding substrate and infrabasal plate electrically connect in through hole, embeds and also has conduction on the upside of substrate
Material makes to be formed between embedding substrate and upper substrate to electrically connect, by embedding the conductive material of the upper and lower both sides of substrate and embedding substrate
The internal electrical connection between circuit realiration superstructure and lower package body.
Multichannel stack package structure the most according to claim 1, it is characterised in that: described plastic packaging glue is completely covered lower envelope
Fill body chip and embed substrate, or described plastic packaging glue is not completely covered lower package body chip or embeds substrate, but by lower envelope
Dress body chip upper surface and/or embedding upper surface of base plate come out.
Multichannel stack package structure the most according to claim 1, it is characterised in that: described embedding substrate is covered by plastic packaging glue
Conductive material on the upside of Gai Shiqi electrically connects through the plastic packaging glue embedding surface with upper substrate formation；Described embedding substrate with
Between infrabasal plate, the packing material in gap is plastic packaging glue.
Multichannel stack package structure the most according to claim 1, it is characterised in that: described upper substrate and lower package body it
Between for seamless applying or there is gap, time seamless applying, upper substrate lower surface is covered by described plastic packaging glue, retains gap or at seam
In gap, all or part of region arranges seal, sealing materials, embeds the conductive material on the upside of substrate through sealing-in when being provided with seal, sealing materials
Material is formed with upper substrate and electrically connects.
5. according to the multichannel stack package structure described in claim 1-4 any one, it is characterised in that: described plastic packaging glue
Completely or partially can be replaced by other sealing adhesives or filler.
Multichannel stack package structure the most according to claim 1, it is characterised in that: described lower package body chip comprises one
Individual or multiple chips, are positioned on infrabasal plate upper surface with stacking, tiling or both compound modes, and with wire bonding, upside-down mounting
Weldering or both combinations or other modes are formed with infrabasal plate and electrically connect；Described infrabasal plate lower surface can be with the print being positioned at lower section
Printed circuit board or other devices or object form electrical connection.
Multichannel stack package structure the most according to claim 1, it is characterised in that: described superstructure is provided with upper substrate
Perforation or window, or upper substrate be above metal framework structure, or upper substrate partly or entirely not by plastic packaging；On described
Rotating fields is to form at least one random devices electrically connected or object or a combination thereof with lower package body；Put in described superstructure
Putting one or more chip, described chip is superstructure chip, and superstructure chip is with stacking, tiling or both sides of combination
Formula is positioned in superstructure, and is electrically connected with upper substrate formation with wire bonding, flip chip bonding or both combinations or other modes
Connect.
Multichannel stack package structure the most according to claim 1, it is characterised in that: described upper substrate upper surface or under
Upper surface of base plate places passive device or the electronic devices and components encapsulated.
Multichannel stack package structure the most according to claim 1, it is characterised in that: with downside on the upside of described embedding substrate
Conductive material be one or more electricity intercommunication materials or a combination thereof, embed formed between substrate and described upper substrate to
A few electrical connection, also forms at least one between embedding substrate and described infrabasal plate and electrically connects.
10. a method for packing for multichannel stack package structure, including the system of superstructure (referred to herein as upper packaging body)
Make technique, the processing technology of lower package body and the interconnection process of upper and lower encapsulation, it is characterised in that:
Described lower package body processing technology includes step:
1) solder ball is implanted at infrabasal plate upper surface；
2) embed substrate to be positioned on solder ball, make embedding baseplate-laminating above infrabasal plate through Reflow Soldering；
3) upper surface of base plate implantation solder ball is being embedded；
4) with upside-down mounting mode by one or more chip attachment the upper surface of infrabasal plate and with infrabasal plate formed electrically connect；
5) carrying out plastic packaging at infrabasal plate upper surface, plastic packaging glue is packed in the gap embedded between substrate and infrabasal plate, and plastic packaging
Glue is completely covered flip-chip, embeds substrate and embed the solder ball on the upside of substrate；Seam between flip-chip and infrabasal plate
A underfill may material of filling in advance is had in gap, or the most unfilled but in plastic package process, plastic packaging glue is filled into upside-down mounting core
In gap between sheet and infrabasal plate；
6) use the plastic packaging glue above solder ball on the upside of laser ablation process removal embedding substrate, expose its top；
The processing technology of described upper packaging body includes step:
One or more chips are encapsulated at upper substrate upper surface；
Implant multiple thin space soldered balls in the bottom surface of upper substrate, the position of these soldered balls is corresponding is embedding the solder ball on the upside of substrate
Top.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112652542A (en) * | 2020-12-22 | 2021-04-13 | 厦门通富微电子有限公司 | Three-dimensional stacked fan-out type chip packaging method and packaging structure |
| CN117202481A (en) * | 2023-09-08 | 2023-12-08 | 中国电子科技集团公司第二十六研究所 | Module based on three-dimensional stacked structure and preparation method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101632175A (en) * | 2007-03-12 | 2010-01-20 | 美光科技公司 | Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor com |
| CN102804364A (en) * | 2009-06-26 | 2012-11-28 | 英特尔公司 | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
| CN103681365A (en) * | 2012-08-31 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | Package-on-package (POP) structure and manufacturing method for POP structure |
| US20140264946A1 (en) * | 2013-03-15 | 2014-09-18 | Qualcomm Incorporated | Package-on-package structure with reduced height |
| US20140264914A1 (en) * | 2013-03-15 | 2014-09-18 | Thorsten Meyer | Chip package-in-package and method thereof |
| US20150024552A1 (en) * | 2013-07-22 | 2015-01-22 | Zhen Ding Technology Co., Ltd. | Substrate, chip package and method for manufacturing substrate |
| CN104576409A (en) * | 2013-10-25 | 2015-04-29 | 钰桥半导体股份有限公司 | Semiconductor device with face-to-face chips on interposer and method of manufacturing the same |
| CN205881899U (en) * | 2016-08-15 | 2017-01-11 | 黄卫东 | Multichannel stacked package structure |
-
2016
- 2016-08-15 CN CN201610664483.4A patent/CN106098676A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101632175A (en) * | 2007-03-12 | 2010-01-20 | 美光科技公司 | Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor com |
| CN102804364A (en) * | 2009-06-26 | 2012-11-28 | 英特尔公司 | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
| CN103681365A (en) * | 2012-08-31 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | Package-on-package (POP) structure and manufacturing method for POP structure |
| US20140264946A1 (en) * | 2013-03-15 | 2014-09-18 | Qualcomm Incorporated | Package-on-package structure with reduced height |
| US20140264914A1 (en) * | 2013-03-15 | 2014-09-18 | Thorsten Meyer | Chip package-in-package and method thereof |
| US20150024552A1 (en) * | 2013-07-22 | 2015-01-22 | Zhen Ding Technology Co., Ltd. | Substrate, chip package and method for manufacturing substrate |
| CN104576409A (en) * | 2013-10-25 | 2015-04-29 | 钰桥半导体股份有限公司 | Semiconductor device with face-to-face chips on interposer and method of manufacturing the same |
| CN205881899U (en) * | 2016-08-15 | 2017-01-11 | 黄卫东 | Multichannel stacked package structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112652542A (en) * | 2020-12-22 | 2021-04-13 | 厦门通富微电子有限公司 | Three-dimensional stacked fan-out type chip packaging method and packaging structure |
| CN112652542B (en) * | 2020-12-22 | 2023-06-16 | 厦门通富微电子有限公司 | Three-dimensional stacked fan-out chip packaging method and packaging structure |
| CN117202481A (en) * | 2023-09-08 | 2023-12-08 | 中国电子科技集团公司第二十六研究所 | Module based on three-dimensional stacked structure and preparation method thereof |
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