CN105762084A - Packaging method and packaging device for flip chip - Google Patents

Packaging method and packaging device for flip chip Download PDF

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Publication number
CN105762084A
CN105762084A CN201610282085.6A CN201610282085A CN105762084A CN 105762084 A CN105762084 A CN 105762084A CN 201610282085 A CN201610282085 A CN 201610282085A CN 105762084 A CN105762084 A CN 105762084A
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China
Prior art keywords
packaging
base plate
semiconductor chip
carrier
bearing area
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CN201610282085.6A
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Chinese (zh)
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CN105762084B (en
Inventor
石磊
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Nantong Fujitsu Microelectronics Co Ltd
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Nantong Fujitsu Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The invention discloses a packaging method and packaging device for a flip chip. The method includes the following steps: a carrier and a packaging substrate are provided, the carrier includes a bearing area, a fixing part is arranged on the carrier, and the packaging substrate is used for packaging a semiconductor chip; and the fixing part is utilized to fix the carrier on a machine table of packaging equipment, and the packaging substrate is fixed in the bearing area so as to package the semiconductor chip. Through the abovementioned method, the packaging method can save substrate space, and reduce substrate material waste, which is in favor of reducing cost.

Description

The method for packing of flip-chip and packaging system
Technical field
The present invention relates to technical field of semiconductors, particularly relate to method for packing and the packaging system of a kind of flip-chip.
Background technology
Interconnection technique is one of key technology in microelectronics Packaging, and microelectronics Packaging product quality, efficiency and cost are had significant impact, mainly includes wire bonding and two kinds of encapsulation technologies of flip-chip (Flipchip).Flip-Chip Using has high density, high-performance and compact feature, it is possible to such that packaging cost is lower, easily realize stacked chips and three-dimension packaging technique, it has also become the main development of encapsulation technology finds.
Consult Fig. 1 and Fig. 2, flip-chip packaging techniques mainly deposits tin-lead ball 13 in the action face of semiconductor chip 11, then the action face of semiconductor chip 11 overturns heating down to utilize melted tin-lead ball 13 to combine with the circuit on base board unit 12 or other carrier, circuit board etc. or pin.After semiconductor chip 11 and base board unit 12 are combined; semiconductor chip 11 is carried out plastic packaging; thus form encapsulated layer 14 on the surface of semiconductor chip 11, encapsulated layer 14 wraps up the surface of whole semiconductor chip 11, to protect semiconductor chip 11 and base board unit 12.
As shown in Figure 2, in existing encapsulation technology, in most cases it is by " multi-chip package ", namely one piece of mother substrate 20 is used to be divided into multiple base board unit 12, then multiple semiconductor chips 11 are inverted on multiple base board unit 12 one by one, each base board unit 12 one semiconductor chip 11 of corresponding encapsulation.After being inverted on base board unit 12 by semiconductor chip 11, semiconductor chip 11 is carried out plastic packaging, then cut to separate multiple base board unit to mother substrate 20, thus obtaining multiple independent encapsulating structure.Owing to mother substrate 20 area is relatively big, easy affected by force in encapsulation process and produce deformation warpage, therefore generally reserve certain space between base board unit 12 or the subregion between base board unit 12 hollow out to reduce subjected to stress.
In encapsulation process, mother substrate 20 is placed directly within the board of sealed in unit, in order to the board of mother substrate 20 and equipment is fixed, such as in plastic packaging process, mother substrate 20 need to be fixed with the board of plastic packaging equipment, mother substrate 20 is usually provided with hole 201, location, then by the positioning needle on board through the hole, location 201 on mother substrate 20, thus being fixed on board by mother substrate 20.But, in aforesaid way, mother substrate 20 needs reserved certain space to arrange hole 201, location, the substrate regions being provided with hole 201, location after dicing will be dropped, mother substrate cannot be used for packaged semiconductor completely thus, cause that baseplate material is wasted, be unfavorable for that production cost reduces.
Summary of the invention
The technical problem that present invention mainly solves is to provide method for packing and the packaging system of a kind of flip-chip, it is possible to increase the utilization rate of substrate, is conducive to cost to reduce.
For solving above-mentioned technical problem, the technical scheme that the present invention adopts is: provide the method for packing of a kind of flip-chip, including: providing carrier and base plate for packaging, described carrier includes bearing area, and described carrier is provided with fixed part, described base plate for packaging is used for packaged semiconductor；Utilize described fixed part to be fixed on the board of sealed in unit by described carrier, and described base plate for packaging is fixed in described bearing area, so that described semiconductor chip is packaged.
Wherein, described carrier is groove structure, and described groove structure includes the four edges frame that head and the tail connect and the bottom portion of groove being connected with described four edges frame, and described bearing area is positioned at described bottom portion of groove, and described fixed part is the hole, location being arranged on described frame.
Wherein, the bottom of described groove is the glued membrane being pasted onto on described frame.
Wherein, described carrier is flat loading plate, and described fixed part is the hole, location being arranged on described loading plate.
Wherein, the quantity of described base plate for packaging is multiple, and multiple described base plate for packaging are separate, and each described base plate for packaging is used for encapsulating at least one described semiconductor chip, and described bearing area is provided with the telltale mark for positioning each described base plate for packaging；Described the step that described base plate for packaging is fixed in described bearing area is included: according to described telltale mark, multiple described base plate for packaging are fixed on described bearing area.
Wherein, the step of described offer base plate carrying frame and base plate for packaging includes: also provide for multiple described semiconductor chip, the surface of described semiconductor chip includes first surface and second surface, described first surface is formed the first connection terminal, described base plate for packaging includes the 3rd surface and the 4th surface, described 3rd surface being formed with the second connection terminal；Described described base plate for packaging is fixed on the step in described bearing area after, including: the 3rd surface of the first surface of described semiconductor chip and corresponding described base plate for packaging is oppositely arranged and is made described first connect terminal and described second and connect terminal and weld together；Encapsulated layer is formed on the surface of described semiconductor chip, and at least second surface described in expose portion.
Wherein, after the surface of described semiconductor chip forms the step of encapsulated layer, including: on the described second surface exposed, form heat dissipating layer.
Wherein, the step forming encapsulated layer on the surface of described semiconductor chip includes: arrange one layer of barrier layer on the portion second surface of described semiconductor chip；The first encapsulating material is filled in space between described barrier layer and described bearing area；Solidify described first encapsulating material and form described encapsulated layer with the surface at described semiconductor chip；Remove described barrier layer, to expose described portion second surface.
Wherein, described barrier layer is for having elastic glued membrane；The step arranging one layer of barrier layer on the described described second surface of the part at described semiconductor chip includes: arranges described barrier layer on the upper film of plastic package die, and makes described upper film be pressed on described second surface by described barrier layer.
Wherein, after removing the step on described barrier layer, including: it is pointed to the encapsulated layer between described base plate for packaging and carries out cutting to separate multiple described base plate for packaging, and make in described base plate for packaging the remaining surface except described 4th surface be each formed with described encapsulated layer.
Wherein, 3rd surface of the described first surface by described semiconductor chip and corresponding described base plate for packaging is oppositely arranged and makes described first to connect after terminal and described second connects the step that terminal welds together, including: between the 3rd surface of the first surface of described semiconductor chip and the described base plate for packaging of correspondence, form Underfill layer.
For solving above-mentioned technical problem, another technical solution used in the present invention is: providing a kind of packaging system, including carrier, described carrier includes bearing area, and described bearing area is used for fixing base plate for packaging, and described base plate for packaging is used for packaged semiconductor；Described carrier is provided with fixed part, to utilize described fixed part to be fixed on the board of sealed in unit by described carrier, so that the semiconductor chip being fixed on the described base plate for packaging in described bearing area to be packaged.
Wherein, described carrier is groove structure, and described groove structure includes the four edges frame that head and the tail connect and the bottom portion of groove being connected with described four edges frame, and described bearing area is positioned at described bottom portion of groove, and described fixed part is the hole, location being arranged on described frame.
Wherein, described bottom portion of groove is the glued membrane being pasted onto on described frame.
The invention has the beneficial effects as follows: be different from the situation of prior art, in the method for packing of the present invention, by providing the carrier being provided with fixed part, fixed part is utilized to be fixed on the board of sealed in unit by carrier, and the base plate for packaging being used for packaged semiconductor is placed in the bearing area of carrier, thus base plate for packaging is fixed on board, and then semiconductor chip can be packaged, base plate for packaging is fixed thus without arranging hole, location on base plate for packaging, substrate space can be saved, reduce baseplate material waste, advantageously reduce cost.
Further, in the encapsulation to semiconductor chip, by exposing the portion second surface of semiconductor chip, compared with the way on the existing surface making plastic packaging layer wrap up whole semiconductor chip, so that semiconductor chip is dispelled the heat by the second surface exposed, can be conducive to improving the radiating effect of semiconductor chip.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of semiconductor chip of prior art；
Fig. 2 is the top view of a kind of mother substrate for packaged semiconductor of prior art；
Fig. 3 is the flow chart of method for packing one embodiment of flip-chip of the present invention；
Fig. 4 is the structural representation of packaging system one embodiment of the present invention；
Fig. 5 is the schematic cross-section along AB direction of the packaging system shown in Fig. 4；
Fig. 6 is the schematic flow sheet of method for packing one embodiment of flip-chip of the present invention, shows the corresponding structural representation of each step in figure；
Fig. 7 is in method for packing one embodiment of flip-chip of the present invention, the structural representation of semiconductor chip；
Fig. 8 is in method for packing one embodiment of flip-chip of the present invention, forms the schematic diagram of heat dissipating layer on the second surface exposed；
Fig. 9 is in method for packing one embodiment of flip-chip of the present invention, forms the schematic flow sheet of encapsulated layer, show the corresponding structural representation of each step in figure on the surface of semiconductor chip；
Figure 10 is in method for packing one embodiment of flip-chip of the present invention, forms the schematic diagram of bottom package layer between semiconductor chip and base plate for packaging.
Detailed description of the invention
Elaborate concrete details in the following description to fully understand the present invention.But the present invention can be different from other modes described here implement with multiple, and those skilled in the art can do similar popularization when without prejudice to intension of the present invention.Therefore the present invention is not by the restriction of following public detailed description of the invention.
For the defect mentioned in background technology, the present invention provides the method for packing of a kind of flip-chip.Below in conjunction with drawings and embodiments, the present invention is described in further detail.
Consult Fig. 3, in method for packing one embodiment of flip-chip of the present invention, comprise the steps:
Step S301: providing carrier and base plate for packaging, carrier includes bearing area, and is provided with fixed part on carrier, base plate for packaging is used for packaged semiconductor.
In conjunction with Fig. 4 and Fig. 5, in an embodiment of the present invention, carrier 40 is a base plate carrying frame, and it is groove structure.Wherein carrier 40 includes the four edges frame 41 that head and the tail connect and the bottom portion of groove 42 being connected with four edges frame 41, and bearing area is positioned at bottom portion of groove 42.Carrier 40 is provided with fixed part, wherein fixed part is the hole, location 411 being arranged on frame 41, such as hole 411, location can be arranged on relative two frame 41, it is also possible to being arranged on adjacent two frame 41, concrete can be configured according to the board of sealed in unit.Frame 41 can adopt metal material to make, it is also possible to plastics, pottery or other materials are made.
Wherein, in present embodiment, bottom portion of groove 42 is the glued membrane being pasted onto on frame.This glued membrane can be dry-film resist, has bigger viscosity, thereby through the fixing base plate for packaging of bonding mode.
Wherein, base plate for packaging can be the mother substrate including multiple base board unit, it is also possible to be the independent base board unit separated from mother substrate.In the present embodiment, base plate for packaging refers to base board unit, one base board unit is such as one piece of circuit board, for packaged semiconductor, and base board unit can also be packaged with other circuit components, such as passive devices etc., wherein on each base plate for packaging, the semiconductor chip of encapsulation can be single and can also be many, specifically can be determined by actual circuit structure.The corresponding one or more encapsulation units of each base plate for packaging, in the present embodiment, it is preferable that the corresponding encapsulation unit of each base plate for packaging.
Step S302: utilize fixed part to be fixed on the board of sealed in unit by carrier, and base plate for packaging is fixed in bearing area, so that semiconductor chip is packaged.
During by semiconductor die package on base plate for packaging, it usually needs through multiple processing steps, for instance cleaning, upside-down mounting, plastic packaging, cutting etc., sealed in unit includes the equipment needed for every one process stations point, for instance upside-down mounting equipment, plastic packaging equipment etc..Utilize the carrier of embodiment of the present invention, when needs are by time fixing for base plate for packaging, it is possible to use base plate for packaging is fixed on the board of sealed in unit to carry out corresponding operation by carrier.
For example, when carrying out reverse installation process, base plate for packaging need to be fixed on the board of upside-down mounting equipment.Now, can first carrier 40 be fixed on the board of upside-down mounting equipment by positioning hole 411, then base plate for packaging being fixed on the bearing area of carrier 40, thus being fixed on by base plate for packaging on the board of upside-down mounting equipment, utilizing upside-down mounting equipment to be inverted on base plate for packaging by semiconductor chip afterwards.Or can also first base plate for packaging be fixed on the bearing area of carrier 40, then carrier 40 is fixed on the board of upside-down mounting equipment.
After being inverted on base plate for packaging by semiconductor chip, semiconductor chip is carried out plastic package process.Specifically, carrier 40 is taken out from the board of upside-down mounting equipment, and by positioning hole 411, the carrier 40 carrying base plate for packaging is fixed on the board of plastic packaging equipment, thus utilizing plastic packaging equipment that the semiconductor chip on base plate for packaging is carried out plastic packaging.After completing plastic packaging, peel off the bottom portion of groove 42 of carrier 40, i.e. glued membrane, thus exposing the bottom of base plate for packaging, in order to carry out subsequent job.Wherein, owing to bottom portion of groove 42 is dry-film resist, therefore can pass through bottom portion of groove 42 is carried out illumination to reduce the viscosity of bottom portion of groove 42, then bottom portion of groove 42 be peeled off frame 41.
In present embodiment, carrier 40 is utilized to be fixed on the board of sealed in unit by base plate for packaging, with by semiconductor die package in base plate for packaging, than existing, hole, location need not be set on mother substrate and can base plate for packaging is fixed on board, therefore mother substrate need not form hole, location by headspace, substrate space can be saved, more base plate for packaging can be obtained for the mother substrate of formed objects, such that it is able to encapsulate more semiconductor chip, advantageously reduce production cost.
In addition, in the present embodiment, one base plate for packaging is the independent base board unit separated from mother substrate, therefore it is be packaged in units of the base board unit less than mother substrate area in encapsulation process, base plate for packaging subjected to stress effect can be reduced to a certain extent, such that it is able to reduce the deformation warpage degree of base plate for packaging.And, for mother substrate, it need not be reserved certain space as existing mother substrate between base board unit or hollow out the subregion between base board unit, the mother substrate space that can save further, make mother substrate can be utilized effectively and more semiconductor chip can be encapsulated, be conducive to reducing further production cost, and mother substrate technique can be simplified.
Further, in the present embodiment, the bottom portion of groove 42 of carrier 40 is glued membrane, therefore after completing plastic packaging, utilizes the software feature of glued membrane can be peeled off by glued membrane preferably, and can reduce the stripping process bottom to base plate for packaging and cause damage.
Wherein, in another embodiment, carrier 40 can also include a base plate further, and base plate can be such as metallic plate or plastic plate etc..Glued membrane is attached on base plate, and the base plate posting glued membrane is connected to be formed the bottom portion of groove 42 of carrier 40 with four edges frame 41, and glued membrane is towards the opening direction of groove, and base plate for packaging is fixed on glued membrane.By arranging a base plate, it is possible to improve the intensity bottom carrier 40, it is to avoid glued membrane fracture in encapsulation process.Certainly, carrier 40 can also be four edges frame and the integrated groove structure of bottom portion of groove.
In other embodiments of the present invention, carrier can also be flat loading plate, the bearing area of loading plate is the region on loading plate, the zone line of such as loading plate is bearing area, and fixed part is the hole, location being arranged on loading plate, it is possible to determine the position in hole, location according to the structure of board.Now, in encapsulation process, when base plate for packaging is fixed on loading plate, it is possible to first paste last layer glued membrane in bearing area, then base plate for packaging is fixed on glued membrane, then loading plate is fixed on board carries out operation by positioning hole.Utilize flat loading plate as the carrier of base plate for packaging, it is possible to realize being fixed on by base plate for packaging on board it is also possible to reduce the manufacturing process of carrier.
In order to describe the method for packing of the present invention better, the base plate for packaging being packaged with semiconductor chip is defined as a packaging body.In order to improve production efficiency, it is common that simultaneously that the encapsulation of multiple base plate for packaging is required semiconductor chip, with while the multiple packaging body of output.Utilizing the carrier 40 of the present invention, it is possible to achieve simultaneously that the encapsulation of multiple base plate for packaging is required semiconductor chip, wherein the bearing area of carrier 40 can be divided into multiple block of cells, each block of cells carries at least one base plate for packaging.
More specifically, consult Fig. 6, and being the flow chart of method for packing one embodiment of flip-chip of the present invention in conjunction with Fig. 4 and Fig. 5, Fig. 6, illustrate the structure that each step is corresponding in figure, in figure, the element effect of identical label is identical.Fig. 6 wherein only illustrates two base plate for packaging, it will be appreciated by persons skilled in the art that its bearing area can carry more base plate for packaging when carrier 40 is sufficiently large, to carry out producing multiple packaging body simultaneously.Described method comprises the steps:
Step S601, except providing carrier 40, multiple base plate for packaging 61, also provides for multiple semiconductor chip 62.Plurality of base plate for packaging 61 is separate, and as a kind of example, figure only illustrates two semiconductor chips 62, each semiconductor chip 62 correspondence is encapsulated on a base plate for packaging 61, but as before, base plate for packaging 61 also can encapsulate more semiconductor chip and other components and parts, can determine according to side circuit.
Wherein, the surface of semiconductor chip 62 includes first surface 621 and second surface 622.First surface 621 is the action face of semiconductor chip 62, namely has the surface of circuit structure, and for the front of semiconductor chip 62, second surface 622 is the back side of semiconductor chip 62.Being formed with the first connection terminal 623 on first surface 621, wherein four first connection terminals 623 shown in figure, first connects terminal 623 is electrically connected with the circuit structure (not shown) in semiconductor chip 62.
Base plate for packaging 61 includes the 3rd relative surface 611 and the 4th surface 612.3rd surface 611 is formed the second connection terminal 613, the 4th surface 612 is formed the 3rd connection terminal 614.Second connection terminal 613 and the 3rd connection terminal 614 are electrically connected to each other, and the second annexation connected between terminal 613, between the 3rd connection terminal 614 and between the second connection terminal 613 and the 3rd connection terminal 614 can need be determined according to side circuit, illustrates only as a kind of example in figure.
Multiple base plate for packaging 61 are fixed on bearing area, are specifically fixed on the bottom portion of groove 42 of carrier 40 by step S602.Wherein, bottom portion of groove 42 being provided with the telltale mark for positioning each base plate for packaging 61, telltale mark can be such as location line or sprocket bit etc..According to telltale mark, multiple base plate for packaging 61 are fixed on bottom portion of groove 42.
Step S603,3rd surface 611 of the first surface 621 of semiconductor chip 62 and corresponding base plate for packaging 61 is oppositely arranged and is made the second connection terminal 613 that first on first surface 621 connects on terminal 623 and the 3rd surface 611 weld together, thus being inverted on base plate for packaging 61 by semiconductor chip 62.Each semiconductor chip 62 correspondence is inverted on a base plate for packaging 61.
Wherein, first connects terminal 623 and can be connected terminal 613 with the second of base plate for packaging 61 after picking scaling powder and interconnect；Can also first by non-conductive adhesive (Non-ConductivePaste, NCP) on the surface of base plate for packaging 61, make the first of semiconductor chip 62 connect terminal 623 by the mode of thermocompression bonding (ThermalCompressBonding, TCB) and be connected terminal 613 realization interconnection with the second of base plate for packaging 61.
Wherein, in a kind of possible embodiment, consulting Fig. 7, the first connection terminal 623 is pedestal, it is possible to be the structure of metal salient point (studbond)+solder that bonding technology is formed.Wherein it is possible to form bond wire salient point 6231 in advance on pad, and make formation solder layer 6232 on metal salient point 6231, thus forming the first connection terminal 623.When the first surface 621 of semiconductor chip 62 and the 3rd surface 611 of base plate for packaging 61 are oppositely arranged, first solder layer 6232 connecting terminal 623 connects terminal 613 with second on the 3rd surface 611 and contacts, thereby through reflow soldering process, the solder layer 6232 on metal salient point 6231 is melted, and then metal salient point 6231 and the second connection terminal 613 are welded together, thus realizing semiconductor chip 62 and the interconnection of base plate for packaging 61.In another embodiment, it is also possible to connect second and terminal 613 is formed metal salient point, then pass through the metal salient point on the second connection terminal 613 and realize being connected the interconnection of terminal 623 phase with the first of semiconductor chip 62.By making the first or second connection terminal form metal salient point to realize base plate for packaging 61 and the interconnection of semiconductor chip 62, by increasing capacitance it is possible to increase the space height between semiconductor chip 62 and base plate for packaging 61, thus the filling being prone in plastic package process plastic packaging material.
Certainly, in other embodiments, the first connection terminal 623 can also be the spherical stannum ball (solderball) formed by solder, it is also possible to be the solder bump (pillarbump) etc. of column.
With continued reference to Fig. 6, step S604, form plastic packaging layer 63 on the surface of semiconductor chip 62, and expose second surface 622.After being fixed on base plate for packaging 61 by semiconductor chip 62, semiconductor chip 62 is carried out plastic packaging, to form plastic packaging layer 63 on the surface of semiconductor chip 62.Specifically, in groove 42, fill capsulation material, then pass through heating or other modes solidify capsulation material, thus forming plastic packaging layer 63.In present embodiment, plastic packaging layer 63 is as the encapsulated layer of semiconductor chip 62, and it uses epoxide resin material to be formed, and namely capsulation material is epoxide resin material.Plastic packaging layer 63 wraps up the most surfaces of semiconductor chip 62, and is formed without plastic packaging layer 63 on second surface 622, so that second surface 622 exposes.
Wherein, exposed second surface 622 is the back side of the semiconductor chip 62 relative with first surface 621, and the side of semiconductor chip 62 and first surface 621 are plastic packaging layer 63 and are wrapped up.Further, the space between first surface 621 and the 3rd surface 611 of base plate for packaging 61 of semiconductor chip 62 is also filled by plastic packaging layer 63.
Wherein, also include step S605, remove bottom portion of groove 42, on the 4th surface 612 of base plate for packaging 61 the 3rd connects formation solder bump 615 on terminal 614, and then form similar ball array encapsulation (BallGridArray, BGA) encapsulation of profile, then be interconnected with next layer of assembling.Wherein solder bump 615 can be solder ball, it is also possible to be the coalition of metal salient point+solder.In other embodiments, directly it is interconnected with next layer of assembling as signal terminal if the 3rd of base plate for packaging 61 the connects terminal 614, form similar grid array encapsulation (LandGridArray, LGA) encapsulation of profile, then form pedestal 615 without connecting the 3rd on terminal 614.
Step S606, the plastic packaging layer 63 being pointed between base plate for packaging 61 carries out cutting to separate multiple base plate for packaging 61, and makes in each base plate for packaging 61 remaining surface except the 4th surface 612 be each formed with plastic packaging layer 63.As it can be seen, in cutting process, plastic packaging layer 63 cuts to separate multiple encapsulating structure, and makes the equal member-retaining portion plastic packaging layer 63 of dual-side of each base plate for packaging 61.Described encapsulating structure refers to a base plate for packaging 61 and the structure of the semiconductor chip 62 being fixed on this base plate for packaging 61.
Owing to being that plastic packaging layer 63 is cut, compared with traditional mode that mother substrate is cut, present embodiment at the equal member-retaining portion plastic packaging layer 63 of the dual-side of base plate for packaging 61, can be conducive to the internal circuit of protection packaging substrate 61 in cutting process.
In traditional packaged type, plastic packaging layer usually wraps up whole semiconductor chip, cause that semiconductor chip outwards dispels the heat only by base plate for packaging, and present embodiment, by by exposed for the second surface 622 relative with first surface 621, distribute so that the heat of semiconductor chip 62 connects terminal 613 not only by the second of base plate for packaging 61 via base plate for packaging 61, and the second surface 621 that can pass through to expose dispels the heat, thus substantially increasing the heat-sinking capability of semiconductor chip 62, make the radiating effect of semiconductor chip 62 more, be conducive to improving the stability of circuit.
In another embodiment of the present invention, in order to improve the heat-sinking capability of semiconductor chip 62 further, consulting Fig. 8, after the surface of semiconductor chip 62 forms the step of plastic packaging layer 63, it also can farther include following steps: forms heat dissipating layer 64 on the second surface 622 exposed.Wherein, heat dissipating layer 64 can adopt the aluminium material with better heat dispersion.Wherein it is possible to be form heat dissipating layer 64 after plastic packaging layer 63 is cut again on the second surface 622 of the exposure of each semiconductor chip 62.
Consulting Fig. 9, in an embodiment of method for packing of the present invention, plastic packaging process can make portion second surface 622 expose by arranging barrier layer.Specifically, forming the step of plastic packaging layer 63 on the surface of semiconductor chip 62, namely the step S604 shown in Fig. 6 farther includes following sub-step:
Sub-step S6041, under upper film 92 matched moulds of plastic package die before pressure, arranges one layer of barrier layer on upper film 92, and described barrier layer is for having elastic glued membrane 91.
Sub-step S6042, is pressed together on the second surface 622 of semiconductor chip 62 by the upper film 92 being provided with glued membrane 91, namely carries out pressing by glued membrane 91 between the upper mould 92 of plastic package die and semiconductor chip 62.Thus glued membrane 91 is arranged on the second surface 622 of semiconductor chip 62.
Sub-step S6043, capsulation material is filled in the space between glued membrane 91 and bearing area, then solidifies capsulation material to form plastic packaging layer 63.Wherein, bearing area is bottom portion of groove 42, and namely capsulation material is filled in the space between glued membrane 91 and bottom portion of groove 42.Capsulation material can be epoxide resin material.Capsulation material is wherein made to fill up the space between semiconductor chip 62 and the 3rd surface 611 of base plate for packaging 61.
Step S6044, removes film 92 and glued membrane 91, to expose and the second surface 622 of glued membrane 91 laminating.
After removing glued membrane 91, perform the step S605 shown in Fig. 6.
In present embodiment, by arranging one layer of glued membrane 91 on the second surface 622 of semiconductor chip 62, thus can stop that in plastic packaging process capsulation material is spilled on this second surface 622, formation plastic packaging layer 63 on this portion second surface 622 therefore can be avoided.In addition, the glued membrane 91 of present embodiment is for having elastic glued membrane, therefore can the upper film 92 of plastic package die be pressed on glued membrane 91, glued membrane 91 can be fitted tightly with the second surface 622 of semiconductor chip 62, avoid capsulation material to overflow to this second surface 622 further, utilize the stress that glued membrane 91 absorbs upper film 92 to be possible to prevent film 92 to be damaged by pressure by semiconductor chip 62 simultaneously.
Additionally, by glued membrane 91, it is possible to regulate the welding and assembling height tolerance that semiconductor chip 62 causes in reflow process.Specifically, by the semiconductor chip 62 after being oppositely arranged and base plate for packaging 61 by Reflow Soldering with after carrying out welding therebetween, multiple semiconductor chips 62 would be likely to occur difference in height, causes the second surface 622 of exposure of multiple semiconductor chip 62 not at grade.And in follow-up plastic packaging process, by arranging, there is elastic glued membrane 91, when pressing plate 92 is pressed on glued membrane 91, the elasticity utilizing glued membrane 91 can so that glued membrane 91 fits tightly with highly inconsistent multiple semiconductor chips 62 simultaneously, avoid existing between glued membrane 91 and relatively low semiconductor chip 62 bigger space, such that it is able to avoid encapsulating material to overflow to the second surface 622 exposed.
Wherein, in an embodiment of the present invention, what flip-chip link adopted is TCB/NCP technique, and the gap between base plate for packaging 61 and semiconductor chip 62 is filled for NCP before carrying out plastic packaging.Specifically, as shown in Figure 10, before the surface of semiconductor chip 62 is formed the step of plastic packaging layer 63, namely before step S604, after semiconductor chip 62 and base plate for packaging 61 are welded together, space between the first surface 621 and the 3rd surface 611 of base plate for packaging 61 of semiconductor chip 62 carries out NCP underfill, to form Underfill layer 34.
In other embodiments, it would however also be possible to employ some glue mode carries out underfill.Certainly, when spacing between semiconductor chip 62 and base plate for packaging 61 is bigger, is conducive to capsulation material to flow into the space between semiconductor chip 62 and base plate for packaging 61, therefore can not carry out underfill, but directly chip be carried out plastic packaging.
When spacing between semiconductor chip 62 and base plate for packaging 61 is less, by the space between semiconductor chip 62 and base plate for packaging 61 first being carried out underfill, it is possible to reduce the probability causing interior void because the material of plastic packaging layer 33 is difficult to fill up the space between first surface 621 and the 3rd surface 611 of base plate for packaging 61 of semiconductor chip 62.
In the above-described embodiment, by arranging glued membrane 91 to stop the first encapsulating material to cover the second surface 622 relative with first surface 621, so that the second surface 622 relative with first surface 621 exposes, in other embodiments of the present invention, it is also possible to expose second surface 622 by other means.Such as, when being not provided with glued membrane 91, semiconductor chip 62 is filled the first encapsulating material, to form the encapsulated layer on the surface wrapping up whole semiconductor chip 62, then pass through the techniques such as cutting, grinding or chemical attack and remove the encapsulated layer on the second surface relative with first surface, thus expose portion second surface.Or, can also by controlling the consumption of the first encapsulating material so that the first encapsulating material after filling is positioned under the second surface relative with first surface, thus avoiding the first encapsulating material to flood the second surface relative with first surface, and then expose the second surface relative with first surface.
In addition, as shown in Figure 6, the second surface 622 exposed is the whole second surface relative with first surface 621, in other embodiments, the second surface exposed can also be the portion second surface relative with first surface 621, and the shape of the second surface exposed can be trapezoidal, circular or irregularly shaped etc..
The present invention also provides for the embodiment of a kind of packaging system, and it is identical with the structure of the carrier described in aforementioned any embodiment and using method that packaging system includes carrier, the structure of wherein said carrier and using method.
The foregoing is only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every equivalent structure utilizing description of the present invention and accompanying drawing content to make or equivalence flow process conversion; or directly or indirectly it is used in other relevant technical fields, all in like manner include in the scope of patent protection of the present invention.

Claims (14)

1. the method for packing of a flip-chip, it is characterised in that including:
Thering is provided carrier and base plate for packaging, described carrier includes bearing area, and is provided with fixed part on described carrier, and described base plate for packaging is used for packaged semiconductor；
Utilize described fixed part to be fixed on the board of sealed in unit by described carrier, and described base plate for packaging is fixed in described bearing area, so that described semiconductor chip is packaged.
2. method for packing according to claim 1, it is characterized in that, described carrier is groove structure, described groove structure includes the four edges frame that head and the tail connect and the bottom portion of groove being connected with described four edges frame, described bearing area is positioned at described bottom portion of groove, and described fixed part is the hole, location being arranged on described frame.
3. method for packing according to claim 2, it is characterised in that described bottom portion of groove is the glued membrane being pasted onto on described frame.
4. method for packing according to claim 1, it is characterised in that described carrier is flat loading plate, described fixed part is the hole, location being arranged on described loading plate.
5. the method for packing according to any one of claim 1-4, it is characterized in that, the quantity of described base plate for packaging is multiple, multiple described base plate for packaging are separate, each described base plate for packaging is used for encapsulating at least one described semiconductor chip, and described bearing area is provided with the telltale mark for positioning each described base plate for packaging；
Described the step that described base plate for packaging is fixed in described bearing area is included:
According to described telltale mark, multiple described base plate for packaging are fixed on described bearing area.
6. method for packing according to claim 5, it is characterised in that the step of described offer base plate carrying frame and base plate for packaging includes:
Also provide for multiple described semiconductor chip, the surface of described semiconductor chip includes first surface and second surface, being formed with the first connection terminal on described first surface, described base plate for packaging includes the 3rd surface and the 4th surface, described 3rd surface being formed with the second connection terminal；
Described described base plate for packaging is fixed on the step in described bearing area after, including:
3rd surface of the first surface of described semiconductor chip and corresponding described base plate for packaging is oppositely arranged and is made described first connect terminal and described second connection terminal welds together；
Encapsulated layer is formed on the surface of described semiconductor chip, and at least second surface described in expose portion.
7. method for packing according to claim 6, it is characterised in that after the surface of described semiconductor chip forms the step of encapsulated layer, including:
The described second surface exposed is formed heat dissipating layer.
8. method for packing according to claim 6, it is characterised in that the step forming encapsulated layer on the surface of described semiconductor chip includes:
The portion second surface of described semiconductor chip arranges one layer of barrier layer；
Capsulation material is filled in space between described barrier layer and described bearing area；
Solidify described capsulation material and form described encapsulated layer with the surface at described semiconductor chip；
Remove described barrier layer, to expose described portion second surface.
9. method for packing according to claim 8, it is characterised in that described barrier layer is for having elastic glued membrane；
The step arranging one layer of barrier layer on the described described second surface of the part at described semiconductor chip includes: arranges described barrier layer on the upper film of plastic package die, and makes described upper film be pressed on described second surface by described barrier layer.
10. method for packing according to claim 8, it is characterised in that after removing the step on described barrier layer, including:
It is pointed to the encapsulated layer between described base plate for packaging and carries out cutting to separate multiple described base plate for packaging, and make in described base plate for packaging the remaining surface except described 4th surface be each formed with described encapsulated layer.
11. method for packing according to claim 6, it is characterized in that, after 3rd surface of the described first surface by described semiconductor chip and corresponding described base plate for packaging is oppositely arranged and makes described first connection terminal and described second to connect the step that terminal welds together, including:
Underfill layer is formed between the 3rd surface of the first surface of described semiconductor chip and the described base plate for packaging of correspondence.
12. a packaging system, it is characterised in that include carrier, described carrier includes bearing area, and described bearing area is used for fixing base plate for packaging, and described base plate for packaging is used for packaged semiconductor；
Described carrier is provided with fixed part, to utilize described fixed part to be fixed on the board of sealed in unit by described carrier, so that the semiconductor chip being fixed on the described base plate for packaging in described bearing area to be packaged.
13. packaging system according to claim 12, it is characterized in that, described carrier is groove structure, described groove structure includes the four edges frame that head and the tail connect and the bottom portion of groove being connected with described four edges frame, described bearing area is positioned at described bottom portion of groove, and described fixed part is the hole, location being arranged on described frame.
14. packaging system according to claim 13, it is characterised in that described bottom portion of groove is the glued membrane being pasted onto on described frame.
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